1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * mt8195-afe-clk.h  --  Mediatek 8195 afe clock ctrl definition
4  *
5  * Copyright (c) 2021 MediaTek Inc.
6  * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
7  *         Trevor Wu <trevor.wu@mediatek.com>
8  */
9 
10 #ifndef _MT8195_AFE_CLK_H_
11 #define _MT8195_AFE_CLK_H_
12 
13 enum {
14 	/* xtal */
15 	MT8195_CLK_XTAL_26M,
16 	/* divider */
17 	MT8195_CLK_TOP_APLL1,
18 	MT8195_CLK_TOP_APLL2,
19 	MT8195_CLK_TOP_APLL12_DIV0,
20 	MT8195_CLK_TOP_APLL12_DIV1,
21 	MT8195_CLK_TOP_APLL12_DIV2,
22 	MT8195_CLK_TOP_APLL12_DIV3,
23 	MT8195_CLK_TOP_APLL12_DIV9,
24 	/* mux */
25 	MT8195_CLK_TOP_A1SYS_HP_SEL,
26 	MT8195_CLK_TOP_AUD_INTBUS_SEL,
27 	MT8195_CLK_TOP_AUDIO_H_SEL,
28 	MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
29 	MT8195_CLK_TOP_DPTX_M_SEL,
30 	MT8195_CLK_TOP_I2SO1_M_SEL,
31 	MT8195_CLK_TOP_I2SO2_M_SEL,
32 	MT8195_CLK_TOP_I2SI1_M_SEL,
33 	MT8195_CLK_TOP_I2SI2_M_SEL,
34 	/* clock gate */
35 	MT8195_CLK_INFRA_AO_AUDIO_26M_B,
36 	MT8195_CLK_SCP_ADSP_AUDIODSP,
37 	MT8195_CLK_AUD_AFE,
38 	MT8195_CLK_AUD_APLL1_TUNER,
39 	MT8195_CLK_AUD_APLL2_TUNER,
40 	MT8195_CLK_AUD_APLL,
41 	MT8195_CLK_AUD_APLL2,
42 	MT8195_CLK_AUD_DAC,
43 	MT8195_CLK_AUD_ADC,
44 	MT8195_CLK_AUD_DAC_HIRES,
45 	MT8195_CLK_AUD_A1SYS_HP,
46 	MT8195_CLK_AUD_ADC_HIRES,
47 	MT8195_CLK_AUD_ADDA6_ADC,
48 	MT8195_CLK_AUD_ADDA6_ADC_HIRES,
49 	MT8195_CLK_AUD_I2SIN,
50 	MT8195_CLK_AUD_TDM_IN,
51 	MT8195_CLK_AUD_I2S_OUT,
52 	MT8195_CLK_AUD_TDM_OUT,
53 	MT8195_CLK_AUD_HDMI_OUT,
54 	MT8195_CLK_AUD_ASRC11,
55 	MT8195_CLK_AUD_ASRC12,
56 	MT8195_CLK_AUD_A1SYS,
57 	MT8195_CLK_AUD_A2SYS,
58 	MT8195_CLK_AUD_PCMIF,
59 	MT8195_CLK_AUD_MEMIF_UL1,
60 	MT8195_CLK_AUD_MEMIF_UL2,
61 	MT8195_CLK_AUD_MEMIF_UL3,
62 	MT8195_CLK_AUD_MEMIF_UL4,
63 	MT8195_CLK_AUD_MEMIF_UL5,
64 	MT8195_CLK_AUD_MEMIF_UL6,
65 	MT8195_CLK_AUD_MEMIF_UL8,
66 	MT8195_CLK_AUD_MEMIF_UL9,
67 	MT8195_CLK_AUD_MEMIF_UL10,
68 	MT8195_CLK_AUD_MEMIF_DL2,
69 	MT8195_CLK_AUD_MEMIF_DL3,
70 	MT8195_CLK_AUD_MEMIF_DL6,
71 	MT8195_CLK_AUD_MEMIF_DL7,
72 	MT8195_CLK_AUD_MEMIF_DL8,
73 	MT8195_CLK_AUD_MEMIF_DL10,
74 	MT8195_CLK_AUD_MEMIF_DL11,
75 	MT8195_CLK_NUM,
76 };
77 
78 enum {
79 	MT8195_MCK_SEL_26M,
80 	MT8195_MCK_SEL_APLL1,
81 	MT8195_MCK_SEL_APLL2,
82 	MT8195_MCK_SEL_APLL3,
83 	MT8195_MCK_SEL_APLL4,
84 	MT8195_MCK_SEL_APLL5,
85 	MT8195_MCK_SEL_HDMIRX_APLL,
86 	MT8195_MCK_SEL_NUM,
87 };
88 
89 enum {
90 	MT8195_AUD_PLL1,
91 	MT8195_AUD_PLL2,
92 	MT8195_AUD_PLL3,
93 	MT8195_AUD_PLL4,
94 	MT8195_AUD_PLL5,
95 	MT8195_AUD_PLL_NUM,
96 };
97 
98 struct mtk_base_afe;
99 
100 int mt8195_afe_get_mclk_source_clk_id(int sel);
101 int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll);
102 int mt8195_afe_get_default_mclk_source_by_rate(int rate);
103 int mt8195_afe_init_clock(struct mtk_base_afe *afe);
104 void mt8195_afe_deinit_clock(struct mtk_base_afe *afe);
105 int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
106 void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
107 int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk);
108 void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk);
109 int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk);
110 void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk);
111 int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
112 			    unsigned int rate);
113 int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
114 			      struct clk *parent);
115 int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe);
116 int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe);
117 int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);
118 int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe);
119 
120 #endif
121