16746cc85STrevor Wu // SPDX-License-Identifier: GPL-2.0 26746cc85STrevor Wu /* 36746cc85STrevor Wu * mt8195-afe-clk.c -- Mediatek 8195 afe clock ctrl 46746cc85STrevor Wu * 56746cc85STrevor Wu * Copyright (c) 2021 MediaTek Inc. 66746cc85STrevor Wu * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 76746cc85STrevor Wu * Trevor Wu <trevor.wu@mediatek.com> 86746cc85STrevor Wu */ 96746cc85STrevor Wu 106746cc85STrevor Wu #include <linux/clk.h> 116746cc85STrevor Wu 126746cc85STrevor Wu #include "mt8195-afe-common.h" 136746cc85STrevor Wu #include "mt8195-afe-clk.h" 146746cc85STrevor Wu #include "mt8195-reg.h" 156746cc85STrevor Wu #include "mt8195-audsys-clk.h" 166746cc85STrevor Wu 176746cc85STrevor Wu static const char *aud_clks[MT8195_CLK_NUM] = { 186746cc85STrevor Wu /* xtal */ 196746cc85STrevor Wu [MT8195_CLK_XTAL_26M] = "clk26m", 206746cc85STrevor Wu /* divider */ 216746cc85STrevor Wu [MT8195_CLK_TOP_APLL1] = "apll1_ck", 226746cc85STrevor Wu [MT8195_CLK_TOP_APLL2] = "apll2_ck", 236746cc85STrevor Wu [MT8195_CLK_TOP_APLL12_DIV0] = "apll12_div0", 246746cc85STrevor Wu [MT8195_CLK_TOP_APLL12_DIV1] = "apll12_div1", 256746cc85STrevor Wu [MT8195_CLK_TOP_APLL12_DIV2] = "apll12_div2", 266746cc85STrevor Wu [MT8195_CLK_TOP_APLL12_DIV3] = "apll12_div3", 276746cc85STrevor Wu [MT8195_CLK_TOP_APLL12_DIV9] = "apll12_div9", 286746cc85STrevor Wu /* mux */ 296746cc85STrevor Wu [MT8195_CLK_TOP_A1SYS_HP_SEL] = "a1sys_hp_sel", 306746cc85STrevor Wu [MT8195_CLK_TOP_AUD_INTBUS_SEL] = "aud_intbus_sel", 316746cc85STrevor Wu [MT8195_CLK_TOP_AUDIO_H_SEL] = "audio_h_sel", 326746cc85STrevor Wu [MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "audio_local_bus_sel", 336746cc85STrevor Wu [MT8195_CLK_TOP_DPTX_M_SEL] = "dptx_m_sel", 346746cc85STrevor Wu [MT8195_CLK_TOP_I2SO1_M_SEL] = "i2so1_m_sel", 356746cc85STrevor Wu [MT8195_CLK_TOP_I2SO2_M_SEL] = "i2so2_m_sel", 366746cc85STrevor Wu [MT8195_CLK_TOP_I2SI1_M_SEL] = "i2si1_m_sel", 376746cc85STrevor Wu [MT8195_CLK_TOP_I2SI2_M_SEL] = "i2si2_m_sel", 386746cc85STrevor Wu /* clock gate */ 396746cc85STrevor Wu [MT8195_CLK_INFRA_AO_AUDIO_26M_B] = "infra_ao_audio_26m_b", 406746cc85STrevor Wu [MT8195_CLK_SCP_ADSP_AUDIODSP] = "scp_adsp_audiodsp", 416746cc85STrevor Wu /* afe clock gate */ 426746cc85STrevor Wu [MT8195_CLK_AUD_AFE] = "aud_afe", 436746cc85STrevor Wu [MT8195_CLK_AUD_APLL] = "aud_apll", 446746cc85STrevor Wu [MT8195_CLK_AUD_APLL2] = "aud_apll2", 456746cc85STrevor Wu [MT8195_CLK_AUD_DAC] = "aud_dac", 466746cc85STrevor Wu [MT8195_CLK_AUD_ADC] = "aud_adc", 476746cc85STrevor Wu [MT8195_CLK_AUD_DAC_HIRES] = "aud_dac_hires", 486746cc85STrevor Wu [MT8195_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp", 496746cc85STrevor Wu [MT8195_CLK_AUD_ADC_HIRES] = "aud_adc_hires", 506746cc85STrevor Wu [MT8195_CLK_AUD_ADDA6_ADC] = "aud_adda6_adc", 516746cc85STrevor Wu [MT8195_CLK_AUD_ADDA6_ADC_HIRES] = "aud_adda6_adc_hires", 526746cc85STrevor Wu [MT8195_CLK_AUD_I2SIN] = "aud_i2sin", 536746cc85STrevor Wu [MT8195_CLK_AUD_TDM_IN] = "aud_tdm_in", 546746cc85STrevor Wu [MT8195_CLK_AUD_I2S_OUT] = "aud_i2s_out", 556746cc85STrevor Wu [MT8195_CLK_AUD_TDM_OUT] = "aud_tdm_out", 566746cc85STrevor Wu [MT8195_CLK_AUD_HDMI_OUT] = "aud_hdmi_out", 576746cc85STrevor Wu [MT8195_CLK_AUD_ASRC11] = "aud_asrc11", 586746cc85STrevor Wu [MT8195_CLK_AUD_ASRC12] = "aud_asrc12", 596746cc85STrevor Wu [MT8195_CLK_AUD_A1SYS] = "aud_a1sys", 606746cc85STrevor Wu [MT8195_CLK_AUD_A2SYS] = "aud_a2sys", 616746cc85STrevor Wu [MT8195_CLK_AUD_PCMIF] = "aud_pcmif", 626746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1", 636746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2", 646746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3", 656746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4", 666746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5", 676746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6", 686746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8", 696746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9", 706746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10", 716746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2", 726746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3", 736746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6", 746746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7", 756746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8", 766746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10", 776746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11", 786746cc85STrevor Wu }; 796746cc85STrevor Wu 806746cc85STrevor Wu int mt8195_afe_get_mclk_source_clk_id(int sel) 816746cc85STrevor Wu { 826746cc85STrevor Wu switch (sel) { 836746cc85STrevor Wu case MT8195_MCK_SEL_26M: 846746cc85STrevor Wu return MT8195_CLK_XTAL_26M; 856746cc85STrevor Wu case MT8195_MCK_SEL_APLL1: 866746cc85STrevor Wu return MT8195_CLK_TOP_APLL1; 876746cc85STrevor Wu case MT8195_MCK_SEL_APLL2: 886746cc85STrevor Wu return MT8195_CLK_TOP_APLL2; 896746cc85STrevor Wu default: 906746cc85STrevor Wu return -EINVAL; 916746cc85STrevor Wu } 926746cc85STrevor Wu } 936746cc85STrevor Wu 946746cc85STrevor Wu int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll) 956746cc85STrevor Wu { 966746cc85STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 976746cc85STrevor Wu int clk_id = mt8195_afe_get_mclk_source_clk_id(apll); 986746cc85STrevor Wu 996746cc85STrevor Wu if (clk_id < 0) { 1006746cc85STrevor Wu dev_dbg(afe->dev, "invalid clk id\n"); 1016746cc85STrevor Wu return 0; 1026746cc85STrevor Wu } 1036746cc85STrevor Wu 1046746cc85STrevor Wu return clk_get_rate(afe_priv->clk[clk_id]); 1056746cc85STrevor Wu } 1066746cc85STrevor Wu 1076746cc85STrevor Wu int mt8195_afe_get_default_mclk_source_by_rate(int rate) 1086746cc85STrevor Wu { 1096746cc85STrevor Wu return ((rate % 8000) == 0) ? 1106746cc85STrevor Wu MT8195_MCK_SEL_APLL1 : MT8195_MCK_SEL_APLL2; 1116746cc85STrevor Wu } 1126746cc85STrevor Wu 1136746cc85STrevor Wu int mt8195_afe_init_clock(struct mtk_base_afe *afe) 1146746cc85STrevor Wu { 1156746cc85STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 1166746cc85STrevor Wu int i; 1176746cc85STrevor Wu 1186746cc85STrevor Wu mt8195_audsys_clk_register(afe); 1196746cc85STrevor Wu 1206746cc85STrevor Wu afe_priv->clk = 1216746cc85STrevor Wu devm_kcalloc(afe->dev, MT8195_CLK_NUM, sizeof(*afe_priv->clk), 1226746cc85STrevor Wu GFP_KERNEL); 1236746cc85STrevor Wu if (!afe_priv->clk) 1246746cc85STrevor Wu return -ENOMEM; 1256746cc85STrevor Wu 1266746cc85STrevor Wu for (i = 0; i < MT8195_CLK_NUM; i++) { 1276746cc85STrevor Wu afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); 1286746cc85STrevor Wu if (IS_ERR(afe_priv->clk[i])) { 1296746cc85STrevor Wu dev_dbg(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n", 1306746cc85STrevor Wu __func__, aud_clks[i], 1316746cc85STrevor Wu PTR_ERR(afe_priv->clk[i])); 1326746cc85STrevor Wu return PTR_ERR(afe_priv->clk[i]); 1336746cc85STrevor Wu } 1346746cc85STrevor Wu } 1356746cc85STrevor Wu 1366746cc85STrevor Wu return 0; 1376746cc85STrevor Wu } 1386746cc85STrevor Wu 1396746cc85STrevor Wu void mt8195_afe_deinit_clock(struct mtk_base_afe *afe) 1406746cc85STrevor Wu { 1416746cc85STrevor Wu mt8195_audsys_clk_unregister(afe); 1426746cc85STrevor Wu } 1436746cc85STrevor Wu 1446746cc85STrevor Wu int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk) 1456746cc85STrevor Wu { 1466746cc85STrevor Wu int ret; 1476746cc85STrevor Wu 1486746cc85STrevor Wu if (clk) { 1496746cc85STrevor Wu ret = clk_prepare_enable(clk); 1506746cc85STrevor Wu if (ret) { 1516746cc85STrevor Wu dev_dbg(afe->dev, "%s(), failed to enable clk\n", 1526746cc85STrevor Wu __func__); 1536746cc85STrevor Wu return ret; 1546746cc85STrevor Wu } 1556746cc85STrevor Wu } else { 1566746cc85STrevor Wu dev_dbg(afe->dev, "NULL clk\n"); 1576746cc85STrevor Wu } 1586746cc85STrevor Wu return 0; 1596746cc85STrevor Wu } 1606746cc85STrevor Wu EXPORT_SYMBOL_GPL(mt8195_afe_enable_clk); 1616746cc85STrevor Wu 1626746cc85STrevor Wu void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk) 1636746cc85STrevor Wu { 1646746cc85STrevor Wu if (clk) 1656746cc85STrevor Wu clk_disable_unprepare(clk); 1666746cc85STrevor Wu else 1676746cc85STrevor Wu dev_dbg(afe->dev, "NULL clk\n"); 1686746cc85STrevor Wu } 1696746cc85STrevor Wu EXPORT_SYMBOL_GPL(mt8195_afe_disable_clk); 1706746cc85STrevor Wu 1716746cc85STrevor Wu int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk) 1726746cc85STrevor Wu { 1736746cc85STrevor Wu int ret; 1746746cc85STrevor Wu 1756746cc85STrevor Wu if (clk) { 1766746cc85STrevor Wu ret = clk_prepare(clk); 1776746cc85STrevor Wu if (ret) { 1786746cc85STrevor Wu dev_dbg(afe->dev, "%s(), failed to prepare clk\n", 1796746cc85STrevor Wu __func__); 1806746cc85STrevor Wu return ret; 1816746cc85STrevor Wu } 1826746cc85STrevor Wu } else { 1836746cc85STrevor Wu dev_dbg(afe->dev, "NULL clk\n"); 1846746cc85STrevor Wu } 1856746cc85STrevor Wu return 0; 1866746cc85STrevor Wu } 1876746cc85STrevor Wu 1886746cc85STrevor Wu void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk) 1896746cc85STrevor Wu { 1906746cc85STrevor Wu if (clk) 1916746cc85STrevor Wu clk_unprepare(clk); 1926746cc85STrevor Wu else 1936746cc85STrevor Wu dev_dbg(afe->dev, "NULL clk\n"); 1946746cc85STrevor Wu } 1956746cc85STrevor Wu 1966746cc85STrevor Wu int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk) 1976746cc85STrevor Wu { 1986746cc85STrevor Wu int ret; 1996746cc85STrevor Wu 2006746cc85STrevor Wu if (clk) { 2016746cc85STrevor Wu ret = clk_enable(clk); 2026746cc85STrevor Wu if (ret) { 2036746cc85STrevor Wu dev_dbg(afe->dev, "%s(), failed to clk enable\n", 2046746cc85STrevor Wu __func__); 2056746cc85STrevor Wu return ret; 2066746cc85STrevor Wu } 2076746cc85STrevor Wu } else { 2086746cc85STrevor Wu dev_dbg(afe->dev, "NULL clk\n"); 2096746cc85STrevor Wu } 2106746cc85STrevor Wu return 0; 2116746cc85STrevor Wu } 2126746cc85STrevor Wu 2136746cc85STrevor Wu void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk) 2146746cc85STrevor Wu { 2156746cc85STrevor Wu if (clk) 2166746cc85STrevor Wu clk_disable(clk); 2176746cc85STrevor Wu else 2186746cc85STrevor Wu dev_dbg(afe->dev, "NULL clk\n"); 2196746cc85STrevor Wu } 2206746cc85STrevor Wu 2216746cc85STrevor Wu int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, 2226746cc85STrevor Wu unsigned int rate) 2236746cc85STrevor Wu { 2246746cc85STrevor Wu int ret; 2256746cc85STrevor Wu 2266746cc85STrevor Wu if (clk) { 2276746cc85STrevor Wu ret = clk_set_rate(clk, rate); 2286746cc85STrevor Wu if (ret) { 2296746cc85STrevor Wu dev_dbg(afe->dev, "%s(), failed to set clk rate\n", 2306746cc85STrevor Wu __func__); 2316746cc85STrevor Wu return ret; 2326746cc85STrevor Wu } 2336746cc85STrevor Wu } 2346746cc85STrevor Wu 2356746cc85STrevor Wu return 0; 2366746cc85STrevor Wu } 2376746cc85STrevor Wu 2386746cc85STrevor Wu int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, 2396746cc85STrevor Wu struct clk *parent) 2406746cc85STrevor Wu { 2416746cc85STrevor Wu int ret; 2426746cc85STrevor Wu 2436746cc85STrevor Wu if (clk && parent) { 2446746cc85STrevor Wu ret = clk_set_parent(clk, parent); 2456746cc85STrevor Wu if (ret) { 2466746cc85STrevor Wu dev_dbg(afe->dev, "%s(), failed to set clk parent\n", 2476746cc85STrevor Wu __func__); 2486746cc85STrevor Wu return ret; 2496746cc85STrevor Wu } 2506746cc85STrevor Wu } 2516746cc85STrevor Wu 2526746cc85STrevor Wu return 0; 2536746cc85STrevor Wu } 2546746cc85STrevor Wu 2556746cc85STrevor Wu static unsigned int get_top_cg_reg(unsigned int cg_type) 2566746cc85STrevor Wu { 2576746cc85STrevor Wu switch (cg_type) { 2586746cc85STrevor Wu case MT8195_TOP_CG_A1SYS_TIMING: 2596746cc85STrevor Wu case MT8195_TOP_CG_A2SYS_TIMING: 2606746cc85STrevor Wu case MT8195_TOP_CG_26M_TIMING: 2616746cc85STrevor Wu return ASYS_TOP_CON; 2626746cc85STrevor Wu default: 2636746cc85STrevor Wu return 0; 2646746cc85STrevor Wu } 2656746cc85STrevor Wu } 2666746cc85STrevor Wu 2676746cc85STrevor Wu static unsigned int get_top_cg_mask(unsigned int cg_type) 2686746cc85STrevor Wu { 2696746cc85STrevor Wu switch (cg_type) { 2706746cc85STrevor Wu case MT8195_TOP_CG_A1SYS_TIMING: 2716746cc85STrevor Wu return ASYS_TOP_CON_A1SYS_TIMING_ON; 2726746cc85STrevor Wu case MT8195_TOP_CG_A2SYS_TIMING: 2736746cc85STrevor Wu return ASYS_TOP_CON_A2SYS_TIMING_ON; 2746746cc85STrevor Wu case MT8195_TOP_CG_26M_TIMING: 2756746cc85STrevor Wu return ASYS_TOP_CON_26M_TIMING_ON; 2766746cc85STrevor Wu default: 2776746cc85STrevor Wu return 0; 2786746cc85STrevor Wu } 2796746cc85STrevor Wu } 2806746cc85STrevor Wu 2816746cc85STrevor Wu static unsigned int get_top_cg_on_val(unsigned int cg_type) 2826746cc85STrevor Wu { 2836746cc85STrevor Wu switch (cg_type) { 2846746cc85STrevor Wu case MT8195_TOP_CG_A1SYS_TIMING: 2856746cc85STrevor Wu case MT8195_TOP_CG_A2SYS_TIMING: 2866746cc85STrevor Wu case MT8195_TOP_CG_26M_TIMING: 2876746cc85STrevor Wu return get_top_cg_mask(cg_type); 2886746cc85STrevor Wu default: 2896746cc85STrevor Wu return 0; 2906746cc85STrevor Wu } 2916746cc85STrevor Wu } 2926746cc85STrevor Wu 2936746cc85STrevor Wu static unsigned int get_top_cg_off_val(unsigned int cg_type) 2946746cc85STrevor Wu { 2956746cc85STrevor Wu switch (cg_type) { 2966746cc85STrevor Wu case MT8195_TOP_CG_A1SYS_TIMING: 2976746cc85STrevor Wu case MT8195_TOP_CG_A2SYS_TIMING: 2986746cc85STrevor Wu case MT8195_TOP_CG_26M_TIMING: 2996746cc85STrevor Wu return 0; 3006746cc85STrevor Wu default: 3016746cc85STrevor Wu return get_top_cg_mask(cg_type); 3026746cc85STrevor Wu } 3036746cc85STrevor Wu } 3046746cc85STrevor Wu 3056746cc85STrevor Wu static int mt8195_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type) 3066746cc85STrevor Wu { 3076746cc85STrevor Wu unsigned int reg = get_top_cg_reg(cg_type); 3086746cc85STrevor Wu unsigned int mask = get_top_cg_mask(cg_type); 3096746cc85STrevor Wu unsigned int val = get_top_cg_on_val(cg_type); 3106746cc85STrevor Wu 3116746cc85STrevor Wu regmap_update_bits(afe->regmap, reg, mask, val); 3126746cc85STrevor Wu return 0; 3136746cc85STrevor Wu } 3146746cc85STrevor Wu 3156746cc85STrevor Wu static int mt8195_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type) 3166746cc85STrevor Wu { 3176746cc85STrevor Wu unsigned int reg = get_top_cg_reg(cg_type); 3186746cc85STrevor Wu unsigned int mask = get_top_cg_mask(cg_type); 3196746cc85STrevor Wu unsigned int val = get_top_cg_off_val(cg_type); 3206746cc85STrevor Wu 3216746cc85STrevor Wu regmap_update_bits(afe->regmap, reg, mask, val); 3226746cc85STrevor Wu return 0; 3236746cc85STrevor Wu } 3246746cc85STrevor Wu 3256746cc85STrevor Wu int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe) 3266746cc85STrevor Wu { 3276746cc85STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 3286746cc85STrevor Wu int i; 329*91745b03SColin Ian King static const unsigned int clk_array[] = { 3306746cc85STrevor Wu MT8195_CLK_SCP_ADSP_AUDIODSP, /* bus clock for infra */ 3316746cc85STrevor Wu MT8195_CLK_TOP_AUDIO_H_SEL, /* clock for ADSP bus */ 3326746cc85STrevor Wu MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL, /* bus clock for DRAM access */ 3336746cc85STrevor Wu MT8195_CLK_TOP_AUD_INTBUS_SEL, /* bus clock for AFE SRAM access */ 3346746cc85STrevor Wu MT8195_CLK_INFRA_AO_AUDIO_26M_B, /* audio 26M clock */ 3356746cc85STrevor Wu MT8195_CLK_AUD_AFE, /* AFE HW master switch */ 3366746cc85STrevor Wu MT8195_CLK_AUD_A1SYS_HP, /* AFE HW clock*/ 3376746cc85STrevor Wu MT8195_CLK_AUD_A1SYS, /* AFE HW clock */ 3386746cc85STrevor Wu }; 3396746cc85STrevor Wu 3406746cc85STrevor Wu for (i = 0; i < ARRAY_SIZE(clk_array); i++) 3416746cc85STrevor Wu mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]); 3426746cc85STrevor Wu 3436746cc85STrevor Wu return 0; 3446746cc85STrevor Wu } 3456746cc85STrevor Wu 3466746cc85STrevor Wu int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe) 3476746cc85STrevor Wu { 3486746cc85STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 3496746cc85STrevor Wu int i; 350*91745b03SColin Ian King static const unsigned int clk_array[] = { 3516746cc85STrevor Wu MT8195_CLK_AUD_A1SYS, 3526746cc85STrevor Wu MT8195_CLK_AUD_A1SYS_HP, 3536746cc85STrevor Wu MT8195_CLK_AUD_AFE, 3546746cc85STrevor Wu MT8195_CLK_INFRA_AO_AUDIO_26M_B, 3556746cc85STrevor Wu MT8195_CLK_TOP_AUD_INTBUS_SEL, 3566746cc85STrevor Wu MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL, 3576746cc85STrevor Wu MT8195_CLK_TOP_AUDIO_H_SEL, 3586746cc85STrevor Wu MT8195_CLK_SCP_ADSP_AUDIODSP, 3596746cc85STrevor Wu }; 3606746cc85STrevor Wu 3616746cc85STrevor Wu for (i = 0; i < ARRAY_SIZE(clk_array); i++) 3626746cc85STrevor Wu mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]); 3636746cc85STrevor Wu 3646746cc85STrevor Wu return 0; 3656746cc85STrevor Wu } 3666746cc85STrevor Wu 3676746cc85STrevor Wu static int mt8195_afe_enable_afe_on(struct mtk_base_afe *afe) 3686746cc85STrevor Wu { 3696746cc85STrevor Wu regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1); 3706746cc85STrevor Wu return 0; 3716746cc85STrevor Wu } 3726746cc85STrevor Wu 3736746cc85STrevor Wu static int mt8195_afe_disable_afe_on(struct mtk_base_afe *afe) 3746746cc85STrevor Wu { 3756746cc85STrevor Wu regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0); 3766746cc85STrevor Wu return 0; 3776746cc85STrevor Wu } 3786746cc85STrevor Wu 3796746cc85STrevor Wu static int mt8195_afe_enable_timing_sys(struct mtk_base_afe *afe) 3806746cc85STrevor Wu { 3816746cc85STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 3826746cc85STrevor Wu int i; 383*91745b03SColin Ian King static const unsigned int clk_array[] = { 3846746cc85STrevor Wu MT8195_CLK_AUD_A1SYS, 3856746cc85STrevor Wu MT8195_CLK_AUD_A2SYS, 3866746cc85STrevor Wu }; 387*91745b03SColin Ian King static const unsigned int cg_array[] = { 3886746cc85STrevor Wu MT8195_TOP_CG_A1SYS_TIMING, 3896746cc85STrevor Wu MT8195_TOP_CG_A2SYS_TIMING, 3906746cc85STrevor Wu MT8195_TOP_CG_26M_TIMING, 3916746cc85STrevor Wu }; 3926746cc85STrevor Wu 3936746cc85STrevor Wu for (i = 0; i < ARRAY_SIZE(clk_array); i++) 3946746cc85STrevor Wu mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]); 3956746cc85STrevor Wu 3966746cc85STrevor Wu for (i = 0; i < ARRAY_SIZE(cg_array); i++) 3976746cc85STrevor Wu mt8195_afe_enable_top_cg(afe, cg_array[i]); 3986746cc85STrevor Wu 3996746cc85STrevor Wu return 0; 4006746cc85STrevor Wu } 4016746cc85STrevor Wu 4026746cc85STrevor Wu static int mt8195_afe_disable_timing_sys(struct mtk_base_afe *afe) 4036746cc85STrevor Wu { 4046746cc85STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 4056746cc85STrevor Wu int i; 406*91745b03SColin Ian King static const unsigned int clk_array[] = { 4076746cc85STrevor Wu MT8195_CLK_AUD_A2SYS, 4086746cc85STrevor Wu MT8195_CLK_AUD_A1SYS, 4096746cc85STrevor Wu }; 410*91745b03SColin Ian King static const unsigned int cg_array[] = { 4116746cc85STrevor Wu MT8195_TOP_CG_26M_TIMING, 4126746cc85STrevor Wu MT8195_TOP_CG_A2SYS_TIMING, 4136746cc85STrevor Wu MT8195_TOP_CG_A1SYS_TIMING, 4146746cc85STrevor Wu }; 4156746cc85STrevor Wu 4166746cc85STrevor Wu for (i = 0; i < ARRAY_SIZE(cg_array); i++) 4176746cc85STrevor Wu mt8195_afe_disable_top_cg(afe, cg_array[i]); 4186746cc85STrevor Wu 4196746cc85STrevor Wu for (i = 0; i < ARRAY_SIZE(clk_array); i++) 4206746cc85STrevor Wu mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]); 4216746cc85STrevor Wu 4226746cc85STrevor Wu return 0; 4236746cc85STrevor Wu } 4246746cc85STrevor Wu 4256746cc85STrevor Wu int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe) 4266746cc85STrevor Wu { 4276746cc85STrevor Wu mt8195_afe_enable_timing_sys(afe); 4286746cc85STrevor Wu 4296746cc85STrevor Wu mt8195_afe_enable_afe_on(afe); 4306746cc85STrevor Wu 4316746cc85STrevor Wu return 0; 4326746cc85STrevor Wu } 4336746cc85STrevor Wu 4346746cc85STrevor Wu int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe) 4356746cc85STrevor Wu { 4366746cc85STrevor Wu mt8195_afe_disable_afe_on(afe); 4376746cc85STrevor Wu 4386746cc85STrevor Wu mt8195_afe_disable_timing_sys(afe); 4396746cc85STrevor Wu 4406746cc85STrevor Wu return 0; 4416746cc85STrevor Wu } 442