1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // MediaTek ALSA SoC Audio DAI I2S Control 4 // 5 // Copyright (c) 2020 MediaTek Inc. 6 // Author: Shane Chien <shane.chien@mediatek.com> 7 // 8 9 #include <linux/bitops.h> 10 #include <linux/regmap.h> 11 #include <sound/pcm_params.h> 12 13 #include "mt8192-afe-clk.h" 14 #include "mt8192-afe-common.h" 15 #include "mt8192-afe-gpio.h" 16 #include "mt8192-interconnection.h" 17 18 enum { 19 I2S_FMT_EIAJ = 0, 20 I2S_FMT_I2S = 1, 21 }; 22 23 enum { 24 I2S_WLEN_16_BIT = 0, 25 I2S_WLEN_32_BIT = 1, 26 }; 27 28 enum { 29 I2S_HD_NORMAL = 0, 30 I2S_HD_LOW_JITTER = 1, 31 }; 32 33 enum { 34 I2S1_SEL_O28_O29 = 0, 35 I2S1_SEL_O03_O04 = 1, 36 }; 37 38 enum { 39 I2S_IN_PAD_CONNSYS = 0, 40 I2S_IN_PAD_IO_MUX = 1, 41 }; 42 43 struct mtk_afe_i2s_priv { 44 int id; 45 int rate; /* for determine which apll to use */ 46 int low_jitter_en; 47 48 int share_i2s_id; 49 50 int mclk_id; 51 int mclk_rate; 52 int mclk_apll; 53 }; 54 55 static unsigned int get_i2s_wlen(snd_pcm_format_t format) 56 { 57 return snd_pcm_format_physical_width(format) <= 16 ? 58 I2S_WLEN_16_BIT : I2S_WLEN_32_BIT; 59 } 60 61 #define MTK_AFE_I2S0_KCONTROL_NAME "I2S0_HD_Mux" 62 #define MTK_AFE_I2S1_KCONTROL_NAME "I2S1_HD_Mux" 63 #define MTK_AFE_I2S2_KCONTROL_NAME "I2S2_HD_Mux" 64 #define MTK_AFE_I2S3_KCONTROL_NAME "I2S3_HD_Mux" 65 #define MTK_AFE_I2S5_KCONTROL_NAME "I2S5_HD_Mux" 66 #define MTK_AFE_I2S6_KCONTROL_NAME "I2S6_HD_Mux" 67 #define MTK_AFE_I2S7_KCONTROL_NAME "I2S7_HD_Mux" 68 #define MTK_AFE_I2S8_KCONTROL_NAME "I2S8_HD_Mux" 69 #define MTK_AFE_I2S9_KCONTROL_NAME "I2S9_HD_Mux" 70 71 #define I2S0_HD_EN_W_NAME "I2S0_HD_EN" 72 #define I2S1_HD_EN_W_NAME "I2S1_HD_EN" 73 #define I2S2_HD_EN_W_NAME "I2S2_HD_EN" 74 #define I2S3_HD_EN_W_NAME "I2S3_HD_EN" 75 #define I2S5_HD_EN_W_NAME "I2S5_HD_EN" 76 #define I2S6_HD_EN_W_NAME "I2S6_HD_EN" 77 #define I2S7_HD_EN_W_NAME "I2S7_HD_EN" 78 #define I2S8_HD_EN_W_NAME "I2S8_HD_EN" 79 #define I2S9_HD_EN_W_NAME "I2S9_HD_EN" 80 81 #define I2S0_MCLK_EN_W_NAME "I2S0_MCLK_EN" 82 #define I2S1_MCLK_EN_W_NAME "I2S1_MCLK_EN" 83 #define I2S2_MCLK_EN_W_NAME "I2S2_MCLK_EN" 84 #define I2S3_MCLK_EN_W_NAME "I2S3_MCLK_EN" 85 #define I2S5_MCLK_EN_W_NAME "I2S5_MCLK_EN" 86 #define I2S6_MCLK_EN_W_NAME "I2S6_MCLK_EN" 87 #define I2S7_MCLK_EN_W_NAME "I2S7_MCLK_EN" 88 #define I2S8_MCLK_EN_W_NAME "I2S8_MCLK_EN" 89 #define I2S9_MCLK_EN_W_NAME "I2S9_MCLK_EN" 90 91 static int get_i2s_id_by_name(struct mtk_base_afe *afe, 92 const char *name) 93 { 94 if (strncmp(name, "I2S0", 4) == 0) 95 return MT8192_DAI_I2S_0; 96 else if (strncmp(name, "I2S1", 4) == 0) 97 return MT8192_DAI_I2S_1; 98 else if (strncmp(name, "I2S2", 4) == 0) 99 return MT8192_DAI_I2S_2; 100 else if (strncmp(name, "I2S3", 4) == 0) 101 return MT8192_DAI_I2S_3; 102 else if (strncmp(name, "I2S5", 4) == 0) 103 return MT8192_DAI_I2S_5; 104 else if (strncmp(name, "I2S6", 4) == 0) 105 return MT8192_DAI_I2S_6; 106 else if (strncmp(name, "I2S7", 4) == 0) 107 return MT8192_DAI_I2S_7; 108 else if (strncmp(name, "I2S8", 4) == 0) 109 return MT8192_DAI_I2S_8; 110 else if (strncmp(name, "I2S9", 4) == 0) 111 return MT8192_DAI_I2S_9; 112 else 113 return -EINVAL; 114 } 115 116 static struct mtk_afe_i2s_priv *get_i2s_priv_by_name(struct mtk_base_afe *afe, 117 const char *name) 118 { 119 struct mt8192_afe_private *afe_priv = afe->platform_priv; 120 int dai_id = get_i2s_id_by_name(afe, name); 121 122 if (dai_id < 0) 123 return NULL; 124 125 return afe_priv->dai_priv[dai_id]; 126 } 127 128 /* low jitter control */ 129 static const char * const mt8192_i2s_hd_str[] = { 130 "Normal", "Low_Jitter" 131 }; 132 133 static SOC_ENUM_SINGLE_EXT_DECL(mt8192_i2s_enum, mt8192_i2s_hd_str); 134 135 static int mt8192_i2s_hd_get(struct snd_kcontrol *kcontrol, 136 struct snd_ctl_elem_value *ucontrol) 137 { 138 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 139 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 140 struct mtk_afe_i2s_priv *i2s_priv; 141 142 i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name); 143 144 if (!i2s_priv) { 145 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__); 146 return -EINVAL; 147 } 148 149 ucontrol->value.integer.value[0] = i2s_priv->low_jitter_en; 150 151 return 0; 152 } 153 154 static int mt8192_i2s_hd_set(struct snd_kcontrol *kcontrol, 155 struct snd_ctl_elem_value *ucontrol) 156 { 157 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 158 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 159 struct mtk_afe_i2s_priv *i2s_priv; 160 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 161 int hd_en; 162 163 if (ucontrol->value.enumerated.item[0] >= e->items) 164 return -EINVAL; 165 166 hd_en = ucontrol->value.integer.value[0]; 167 168 dev_dbg(afe->dev, "%s(), kcontrol name %s, hd_en %d\n", 169 __func__, kcontrol->id.name, hd_en); 170 171 i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name); 172 173 if (!i2s_priv) { 174 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__); 175 return -EINVAL; 176 } 177 178 i2s_priv->low_jitter_en = hd_en; 179 180 return 0; 181 } 182 183 static const struct snd_kcontrol_new mtk_dai_i2s_controls[] = { 184 SOC_ENUM_EXT(MTK_AFE_I2S0_KCONTROL_NAME, mt8192_i2s_enum, 185 mt8192_i2s_hd_get, mt8192_i2s_hd_set), 186 SOC_ENUM_EXT(MTK_AFE_I2S1_KCONTROL_NAME, mt8192_i2s_enum, 187 mt8192_i2s_hd_get, mt8192_i2s_hd_set), 188 SOC_ENUM_EXT(MTK_AFE_I2S2_KCONTROL_NAME, mt8192_i2s_enum, 189 mt8192_i2s_hd_get, mt8192_i2s_hd_set), 190 SOC_ENUM_EXT(MTK_AFE_I2S3_KCONTROL_NAME, mt8192_i2s_enum, 191 mt8192_i2s_hd_get, mt8192_i2s_hd_set), 192 SOC_ENUM_EXT(MTK_AFE_I2S5_KCONTROL_NAME, mt8192_i2s_enum, 193 mt8192_i2s_hd_get, mt8192_i2s_hd_set), 194 SOC_ENUM_EXT(MTK_AFE_I2S6_KCONTROL_NAME, mt8192_i2s_enum, 195 mt8192_i2s_hd_get, mt8192_i2s_hd_set), 196 SOC_ENUM_EXT(MTK_AFE_I2S7_KCONTROL_NAME, mt8192_i2s_enum, 197 mt8192_i2s_hd_get, mt8192_i2s_hd_set), 198 SOC_ENUM_EXT(MTK_AFE_I2S8_KCONTROL_NAME, mt8192_i2s_enum, 199 mt8192_i2s_hd_get, mt8192_i2s_hd_set), 200 SOC_ENUM_EXT(MTK_AFE_I2S9_KCONTROL_NAME, mt8192_i2s_enum, 201 mt8192_i2s_hd_get, mt8192_i2s_hd_set), 202 }; 203 204 /* dai component */ 205 /* i2s virtual mux to output widget */ 206 static const char * const i2s_mux_map[] = { 207 "Normal", "Dummy_Widget", 208 }; 209 210 static int i2s_mux_map_value[] = { 211 0, 1, 212 }; 213 214 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s_mux_map_enum, 215 SND_SOC_NOPM, 216 0, 217 1, 218 i2s_mux_map, 219 i2s_mux_map_value); 220 221 static const struct snd_kcontrol_new i2s0_in_mux_control = 222 SOC_DAPM_ENUM("I2S0 In Select", i2s_mux_map_enum); 223 224 static const struct snd_kcontrol_new i2s8_in_mux_control = 225 SOC_DAPM_ENUM("I2S8 In Select", i2s_mux_map_enum); 226 227 static const struct snd_kcontrol_new i2s1_out_mux_control = 228 SOC_DAPM_ENUM("I2S1 Out Select", i2s_mux_map_enum); 229 230 static const struct snd_kcontrol_new i2s3_out_mux_control = 231 SOC_DAPM_ENUM("I2S3 Out Select", i2s_mux_map_enum); 232 233 static const struct snd_kcontrol_new i2s5_out_mux_control = 234 SOC_DAPM_ENUM("I2S5 Out Select", i2s_mux_map_enum); 235 236 static const struct snd_kcontrol_new i2s7_out_mux_control = 237 SOC_DAPM_ENUM("I2S7 Out Select", i2s_mux_map_enum); 238 239 static const struct snd_kcontrol_new i2s9_out_mux_control = 240 SOC_DAPM_ENUM("I2S9 Out Select", i2s_mux_map_enum); 241 242 /* Tinyconn Mux */ 243 enum { 244 TINYCONN_CH1_MUX_DL1 = 0x0, 245 TINYCONN_CH2_MUX_DL1 = 0x1, 246 TINYCONN_CH1_MUX_DL12 = 0x2, 247 TINYCONN_CH2_MUX_DL12 = 0x3, 248 TINYCONN_CH1_MUX_DL2 = 0x4, 249 TINYCONN_CH2_MUX_DL2 = 0x5, 250 TINYCONN_CH1_MUX_DL3 = 0x6, 251 TINYCONN_CH2_MUX_DL3 = 0x7, 252 TINYCONN_MUX_NONE = 0x1f, 253 }; 254 255 static const char * const tinyconn_mux_map[] = { 256 "NONE", 257 "DL1_CH1", 258 "DL1_CH2", 259 "DL12_CH1", 260 "DL12_CH2", 261 "DL2_CH1", 262 "DL2_CH2", 263 "DL3_CH1", 264 "DL3_CH2", 265 }; 266 267 static int tinyconn_mux_map_value[] = { 268 TINYCONN_MUX_NONE, 269 TINYCONN_CH1_MUX_DL1, 270 TINYCONN_CH2_MUX_DL1, 271 TINYCONN_CH1_MUX_DL12, 272 TINYCONN_CH2_MUX_DL12, 273 TINYCONN_CH1_MUX_DL2, 274 TINYCONN_CH2_MUX_DL2, 275 TINYCONN_CH1_MUX_DL3, 276 TINYCONN_CH2_MUX_DL3, 277 }; 278 279 static SOC_VALUE_ENUM_SINGLE_DECL(i2s1_tinyconn_ch1_mux_map_enum, 280 AFE_TINY_CONN5, 281 O_20_CFG_SFT, 282 O_20_CFG_MASK, 283 tinyconn_mux_map, 284 tinyconn_mux_map_value); 285 static const struct snd_kcontrol_new i2s1_tinyconn_ch1_mux_control = 286 SOC_DAPM_ENUM("i2s1 ch1 tinyconn Select", 287 i2s1_tinyconn_ch1_mux_map_enum); 288 289 static SOC_VALUE_ENUM_SINGLE_DECL(i2s1_tinyconn_ch2_mux_map_enum, 290 AFE_TINY_CONN5, 291 O_21_CFG_SFT, 292 O_21_CFG_MASK, 293 tinyconn_mux_map, 294 tinyconn_mux_map_value); 295 static const struct snd_kcontrol_new i2s1_tinyconn_ch2_mux_control = 296 SOC_DAPM_ENUM("i2s1 ch2 tinyconn Select", 297 i2s1_tinyconn_ch2_mux_map_enum); 298 299 static SOC_VALUE_ENUM_SINGLE_DECL(i2s3_tinyconn_ch1_mux_map_enum, 300 AFE_TINY_CONN5, 301 O_22_CFG_SFT, 302 O_22_CFG_MASK, 303 tinyconn_mux_map, 304 tinyconn_mux_map_value); 305 static const struct snd_kcontrol_new i2s3_tinyconn_ch1_mux_control = 306 SOC_DAPM_ENUM("i2s3 ch1 tinyconn Select", 307 i2s3_tinyconn_ch1_mux_map_enum); 308 309 static SOC_VALUE_ENUM_SINGLE_DECL(i2s3_tinyconn_ch2_mux_map_enum, 310 AFE_TINY_CONN5, 311 O_23_CFG_SFT, 312 O_23_CFG_MASK, 313 tinyconn_mux_map, 314 tinyconn_mux_map_value); 315 static const struct snd_kcontrol_new i2s3_tinyconn_ch2_mux_control = 316 SOC_DAPM_ENUM("i2s3 ch2 tinyconn Select", 317 i2s3_tinyconn_ch2_mux_map_enum); 318 319 /* i2s in lpbk */ 320 static const char * const i2s_lpbk_mux_map[] = { 321 "Normal", "Lpbk", 322 }; 323 324 static int i2s_lpbk_mux_map_value[] = { 325 0, 1, 326 }; 327 328 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s0_lpbk_mux_map_enum, 329 AFE_I2S_CON, 330 I2S_LOOPBACK_SFT, 331 1, 332 i2s_lpbk_mux_map, 333 i2s_lpbk_mux_map_value); 334 335 static const struct snd_kcontrol_new i2s0_lpbk_mux_control = 336 SOC_DAPM_ENUM("I2S Lpbk Select", i2s0_lpbk_mux_map_enum); 337 338 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s2_lpbk_mux_map_enum, 339 AFE_I2S_CON2, 340 I2S3_LOOPBACK_SFT, 341 1, 342 i2s_lpbk_mux_map, 343 i2s_lpbk_mux_map_value); 344 345 static const struct snd_kcontrol_new i2s2_lpbk_mux_control = 346 SOC_DAPM_ENUM("I2S Lpbk Select", i2s2_lpbk_mux_map_enum); 347 348 /* interconnection */ 349 static const struct snd_kcontrol_new mtk_i2s3_ch1_mix[] = { 350 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN0, I_DL1_CH1, 1, 0), 351 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN0, I_DL2_CH1, 1, 0), 352 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN0, I_DL3_CH1, 1, 0), 353 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN0, I_DL12_CH1, 1, 0), 354 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN0_1, I_DL6_CH1, 1, 0), 355 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN0_1, I_DL4_CH1, 1, 0), 356 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN0_1, I_DL5_CH1, 1, 0), 357 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN0_1, I_DL8_CH1, 1, 0), 358 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH1", AFE_CONN0_1, I_DL9_CH1, 1, 0), 359 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN0, 360 I_GAIN1_OUT_CH1, 1, 0), 361 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN0, 362 I_ADDA_UL_CH1, 1, 0), 363 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN0, 364 I_ADDA_UL_CH2, 1, 0), 365 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN0, 366 I_ADDA_UL_CH3, 1, 0), 367 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN0, 368 I_PCM_1_CAP_CH1, 1, 0), 369 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN0, 370 I_PCM_2_CAP_CH1, 1, 0), 371 }; 372 373 static const struct snd_kcontrol_new mtk_i2s3_ch2_mix[] = { 374 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN1, I_DL1_CH2, 1, 0), 375 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN1, I_DL2_CH2, 1, 0), 376 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN1, I_DL3_CH2, 1, 0), 377 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN1, I_DL12_CH2, 1, 0), 378 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN1_1, I_DL6_CH2, 1, 0), 379 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN1_1, I_DL4_CH2, 1, 0), 380 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN1_1, I_DL5_CH2, 1, 0), 381 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN1_1, I_DL8_CH2, 1, 0), 382 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH2", AFE_CONN1_1, I_DL9_CH2, 1, 0), 383 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN1, 384 I_GAIN1_OUT_CH2, 1, 0), 385 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN1, 386 I_ADDA_UL_CH1, 1, 0), 387 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN1, 388 I_ADDA_UL_CH2, 1, 0), 389 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN1, 390 I_ADDA_UL_CH3, 1, 0), 391 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN1, 392 I_PCM_1_CAP_CH1, 1, 0), 393 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN1, 394 I_PCM_2_CAP_CH1, 1, 0), 395 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN1, 396 I_PCM_1_CAP_CH2, 1, 0), 397 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN1, 398 I_PCM_2_CAP_CH2, 1, 0), 399 }; 400 401 static const struct snd_kcontrol_new mtk_i2s1_ch1_mix[] = { 402 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN28, I_DL1_CH1, 1, 0), 403 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN28, I_DL2_CH1, 1, 0), 404 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN28, I_DL3_CH1, 1, 0), 405 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN28, I_DL12_CH1, 1, 0), 406 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN28_1, I_DL6_CH1, 1, 0), 407 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN28_1, I_DL4_CH1, 1, 0), 408 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN28_1, I_DL5_CH1, 1, 0), 409 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN28_1, I_DL8_CH1, 1, 0), 410 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH1", AFE_CONN28_1, I_DL9_CH1, 1, 0), 411 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN28, 412 I_GAIN1_OUT_CH1, 1, 0), 413 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN28, 414 I_ADDA_UL_CH1, 1, 0), 415 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN28, 416 I_PCM_1_CAP_CH1, 1, 0), 417 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN28, 418 I_PCM_2_CAP_CH1, 1, 0), 419 }; 420 421 static const struct snd_kcontrol_new mtk_i2s1_ch2_mix[] = { 422 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN29, I_DL1_CH2, 1, 0), 423 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN29, I_DL2_CH2, 1, 0), 424 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN29, I_DL3_CH2, 1, 0), 425 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN29, I_DL12_CH2, 1, 0), 426 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN29_1, I_DL6_CH2, 1, 0), 427 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN29_1, I_DL4_CH2, 1, 0), 428 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN29_1, I_DL5_CH2, 1, 0), 429 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN29_1, I_DL8_CH2, 1, 0), 430 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH2", AFE_CONN29_1, I_DL9_CH2, 1, 0), 431 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN29, 432 I_GAIN1_OUT_CH2, 1, 0), 433 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN29, 434 I_ADDA_UL_CH2, 1, 0), 435 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN29, 436 I_PCM_1_CAP_CH1, 1, 0), 437 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN29, 438 I_PCM_2_CAP_CH1, 1, 0), 439 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN29, 440 I_PCM_1_CAP_CH2, 1, 0), 441 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN29, 442 I_PCM_2_CAP_CH2, 1, 0), 443 }; 444 445 static const struct snd_kcontrol_new mtk_i2s5_ch1_mix[] = { 446 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN30, I_DL1_CH1, 1, 0), 447 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN30, I_DL2_CH1, 1, 0), 448 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN30, I_DL3_CH1, 1, 0), 449 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN30, I_DL12_CH1, 1, 0), 450 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN30_1, I_DL6_CH1, 1, 0), 451 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN30_1, I_DL4_CH1, 1, 0), 452 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN30_1, I_DL5_CH1, 1, 0), 453 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN30_1, I_DL8_CH1, 1, 0), 454 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH1", AFE_CONN30_1, I_DL9_CH1, 1, 0), 455 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN30, 456 I_GAIN1_OUT_CH1, 1, 0), 457 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN30, 458 I_ADDA_UL_CH1, 1, 0), 459 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN30, 460 I_PCM_1_CAP_CH1, 1, 0), 461 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN30, 462 I_PCM_2_CAP_CH1, 1, 0), 463 }; 464 465 static const struct snd_kcontrol_new mtk_i2s5_ch2_mix[] = { 466 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN31, I_DL1_CH2, 1, 0), 467 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN31, I_DL2_CH2, 1, 0), 468 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN31, I_DL3_CH2, 1, 0), 469 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN31, I_DL12_CH2, 1, 0), 470 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN31_1, I_DL6_CH2, 1, 0), 471 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN31_1, I_DL4_CH2, 1, 0), 472 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN31_1, I_DL5_CH2, 1, 0), 473 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN31_1, I_DL8_CH2, 1, 0), 474 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH2", AFE_CONN31_1, I_DL9_CH2, 1, 0), 475 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN31, 476 I_GAIN1_OUT_CH2, 1, 0), 477 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN31, 478 I_ADDA_UL_CH2, 1, 0), 479 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN31, 480 I_PCM_1_CAP_CH1, 1, 0), 481 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN31, 482 I_PCM_2_CAP_CH1, 1, 0), 483 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN31, 484 I_PCM_1_CAP_CH2, 1, 0), 485 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN31, 486 I_PCM_2_CAP_CH2, 1, 0), 487 }; 488 489 static const struct snd_kcontrol_new mtk_i2s7_ch1_mix[] = { 490 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN54, I_DL1_CH1, 1, 0), 491 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN54, I_DL2_CH1, 1, 0), 492 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN54, I_DL3_CH1, 1, 0), 493 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN54, I_DL12_CH1, 1, 0), 494 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN54_1, I_DL6_CH1, 1, 0), 495 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN54_1, I_DL4_CH1, 1, 0), 496 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN54_1, I_DL5_CH1, 1, 0), 497 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH1", AFE_CONN54_1, I_DL9_CH1, 1, 0), 498 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN54, 499 I_GAIN1_OUT_CH1, 1, 0), 500 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN54, 501 I_ADDA_UL_CH1, 1, 0), 502 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN54, 503 I_PCM_1_CAP_CH1, 1, 0), 504 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN54, 505 I_PCM_2_CAP_CH1, 1, 0), 506 }; 507 508 static const struct snd_kcontrol_new mtk_i2s7_ch2_mix[] = { 509 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN55, I_DL1_CH2, 1, 0), 510 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN55, I_DL2_CH2, 1, 0), 511 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN55, I_DL3_CH2, 1, 0), 512 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN55, I_DL12_CH2, 1, 0), 513 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN55_1, I_DL6_CH2, 1, 0), 514 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN55_1, I_DL4_CH2, 1, 0), 515 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN55_1, I_DL5_CH2, 1, 0), 516 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH2", AFE_CONN55_1, I_DL9_CH2, 1, 0), 517 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN55, 518 I_GAIN1_OUT_CH2, 1, 0), 519 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN55, 520 I_ADDA_UL_CH2, 1, 0), 521 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN55, 522 I_PCM_1_CAP_CH1, 1, 0), 523 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN55, 524 I_PCM_2_CAP_CH1, 1, 0), 525 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN55, 526 I_PCM_1_CAP_CH2, 1, 0), 527 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN55, 528 I_PCM_2_CAP_CH2, 1, 0), 529 }; 530 531 static const struct snd_kcontrol_new mtk_i2s9_ch1_mix[] = { 532 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN56, I_DL1_CH1, 1, 0), 533 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN56, I_DL2_CH1, 1, 0), 534 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN56, I_DL3_CH1, 1, 0), 535 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN56, I_DL12_CH1, 1, 0), 536 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN56_1, I_DL6_CH1, 1, 0), 537 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN56_1, I_DL4_CH1, 1, 0), 538 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN56_1, I_DL5_CH1, 1, 0), 539 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN56_1, I_DL8_CH1, 1, 0), 540 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH1", AFE_CONN56_1, I_DL9_CH1, 1, 0), 541 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN56, 542 I_GAIN1_OUT_CH1, 1, 0), 543 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN56, 544 I_ADDA_UL_CH1, 1, 0), 545 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN56, 546 I_PCM_1_CAP_CH1, 1, 0), 547 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN56, 548 I_PCM_2_CAP_CH1, 1, 0), 549 }; 550 551 static const struct snd_kcontrol_new mtk_i2s9_ch2_mix[] = { 552 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN57, I_DL1_CH2, 1, 0), 553 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN57, I_DL2_CH2, 1, 0), 554 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN57, I_DL3_CH2, 1, 0), 555 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN57, I_DL12_CH2, 1, 0), 556 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN57_1, I_DL6_CH2, 1, 0), 557 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN57_1, I_DL4_CH2, 1, 0), 558 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN57_1, I_DL5_CH2, 1, 0), 559 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN57_1, I_DL8_CH2, 1, 0), 560 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH2", AFE_CONN57_1, I_DL9_CH2, 1, 0), 561 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN57, 562 I_GAIN1_OUT_CH2, 1, 0), 563 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN57, 564 I_ADDA_UL_CH2, 1, 0), 565 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN57, 566 I_PCM_1_CAP_CH1, 1, 0), 567 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN57, 568 I_PCM_2_CAP_CH1, 1, 0), 569 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN57, 570 I_PCM_1_CAP_CH2, 1, 0), 571 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN57, 572 I_PCM_2_CAP_CH2, 1, 0), 573 }; 574 575 enum { 576 SUPPLY_SEQ_APLL, 577 SUPPLY_SEQ_I2S_MCLK_EN, 578 SUPPLY_SEQ_I2S_HD_EN, 579 SUPPLY_SEQ_I2S_EN, 580 }; 581 582 static int mtk_i2s_en_event(struct snd_soc_dapm_widget *w, 583 struct snd_kcontrol *kcontrol, 584 int event) 585 { 586 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 587 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 588 struct mtk_afe_i2s_priv *i2s_priv; 589 590 i2s_priv = get_i2s_priv_by_name(afe, w->name); 591 592 if (!i2s_priv) { 593 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__); 594 return -EINVAL; 595 } 596 597 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 598 __func__, w->name, event); 599 600 switch (event) { 601 case SND_SOC_DAPM_PRE_PMU: 602 mt8192_afe_gpio_request(afe->dev, true, i2s_priv->id, 0); 603 break; 604 case SND_SOC_DAPM_POST_PMD: 605 mt8192_afe_gpio_request(afe->dev, false, i2s_priv->id, 0); 606 break; 607 default: 608 break; 609 } 610 611 return 0; 612 } 613 614 static int mtk_apll_event(struct snd_soc_dapm_widget *w, 615 struct snd_kcontrol *kcontrol, 616 int event) 617 { 618 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 619 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 620 621 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 622 __func__, w->name, event); 623 624 switch (event) { 625 case SND_SOC_DAPM_PRE_PMU: 626 if (strcmp(w->name, APLL1_W_NAME) == 0) 627 mt8192_apll1_enable(afe); 628 else 629 mt8192_apll2_enable(afe); 630 break; 631 case SND_SOC_DAPM_POST_PMD: 632 if (strcmp(w->name, APLL1_W_NAME) == 0) 633 mt8192_apll1_disable(afe); 634 else 635 mt8192_apll2_disable(afe); 636 break; 637 default: 638 break; 639 } 640 641 return 0; 642 } 643 644 static int i2s_out_tinyconn_event(struct snd_soc_dapm_widget *w, 645 struct snd_kcontrol *kcontrol, 646 int event) 647 { 648 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 649 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 650 unsigned int reg; 651 unsigned int reg_shift; 652 unsigned int reg_mask_shift; 653 654 dev_dbg(afe->dev, "%s(), event 0x%x\n", __func__, event); 655 656 if (strstr(w->name, "I2S1")) { 657 reg = AFE_I2S_CON1; 658 reg_shift = I2S2_32BIT_EN_SFT; 659 reg_mask_shift = I2S2_32BIT_EN_MASK_SFT; 660 } else if (strstr(w->name, "I2S3")) { 661 reg = AFE_I2S_CON3; 662 reg_shift = I2S4_32BIT_EN_SFT; 663 reg_mask_shift = I2S4_32BIT_EN_MASK_SFT; 664 } else if (strstr(w->name, "I2S5")) { 665 reg = AFE_I2S_CON4; 666 reg_shift = I2S5_32BIT_EN_SFT; 667 reg_mask_shift = I2S5_32BIT_EN_MASK_SFT; 668 } else if (strstr(w->name, "I2S7")) { 669 reg = AFE_I2S_CON7; 670 reg_shift = I2S7_32BIT_EN_SFT; 671 reg_mask_shift = I2S7_32BIT_EN_MASK_SFT; 672 } else if (strstr(w->name, "I2S9")) { 673 reg = AFE_I2S_CON9; 674 reg_shift = I2S9_32BIT_EN_SFT; 675 reg_mask_shift = I2S9_32BIT_EN_MASK_SFT; 676 } else { 677 reg = AFE_I2S_CON1; 678 reg_shift = I2S2_32BIT_EN_SFT; 679 reg_mask_shift = I2S2_32BIT_EN_MASK_SFT; 680 dev_warn(afe->dev, "%s(), error widget name %s, use i2s1\n", 681 __func__, w->name); 682 } 683 684 switch (event) { 685 case SND_SOC_DAPM_PRE_PMU: 686 regmap_update_bits(afe->regmap, reg, reg_mask_shift, 687 0x1 << reg_shift); 688 break; 689 case SND_SOC_DAPM_PRE_PMD: 690 regmap_update_bits(afe->regmap, reg, reg_mask_shift, 691 0x0 << reg_shift); 692 break; 693 default: 694 break; 695 } 696 697 return 0; 698 } 699 700 static int mtk_mclk_en_event(struct snd_soc_dapm_widget *w, 701 struct snd_kcontrol *kcontrol, 702 int event) 703 { 704 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 705 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 706 struct mtk_afe_i2s_priv *i2s_priv; 707 708 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 709 __func__, w->name, event); 710 711 i2s_priv = get_i2s_priv_by_name(afe, w->name); 712 if (!i2s_priv) { 713 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__); 714 return -EINVAL; 715 } 716 717 switch (event) { 718 case SND_SOC_DAPM_PRE_PMU: 719 mt8192_mck_enable(afe, i2s_priv->mclk_id, i2s_priv->mclk_rate); 720 break; 721 case SND_SOC_DAPM_POST_PMD: 722 i2s_priv->mclk_rate = 0; 723 mt8192_mck_disable(afe, i2s_priv->mclk_id); 724 break; 725 default: 726 break; 727 } 728 729 return 0; 730 } 731 732 static const struct snd_soc_dapm_widget mtk_dai_i2s_widgets[] = { 733 SND_SOC_DAPM_INPUT("CONNSYS"), 734 735 SND_SOC_DAPM_MIXER("I2S1_CH1", SND_SOC_NOPM, 0, 0, 736 mtk_i2s1_ch1_mix, 737 ARRAY_SIZE(mtk_i2s1_ch1_mix)), 738 SND_SOC_DAPM_MIXER("I2S1_CH2", SND_SOC_NOPM, 0, 0, 739 mtk_i2s1_ch2_mix, 740 ARRAY_SIZE(mtk_i2s1_ch2_mix)), 741 742 SND_SOC_DAPM_MIXER("I2S3_CH1", SND_SOC_NOPM, 0, 0, 743 mtk_i2s3_ch1_mix, 744 ARRAY_SIZE(mtk_i2s3_ch1_mix)), 745 SND_SOC_DAPM_MIXER("I2S3_CH2", SND_SOC_NOPM, 0, 0, 746 mtk_i2s3_ch2_mix, 747 ARRAY_SIZE(mtk_i2s3_ch2_mix)), 748 749 SND_SOC_DAPM_MIXER("I2S5_CH1", SND_SOC_NOPM, 0, 0, 750 mtk_i2s5_ch1_mix, 751 ARRAY_SIZE(mtk_i2s5_ch1_mix)), 752 SND_SOC_DAPM_MIXER("I2S5_CH2", SND_SOC_NOPM, 0, 0, 753 mtk_i2s5_ch2_mix, 754 ARRAY_SIZE(mtk_i2s5_ch2_mix)), 755 756 SND_SOC_DAPM_MIXER("I2S7_CH1", SND_SOC_NOPM, 0, 0, 757 mtk_i2s7_ch1_mix, 758 ARRAY_SIZE(mtk_i2s7_ch1_mix)), 759 SND_SOC_DAPM_MIXER("I2S7_CH2", SND_SOC_NOPM, 0, 0, 760 mtk_i2s7_ch2_mix, 761 ARRAY_SIZE(mtk_i2s7_ch2_mix)), 762 763 SND_SOC_DAPM_MIXER("I2S9_CH1", SND_SOC_NOPM, 0, 0, 764 mtk_i2s9_ch1_mix, 765 ARRAY_SIZE(mtk_i2s9_ch1_mix)), 766 SND_SOC_DAPM_MIXER("I2S9_CH2", SND_SOC_NOPM, 0, 0, 767 mtk_i2s9_ch2_mix, 768 ARRAY_SIZE(mtk_i2s9_ch2_mix)), 769 770 SND_SOC_DAPM_MUX_E("I2S1_TINYCONN_CH1_MUX", SND_SOC_NOPM, 0, 0, 771 &i2s1_tinyconn_ch1_mux_control, 772 i2s_out_tinyconn_event, 773 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 774 SND_SOC_DAPM_MUX_E("I2S1_TINYCONN_CH2_MUX", SND_SOC_NOPM, 0, 0, 775 &i2s1_tinyconn_ch2_mux_control, 776 i2s_out_tinyconn_event, 777 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 778 SND_SOC_DAPM_MUX_E("I2S3_TINYCONN_CH1_MUX", SND_SOC_NOPM, 0, 0, 779 &i2s3_tinyconn_ch1_mux_control, 780 i2s_out_tinyconn_event, 781 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 782 SND_SOC_DAPM_MUX_E("I2S3_TINYCONN_CH2_MUX", SND_SOC_NOPM, 0, 0, 783 &i2s3_tinyconn_ch2_mux_control, 784 i2s_out_tinyconn_event, 785 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 786 787 /* i2s en*/ 788 SND_SOC_DAPM_SUPPLY_S("I2S0_EN", SUPPLY_SEQ_I2S_EN, 789 AFE_I2S_CON, I2S_EN_SFT, 0, 790 mtk_i2s_en_event, 791 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 792 SND_SOC_DAPM_SUPPLY_S("I2S1_EN", SUPPLY_SEQ_I2S_EN, 793 AFE_I2S_CON1, I2S_EN_SFT, 0, 794 mtk_i2s_en_event, 795 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 796 SND_SOC_DAPM_SUPPLY_S("I2S2_EN", SUPPLY_SEQ_I2S_EN, 797 AFE_I2S_CON2, I2S_EN_SFT, 0, 798 mtk_i2s_en_event, 799 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 800 SND_SOC_DAPM_SUPPLY_S("I2S3_EN", SUPPLY_SEQ_I2S_EN, 801 AFE_I2S_CON3, I2S_EN_SFT, 0, 802 mtk_i2s_en_event, 803 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 804 SND_SOC_DAPM_SUPPLY_S("I2S5_EN", SUPPLY_SEQ_I2S_EN, 805 AFE_I2S_CON4, I2S5_EN_SFT, 0, 806 mtk_i2s_en_event, 807 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 808 SND_SOC_DAPM_SUPPLY_S("I2S6_EN", SUPPLY_SEQ_I2S_EN, 809 AFE_I2S_CON6, I2S6_EN_SFT, 0, 810 mtk_i2s_en_event, 811 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 812 SND_SOC_DAPM_SUPPLY_S("I2S7_EN", SUPPLY_SEQ_I2S_EN, 813 AFE_I2S_CON7, I2S7_EN_SFT, 0, 814 mtk_i2s_en_event, 815 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 816 SND_SOC_DAPM_SUPPLY_S("I2S8_EN", SUPPLY_SEQ_I2S_EN, 817 AFE_I2S_CON8, I2S8_EN_SFT, 0, 818 mtk_i2s_en_event, 819 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 820 SND_SOC_DAPM_SUPPLY_S("I2S9_EN", SUPPLY_SEQ_I2S_EN, 821 AFE_I2S_CON9, I2S9_EN_SFT, 0, 822 mtk_i2s_en_event, 823 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 824 /* i2s hd en */ 825 SND_SOC_DAPM_SUPPLY_S(I2S0_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, 826 AFE_I2S_CON, I2S1_HD_EN_SFT, 0, NULL, 0), 827 SND_SOC_DAPM_SUPPLY_S(I2S1_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, 828 AFE_I2S_CON1, I2S2_HD_EN_SFT, 0, NULL, 0), 829 SND_SOC_DAPM_SUPPLY_S(I2S2_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, 830 AFE_I2S_CON2, I2S3_HD_EN_SFT, 0, NULL, 0), 831 SND_SOC_DAPM_SUPPLY_S(I2S3_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, 832 AFE_I2S_CON3, I2S4_HD_EN_SFT, 0, NULL, 0), 833 SND_SOC_DAPM_SUPPLY_S(I2S5_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, 834 AFE_I2S_CON4, I2S5_HD_EN_SFT, 0, NULL, 0), 835 SND_SOC_DAPM_SUPPLY_S(I2S6_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, 836 AFE_I2S_CON6, I2S6_HD_EN_SFT, 0, NULL, 0), 837 SND_SOC_DAPM_SUPPLY_S(I2S7_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, 838 AFE_I2S_CON7, I2S7_HD_EN_SFT, 0, NULL, 0), 839 SND_SOC_DAPM_SUPPLY_S(I2S8_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, 840 AFE_I2S_CON8, I2S8_HD_EN_SFT, 0, NULL, 0), 841 SND_SOC_DAPM_SUPPLY_S(I2S9_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, 842 AFE_I2S_CON9, I2S9_HD_EN_SFT, 0, NULL, 0), 843 844 /* i2s mclk en */ 845 SND_SOC_DAPM_SUPPLY_S(I2S0_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 846 SND_SOC_NOPM, 0, 0, 847 mtk_mclk_en_event, 848 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 849 SND_SOC_DAPM_SUPPLY_S(I2S1_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 850 SND_SOC_NOPM, 0, 0, 851 mtk_mclk_en_event, 852 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 853 SND_SOC_DAPM_SUPPLY_S(I2S2_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 854 SND_SOC_NOPM, 0, 0, 855 mtk_mclk_en_event, 856 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 857 SND_SOC_DAPM_SUPPLY_S(I2S3_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 858 SND_SOC_NOPM, 0, 0, 859 mtk_mclk_en_event, 860 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 861 SND_SOC_DAPM_SUPPLY_S(I2S5_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 862 SND_SOC_NOPM, 0, 0, 863 mtk_mclk_en_event, 864 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 865 SND_SOC_DAPM_SUPPLY_S(I2S6_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 866 SND_SOC_NOPM, 0, 0, 867 mtk_mclk_en_event, 868 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 869 SND_SOC_DAPM_SUPPLY_S(I2S7_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 870 SND_SOC_NOPM, 0, 0, 871 mtk_mclk_en_event, 872 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 873 SND_SOC_DAPM_SUPPLY_S(I2S8_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 874 SND_SOC_NOPM, 0, 0, 875 mtk_mclk_en_event, 876 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 877 SND_SOC_DAPM_SUPPLY_S(I2S9_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 878 SND_SOC_NOPM, 0, 0, 879 mtk_mclk_en_event, 880 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 881 882 /* apll */ 883 SND_SOC_DAPM_SUPPLY_S(APLL1_W_NAME, SUPPLY_SEQ_APLL, 884 SND_SOC_NOPM, 0, 0, 885 mtk_apll_event, 886 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 887 SND_SOC_DAPM_SUPPLY_S(APLL2_W_NAME, SUPPLY_SEQ_APLL, 888 SND_SOC_NOPM, 0, 0, 889 mtk_apll_event, 890 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 891 892 /* allow i2s on without codec on */ 893 SND_SOC_DAPM_OUTPUT("I2S_DUMMY_OUT"), 894 SND_SOC_DAPM_MUX("I2S1_Out_Mux", 895 SND_SOC_NOPM, 0, 0, &i2s1_out_mux_control), 896 SND_SOC_DAPM_MUX("I2S3_Out_Mux", 897 SND_SOC_NOPM, 0, 0, &i2s3_out_mux_control), 898 SND_SOC_DAPM_MUX("I2S5_Out_Mux", 899 SND_SOC_NOPM, 0, 0, &i2s5_out_mux_control), 900 SND_SOC_DAPM_MUX("I2S7_Out_Mux", 901 SND_SOC_NOPM, 0, 0, &i2s7_out_mux_control), 902 SND_SOC_DAPM_MUX("I2S9_Out_Mux", 903 SND_SOC_NOPM, 0, 0, &i2s9_out_mux_control), 904 905 SND_SOC_DAPM_INPUT("I2S_DUMMY_IN"), 906 SND_SOC_DAPM_MUX("I2S0_In_Mux", 907 SND_SOC_NOPM, 0, 0, &i2s0_in_mux_control), 908 SND_SOC_DAPM_MUX("I2S8_In_Mux", 909 SND_SOC_NOPM, 0, 0, &i2s8_in_mux_control), 910 911 /* i2s in lpbk */ 912 SND_SOC_DAPM_MUX("I2S0_Lpbk_Mux", 913 SND_SOC_NOPM, 0, 0, &i2s0_lpbk_mux_control), 914 SND_SOC_DAPM_MUX("I2S2_Lpbk_Mux", 915 SND_SOC_NOPM, 0, 0, &i2s2_lpbk_mux_control), 916 }; 917 918 static int mtk_afe_i2s_share_connect(struct snd_soc_dapm_widget *source, 919 struct snd_soc_dapm_widget *sink) 920 { 921 struct snd_soc_dapm_widget *w = sink; 922 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 923 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 924 struct mtk_afe_i2s_priv *i2s_priv; 925 926 i2s_priv = get_i2s_priv_by_name(afe, sink->name); 927 if (!i2s_priv) { 928 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__); 929 return 0; 930 } 931 932 if (i2s_priv->share_i2s_id < 0) 933 return 0; 934 935 return i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name); 936 } 937 938 static int mtk_afe_i2s_hd_connect(struct snd_soc_dapm_widget *source, 939 struct snd_soc_dapm_widget *sink) 940 { 941 struct snd_soc_dapm_widget *w = sink; 942 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 943 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 944 struct mtk_afe_i2s_priv *i2s_priv; 945 946 i2s_priv = get_i2s_priv_by_name(afe, sink->name); 947 if (!i2s_priv) { 948 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__); 949 return 0; 950 } 951 952 if (get_i2s_id_by_name(afe, sink->name) == 953 get_i2s_id_by_name(afe, source->name)) 954 return i2s_priv->low_jitter_en; 955 956 /* check if share i2s need hd en */ 957 if (i2s_priv->share_i2s_id < 0) 958 return 0; 959 960 if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name)) 961 return i2s_priv->low_jitter_en; 962 963 return 0; 964 } 965 966 static int mtk_afe_i2s_apll_connect(struct snd_soc_dapm_widget *source, 967 struct snd_soc_dapm_widget *sink) 968 { 969 struct snd_soc_dapm_widget *w = sink; 970 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 971 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 972 struct mtk_afe_i2s_priv *i2s_priv; 973 int cur_apll; 974 int i2s_need_apll; 975 976 i2s_priv = get_i2s_priv_by_name(afe, w->name); 977 if (!i2s_priv) { 978 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__); 979 return 0; 980 } 981 982 /* which apll */ 983 cur_apll = mt8192_get_apll_by_name(afe, source->name); 984 985 /* choose APLL from i2s rate */ 986 i2s_need_apll = mt8192_get_apll_by_rate(afe, i2s_priv->rate); 987 988 if (i2s_need_apll == cur_apll) 989 return 1; 990 991 return 0; 992 } 993 994 static int mtk_afe_i2s_mclk_connect(struct snd_soc_dapm_widget *source, 995 struct snd_soc_dapm_widget *sink) 996 { 997 struct snd_soc_dapm_widget *w = sink; 998 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 999 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 1000 struct mtk_afe_i2s_priv *i2s_priv; 1001 1002 i2s_priv = get_i2s_priv_by_name(afe, sink->name); 1003 if (!i2s_priv) { 1004 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__); 1005 return 0; 1006 } 1007 1008 if (get_i2s_id_by_name(afe, sink->name) == 1009 get_i2s_id_by_name(afe, source->name)) 1010 return (i2s_priv->mclk_rate > 0) ? 1 : 0; 1011 1012 /* check if share i2s need mclk */ 1013 if (i2s_priv->share_i2s_id < 0) 1014 return 0; 1015 1016 if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name)) 1017 return (i2s_priv->mclk_rate > 0) ? 1 : 0; 1018 1019 return 0; 1020 } 1021 1022 static int mtk_afe_mclk_apll_connect(struct snd_soc_dapm_widget *source, 1023 struct snd_soc_dapm_widget *sink) 1024 { 1025 struct snd_soc_dapm_widget *w = sink; 1026 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1027 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 1028 struct mtk_afe_i2s_priv *i2s_priv; 1029 int cur_apll; 1030 1031 i2s_priv = get_i2s_priv_by_name(afe, w->name); 1032 if (!i2s_priv) { 1033 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__); 1034 return 0; 1035 } 1036 1037 /* which apll */ 1038 cur_apll = mt8192_get_apll_by_name(afe, source->name); 1039 1040 if (i2s_priv->mclk_apll == cur_apll) 1041 return 1; 1042 1043 return 0; 1044 } 1045 1046 static const struct snd_soc_dapm_route mtk_dai_i2s_routes[] = { 1047 {"Connsys I2S", NULL, "CONNSYS"}, 1048 1049 /* i2s0 */ 1050 {"I2S0", NULL, "I2S0_EN"}, 1051 {"I2S0", NULL, "I2S1_EN", mtk_afe_i2s_share_connect}, 1052 {"I2S0", NULL, "I2S2_EN", mtk_afe_i2s_share_connect}, 1053 {"I2S0", NULL, "I2S3_EN", mtk_afe_i2s_share_connect}, 1054 {"I2S0", NULL, "I2S5_EN", mtk_afe_i2s_share_connect}, 1055 {"I2S0", NULL, "I2S6_EN", mtk_afe_i2s_share_connect}, 1056 {"I2S0", NULL, "I2S7_EN", mtk_afe_i2s_share_connect}, 1057 {"I2S0", NULL, "I2S8_EN", mtk_afe_i2s_share_connect}, 1058 {"I2S0", NULL, "I2S9_EN", mtk_afe_i2s_share_connect}, 1059 1060 {"I2S0", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1061 {"I2S0", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1062 {"I2S0", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1063 {"I2S0", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1064 {"I2S0", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1065 {"I2S0", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1066 {"I2S0", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1067 {"I2S0", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1068 {"I2S0", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1069 {I2S0_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1070 {I2S0_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1071 1072 {"I2S0", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1073 {"I2S0", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1074 {"I2S0", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1075 {"I2S0", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1076 {"I2S0", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1077 {"I2S0", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1078 {"I2S0", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1079 {"I2S0", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1080 {"I2S0", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1081 {I2S0_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1082 {I2S0_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1083 1084 /* i2s1 */ 1085 {"I2S1_CH1", "DL1_CH1", "DL1"}, 1086 {"I2S1_CH2", "DL1_CH2", "DL1"}, 1087 {"I2S1_TINYCONN_CH1_MUX", "DL1_CH1", "DL1"}, 1088 {"I2S1_TINYCONN_CH2_MUX", "DL1_CH2", "DL1"}, 1089 1090 {"I2S1_CH1", "DL2_CH1", "DL2"}, 1091 {"I2S1_CH2", "DL2_CH2", "DL2"}, 1092 {"I2S1_TINYCONN_CH1_MUX", "DL2_CH1", "DL2"}, 1093 {"I2S1_TINYCONN_CH2_MUX", "DL2_CH2", "DL2"}, 1094 1095 {"I2S1_CH1", "DL3_CH1", "DL3"}, 1096 {"I2S1_CH2", "DL3_CH2", "DL3"}, 1097 {"I2S1_TINYCONN_CH1_MUX", "DL3_CH1", "DL3"}, 1098 {"I2S1_TINYCONN_CH2_MUX", "DL3_CH2", "DL3"}, 1099 1100 {"I2S1_CH1", "DL12_CH1", "DL12"}, 1101 {"I2S1_CH2", "DL12_CH2", "DL12"}, 1102 {"I2S1_TINYCONN_CH1_MUX", "DL12_CH1", "DL12"}, 1103 {"I2S1_TINYCONN_CH2_MUX", "DL12_CH2", "DL12"}, 1104 1105 {"I2S1_CH1", "DL4_CH1", "DL4"}, 1106 {"I2S1_CH2", "DL4_CH2", "DL4"}, 1107 1108 {"I2S1_CH1", "DL5_CH1", "DL5"}, 1109 {"I2S1_CH2", "DL5_CH2", "DL5"}, 1110 1111 {"I2S1_CH1", "DL6_CH1", "DL6"}, 1112 {"I2S1_CH2", "DL6_CH2", "DL6"}, 1113 1114 {"I2S1_CH1", "DL8_CH1", "DL8"}, 1115 {"I2S1_CH2", "DL8_CH2", "DL8"}, 1116 1117 {"I2S1", NULL, "I2S1_CH1"}, 1118 {"I2S1", NULL, "I2S1_CH2"}, 1119 {"I2S1", NULL, "I2S3_TINYCONN_CH1_MUX"}, 1120 {"I2S1", NULL, "I2S3_TINYCONN_CH2_MUX"}, 1121 1122 {"I2S1", NULL, "I2S0_EN", mtk_afe_i2s_share_connect}, 1123 {"I2S1", NULL, "I2S1_EN"}, 1124 {"I2S1", NULL, "I2S2_EN", mtk_afe_i2s_share_connect}, 1125 {"I2S1", NULL, "I2S3_EN", mtk_afe_i2s_share_connect}, 1126 {"I2S1", NULL, "I2S5_EN", mtk_afe_i2s_share_connect}, 1127 {"I2S1", NULL, "I2S6_EN", mtk_afe_i2s_share_connect}, 1128 {"I2S1", NULL, "I2S7_EN", mtk_afe_i2s_share_connect}, 1129 {"I2S1", NULL, "I2S8_EN", mtk_afe_i2s_share_connect}, 1130 {"I2S1", NULL, "I2S9_EN", mtk_afe_i2s_share_connect}, 1131 1132 {"I2S1", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1133 {"I2S1", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1134 {"I2S1", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1135 {"I2S1", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1136 {"I2S1", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1137 {"I2S1", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1138 {"I2S1", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1139 {"I2S1", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1140 {"I2S1", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1141 {I2S1_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1142 {I2S1_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1143 1144 {"I2S1", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1145 {"I2S1", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1146 {"I2S1", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1147 {"I2S1", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1148 {"I2S1", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1149 {"I2S1", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1150 {"I2S1", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1151 {"I2S1", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1152 {"I2S1", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1153 {I2S1_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1154 {I2S1_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1155 1156 /* i2s2 */ 1157 {"I2S2", NULL, "I2S0_EN", mtk_afe_i2s_share_connect}, 1158 {"I2S2", NULL, "I2S1_EN", mtk_afe_i2s_share_connect}, 1159 {"I2S2", NULL, "I2S2_EN"}, 1160 {"I2S2", NULL, "I2S3_EN", mtk_afe_i2s_share_connect}, 1161 {"I2S2", NULL, "I2S5_EN", mtk_afe_i2s_share_connect}, 1162 {"I2S2", NULL, "I2S6_EN", mtk_afe_i2s_share_connect}, 1163 {"I2S2", NULL, "I2S7_EN", mtk_afe_i2s_share_connect}, 1164 {"I2S2", NULL, "I2S8_EN", mtk_afe_i2s_share_connect}, 1165 {"I2S2", NULL, "I2S9_EN", mtk_afe_i2s_share_connect}, 1166 1167 {"I2S2", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1168 {"I2S2", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1169 {"I2S2", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1170 {"I2S2", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1171 {"I2S2", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1172 {"I2S2", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1173 {"I2S2", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1174 {"I2S2", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1175 {"I2S2", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1176 {I2S2_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1177 {I2S2_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1178 1179 {"I2S2", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1180 {"I2S2", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1181 {"I2S2", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1182 {"I2S2", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1183 {"I2S2", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1184 {"I2S2", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1185 {"I2S2", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1186 {"I2S2", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1187 {"I2S2", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1188 {I2S2_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1189 {I2S2_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1190 1191 /* i2s3 */ 1192 {"I2S3_CH1", "DL1_CH1", "DL1"}, 1193 {"I2S3_CH2", "DL1_CH2", "DL1"}, 1194 {"I2S3_TINYCONN_CH1_MUX", "DL1_CH1", "DL1"}, 1195 {"I2S3_TINYCONN_CH2_MUX", "DL1_CH2", "DL1"}, 1196 1197 {"I2S3_CH1", "DL2_CH1", "DL2"}, 1198 {"I2S3_CH2", "DL2_CH2", "DL2"}, 1199 {"I2S3_TINYCONN_CH1_MUX", "DL2_CH1", "DL2"}, 1200 {"I2S3_TINYCONN_CH2_MUX", "DL2_CH2", "DL2"}, 1201 1202 {"I2S3_CH1", "DL3_CH1", "DL3"}, 1203 {"I2S3_CH2", "DL3_CH2", "DL3"}, 1204 {"I2S3_TINYCONN_CH1_MUX", "DL3_CH1", "DL3"}, 1205 {"I2S3_TINYCONN_CH2_MUX", "DL3_CH2", "DL3"}, 1206 1207 {"I2S3_CH1", "DL12_CH1", "DL12"}, 1208 {"I2S3_CH2", "DL12_CH2", "DL12"}, 1209 {"I2S3_TINYCONN_CH1_MUX", "DL12_CH1", "DL12"}, 1210 {"I2S3_TINYCONN_CH2_MUX", "DL12_CH2", "DL12"}, 1211 1212 {"I2S3_CH1", "DL4_CH1", "DL4"}, 1213 {"I2S3_CH2", "DL4_CH2", "DL4"}, 1214 1215 {"I2S3_CH1", "DL5_CH1", "DL5"}, 1216 {"I2S3_CH2", "DL5_CH2", "DL5"}, 1217 1218 {"I2S3_CH1", "DL6_CH1", "DL6"}, 1219 {"I2S3_CH2", "DL6_CH2", "DL6"}, 1220 1221 {"I2S3_CH1", "DL8_CH1", "DL8"}, 1222 {"I2S3_CH2", "DL8_CH2", "DL8"}, 1223 1224 {"I2S3", NULL, "I2S3_CH1"}, 1225 {"I2S3", NULL, "I2S3_CH2"}, 1226 {"I2S3", NULL, "I2S3_TINYCONN_CH1_MUX"}, 1227 {"I2S3", NULL, "I2S3_TINYCONN_CH2_MUX"}, 1228 1229 {"I2S3", NULL, "I2S0_EN", mtk_afe_i2s_share_connect}, 1230 {"I2S3", NULL, "I2S1_EN", mtk_afe_i2s_share_connect}, 1231 {"I2S3", NULL, "I2S2_EN", mtk_afe_i2s_share_connect}, 1232 {"I2S3", NULL, "I2S3_EN"}, 1233 {"I2S3", NULL, "I2S5_EN", mtk_afe_i2s_share_connect}, 1234 {"I2S3", NULL, "I2S6_EN", mtk_afe_i2s_share_connect}, 1235 {"I2S3", NULL, "I2S7_EN", mtk_afe_i2s_share_connect}, 1236 {"I2S3", NULL, "I2S8_EN", mtk_afe_i2s_share_connect}, 1237 {"I2S3", NULL, "I2S9_EN", mtk_afe_i2s_share_connect}, 1238 1239 {"I2S3", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1240 {"I2S3", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1241 {"I2S3", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1242 {"I2S3", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1243 {"I2S3", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1244 {"I2S3", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1245 {"I2S3", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1246 {"I2S3", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1247 {"I2S3", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1248 {I2S3_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1249 {I2S3_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1250 1251 {"I2S3", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1252 {"I2S3", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1253 {"I2S3", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1254 {"I2S3", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1255 {"I2S3", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1256 {"I2S3", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1257 {"I2S3", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1258 {"I2S3", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1259 {"I2S3", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1260 {I2S3_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1261 {I2S3_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1262 1263 /* i2s5 */ 1264 {"I2S5_CH1", "DL1_CH1", "DL1"}, 1265 {"I2S5_CH2", "DL1_CH2", "DL1"}, 1266 1267 {"I2S5_CH1", "DL2_CH1", "DL2"}, 1268 {"I2S5_CH2", "DL2_CH2", "DL2"}, 1269 1270 {"I2S5_CH1", "DL3_CH1", "DL3"}, 1271 {"I2S5_CH2", "DL3_CH2", "DL3"}, 1272 1273 {"I2S5_CH1", "DL12_CH1", "DL12"}, 1274 {"I2S5_CH2", "DL12_CH2", "DL12"}, 1275 1276 {"I2S5_CH1", "DL4_CH1", "DL4"}, 1277 {"I2S5_CH2", "DL4_CH2", "DL4"}, 1278 1279 {"I2S5_CH1", "DL5_CH1", "DL5"}, 1280 {"I2S5_CH2", "DL5_CH2", "DL5"}, 1281 1282 {"I2S5_CH1", "DL6_CH1", "DL6"}, 1283 {"I2S5_CH2", "DL6_CH2", "DL6"}, 1284 1285 {"I2S5_CH1", "DL8_CH1", "DL8"}, 1286 {"I2S5_CH2", "DL8_CH2", "DL8"}, 1287 1288 {"I2S5", NULL, "I2S5_CH1"}, 1289 {"I2S5", NULL, "I2S5_CH2"}, 1290 1291 {"I2S5", NULL, "I2S0_EN", mtk_afe_i2s_share_connect}, 1292 {"I2S5", NULL, "I2S1_EN", mtk_afe_i2s_share_connect}, 1293 {"I2S5", NULL, "I2S2_EN", mtk_afe_i2s_share_connect}, 1294 {"I2S5", NULL, "I2S3_EN", mtk_afe_i2s_share_connect}, 1295 {"I2S5", NULL, "I2S5_EN"}, 1296 {"I2S5", NULL, "I2S6_EN", mtk_afe_i2s_share_connect}, 1297 {"I2S5", NULL, "I2S7_EN", mtk_afe_i2s_share_connect}, 1298 {"I2S5", NULL, "I2S8_EN", mtk_afe_i2s_share_connect}, 1299 {"I2S5", NULL, "I2S9_EN", mtk_afe_i2s_share_connect}, 1300 1301 {"I2S5", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1302 {"I2S5", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1303 {"I2S5", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1304 {"I2S5", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1305 {"I2S5", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1306 {"I2S5", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1307 {"I2S5", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1308 {"I2S5", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1309 {"I2S5", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1310 {I2S5_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1311 {I2S5_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1312 1313 {"I2S5", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1314 {"I2S5", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1315 {"I2S5", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1316 {"I2S5", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1317 {"I2S5", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1318 {"I2S5", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1319 {"I2S5", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1320 {"I2S5", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1321 {"I2S5", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1322 {I2S5_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1323 {I2S5_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1324 1325 /* i2s6 */ 1326 {"I2S6", NULL, "I2S0_EN", mtk_afe_i2s_share_connect}, 1327 {"I2S6", NULL, "I2S1_EN", mtk_afe_i2s_share_connect}, 1328 {"I2S6", NULL, "I2S2_EN", mtk_afe_i2s_share_connect}, 1329 {"I2S6", NULL, "I2S3_EN", mtk_afe_i2s_share_connect}, 1330 {"I2S6", NULL, "I2S5_EN", mtk_afe_i2s_share_connect}, 1331 {"I2S6", NULL, "I2S6_EN"}, 1332 {"I2S6", NULL, "I2S7_EN", mtk_afe_i2s_share_connect}, 1333 {"I2S6", NULL, "I2S8_EN", mtk_afe_i2s_share_connect}, 1334 {"I2S6", NULL, "I2S9_EN", mtk_afe_i2s_share_connect}, 1335 1336 {"I2S6", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1337 {"I2S6", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1338 {"I2S6", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1339 {"I2S6", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1340 {"I2S6", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1341 {"I2S6", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1342 {"I2S6", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1343 {"I2S6", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1344 {"I2S6", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1345 {I2S6_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1346 {I2S6_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1347 1348 {"I2S6", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1349 {"I2S6", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1350 {"I2S6", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1351 {"I2S6", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1352 {"I2S6", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1353 {"I2S6", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1354 {"I2S6", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1355 {"I2S6", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1356 {"I2S6", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1357 {I2S6_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1358 {I2S6_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1359 1360 /* i2s7 */ 1361 {"I2S7", NULL, "I2S7_CH1"}, 1362 {"I2S7", NULL, "I2S7_CH2"}, 1363 1364 {"I2S7", NULL, "I2S0_EN", mtk_afe_i2s_share_connect}, 1365 {"I2S7", NULL, "I2S1_EN", mtk_afe_i2s_share_connect}, 1366 {"I2S7", NULL, "I2S2_EN", mtk_afe_i2s_share_connect}, 1367 {"I2S7", NULL, "I2S3_EN", mtk_afe_i2s_share_connect}, 1368 {"I2S7", NULL, "I2S5_EN", mtk_afe_i2s_share_connect}, 1369 {"I2S7", NULL, "I2S6_EN", mtk_afe_i2s_share_connect}, 1370 {"I2S7", NULL, "I2S7_EN"}, 1371 {"I2S7", NULL, "I2S8_EN", mtk_afe_i2s_share_connect}, 1372 {"I2S7", NULL, "I2S9_EN", mtk_afe_i2s_share_connect}, 1373 1374 {"I2S7", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1375 {"I2S7", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1376 {"I2S7", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1377 {"I2S7", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1378 {"I2S7", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1379 {"I2S7", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1380 {"I2S7", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1381 {"I2S7", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1382 {"I2S7", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1383 {I2S7_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1384 {I2S7_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1385 1386 {"I2S7", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1387 {"I2S7", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1388 {"I2S7", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1389 {"I2S7", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1390 {"I2S7", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1391 {"I2S7", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1392 {"I2S7", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1393 {"I2S7", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1394 {"I2S7", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1395 {I2S7_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1396 {I2S7_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1397 1398 /* i2s8 */ 1399 {"I2S8", NULL, "I2S0_EN", mtk_afe_i2s_share_connect}, 1400 {"I2S8", NULL, "I2S1_EN", mtk_afe_i2s_share_connect}, 1401 {"I2S8", NULL, "I2S2_EN", mtk_afe_i2s_share_connect}, 1402 {"I2S8", NULL, "I2S3_EN", mtk_afe_i2s_share_connect}, 1403 {"I2S8", NULL, "I2S5_EN", mtk_afe_i2s_share_connect}, 1404 {"I2S8", NULL, "I2S6_EN", mtk_afe_i2s_share_connect}, 1405 {"I2S8", NULL, "I2S7_EN", mtk_afe_i2s_share_connect}, 1406 {"I2S8", NULL, "I2S8_EN"}, 1407 {"I2S8", NULL, "I2S9_EN", mtk_afe_i2s_share_connect}, 1408 1409 {"I2S8", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1410 {"I2S8", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1411 {"I2S8", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1412 {"I2S8", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1413 {"I2S8", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1414 {"I2S8", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1415 {"I2S8", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1416 {"I2S8", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1417 {"I2S8", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1418 {I2S8_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1419 {I2S8_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1420 1421 {"I2S8", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1422 {"I2S8", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1423 {"I2S8", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1424 {"I2S8", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1425 {"I2S8", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1426 {"I2S8", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1427 {"I2S8", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1428 {"I2S8", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1429 {"I2S8", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1430 {I2S8_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1431 {I2S8_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1432 1433 /* i2s9 */ 1434 {"I2S9_CH1", "DL1_CH1", "DL1"}, 1435 {"I2S9_CH2", "DL1_CH2", "DL1"}, 1436 1437 {"I2S9_CH1", "DL2_CH1", "DL2"}, 1438 {"I2S9_CH2", "DL2_CH2", "DL2"}, 1439 1440 {"I2S9_CH1", "DL3_CH1", "DL3"}, 1441 {"I2S9_CH2", "DL3_CH2", "DL3"}, 1442 1443 {"I2S9_CH1", "DL12_CH1", "DL12"}, 1444 {"I2S9_CH2", "DL12_CH2", "DL12"}, 1445 1446 {"I2S9_CH1", "DL4_CH1", "DL4"}, 1447 {"I2S9_CH2", "DL4_CH2", "DL4"}, 1448 1449 {"I2S9_CH1", "DL5_CH1", "DL5"}, 1450 {"I2S9_CH2", "DL5_CH2", "DL5"}, 1451 1452 {"I2S9_CH1", "DL6_CH1", "DL6"}, 1453 {"I2S9_CH2", "DL6_CH2", "DL6"}, 1454 1455 {"I2S9_CH1", "DL8_CH1", "DL8"}, 1456 {"I2S9_CH2", "DL8_CH2", "DL8"}, 1457 1458 {"I2S9_CH1", "DL9_CH1", "DL9"}, 1459 {"I2S9_CH2", "DL9_CH2", "DL9"}, 1460 1461 {"I2S9", NULL, "I2S9_CH1"}, 1462 {"I2S9", NULL, "I2S9_CH2"}, 1463 1464 {"I2S9", NULL, "I2S0_EN", mtk_afe_i2s_share_connect}, 1465 {"I2S9", NULL, "I2S1_EN", mtk_afe_i2s_share_connect}, 1466 {"I2S9", NULL, "I2S2_EN", mtk_afe_i2s_share_connect}, 1467 {"I2S9", NULL, "I2S3_EN", mtk_afe_i2s_share_connect}, 1468 {"I2S9", NULL, "I2S5_EN", mtk_afe_i2s_share_connect}, 1469 {"I2S9", NULL, "I2S6_EN", mtk_afe_i2s_share_connect}, 1470 {"I2S9", NULL, "I2S7_EN", mtk_afe_i2s_share_connect}, 1471 {"I2S9", NULL, "I2S8_EN", mtk_afe_i2s_share_connect}, 1472 {"I2S9", NULL, "I2S9_EN"}, 1473 1474 {"I2S9", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1475 {"I2S9", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1476 {"I2S9", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1477 {"I2S9", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1478 {"I2S9", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1479 {"I2S9", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1480 {"I2S9", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1481 {"I2S9", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1482 {"I2S9", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 1483 {I2S9_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 1484 {I2S9_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 1485 1486 {"I2S9", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1487 {"I2S9", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1488 {"I2S9", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1489 {"I2S9", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1490 {"I2S9", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1491 {"I2S9", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1492 {"I2S9", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1493 {"I2S9", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1494 {"I2S9", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 1495 {I2S9_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 1496 {I2S9_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 1497 1498 /* allow i2s on without codec on */ 1499 {"I2S0", NULL, "I2S0_In_Mux"}, 1500 {"I2S0_In_Mux", "Dummy_Widget", "I2S_DUMMY_IN"}, 1501 1502 {"I2S8", NULL, "I2S8_In_Mux"}, 1503 {"I2S8_In_Mux", "Dummy_Widget", "I2S_DUMMY_IN"}, 1504 1505 {"I2S1_Out_Mux", "Dummy_Widget", "I2S1"}, 1506 {"I2S_DUMMY_OUT", NULL, "I2S1_Out_Mux"}, 1507 1508 {"I2S3_Out_Mux", "Dummy_Widget", "I2S3"}, 1509 {"I2S_DUMMY_OUT", NULL, "I2S3_Out_Mux"}, 1510 1511 {"I2S5_Out_Mux", "Dummy_Widget", "I2S5"}, 1512 {"I2S_DUMMY_OUT", NULL, "I2S5_Out_Mux"}, 1513 1514 {"I2S7_Out_Mux", "Dummy_Widget", "I2S7"}, 1515 {"I2S_DUMMY_OUT", NULL, "I2S7_Out_Mux"}, 1516 1517 {"I2S9_Out_Mux", "Dummy_Widget", "I2S9"}, 1518 {"I2S_DUMMY_OUT", NULL, "I2S9_Out_Mux"}, 1519 1520 /* i2s in lpbk */ 1521 {"I2S0_Lpbk_Mux", "Lpbk", "I2S3"}, 1522 {"I2S2_Lpbk_Mux", "Lpbk", "I2S1"}, 1523 {"I2S0", NULL, "I2S0_Lpbk_Mux"}, 1524 {"I2S2", NULL, "I2S2_Lpbk_Mux"}, 1525 }; 1526 1527 /* dai ops */ 1528 static int mtk_dai_connsys_i2s_hw_params(struct snd_pcm_substream *substream, 1529 struct snd_pcm_hw_params *params, 1530 struct snd_soc_dai *dai) 1531 { 1532 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1533 unsigned int rate = params_rate(params); 1534 unsigned int rate_reg = mt8192_rate_transform(afe->dev, 1535 rate, dai->id); 1536 unsigned int i2s_con = 0; 1537 1538 dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n", 1539 __func__, dai->id, substream->stream, rate); 1540 1541 /* non-inverse, i2s mode, proxy mode, 16bits, from connsys */ 1542 i2s_con |= 0 << INV_PAD_CTRL_SFT; 1543 i2s_con |= I2S_FMT_I2S << I2S_FMT_SFT; 1544 i2s_con |= 1 << I2S_SRC_SFT; 1545 i2s_con |= get_i2s_wlen(SNDRV_PCM_FORMAT_S16_LE) << I2S_WLEN_SFT; 1546 i2s_con |= 0 << I2SIN_PAD_SEL_SFT; 1547 regmap_write(afe->regmap, AFE_CONNSYS_I2S_CON, i2s_con); 1548 1549 /* use asrc */ 1550 regmap_update_bits(afe->regmap, 1551 AFE_CONNSYS_I2S_CON, 1552 I2S_BYPSRC_MASK_SFT, 1553 0x0 << I2S_BYPSRC_SFT); 1554 1555 /* proxy mode, set i2s for asrc */ 1556 regmap_update_bits(afe->regmap, 1557 AFE_CONNSYS_I2S_CON, 1558 I2S_MODE_MASK_SFT, 1559 rate_reg << I2S_MODE_SFT); 1560 1561 switch (rate) { 1562 case 32000: 1563 regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x140000); 1564 break; 1565 case 44100: 1566 regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x001B9000); 1567 break; 1568 default: 1569 regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x001E0000); 1570 break; 1571 } 1572 1573 /* Calibration setting */ 1574 regmap_write(afe->regmap, AFE_ASRC_2CH_CON4, 0x00140000); 1575 regmap_write(afe->regmap, AFE_ASRC_2CH_CON9, 0x00036000); 1576 regmap_write(afe->regmap, AFE_ASRC_2CH_CON10, 0x0002FC00); 1577 regmap_write(afe->regmap, AFE_ASRC_2CH_CON6, 0x00007EF4); 1578 regmap_write(afe->regmap, AFE_ASRC_2CH_CON5, 0x00FF5986); 1579 1580 /* 0:Stereo 1:Mono */ 1581 regmap_update_bits(afe->regmap, 1582 AFE_ASRC_2CH_CON2, 1583 CHSET_IS_MONO_MASK_SFT, 1584 0x0 << CHSET_IS_MONO_SFT); 1585 1586 return 0; 1587 } 1588 1589 static int mtk_dai_connsys_i2s_trigger(struct snd_pcm_substream *substream, 1590 int cmd, struct snd_soc_dai *dai) 1591 { 1592 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1593 struct mt8192_afe_private *afe_priv = afe->platform_priv; 1594 1595 dev_dbg(afe->dev, "%s(), cmd %d, stream %d\n", 1596 __func__, cmd, substream->stream); 1597 1598 switch (cmd) { 1599 case SNDRV_PCM_TRIGGER_START: 1600 case SNDRV_PCM_TRIGGER_RESUME: 1601 /* i2s enable */ 1602 regmap_update_bits(afe->regmap, 1603 AFE_CONNSYS_I2S_CON, 1604 I2S_EN_MASK_SFT, 1605 0x1 << I2S_EN_SFT); 1606 1607 /* calibrator enable */ 1608 regmap_update_bits(afe->regmap, 1609 AFE_ASRC_2CH_CON5, 1610 CALI_EN_MASK_SFT, 1611 0x1 << CALI_EN_SFT); 1612 1613 /* asrc enable */ 1614 regmap_update_bits(afe->regmap, 1615 AFE_ASRC_2CH_CON0, 1616 CON0_CHSET_STR_CLR_MASK_SFT, 1617 0x1 << CON0_CHSET_STR_CLR_SFT); 1618 regmap_update_bits(afe->regmap, 1619 AFE_ASRC_2CH_CON0, 1620 CON0_ASM_ON_MASK_SFT, 1621 0x1 << CON0_ASM_ON_SFT); 1622 1623 afe_priv->dai_on[dai->id] = true; 1624 break; 1625 case SNDRV_PCM_TRIGGER_STOP: 1626 case SNDRV_PCM_TRIGGER_SUSPEND: 1627 regmap_update_bits(afe->regmap, 1628 AFE_ASRC_2CH_CON0, 1629 CON0_ASM_ON_MASK_SFT, 1630 0 << CON0_ASM_ON_SFT); 1631 regmap_update_bits(afe->regmap, 1632 AFE_ASRC_2CH_CON5, 1633 CALI_EN_MASK_SFT, 1634 0 << CALI_EN_SFT); 1635 1636 /* i2s disable */ 1637 regmap_update_bits(afe->regmap, 1638 AFE_CONNSYS_I2S_CON, 1639 I2S_EN_MASK_SFT, 1640 0x0 << I2S_EN_SFT); 1641 1642 /* bypass asrc */ 1643 regmap_update_bits(afe->regmap, 1644 AFE_CONNSYS_I2S_CON, 1645 I2S_BYPSRC_MASK_SFT, 1646 0x1 << I2S_BYPSRC_SFT); 1647 1648 afe_priv->dai_on[dai->id] = false; 1649 break; 1650 default: 1651 return -EINVAL; 1652 } 1653 return 0; 1654 } 1655 1656 static const struct snd_soc_dai_ops mtk_dai_connsys_i2s_ops = { 1657 .hw_params = mtk_dai_connsys_i2s_hw_params, 1658 .trigger = mtk_dai_connsys_i2s_trigger, 1659 }; 1660 1661 /* i2s */ 1662 static int mtk_dai_i2s_config(struct mtk_base_afe *afe, 1663 struct snd_pcm_hw_params *params, 1664 int i2s_id) 1665 { 1666 struct mt8192_afe_private *afe_priv = afe->platform_priv; 1667 struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[i2s_id]; 1668 1669 unsigned int rate = params_rate(params); 1670 unsigned int rate_reg = mt8192_rate_transform(afe->dev, 1671 rate, i2s_id); 1672 snd_pcm_format_t format = params_format(params); 1673 unsigned int i2s_con = 0; 1674 int ret = 0; 1675 1676 dev_dbg(afe->dev, "%s(), id %d, rate %d, format %d\n", 1677 __func__, i2s_id, rate, format); 1678 1679 if (i2s_priv) 1680 i2s_priv->rate = rate; 1681 else 1682 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__); 1683 1684 switch (i2s_id) { 1685 case MT8192_DAI_I2S_0: 1686 i2s_con = I2S_IN_PAD_IO_MUX << I2SIN_PAD_SEL_SFT; 1687 i2s_con |= rate_reg << I2S_OUT_MODE_SFT; 1688 i2s_con |= I2S_FMT_I2S << I2S_FMT_SFT; 1689 i2s_con |= get_i2s_wlen(format) << I2S_WLEN_SFT; 1690 regmap_update_bits(afe->regmap, AFE_I2S_CON, 1691 0xffffeffe, i2s_con); 1692 break; 1693 case MT8192_DAI_I2S_1: 1694 i2s_con = I2S1_SEL_O28_O29 << I2S2_SEL_O03_O04_SFT; 1695 i2s_con |= rate_reg << I2S2_OUT_MODE_SFT; 1696 i2s_con |= I2S_FMT_I2S << I2S2_FMT_SFT; 1697 i2s_con |= get_i2s_wlen(format) << I2S2_WLEN_SFT; 1698 regmap_update_bits(afe->regmap, AFE_I2S_CON1, 1699 0xffffeffe, i2s_con); 1700 break; 1701 case MT8192_DAI_I2S_2: 1702 i2s_con = 8 << I2S3_UPDATE_WORD_SFT; 1703 i2s_con |= rate_reg << I2S3_OUT_MODE_SFT; 1704 i2s_con |= I2S_FMT_I2S << I2S3_FMT_SFT; 1705 i2s_con |= get_i2s_wlen(format) << I2S3_WLEN_SFT; 1706 regmap_update_bits(afe->regmap, AFE_I2S_CON2, 1707 0xffffeffe, i2s_con); 1708 break; 1709 case MT8192_DAI_I2S_3: 1710 i2s_con = rate_reg << I2S4_OUT_MODE_SFT; 1711 i2s_con |= I2S_FMT_I2S << I2S4_FMT_SFT; 1712 i2s_con |= get_i2s_wlen(format) << I2S4_WLEN_SFT; 1713 regmap_update_bits(afe->regmap, AFE_I2S_CON3, 1714 0xffffeffe, i2s_con); 1715 break; 1716 case MT8192_DAI_I2S_5: 1717 i2s_con = rate_reg << I2S5_OUT_MODE_SFT; 1718 i2s_con |= I2S_FMT_I2S << I2S5_FMT_SFT; 1719 i2s_con |= get_i2s_wlen(format) << I2S5_WLEN_SFT; 1720 regmap_update_bits(afe->regmap, AFE_I2S_CON4, 1721 0xffffeffe, i2s_con); 1722 break; 1723 case MT8192_DAI_I2S_6: 1724 i2s_con = rate_reg << I2S6_OUT_MODE_SFT; 1725 i2s_con |= I2S_FMT_I2S << I2S6_FMT_SFT; 1726 i2s_con |= get_i2s_wlen(format) << I2S6_WLEN_SFT; 1727 regmap_update_bits(afe->regmap, AFE_I2S_CON6, 1728 0xffffeffe, i2s_con); 1729 break; 1730 case MT8192_DAI_I2S_7: 1731 i2s_con = rate_reg << I2S7_OUT_MODE_SFT; 1732 i2s_con |= I2S_FMT_I2S << I2S7_FMT_SFT; 1733 i2s_con |= get_i2s_wlen(format) << I2S7_WLEN_SFT; 1734 regmap_update_bits(afe->regmap, AFE_I2S_CON7, 1735 0xffffeffe, i2s_con); 1736 break; 1737 case MT8192_DAI_I2S_8: 1738 i2s_con = rate_reg << I2S8_OUT_MODE_SFT; 1739 i2s_con |= I2S_FMT_I2S << I2S8_FMT_SFT; 1740 i2s_con |= get_i2s_wlen(format) << I2S8_WLEN_SFT; 1741 regmap_update_bits(afe->regmap, AFE_I2S_CON8, 1742 0xffffeffe, i2s_con); 1743 break; 1744 case MT8192_DAI_I2S_9: 1745 i2s_con = rate_reg << I2S9_OUT_MODE_SFT; 1746 i2s_con |= I2S_FMT_I2S << I2S9_FMT_SFT; 1747 i2s_con |= get_i2s_wlen(format) << I2S9_WLEN_SFT; 1748 regmap_update_bits(afe->regmap, AFE_I2S_CON9, 1749 0xffffeffe, i2s_con); 1750 break; 1751 default: 1752 dev_warn(afe->dev, "%s(), id %d not support\n", 1753 __func__, i2s_id); 1754 return -EINVAL; 1755 } 1756 1757 /* set share i2s */ 1758 if (i2s_priv && i2s_priv->share_i2s_id >= 0) 1759 ret = mtk_dai_i2s_config(afe, params, i2s_priv->share_i2s_id); 1760 1761 return ret; 1762 } 1763 1764 static int mtk_dai_i2s_hw_params(struct snd_pcm_substream *substream, 1765 struct snd_pcm_hw_params *params, 1766 struct snd_soc_dai *dai) 1767 { 1768 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1769 1770 return mtk_dai_i2s_config(afe, params, dai->id); 1771 } 1772 1773 static int mtk_dai_i2s_set_sysclk(struct snd_soc_dai *dai, 1774 int clk_id, unsigned int freq, int dir) 1775 { 1776 struct mtk_base_afe *afe = dev_get_drvdata(dai->dev); 1777 struct mt8192_afe_private *afe_priv = afe->platform_priv; 1778 struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[dai->id]; 1779 int apll; 1780 int apll_rate; 1781 1782 if (!i2s_priv) { 1783 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__); 1784 return -EINVAL; 1785 } 1786 1787 if (dir != SND_SOC_CLOCK_OUT) { 1788 dev_warn(afe->dev, "%s(), dir != SND_SOC_CLOCK_OUT", __func__); 1789 return -EINVAL; 1790 } 1791 1792 dev_dbg(afe->dev, "%s(), freq %d\n", __func__, freq); 1793 1794 apll = mt8192_get_apll_by_rate(afe, freq); 1795 apll_rate = mt8192_get_apll_rate(afe, apll); 1796 1797 if (freq > apll_rate) { 1798 dev_warn(afe->dev, "%s(), freq > apll rate", __func__); 1799 return -EINVAL; 1800 } 1801 1802 if (apll_rate % freq != 0) { 1803 dev_warn(afe->dev, "%s(), APLL can't gen freq Hz", __func__); 1804 return -EINVAL; 1805 } 1806 1807 i2s_priv->mclk_rate = freq; 1808 i2s_priv->mclk_apll = apll; 1809 1810 if (i2s_priv->share_i2s_id > 0) { 1811 struct mtk_afe_i2s_priv *share_i2s_priv; 1812 1813 share_i2s_priv = afe_priv->dai_priv[i2s_priv->share_i2s_id]; 1814 if (!share_i2s_priv) { 1815 dev_warn(afe->dev, "%s(), share_i2s_priv = NULL", 1816 __func__); 1817 return -EINVAL; 1818 } 1819 1820 share_i2s_priv->mclk_rate = i2s_priv->mclk_rate; 1821 share_i2s_priv->mclk_apll = i2s_priv->mclk_apll; 1822 } 1823 1824 return 0; 1825 } 1826 1827 static const struct snd_soc_dai_ops mtk_dai_i2s_ops = { 1828 .hw_params = mtk_dai_i2s_hw_params, 1829 .set_sysclk = mtk_dai_i2s_set_sysclk, 1830 }; 1831 1832 /* dai driver */ 1833 #define MTK_CONNSYS_I2S_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 1834 1835 #define MTK_I2S_RATES (SNDRV_PCM_RATE_8000_48000 |\ 1836 SNDRV_PCM_RATE_88200 |\ 1837 SNDRV_PCM_RATE_96000 |\ 1838 SNDRV_PCM_RATE_176400 |\ 1839 SNDRV_PCM_RATE_192000) 1840 1841 #define MTK_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1842 SNDRV_PCM_FMTBIT_S24_LE |\ 1843 SNDRV_PCM_FMTBIT_S32_LE) 1844 1845 static struct snd_soc_dai_driver mtk_dai_i2s_driver[] = { 1846 { 1847 .name = "CONNSYS_I2S", 1848 .id = MT8192_DAI_CONNSYS_I2S, 1849 .capture = { 1850 .stream_name = "Connsys I2S", 1851 .channels_min = 1, 1852 .channels_max = 2, 1853 .rates = MTK_CONNSYS_I2S_RATES, 1854 .formats = MTK_I2S_FORMATS, 1855 }, 1856 .ops = &mtk_dai_connsys_i2s_ops, 1857 }, 1858 { 1859 .name = "I2S0", 1860 .id = MT8192_DAI_I2S_0, 1861 .capture = { 1862 .stream_name = "I2S0", 1863 .channels_min = 1, 1864 .channels_max = 2, 1865 .rates = MTK_I2S_RATES, 1866 .formats = MTK_I2S_FORMATS, 1867 }, 1868 .ops = &mtk_dai_i2s_ops, 1869 }, 1870 { 1871 .name = "I2S1", 1872 .id = MT8192_DAI_I2S_1, 1873 .playback = { 1874 .stream_name = "I2S1", 1875 .channels_min = 1, 1876 .channels_max = 2, 1877 .rates = MTK_I2S_RATES, 1878 .formats = MTK_I2S_FORMATS, 1879 }, 1880 .ops = &mtk_dai_i2s_ops, 1881 }, 1882 { 1883 .name = "I2S2", 1884 .id = MT8192_DAI_I2S_2, 1885 .capture = { 1886 .stream_name = "I2S2", 1887 .channels_min = 1, 1888 .channels_max = 2, 1889 .rates = MTK_I2S_RATES, 1890 .formats = MTK_I2S_FORMATS, 1891 }, 1892 .ops = &mtk_dai_i2s_ops, 1893 }, 1894 { 1895 .name = "I2S3", 1896 .id = MT8192_DAI_I2S_3, 1897 .playback = { 1898 .stream_name = "I2S3", 1899 .channels_min = 1, 1900 .channels_max = 2, 1901 .rates = MTK_I2S_RATES, 1902 .formats = MTK_I2S_FORMATS, 1903 }, 1904 .ops = &mtk_dai_i2s_ops, 1905 }, 1906 { 1907 .name = "I2S5", 1908 .id = MT8192_DAI_I2S_5, 1909 .playback = { 1910 .stream_name = "I2S5", 1911 .channels_min = 1, 1912 .channels_max = 2, 1913 .rates = MTK_I2S_RATES, 1914 .formats = MTK_I2S_FORMATS, 1915 }, 1916 .ops = &mtk_dai_i2s_ops, 1917 }, 1918 { 1919 .name = "I2S6", 1920 .id = MT8192_DAI_I2S_6, 1921 .capture = { 1922 .stream_name = "I2S6", 1923 .channels_min = 1, 1924 .channels_max = 2, 1925 .rates = MTK_I2S_RATES, 1926 .formats = MTK_I2S_FORMATS, 1927 }, 1928 .ops = &mtk_dai_i2s_ops, 1929 }, 1930 { 1931 .name = "I2S7", 1932 .id = MT8192_DAI_I2S_7, 1933 .playback = { 1934 .stream_name = "I2S7", 1935 .channels_min = 1, 1936 .channels_max = 2, 1937 .rates = MTK_I2S_RATES, 1938 .formats = MTK_I2S_FORMATS, 1939 }, 1940 .ops = &mtk_dai_i2s_ops, 1941 }, 1942 { 1943 .name = "I2S8", 1944 .id = MT8192_DAI_I2S_8, 1945 .capture = { 1946 .stream_name = "I2S8", 1947 .channels_min = 1, 1948 .channels_max = 2, 1949 .rates = MTK_I2S_RATES, 1950 .formats = MTK_I2S_FORMATS, 1951 }, 1952 .ops = &mtk_dai_i2s_ops, 1953 }, 1954 { 1955 .name = "I2S9", 1956 .id = MT8192_DAI_I2S_9, 1957 .playback = { 1958 .stream_name = "I2S9", 1959 .channels_min = 1, 1960 .channels_max = 2, 1961 .rates = MTK_I2S_RATES, 1962 .formats = MTK_I2S_FORMATS, 1963 }, 1964 .ops = &mtk_dai_i2s_ops, 1965 } 1966 }; 1967 1968 /* this enum is merely for mtk_afe_i2s_priv declare */ 1969 enum { 1970 DAI_I2S0 = 0, 1971 DAI_I2S1, 1972 DAI_I2S2, 1973 DAI_I2S3, 1974 DAI_I2S5, 1975 DAI_I2S6, 1976 DAI_I2S7, 1977 DAI_I2S8, 1978 DAI_I2S9, 1979 DAI_I2S_NUM, 1980 }; 1981 1982 static const struct mtk_afe_i2s_priv mt8192_i2s_priv[DAI_I2S_NUM] = { 1983 [DAI_I2S0] = { 1984 .id = MT8192_DAI_I2S_0, 1985 .mclk_id = MT8192_I2S0_MCK, 1986 .share_i2s_id = -1, 1987 }, 1988 [DAI_I2S1] = { 1989 .id = MT8192_DAI_I2S_1, 1990 .mclk_id = MT8192_I2S1_MCK, 1991 .share_i2s_id = -1, 1992 }, 1993 [DAI_I2S2] = { 1994 .id = MT8192_DAI_I2S_2, 1995 .mclk_id = MT8192_I2S2_MCK, 1996 .share_i2s_id = -1, 1997 }, 1998 [DAI_I2S3] = { 1999 .id = MT8192_DAI_I2S_3, 2000 .mclk_id = MT8192_I2S3_MCK, 2001 .share_i2s_id = -1, 2002 }, 2003 [DAI_I2S5] = { 2004 .id = MT8192_DAI_I2S_5, 2005 .mclk_id = MT8192_I2S5_MCK, 2006 .share_i2s_id = -1, 2007 }, 2008 [DAI_I2S6] = { 2009 .id = MT8192_DAI_I2S_6, 2010 .mclk_id = MT8192_I2S6_MCK, 2011 .share_i2s_id = -1, 2012 }, 2013 [DAI_I2S7] = { 2014 .id = MT8192_DAI_I2S_7, 2015 .mclk_id = MT8192_I2S7_MCK, 2016 .share_i2s_id = -1, 2017 }, 2018 [DAI_I2S8] = { 2019 .id = MT8192_DAI_I2S_8, 2020 .mclk_id = MT8192_I2S8_MCK, 2021 .share_i2s_id = -1, 2022 }, 2023 [DAI_I2S9] = { 2024 .id = MT8192_DAI_I2S_9, 2025 .mclk_id = MT8192_I2S9_MCK, 2026 .share_i2s_id = -1, 2027 }, 2028 }; 2029 2030 /** 2031 * mt8192_dai_i2s_set_share() - Set up I2S ports to share a single clock. 2032 * @afe: Pointer to &struct mtk_base_afe 2033 * @main_i2s_name: The name of the I2S port that will provide the clock 2034 * @secondary_i2s_name: The name of the I2S port that will use this clock 2035 */ 2036 int mt8192_dai_i2s_set_share(struct mtk_base_afe *afe, const char *main_i2s_name, 2037 const char *secondary_i2s_name) 2038 { 2039 struct mtk_afe_i2s_priv *secondary_i2s_priv; 2040 int main_i2s_id; 2041 2042 secondary_i2s_priv = get_i2s_priv_by_name(afe, secondary_i2s_name); 2043 if (!secondary_i2s_priv) 2044 return -EINVAL; 2045 2046 main_i2s_id = get_i2s_id_by_name(afe, main_i2s_name); 2047 if (main_i2s_id < 0) 2048 return main_i2s_id; 2049 2050 secondary_i2s_priv->share_i2s_id = main_i2s_id; 2051 2052 return 0; 2053 } 2054 EXPORT_SYMBOL_GPL(mt8192_dai_i2s_set_share); 2055 2056 static int mt8192_dai_i2s_set_priv(struct mtk_base_afe *afe) 2057 { 2058 int i; 2059 int ret; 2060 2061 for (i = 0; i < DAI_I2S_NUM; i++) { 2062 ret = mt8192_dai_set_priv(afe, mt8192_i2s_priv[i].id, 2063 sizeof(struct mtk_afe_i2s_priv), 2064 &mt8192_i2s_priv[i]); 2065 if (ret) 2066 return ret; 2067 } 2068 2069 return 0; 2070 } 2071 2072 int mt8192_dai_i2s_register(struct mtk_base_afe *afe) 2073 { 2074 struct mtk_base_afe_dai *dai; 2075 int ret; 2076 2077 dev_dbg(afe->dev, "%s()\n", __func__); 2078 2079 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 2080 if (!dai) 2081 return -ENOMEM; 2082 2083 list_add(&dai->list, &afe->sub_dais); 2084 2085 dai->dai_drivers = mtk_dai_i2s_driver; 2086 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_i2s_driver); 2087 2088 dai->controls = mtk_dai_i2s_controls; 2089 dai->num_controls = ARRAY_SIZE(mtk_dai_i2s_controls); 2090 dai->dapm_widgets = mtk_dai_i2s_widgets; 2091 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_i2s_widgets); 2092 dai->dapm_routes = mtk_dai_i2s_routes; 2093 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_i2s_routes); 2094 2095 /* set all dai i2s private data */ 2096 ret = mt8192_dai_i2s_set_priv(afe); 2097 if (ret) 2098 return ret; 2099 2100 return 0; 2101 } 2102