1*607ac485SJiaxin Yu // SPDX-License-Identifier: GPL-2.0 2*607ac485SJiaxin Yu // 3*607ac485SJiaxin Yu // MediaTek ALSA SoC Audio DAI ADDA Control 4*607ac485SJiaxin Yu // 5*607ac485SJiaxin Yu // Copyright (c) 2020 MediaTek Inc. 6*607ac485SJiaxin Yu // Author: Shane Chien <shane.chien@mediatek.com> 7*607ac485SJiaxin Yu // 8*607ac485SJiaxin Yu 9*607ac485SJiaxin Yu #include <linux/delay.h> 10*607ac485SJiaxin Yu #include <linux/regmap.h> 11*607ac485SJiaxin Yu 12*607ac485SJiaxin Yu #include "mt8192-afe-clk.h" 13*607ac485SJiaxin Yu #include "mt8192-afe-common.h" 14*607ac485SJiaxin Yu #include "mt8192-afe-gpio.h" 15*607ac485SJiaxin Yu #include "mt8192-interconnection.h" 16*607ac485SJiaxin Yu 17*607ac485SJiaxin Yu enum { 18*607ac485SJiaxin Yu UL_IIR_SW = 0, 19*607ac485SJiaxin Yu UL_IIR_5HZ, 20*607ac485SJiaxin Yu UL_IIR_10HZ, 21*607ac485SJiaxin Yu UL_IIR_25HZ, 22*607ac485SJiaxin Yu UL_IIR_50HZ, 23*607ac485SJiaxin Yu UL_IIR_75HZ, 24*607ac485SJiaxin Yu }; 25*607ac485SJiaxin Yu 26*607ac485SJiaxin Yu enum { 27*607ac485SJiaxin Yu AUDIO_SDM_LEVEL_MUTE = 0, 28*607ac485SJiaxin Yu AUDIO_SDM_LEVEL_NORMAL = 0x1d, 29*607ac485SJiaxin Yu /* if you change level normal */ 30*607ac485SJiaxin Yu /* you need to change formula of hp impedance and dc trim too */ 31*607ac485SJiaxin Yu }; 32*607ac485SJiaxin Yu 33*607ac485SJiaxin Yu enum { 34*607ac485SJiaxin Yu AUDIO_SDM_2ND = 0, 35*607ac485SJiaxin Yu AUDIO_SDM_3RD, 36*607ac485SJiaxin Yu }; 37*607ac485SJiaxin Yu 38*607ac485SJiaxin Yu enum { 39*607ac485SJiaxin Yu DELAY_DATA_MISO1 = 0, 40*607ac485SJiaxin Yu DELAY_DATA_MISO2, 41*607ac485SJiaxin Yu }; 42*607ac485SJiaxin Yu 43*607ac485SJiaxin Yu enum { 44*607ac485SJiaxin Yu MTK_AFE_ADDA_DL_RATE_8K = 0, 45*607ac485SJiaxin Yu MTK_AFE_ADDA_DL_RATE_11K = 1, 46*607ac485SJiaxin Yu MTK_AFE_ADDA_DL_RATE_12K = 2, 47*607ac485SJiaxin Yu MTK_AFE_ADDA_DL_RATE_16K = 3, 48*607ac485SJiaxin Yu MTK_AFE_ADDA_DL_RATE_22K = 4, 49*607ac485SJiaxin Yu MTK_AFE_ADDA_DL_RATE_24K = 5, 50*607ac485SJiaxin Yu MTK_AFE_ADDA_DL_RATE_32K = 6, 51*607ac485SJiaxin Yu MTK_AFE_ADDA_DL_RATE_44K = 7, 52*607ac485SJiaxin Yu MTK_AFE_ADDA_DL_RATE_48K = 8, 53*607ac485SJiaxin Yu MTK_AFE_ADDA_DL_RATE_96K = 9, 54*607ac485SJiaxin Yu MTK_AFE_ADDA_DL_RATE_192K = 10, 55*607ac485SJiaxin Yu }; 56*607ac485SJiaxin Yu 57*607ac485SJiaxin Yu enum { 58*607ac485SJiaxin Yu MTK_AFE_ADDA_UL_RATE_8K = 0, 59*607ac485SJiaxin Yu MTK_AFE_ADDA_UL_RATE_16K = 1, 60*607ac485SJiaxin Yu MTK_AFE_ADDA_UL_RATE_32K = 2, 61*607ac485SJiaxin Yu MTK_AFE_ADDA_UL_RATE_48K = 3, 62*607ac485SJiaxin Yu MTK_AFE_ADDA_UL_RATE_96K = 4, 63*607ac485SJiaxin Yu MTK_AFE_ADDA_UL_RATE_192K = 5, 64*607ac485SJiaxin Yu MTK_AFE_ADDA_UL_RATE_48K_HD = 6, 65*607ac485SJiaxin Yu }; 66*607ac485SJiaxin Yu 67*607ac485SJiaxin Yu #define SDM_AUTO_RESET_THRESHOLD 0x190000 68*607ac485SJiaxin Yu 69*607ac485SJiaxin Yu static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe, 70*607ac485SJiaxin Yu unsigned int rate) 71*607ac485SJiaxin Yu { 72*607ac485SJiaxin Yu switch (rate) { 73*607ac485SJiaxin Yu case 8000: 74*607ac485SJiaxin Yu return MTK_AFE_ADDA_DL_RATE_8K; 75*607ac485SJiaxin Yu case 11025: 76*607ac485SJiaxin Yu return MTK_AFE_ADDA_DL_RATE_11K; 77*607ac485SJiaxin Yu case 12000: 78*607ac485SJiaxin Yu return MTK_AFE_ADDA_DL_RATE_12K; 79*607ac485SJiaxin Yu case 16000: 80*607ac485SJiaxin Yu return MTK_AFE_ADDA_DL_RATE_16K; 81*607ac485SJiaxin Yu case 22050: 82*607ac485SJiaxin Yu return MTK_AFE_ADDA_DL_RATE_22K; 83*607ac485SJiaxin Yu case 24000: 84*607ac485SJiaxin Yu return MTK_AFE_ADDA_DL_RATE_24K; 85*607ac485SJiaxin Yu case 32000: 86*607ac485SJiaxin Yu return MTK_AFE_ADDA_DL_RATE_32K; 87*607ac485SJiaxin Yu case 44100: 88*607ac485SJiaxin Yu return MTK_AFE_ADDA_DL_RATE_44K; 89*607ac485SJiaxin Yu case 48000: 90*607ac485SJiaxin Yu return MTK_AFE_ADDA_DL_RATE_48K; 91*607ac485SJiaxin Yu case 96000: 92*607ac485SJiaxin Yu return MTK_AFE_ADDA_DL_RATE_96K; 93*607ac485SJiaxin Yu case 192000: 94*607ac485SJiaxin Yu return MTK_AFE_ADDA_DL_RATE_192K; 95*607ac485SJiaxin Yu default: 96*607ac485SJiaxin Yu dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n", 97*607ac485SJiaxin Yu __func__, rate); 98*607ac485SJiaxin Yu return MTK_AFE_ADDA_DL_RATE_48K; 99*607ac485SJiaxin Yu } 100*607ac485SJiaxin Yu } 101*607ac485SJiaxin Yu 102*607ac485SJiaxin Yu static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe, 103*607ac485SJiaxin Yu unsigned int rate) 104*607ac485SJiaxin Yu { 105*607ac485SJiaxin Yu switch (rate) { 106*607ac485SJiaxin Yu case 8000: 107*607ac485SJiaxin Yu return MTK_AFE_ADDA_UL_RATE_8K; 108*607ac485SJiaxin Yu case 16000: 109*607ac485SJiaxin Yu return MTK_AFE_ADDA_UL_RATE_16K; 110*607ac485SJiaxin Yu case 32000: 111*607ac485SJiaxin Yu return MTK_AFE_ADDA_UL_RATE_32K; 112*607ac485SJiaxin Yu case 48000: 113*607ac485SJiaxin Yu return MTK_AFE_ADDA_UL_RATE_48K; 114*607ac485SJiaxin Yu case 96000: 115*607ac485SJiaxin Yu return MTK_AFE_ADDA_UL_RATE_96K; 116*607ac485SJiaxin Yu case 192000: 117*607ac485SJiaxin Yu return MTK_AFE_ADDA_UL_RATE_192K; 118*607ac485SJiaxin Yu default: 119*607ac485SJiaxin Yu dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n", 120*607ac485SJiaxin Yu __func__, rate); 121*607ac485SJiaxin Yu return MTK_AFE_ADDA_UL_RATE_48K; 122*607ac485SJiaxin Yu } 123*607ac485SJiaxin Yu } 124*607ac485SJiaxin Yu 125*607ac485SJiaxin Yu /* dai component */ 126*607ac485SJiaxin Yu static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = { 127*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0), 128*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN3, I_DL12_CH1, 1, 0), 129*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0), 130*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0), 131*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN3_1, I_DL4_CH1, 1, 0), 132*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN3_1, I_DL5_CH1, 1, 0), 133*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN3_1, I_DL6_CH1, 1, 0), 134*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN3_1, I_DL8_CH1, 1, 0), 135*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN3, 136*607ac485SJiaxin Yu I_ADDA_UL_CH3, 1, 0), 137*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3, 138*607ac485SJiaxin Yu I_ADDA_UL_CH2, 1, 0), 139*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3, 140*607ac485SJiaxin Yu I_ADDA_UL_CH1, 1, 0), 141*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN3, 142*607ac485SJiaxin Yu I_GAIN1_OUT_CH1, 1, 0), 143*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3, 144*607ac485SJiaxin Yu I_PCM_1_CAP_CH1, 1, 0), 145*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3, 146*607ac485SJiaxin Yu I_PCM_2_CAP_CH1, 1, 0), 147*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1", AFE_CONN3_1, 148*607ac485SJiaxin Yu I_SRC_1_OUT_CH1, 1, 0), 149*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH1", AFE_CONN3_1, 150*607ac485SJiaxin Yu I_SRC_2_OUT_CH1, 1, 0), 151*607ac485SJiaxin Yu }; 152*607ac485SJiaxin Yu 153*607ac485SJiaxin Yu static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = { 154*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0), 155*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0), 156*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN4, I_DL12_CH2, 1, 0), 157*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0), 158*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0), 159*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0), 160*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0), 161*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN4_1, I_DL4_CH2, 1, 0), 162*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN4_1, I_DL5_CH2, 1, 0), 163*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN4_1, I_DL6_CH2, 1, 0), 164*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN4_1, I_DL8_CH2, 1, 0), 165*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN4, 166*607ac485SJiaxin Yu I_ADDA_UL_CH3, 1, 0), 167*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4, 168*607ac485SJiaxin Yu I_ADDA_UL_CH2, 1, 0), 169*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4, 170*607ac485SJiaxin Yu I_ADDA_UL_CH1, 1, 0), 171*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN4, 172*607ac485SJiaxin Yu I_GAIN1_OUT_CH2, 1, 0), 173*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4, 174*607ac485SJiaxin Yu I_PCM_1_CAP_CH1, 1, 0), 175*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4, 176*607ac485SJiaxin Yu I_PCM_2_CAP_CH1, 1, 0), 177*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4, 178*607ac485SJiaxin Yu I_PCM_1_CAP_CH2, 1, 0), 179*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4, 180*607ac485SJiaxin Yu I_PCM_2_CAP_CH2, 1, 0), 181*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2", AFE_CONN4_1, 182*607ac485SJiaxin Yu I_SRC_1_OUT_CH2, 1, 0), 183*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH2", AFE_CONN4_1, 184*607ac485SJiaxin Yu I_SRC_2_OUT_CH2, 1, 0), 185*607ac485SJiaxin Yu }; 186*607ac485SJiaxin Yu 187*607ac485SJiaxin Yu static const struct snd_kcontrol_new mtk_adda_dl_ch3_mix[] = { 188*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN52, I_DL1_CH1, 1, 0), 189*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN52, I_DL12_CH1, 1, 0), 190*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN52, I_DL2_CH1, 1, 0), 191*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN52, I_DL3_CH1, 1, 0), 192*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN52_1, I_DL4_CH1, 1, 0), 193*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN52_1, I_DL5_CH1, 1, 0), 194*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN52_1, I_DL6_CH1, 1, 0), 195*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN52, 196*607ac485SJiaxin Yu I_ADDA_UL_CH3, 1, 0), 197*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN52, 198*607ac485SJiaxin Yu I_ADDA_UL_CH2, 1, 0), 199*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN52, 200*607ac485SJiaxin Yu I_ADDA_UL_CH1, 1, 0), 201*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN52, 202*607ac485SJiaxin Yu I_GAIN1_OUT_CH1, 1, 0), 203*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN52, 204*607ac485SJiaxin Yu I_PCM_1_CAP_CH1, 1, 0), 205*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN52, 206*607ac485SJiaxin Yu I_PCM_2_CAP_CH1, 1, 0), 207*607ac485SJiaxin Yu }; 208*607ac485SJiaxin Yu 209*607ac485SJiaxin Yu static const struct snd_kcontrol_new mtk_adda_dl_ch4_mix[] = { 210*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN53, I_DL1_CH1, 1, 0), 211*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN53, I_DL1_CH2, 1, 0), 212*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN53, I_DL12_CH2, 1, 0), 213*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN53, I_DL2_CH1, 1, 0), 214*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN53, I_DL2_CH2, 1, 0), 215*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN53, I_DL3_CH1, 1, 0), 216*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN53, I_DL3_CH2, 1, 0), 217*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN53_1, I_DL4_CH2, 1, 0), 218*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN53_1, I_DL5_CH2, 1, 0), 219*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN53_1, I_DL6_CH1, 1, 0), 220*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN53, 221*607ac485SJiaxin Yu I_ADDA_UL_CH3, 1, 0), 222*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN53, 223*607ac485SJiaxin Yu I_ADDA_UL_CH2, 1, 0), 224*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN53, 225*607ac485SJiaxin Yu I_ADDA_UL_CH1, 1, 0), 226*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN53, 227*607ac485SJiaxin Yu I_GAIN1_OUT_CH2, 1, 0), 228*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN53, 229*607ac485SJiaxin Yu I_PCM_1_CAP_CH1, 1, 0), 230*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN53, 231*607ac485SJiaxin Yu I_PCM_2_CAP_CH1, 1, 0), 232*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN53, 233*607ac485SJiaxin Yu I_PCM_1_CAP_CH2, 1, 0), 234*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN53, 235*607ac485SJiaxin Yu I_PCM_2_CAP_CH2, 1, 0), 236*607ac485SJiaxin Yu }; 237*607ac485SJiaxin Yu 238*607ac485SJiaxin Yu static const struct snd_kcontrol_new mtk_stf_ch1_mix[] = { 239*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN19, 240*607ac485SJiaxin Yu I_ADDA_UL_CH1, 1, 0), 241*607ac485SJiaxin Yu }; 242*607ac485SJiaxin Yu 243*607ac485SJiaxin Yu static const struct snd_kcontrol_new mtk_stf_ch2_mix[] = { 244*607ac485SJiaxin Yu SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN20, 245*607ac485SJiaxin Yu I_ADDA_UL_CH2, 1, 0), 246*607ac485SJiaxin Yu }; 247*607ac485SJiaxin Yu 248*607ac485SJiaxin Yu enum { 249*607ac485SJiaxin Yu SUPPLY_SEQ_ADDA_AFE_ON, 250*607ac485SJiaxin Yu SUPPLY_SEQ_ADDA_DL_ON, 251*607ac485SJiaxin Yu SUPPLY_SEQ_ADDA_AUD_PAD_TOP, 252*607ac485SJiaxin Yu SUPPLY_SEQ_ADDA_MTKAIF_CFG, 253*607ac485SJiaxin Yu SUPPLY_SEQ_ADDA6_MTKAIF_CFG, 254*607ac485SJiaxin Yu SUPPLY_SEQ_ADDA_FIFO, 255*607ac485SJiaxin Yu SUPPLY_SEQ_ADDA_AP_DMIC, 256*607ac485SJiaxin Yu SUPPLY_SEQ_ADDA_UL_ON, 257*607ac485SJiaxin Yu }; 258*607ac485SJiaxin Yu 259*607ac485SJiaxin Yu static int mtk_adda_ul_src_dmic(struct mtk_base_afe *afe, int id) 260*607ac485SJiaxin Yu { 261*607ac485SJiaxin Yu unsigned int reg; 262*607ac485SJiaxin Yu 263*607ac485SJiaxin Yu switch (id) { 264*607ac485SJiaxin Yu case MT8192_DAI_ADDA: 265*607ac485SJiaxin Yu case MT8192_DAI_AP_DMIC: 266*607ac485SJiaxin Yu reg = AFE_ADDA_UL_SRC_CON0; 267*607ac485SJiaxin Yu break; 268*607ac485SJiaxin Yu case MT8192_DAI_ADDA_CH34: 269*607ac485SJiaxin Yu case MT8192_DAI_AP_DMIC_CH34: 270*607ac485SJiaxin Yu reg = AFE_ADDA6_UL_SRC_CON0; 271*607ac485SJiaxin Yu break; 272*607ac485SJiaxin Yu default: 273*607ac485SJiaxin Yu return -EINVAL; 274*607ac485SJiaxin Yu } 275*607ac485SJiaxin Yu 276*607ac485SJiaxin Yu /* dmic mode, 3.25M*/ 277*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, reg, 278*607ac485SJiaxin Yu DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT, 279*607ac485SJiaxin Yu 0x0); 280*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, reg, 281*607ac485SJiaxin Yu DMIC_LOW_POWER_MODE_CTL_MASK_SFT, 282*607ac485SJiaxin Yu 0x0); 283*607ac485SJiaxin Yu 284*607ac485SJiaxin Yu /* turn on dmic, ch1, ch2 */ 285*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, reg, 286*607ac485SJiaxin Yu UL_SDM_3_LEVEL_CTL_MASK_SFT, 287*607ac485SJiaxin Yu 0x1 << UL_SDM_3_LEVEL_CTL_SFT); 288*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, reg, 289*607ac485SJiaxin Yu UL_MODE_3P25M_CH1_CTL_MASK_SFT, 290*607ac485SJiaxin Yu 0x1 << UL_MODE_3P25M_CH1_CTL_SFT); 291*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, reg, 292*607ac485SJiaxin Yu UL_MODE_3P25M_CH2_CTL_MASK_SFT, 293*607ac485SJiaxin Yu 0x1 << UL_MODE_3P25M_CH2_CTL_SFT); 294*607ac485SJiaxin Yu return 0; 295*607ac485SJiaxin Yu } 296*607ac485SJiaxin Yu 297*607ac485SJiaxin Yu static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w, 298*607ac485SJiaxin Yu struct snd_kcontrol *kcontrol, 299*607ac485SJiaxin Yu int event) 300*607ac485SJiaxin Yu { 301*607ac485SJiaxin Yu struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 302*607ac485SJiaxin Yu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 303*607ac485SJiaxin Yu struct mt8192_afe_private *afe_priv = afe->platform_priv; 304*607ac485SJiaxin Yu int mtkaif_dmic = afe_priv->mtkaif_dmic; 305*607ac485SJiaxin Yu 306*607ac485SJiaxin Yu dev_info(afe->dev, "%s(), name %s, event 0x%x, mtkaif_dmic %d\n", 307*607ac485SJiaxin Yu __func__, w->name, event, mtkaif_dmic); 308*607ac485SJiaxin Yu 309*607ac485SJiaxin Yu switch (event) { 310*607ac485SJiaxin Yu case SND_SOC_DAPM_PRE_PMU: 311*607ac485SJiaxin Yu mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA, 1); 312*607ac485SJiaxin Yu 313*607ac485SJiaxin Yu /* update setting to dmic */ 314*607ac485SJiaxin Yu if (mtkaif_dmic) { 315*607ac485SJiaxin Yu /* mtkaif_rxif_data_mode = 1, dmic */ 316*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, 317*607ac485SJiaxin Yu 0x1, 0x1); 318*607ac485SJiaxin Yu 319*607ac485SJiaxin Yu /* dmic mode, 3.25M*/ 320*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, 321*607ac485SJiaxin Yu MTKAIF_RXIF_VOICE_MODE_MASK_SFT, 322*607ac485SJiaxin Yu 0x0); 323*607ac485SJiaxin Yu mtk_adda_ul_src_dmic(afe, MT8192_DAI_ADDA); 324*607ac485SJiaxin Yu } 325*607ac485SJiaxin Yu break; 326*607ac485SJiaxin Yu case SND_SOC_DAPM_POST_PMD: 327*607ac485SJiaxin Yu /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 328*607ac485SJiaxin Yu usleep_range(125, 135); 329*607ac485SJiaxin Yu mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA, 1); 330*607ac485SJiaxin Yu break; 331*607ac485SJiaxin Yu default: 332*607ac485SJiaxin Yu break; 333*607ac485SJiaxin Yu } 334*607ac485SJiaxin Yu 335*607ac485SJiaxin Yu return 0; 336*607ac485SJiaxin Yu } 337*607ac485SJiaxin Yu 338*607ac485SJiaxin Yu static int mtk_adda_ch34_ul_event(struct snd_soc_dapm_widget *w, 339*607ac485SJiaxin Yu struct snd_kcontrol *kcontrol, 340*607ac485SJiaxin Yu int event) 341*607ac485SJiaxin Yu { 342*607ac485SJiaxin Yu struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 343*607ac485SJiaxin Yu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 344*607ac485SJiaxin Yu struct mt8192_afe_private *afe_priv = afe->platform_priv; 345*607ac485SJiaxin Yu int mtkaif_dmic = afe_priv->mtkaif_dmic_ch34; 346*607ac485SJiaxin Yu int mtkaif_adda6_only = afe_priv->mtkaif_adda6_only; 347*607ac485SJiaxin Yu 348*607ac485SJiaxin Yu dev_info(afe->dev, 349*607ac485SJiaxin Yu "%s(), name %s, event 0x%x, mtkaif_dmic %d, mtkaif_adda6_only %d\n", 350*607ac485SJiaxin Yu __func__, w->name, event, mtkaif_dmic, mtkaif_adda6_only); 351*607ac485SJiaxin Yu 352*607ac485SJiaxin Yu switch (event) { 353*607ac485SJiaxin Yu case SND_SOC_DAPM_PRE_PMU: 354*607ac485SJiaxin Yu mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA_CH34, 355*607ac485SJiaxin Yu 1); 356*607ac485SJiaxin Yu 357*607ac485SJiaxin Yu /* update setting to dmic */ 358*607ac485SJiaxin Yu if (mtkaif_dmic) { 359*607ac485SJiaxin Yu /* mtkaif_rxif_data_mode = 1, dmic */ 360*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 361*607ac485SJiaxin Yu AFE_ADDA6_MTKAIF_RX_CFG0, 362*607ac485SJiaxin Yu 0x1, 0x1); 363*607ac485SJiaxin Yu 364*607ac485SJiaxin Yu /* dmic mode, 3.25M*/ 365*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 366*607ac485SJiaxin Yu AFE_ADDA6_MTKAIF_RX_CFG0, 367*607ac485SJiaxin Yu MTKAIF_RXIF_VOICE_MODE_MASK_SFT, 368*607ac485SJiaxin Yu 0x0); 369*607ac485SJiaxin Yu mtk_adda_ul_src_dmic(afe, MT8192_DAI_ADDA_CH34); 370*607ac485SJiaxin Yu } 371*607ac485SJiaxin Yu 372*607ac485SJiaxin Yu /* when using adda6 without adda enabled, 373*607ac485SJiaxin Yu * RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_SFT need to be set or 374*607ac485SJiaxin Yu * data cannot be received. 375*607ac485SJiaxin Yu */ 376*607ac485SJiaxin Yu if (mtkaif_adda6_only) { 377*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 378*607ac485SJiaxin Yu AFE_ADDA_MTKAIF_SYNCWORD_CFG, 379*607ac485SJiaxin Yu 0x1 << 23, 0x1 << 23); 380*607ac485SJiaxin Yu } 381*607ac485SJiaxin Yu break; 382*607ac485SJiaxin Yu case SND_SOC_DAPM_POST_PMD: 383*607ac485SJiaxin Yu /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 384*607ac485SJiaxin Yu usleep_range(125, 135); 385*607ac485SJiaxin Yu mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA_CH34, 386*607ac485SJiaxin Yu 1); 387*607ac485SJiaxin Yu 388*607ac485SJiaxin Yu /* reset dmic */ 389*607ac485SJiaxin Yu afe_priv->mtkaif_dmic_ch34 = 0; 390*607ac485SJiaxin Yu 391*607ac485SJiaxin Yu if (mtkaif_adda6_only) { 392*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 393*607ac485SJiaxin Yu AFE_ADDA_MTKAIF_SYNCWORD_CFG, 394*607ac485SJiaxin Yu 0x1 << 23, 0x0 << 23); 395*607ac485SJiaxin Yu } 396*607ac485SJiaxin Yu break; 397*607ac485SJiaxin Yu default: 398*607ac485SJiaxin Yu break; 399*607ac485SJiaxin Yu } 400*607ac485SJiaxin Yu 401*607ac485SJiaxin Yu return 0; 402*607ac485SJiaxin Yu } 403*607ac485SJiaxin Yu 404*607ac485SJiaxin Yu static int mtk_adda_pad_top_event(struct snd_soc_dapm_widget *w, 405*607ac485SJiaxin Yu struct snd_kcontrol *kcontrol, 406*607ac485SJiaxin Yu int event) 407*607ac485SJiaxin Yu { 408*607ac485SJiaxin Yu struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 409*607ac485SJiaxin Yu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 410*607ac485SJiaxin Yu struct mt8192_afe_private *afe_priv = afe->platform_priv; 411*607ac485SJiaxin Yu 412*607ac485SJiaxin Yu switch (event) { 413*607ac485SJiaxin Yu case SND_SOC_DAPM_PRE_PMU: 414*607ac485SJiaxin Yu if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) 415*607ac485SJiaxin Yu regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x38); 416*607ac485SJiaxin Yu else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2) 417*607ac485SJiaxin Yu regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x30); 418*607ac485SJiaxin Yu else 419*607ac485SJiaxin Yu regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x30); 420*607ac485SJiaxin Yu break; 421*607ac485SJiaxin Yu default: 422*607ac485SJiaxin Yu break; 423*607ac485SJiaxin Yu } 424*607ac485SJiaxin Yu 425*607ac485SJiaxin Yu return 0; 426*607ac485SJiaxin Yu } 427*607ac485SJiaxin Yu 428*607ac485SJiaxin Yu static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w, 429*607ac485SJiaxin Yu struct snd_kcontrol *kcontrol, 430*607ac485SJiaxin Yu int event) 431*607ac485SJiaxin Yu { 432*607ac485SJiaxin Yu struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 433*607ac485SJiaxin Yu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 434*607ac485SJiaxin Yu struct mt8192_afe_private *afe_priv = afe->platform_priv; 435*607ac485SJiaxin Yu int delay_data; 436*607ac485SJiaxin Yu int delay_cycle; 437*607ac485SJiaxin Yu 438*607ac485SJiaxin Yu switch (event) { 439*607ac485SJiaxin Yu case SND_SOC_DAPM_PRE_PMU: 440*607ac485SJiaxin Yu if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) { 441*607ac485SJiaxin Yu /* set protocol 2 */ 442*607ac485SJiaxin Yu regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 443*607ac485SJiaxin Yu 0x00010000); 444*607ac485SJiaxin Yu regmap_write(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, 445*607ac485SJiaxin Yu 0x00010000); 446*607ac485SJiaxin Yu 447*607ac485SJiaxin Yu if (strcmp(w->name, "ADDA_MTKAIF_CFG") == 0 && 448*607ac485SJiaxin Yu (afe_priv->mtkaif_chosen_phase[0] < 0 || 449*607ac485SJiaxin Yu afe_priv->mtkaif_chosen_phase[1] < 0)) { 450*607ac485SJiaxin Yu dev_warn(afe->dev, 451*607ac485SJiaxin Yu "%s(), mtkaif_chosen_phase[0/1]:%d/%d\n", 452*607ac485SJiaxin Yu __func__, 453*607ac485SJiaxin Yu afe_priv->mtkaif_chosen_phase[0], 454*607ac485SJiaxin Yu afe_priv->mtkaif_chosen_phase[1]); 455*607ac485SJiaxin Yu break; 456*607ac485SJiaxin Yu } else if (strcmp(w->name, "ADDA6_MTKAIF_CFG") == 0 && 457*607ac485SJiaxin Yu afe_priv->mtkaif_chosen_phase[2] < 0) { 458*607ac485SJiaxin Yu dev_warn(afe->dev, 459*607ac485SJiaxin Yu "%s(), mtkaif_chosen_phase[2]:%d\n", 460*607ac485SJiaxin Yu __func__, 461*607ac485SJiaxin Yu afe_priv->mtkaif_chosen_phase[2]); 462*607ac485SJiaxin Yu break; 463*607ac485SJiaxin Yu } 464*607ac485SJiaxin Yu 465*607ac485SJiaxin Yu /* mtkaif_rxif_clkinv_adc inverse for calibration */ 466*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 467*607ac485SJiaxin Yu MTKAIF_RXIF_CLKINV_ADC_MASK_SFT, 468*607ac485SJiaxin Yu 0x1 << MTKAIF_RXIF_CLKINV_ADC_SFT); 469*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, 470*607ac485SJiaxin Yu MTKAIF_RXIF_CLKINV_ADC_MASK_SFT, 471*607ac485SJiaxin Yu 0x1 << MTKAIF_RXIF_CLKINV_ADC_SFT); 472*607ac485SJiaxin Yu 473*607ac485SJiaxin Yu /* set delay for ch12 */ 474*607ac485SJiaxin Yu if (afe_priv->mtkaif_phase_cycle[0] >= 475*607ac485SJiaxin Yu afe_priv->mtkaif_phase_cycle[1]) { 476*607ac485SJiaxin Yu delay_data = DELAY_DATA_MISO1; 477*607ac485SJiaxin Yu delay_cycle = afe_priv->mtkaif_phase_cycle[0] - 478*607ac485SJiaxin Yu afe_priv->mtkaif_phase_cycle[1]; 479*607ac485SJiaxin Yu } else { 480*607ac485SJiaxin Yu delay_data = DELAY_DATA_MISO2; 481*607ac485SJiaxin Yu delay_cycle = afe_priv->mtkaif_phase_cycle[1] - 482*607ac485SJiaxin Yu afe_priv->mtkaif_phase_cycle[0]; 483*607ac485SJiaxin Yu } 484*607ac485SJiaxin Yu 485*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 486*607ac485SJiaxin Yu AFE_ADDA_MTKAIF_RX_CFG2, 487*607ac485SJiaxin Yu MTKAIF_RXIF_DELAY_DATA_MASK_SFT, 488*607ac485SJiaxin Yu delay_data << 489*607ac485SJiaxin Yu MTKAIF_RXIF_DELAY_DATA_SFT); 490*607ac485SJiaxin Yu 491*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 492*607ac485SJiaxin Yu AFE_ADDA_MTKAIF_RX_CFG2, 493*607ac485SJiaxin Yu MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT, 494*607ac485SJiaxin Yu delay_cycle << 495*607ac485SJiaxin Yu MTKAIF_RXIF_DELAY_CYCLE_SFT); 496*607ac485SJiaxin Yu 497*607ac485SJiaxin Yu /* set delay between ch3 and ch2 */ 498*607ac485SJiaxin Yu if (afe_priv->mtkaif_phase_cycle[2] >= 499*607ac485SJiaxin Yu afe_priv->mtkaif_phase_cycle[1]) { 500*607ac485SJiaxin Yu delay_data = DELAY_DATA_MISO1; /* ch3 */ 501*607ac485SJiaxin Yu delay_cycle = afe_priv->mtkaif_phase_cycle[2] - 502*607ac485SJiaxin Yu afe_priv->mtkaif_phase_cycle[1]; 503*607ac485SJiaxin Yu } else { 504*607ac485SJiaxin Yu delay_data = DELAY_DATA_MISO2; /* ch2 */ 505*607ac485SJiaxin Yu delay_cycle = afe_priv->mtkaif_phase_cycle[1] - 506*607ac485SJiaxin Yu afe_priv->mtkaif_phase_cycle[2]; 507*607ac485SJiaxin Yu } 508*607ac485SJiaxin Yu 509*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 510*607ac485SJiaxin Yu AFE_ADDA6_MTKAIF_RX_CFG2, 511*607ac485SJiaxin Yu MTKAIF_RXIF_DELAY_DATA_MASK_SFT, 512*607ac485SJiaxin Yu delay_data << 513*607ac485SJiaxin Yu MTKAIF_RXIF_DELAY_DATA_SFT); 514*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 515*607ac485SJiaxin Yu AFE_ADDA6_MTKAIF_RX_CFG2, 516*607ac485SJiaxin Yu MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT, 517*607ac485SJiaxin Yu delay_cycle << 518*607ac485SJiaxin Yu MTKAIF_RXIF_DELAY_CYCLE_SFT); 519*607ac485SJiaxin Yu } else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2) { 520*607ac485SJiaxin Yu regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 521*607ac485SJiaxin Yu 0x00010000); 522*607ac485SJiaxin Yu regmap_write(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, 523*607ac485SJiaxin Yu 0x00010000); 524*607ac485SJiaxin Yu } else { 525*607ac485SJiaxin Yu regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x0); 526*607ac485SJiaxin Yu regmap_write(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, 0x0); 527*607ac485SJiaxin Yu } 528*607ac485SJiaxin Yu break; 529*607ac485SJiaxin Yu default: 530*607ac485SJiaxin Yu break; 531*607ac485SJiaxin Yu } 532*607ac485SJiaxin Yu 533*607ac485SJiaxin Yu return 0; 534*607ac485SJiaxin Yu } 535*607ac485SJiaxin Yu 536*607ac485SJiaxin Yu static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w, 537*607ac485SJiaxin Yu struct snd_kcontrol *kcontrol, 538*607ac485SJiaxin Yu int event) 539*607ac485SJiaxin Yu { 540*607ac485SJiaxin Yu struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 541*607ac485SJiaxin Yu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 542*607ac485SJiaxin Yu 543*607ac485SJiaxin Yu dev_info(afe->dev, "%s(), name %s, event 0x%x\n", 544*607ac485SJiaxin Yu __func__, w->name, event); 545*607ac485SJiaxin Yu 546*607ac485SJiaxin Yu switch (event) { 547*607ac485SJiaxin Yu case SND_SOC_DAPM_PRE_PMU: 548*607ac485SJiaxin Yu mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA, 0); 549*607ac485SJiaxin Yu break; 550*607ac485SJiaxin Yu case SND_SOC_DAPM_POST_PMD: 551*607ac485SJiaxin Yu /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 552*607ac485SJiaxin Yu usleep_range(125, 135); 553*607ac485SJiaxin Yu mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA, 0); 554*607ac485SJiaxin Yu break; 555*607ac485SJiaxin Yu default: 556*607ac485SJiaxin Yu break; 557*607ac485SJiaxin Yu } 558*607ac485SJiaxin Yu 559*607ac485SJiaxin Yu return 0; 560*607ac485SJiaxin Yu } 561*607ac485SJiaxin Yu 562*607ac485SJiaxin Yu static int mtk_adda_ch34_dl_event(struct snd_soc_dapm_widget *w, 563*607ac485SJiaxin Yu struct snd_kcontrol *kcontrol, 564*607ac485SJiaxin Yu int event) 565*607ac485SJiaxin Yu { 566*607ac485SJiaxin Yu struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 567*607ac485SJiaxin Yu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 568*607ac485SJiaxin Yu 569*607ac485SJiaxin Yu dev_info(afe->dev, "%s(), name %s, event 0x%x\n", 570*607ac485SJiaxin Yu __func__, w->name, event); 571*607ac485SJiaxin Yu 572*607ac485SJiaxin Yu switch (event) { 573*607ac485SJiaxin Yu case SND_SOC_DAPM_PRE_PMU: 574*607ac485SJiaxin Yu mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA_CH34, 575*607ac485SJiaxin Yu 0); 576*607ac485SJiaxin Yu break; 577*607ac485SJiaxin Yu case SND_SOC_DAPM_POST_PMD: 578*607ac485SJiaxin Yu /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 579*607ac485SJiaxin Yu usleep_range(125, 135); 580*607ac485SJiaxin Yu mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA_CH34, 581*607ac485SJiaxin Yu 0); 582*607ac485SJiaxin Yu break; 583*607ac485SJiaxin Yu default: 584*607ac485SJiaxin Yu break; 585*607ac485SJiaxin Yu } 586*607ac485SJiaxin Yu 587*607ac485SJiaxin Yu return 0; 588*607ac485SJiaxin Yu } 589*607ac485SJiaxin Yu 590*607ac485SJiaxin Yu /* stf */ 591*607ac485SJiaxin Yu static int stf_positive_gain_get(struct snd_kcontrol *kcontrol, 592*607ac485SJiaxin Yu struct snd_ctl_elem_value *ucontrol) 593*607ac485SJiaxin Yu { 594*607ac485SJiaxin Yu struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 595*607ac485SJiaxin Yu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 596*607ac485SJiaxin Yu struct mt8192_afe_private *afe_priv = afe->platform_priv; 597*607ac485SJiaxin Yu 598*607ac485SJiaxin Yu ucontrol->value.integer.value[0] = afe_priv->stf_positive_gain_db; 599*607ac485SJiaxin Yu return 0; 600*607ac485SJiaxin Yu } 601*607ac485SJiaxin Yu 602*607ac485SJiaxin Yu static int stf_positive_gain_set(struct snd_kcontrol *kcontrol, 603*607ac485SJiaxin Yu struct snd_ctl_elem_value *ucontrol) 604*607ac485SJiaxin Yu { 605*607ac485SJiaxin Yu struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 606*607ac485SJiaxin Yu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 607*607ac485SJiaxin Yu struct mt8192_afe_private *afe_priv = afe->platform_priv; 608*607ac485SJiaxin Yu int gain_db = ucontrol->value.integer.value[0]; 609*607ac485SJiaxin Yu 610*607ac485SJiaxin Yu afe_priv->stf_positive_gain_db = gain_db; 611*607ac485SJiaxin Yu 612*607ac485SJiaxin Yu if (gain_db >= 0 && gain_db <= 24) { 613*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 614*607ac485SJiaxin Yu AFE_SIDETONE_GAIN, 615*607ac485SJiaxin Yu POSITIVE_GAIN_MASK_SFT, 616*607ac485SJiaxin Yu (gain_db / 6) << POSITIVE_GAIN_SFT); 617*607ac485SJiaxin Yu } else { 618*607ac485SJiaxin Yu dev_warn(afe->dev, "%s(), gain_db %d invalid\n", 619*607ac485SJiaxin Yu __func__, gain_db); 620*607ac485SJiaxin Yu } 621*607ac485SJiaxin Yu return 0; 622*607ac485SJiaxin Yu } 623*607ac485SJiaxin Yu 624*607ac485SJiaxin Yu static int mt8192_adda_dmic_get(struct snd_kcontrol *kcontrol, 625*607ac485SJiaxin Yu struct snd_ctl_elem_value *ucontrol) 626*607ac485SJiaxin Yu { 627*607ac485SJiaxin Yu struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 628*607ac485SJiaxin Yu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 629*607ac485SJiaxin Yu struct mt8192_afe_private *afe_priv = afe->platform_priv; 630*607ac485SJiaxin Yu 631*607ac485SJiaxin Yu ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic; 632*607ac485SJiaxin Yu return 0; 633*607ac485SJiaxin Yu } 634*607ac485SJiaxin Yu 635*607ac485SJiaxin Yu static int mt8192_adda_dmic_set(struct snd_kcontrol *kcontrol, 636*607ac485SJiaxin Yu struct snd_ctl_elem_value *ucontrol) 637*607ac485SJiaxin Yu { 638*607ac485SJiaxin Yu struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 639*607ac485SJiaxin Yu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 640*607ac485SJiaxin Yu struct mt8192_afe_private *afe_priv = afe->platform_priv; 641*607ac485SJiaxin Yu int dmic_on; 642*607ac485SJiaxin Yu 643*607ac485SJiaxin Yu dmic_on = ucontrol->value.integer.value[0]; 644*607ac485SJiaxin Yu 645*607ac485SJiaxin Yu dev_info(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n", 646*607ac485SJiaxin Yu __func__, kcontrol->id.name, dmic_on); 647*607ac485SJiaxin Yu 648*607ac485SJiaxin Yu afe_priv->mtkaif_dmic = dmic_on; 649*607ac485SJiaxin Yu afe_priv->mtkaif_dmic_ch34 = dmic_on; 650*607ac485SJiaxin Yu return 0; 651*607ac485SJiaxin Yu } 652*607ac485SJiaxin Yu 653*607ac485SJiaxin Yu static int mt8192_adda6_only_get(struct snd_kcontrol *kcontrol, 654*607ac485SJiaxin Yu struct snd_ctl_elem_value *ucontrol) 655*607ac485SJiaxin Yu { 656*607ac485SJiaxin Yu struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 657*607ac485SJiaxin Yu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 658*607ac485SJiaxin Yu struct mt8192_afe_private *afe_priv = afe->platform_priv; 659*607ac485SJiaxin Yu 660*607ac485SJiaxin Yu ucontrol->value.integer.value[0] = afe_priv->mtkaif_adda6_only; 661*607ac485SJiaxin Yu return 0; 662*607ac485SJiaxin Yu } 663*607ac485SJiaxin Yu 664*607ac485SJiaxin Yu static int mt8192_adda6_only_set(struct snd_kcontrol *kcontrol, 665*607ac485SJiaxin Yu struct snd_ctl_elem_value *ucontrol) 666*607ac485SJiaxin Yu { 667*607ac485SJiaxin Yu struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 668*607ac485SJiaxin Yu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 669*607ac485SJiaxin Yu struct mt8192_afe_private *afe_priv = afe->platform_priv; 670*607ac485SJiaxin Yu int mtkaif_adda6_only; 671*607ac485SJiaxin Yu 672*607ac485SJiaxin Yu mtkaif_adda6_only = ucontrol->value.integer.value[0]; 673*607ac485SJiaxin Yu 674*607ac485SJiaxin Yu dev_info(afe->dev, "%s(), kcontrol name %s, mtkaif_adda6_only %d\n", 675*607ac485SJiaxin Yu __func__, kcontrol->id.name, mtkaif_adda6_only); 676*607ac485SJiaxin Yu 677*607ac485SJiaxin Yu afe_priv->mtkaif_adda6_only = mtkaif_adda6_only; 678*607ac485SJiaxin Yu return 0; 679*607ac485SJiaxin Yu } 680*607ac485SJiaxin Yu 681*607ac485SJiaxin Yu static const struct snd_kcontrol_new mtk_adda_controls[] = { 682*607ac485SJiaxin Yu SOC_SINGLE("Sidetone_Gain", AFE_SIDETONE_GAIN, 683*607ac485SJiaxin Yu SIDE_TONE_GAIN_SFT, SIDE_TONE_GAIN_MASK, 0), 684*607ac485SJiaxin Yu SOC_SINGLE_EXT("Sidetone_Positive_Gain_dB", SND_SOC_NOPM, 0, 100, 0, 685*607ac485SJiaxin Yu stf_positive_gain_get, stf_positive_gain_set), 686*607ac485SJiaxin Yu SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1, 687*607ac485SJiaxin Yu DL_2_GAIN_CTL_PRE_SFT, DL_2_GAIN_CTL_PRE_MASK, 0), 688*607ac485SJiaxin Yu SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0, 689*607ac485SJiaxin Yu mt8192_adda_dmic_get, mt8192_adda_dmic_set), 690*607ac485SJiaxin Yu SOC_SINGLE_BOOL_EXT("MTKAIF_ADDA6_ONLY Switch", 0, 691*607ac485SJiaxin Yu mt8192_adda6_only_get, mt8192_adda6_only_set), 692*607ac485SJiaxin Yu }; 693*607ac485SJiaxin Yu 694*607ac485SJiaxin Yu static const struct snd_kcontrol_new stf_ctl = 695*607ac485SJiaxin Yu SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0); 696*607ac485SJiaxin Yu 697*607ac485SJiaxin Yu static const u16 stf_coeff_table_16k[] = { 698*607ac485SJiaxin Yu 0x049C, 0x09E8, 0x09E0, 0x089C, 699*607ac485SJiaxin Yu 0xFF54, 0xF488, 0xEAFC, 0xEBAC, 700*607ac485SJiaxin Yu 0xfA40, 0x17AC, 0x3D1C, 0x6028, 701*607ac485SJiaxin Yu 0x7538 702*607ac485SJiaxin Yu }; 703*607ac485SJiaxin Yu 704*607ac485SJiaxin Yu static const u16 stf_coeff_table_32k[] = { 705*607ac485SJiaxin Yu 0xFE52, 0x0042, 0x00C5, 0x0194, 706*607ac485SJiaxin Yu 0x029A, 0x03B7, 0x04BF, 0x057D, 707*607ac485SJiaxin Yu 0x05BE, 0x0555, 0x0426, 0x0230, 708*607ac485SJiaxin Yu 0xFF92, 0xFC89, 0xF973, 0xF6C6, 709*607ac485SJiaxin Yu 0xF500, 0xF49D, 0xF603, 0xF970, 710*607ac485SJiaxin Yu 0xFEF3, 0x065F, 0x0F4F, 0x1928, 711*607ac485SJiaxin Yu 0x2329, 0x2C80, 0x345E, 0x3A0D, 712*607ac485SJiaxin Yu 0x3D08 713*607ac485SJiaxin Yu }; 714*607ac485SJiaxin Yu 715*607ac485SJiaxin Yu static const u16 stf_coeff_table_48k[] = { 716*607ac485SJiaxin Yu 0x0401, 0xFFB0, 0xFF5A, 0xFECE, 717*607ac485SJiaxin Yu 0xFE10, 0xFD28, 0xFC21, 0xFB08, 718*607ac485SJiaxin Yu 0xF9EF, 0xF8E8, 0xF80A, 0xF76C, 719*607ac485SJiaxin Yu 0xF724, 0xF746, 0xF7E6, 0xF90F, 720*607ac485SJiaxin Yu 0xFACC, 0xFD1E, 0xFFFF, 0x0364, 721*607ac485SJiaxin Yu 0x0737, 0x0B62, 0x0FC1, 0x1431, 722*607ac485SJiaxin Yu 0x188A, 0x1CA4, 0x2056, 0x237D, 723*607ac485SJiaxin Yu 0x25F9, 0x27B0, 0x2890 724*607ac485SJiaxin Yu }; 725*607ac485SJiaxin Yu 726*607ac485SJiaxin Yu static int mtk_stf_event(struct snd_soc_dapm_widget *w, 727*607ac485SJiaxin Yu struct snd_kcontrol *kcontrol, 728*607ac485SJiaxin Yu int event) 729*607ac485SJiaxin Yu { 730*607ac485SJiaxin Yu struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 731*607ac485SJiaxin Yu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 732*607ac485SJiaxin Yu 733*607ac485SJiaxin Yu size_t half_tap_num; 734*607ac485SJiaxin Yu const u16 *stf_coeff_table; 735*607ac485SJiaxin Yu unsigned int ul_rate, reg_value; 736*607ac485SJiaxin Yu size_t coef_addr; 737*607ac485SJiaxin Yu 738*607ac485SJiaxin Yu regmap_read(afe->regmap, AFE_ADDA_UL_SRC_CON0, &ul_rate); 739*607ac485SJiaxin Yu ul_rate = ul_rate >> UL_VOICE_MODE_CH1_CH2_CTL_SFT; 740*607ac485SJiaxin Yu ul_rate = ul_rate & UL_VOICE_MODE_CH1_CH2_CTL_MASK; 741*607ac485SJiaxin Yu 742*607ac485SJiaxin Yu if (ul_rate == MTK_AFE_ADDA_UL_RATE_48K) { 743*607ac485SJiaxin Yu half_tap_num = ARRAY_SIZE(stf_coeff_table_48k); 744*607ac485SJiaxin Yu stf_coeff_table = stf_coeff_table_48k; 745*607ac485SJiaxin Yu } else if (ul_rate == MTK_AFE_ADDA_UL_RATE_32K) { 746*607ac485SJiaxin Yu half_tap_num = ARRAY_SIZE(stf_coeff_table_32k); 747*607ac485SJiaxin Yu stf_coeff_table = stf_coeff_table_32k; 748*607ac485SJiaxin Yu } else { 749*607ac485SJiaxin Yu half_tap_num = ARRAY_SIZE(stf_coeff_table_16k); 750*607ac485SJiaxin Yu stf_coeff_table = stf_coeff_table_16k; 751*607ac485SJiaxin Yu } 752*607ac485SJiaxin Yu 753*607ac485SJiaxin Yu regmap_read(afe->regmap, AFE_SIDETONE_CON1, ®_value); 754*607ac485SJiaxin Yu 755*607ac485SJiaxin Yu dev_info(afe->dev, "%s(), name %s, event 0x%x, ul_rate 0x%x, AFE_SIDETONE_CON1 0x%x\n", 756*607ac485SJiaxin Yu __func__, w->name, event, ul_rate, reg_value); 757*607ac485SJiaxin Yu 758*607ac485SJiaxin Yu switch (event) { 759*607ac485SJiaxin Yu case SND_SOC_DAPM_PRE_PMU: 760*607ac485SJiaxin Yu /* set side tone gain = 0 */ 761*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 762*607ac485SJiaxin Yu AFE_SIDETONE_GAIN, 763*607ac485SJiaxin Yu SIDE_TONE_GAIN_MASK_SFT, 764*607ac485SJiaxin Yu 0); 765*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 766*607ac485SJiaxin Yu AFE_SIDETONE_GAIN, 767*607ac485SJiaxin Yu POSITIVE_GAIN_MASK_SFT, 768*607ac485SJiaxin Yu 0); 769*607ac485SJiaxin Yu /* don't bypass stf */ 770*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 771*607ac485SJiaxin Yu AFE_SIDETONE_CON1, 772*607ac485SJiaxin Yu 0x1f << 27, 773*607ac485SJiaxin Yu 0x0); 774*607ac485SJiaxin Yu /* set stf half tap num */ 775*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 776*607ac485SJiaxin Yu AFE_SIDETONE_CON1, 777*607ac485SJiaxin Yu SIDE_TONE_HALF_TAP_NUM_MASK_SFT, 778*607ac485SJiaxin Yu half_tap_num << SIDE_TONE_HALF_TAP_NUM_SFT); 779*607ac485SJiaxin Yu 780*607ac485SJiaxin Yu /* set side tone coefficient */ 781*607ac485SJiaxin Yu regmap_read(afe->regmap, AFE_SIDETONE_CON0, ®_value); 782*607ac485SJiaxin Yu for (coef_addr = 0; coef_addr < half_tap_num; coef_addr++) { 783*607ac485SJiaxin Yu bool old_w_ready = (reg_value >> W_RDY_SFT) & 0x1; 784*607ac485SJiaxin Yu bool new_w_ready = 0; 785*607ac485SJiaxin Yu int try_cnt = 0; 786*607ac485SJiaxin Yu 787*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 788*607ac485SJiaxin Yu AFE_SIDETONE_CON0, 789*607ac485SJiaxin Yu 0x39FFFFF, 790*607ac485SJiaxin Yu (1 << R_W_EN_SFT) | 791*607ac485SJiaxin Yu (1 << R_W_SEL_SFT) | 792*607ac485SJiaxin Yu (0 << SEL_CH2_SFT) | 793*607ac485SJiaxin Yu (coef_addr << 794*607ac485SJiaxin Yu SIDE_TONE_COEFFICIENT_ADDR_SFT) | 795*607ac485SJiaxin Yu stf_coeff_table[coef_addr]); 796*607ac485SJiaxin Yu 797*607ac485SJiaxin Yu /* wait until flag write_ready changed */ 798*607ac485SJiaxin Yu for (try_cnt = 0; try_cnt < 10; try_cnt++) { 799*607ac485SJiaxin Yu regmap_read(afe->regmap, 800*607ac485SJiaxin Yu AFE_SIDETONE_CON0, ®_value); 801*607ac485SJiaxin Yu new_w_ready = (reg_value >> W_RDY_SFT) & 0x1; 802*607ac485SJiaxin Yu 803*607ac485SJiaxin Yu /* flip => ok */ 804*607ac485SJiaxin Yu if (new_w_ready == old_w_ready) { 805*607ac485SJiaxin Yu udelay(3); 806*607ac485SJiaxin Yu if (try_cnt == 9) { 807*607ac485SJiaxin Yu dev_warn(afe->dev, 808*607ac485SJiaxin Yu "%s(), write coeff not ready", 809*607ac485SJiaxin Yu __func__); 810*607ac485SJiaxin Yu } 811*607ac485SJiaxin Yu } else { 812*607ac485SJiaxin Yu break; 813*607ac485SJiaxin Yu } 814*607ac485SJiaxin Yu } 815*607ac485SJiaxin Yu /* need write -> read -> write to write next coeff */ 816*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 817*607ac485SJiaxin Yu AFE_SIDETONE_CON0, 818*607ac485SJiaxin Yu R_W_SEL_MASK_SFT, 819*607ac485SJiaxin Yu 0x0); 820*607ac485SJiaxin Yu } 821*607ac485SJiaxin Yu break; 822*607ac485SJiaxin Yu case SND_SOC_DAPM_POST_PMD: 823*607ac485SJiaxin Yu /* bypass stf */ 824*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 825*607ac485SJiaxin Yu AFE_SIDETONE_CON1, 826*607ac485SJiaxin Yu 0x1f << 27, 827*607ac485SJiaxin Yu 0x1f << 27); 828*607ac485SJiaxin Yu 829*607ac485SJiaxin Yu /* set side tone gain = 0 */ 830*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 831*607ac485SJiaxin Yu AFE_SIDETONE_GAIN, 832*607ac485SJiaxin Yu SIDE_TONE_GAIN_MASK_SFT, 833*607ac485SJiaxin Yu 0); 834*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 835*607ac485SJiaxin Yu AFE_SIDETONE_GAIN, 836*607ac485SJiaxin Yu POSITIVE_GAIN_MASK_SFT, 837*607ac485SJiaxin Yu 0); 838*607ac485SJiaxin Yu break; 839*607ac485SJiaxin Yu default: 840*607ac485SJiaxin Yu break; 841*607ac485SJiaxin Yu } 842*607ac485SJiaxin Yu 843*607ac485SJiaxin Yu return 0; 844*607ac485SJiaxin Yu } 845*607ac485SJiaxin Yu 846*607ac485SJiaxin Yu /* stf mux */ 847*607ac485SJiaxin Yu enum { 848*607ac485SJiaxin Yu STF_SRC_ADDA_ADDA6 = 0, 849*607ac485SJiaxin Yu STF_SRC_O19O20, 850*607ac485SJiaxin Yu }; 851*607ac485SJiaxin Yu 852*607ac485SJiaxin Yu static const char *const stf_o19o20_mux_map[] = { 853*607ac485SJiaxin Yu "ADDA_ADDA6", 854*607ac485SJiaxin Yu "O19O20", 855*607ac485SJiaxin Yu }; 856*607ac485SJiaxin Yu 857*607ac485SJiaxin Yu static int stf_o19o20_mux_map_value[] = { 858*607ac485SJiaxin Yu STF_SRC_ADDA_ADDA6, 859*607ac485SJiaxin Yu STF_SRC_O19O20, 860*607ac485SJiaxin Yu }; 861*607ac485SJiaxin Yu 862*607ac485SJiaxin Yu static SOC_VALUE_ENUM_SINGLE_DECL(stf_o19o20_mux_map_enum, 863*607ac485SJiaxin Yu AFE_SIDETONE_CON1, 864*607ac485SJiaxin Yu STF_SOURCE_FROM_O19O20_SFT, 865*607ac485SJiaxin Yu STF_SOURCE_FROM_O19O20_MASK, 866*607ac485SJiaxin Yu stf_o19o20_mux_map, 867*607ac485SJiaxin Yu stf_o19o20_mux_map_value); 868*607ac485SJiaxin Yu 869*607ac485SJiaxin Yu static const struct snd_kcontrol_new stf_o19O20_mux_control = 870*607ac485SJiaxin Yu SOC_DAPM_ENUM("STF_O19O20_MUX", stf_o19o20_mux_map_enum); 871*607ac485SJiaxin Yu 872*607ac485SJiaxin Yu enum { 873*607ac485SJiaxin Yu STF_SRC_ADDA = 0, 874*607ac485SJiaxin Yu STF_SRC_ADDA6, 875*607ac485SJiaxin Yu }; 876*607ac485SJiaxin Yu 877*607ac485SJiaxin Yu static const char *const stf_adda_mux_map[] = { 878*607ac485SJiaxin Yu "ADDA", 879*607ac485SJiaxin Yu "ADDA6", 880*607ac485SJiaxin Yu }; 881*607ac485SJiaxin Yu 882*607ac485SJiaxin Yu static int stf_adda_mux_map_value[] = { 883*607ac485SJiaxin Yu STF_SRC_ADDA, 884*607ac485SJiaxin Yu STF_SRC_ADDA6, 885*607ac485SJiaxin Yu }; 886*607ac485SJiaxin Yu 887*607ac485SJiaxin Yu static SOC_VALUE_ENUM_SINGLE_DECL(stf_adda_mux_map_enum, 888*607ac485SJiaxin Yu AFE_SIDETONE_CON1, 889*607ac485SJiaxin Yu STF_O19O20_OUT_EN_SEL_SFT, 890*607ac485SJiaxin Yu STF_O19O20_OUT_EN_SEL_MASK, 891*607ac485SJiaxin Yu stf_adda_mux_map, 892*607ac485SJiaxin Yu stf_adda_mux_map_value); 893*607ac485SJiaxin Yu 894*607ac485SJiaxin Yu static const struct snd_kcontrol_new stf_adda_mux_control = 895*607ac485SJiaxin Yu SOC_DAPM_ENUM("STF_ADDA_MUX", stf_adda_mux_map_enum); 896*607ac485SJiaxin Yu 897*607ac485SJiaxin Yu /* ADDA UL MUX */ 898*607ac485SJiaxin Yu enum { 899*607ac485SJiaxin Yu ADDA_UL_MUX_MTKAIF = 0, 900*607ac485SJiaxin Yu ADDA_UL_MUX_AP_DMIC, 901*607ac485SJiaxin Yu ADDA_UL_MUX_MASK = 0x1, 902*607ac485SJiaxin Yu }; 903*607ac485SJiaxin Yu 904*607ac485SJiaxin Yu static const char * const adda_ul_mux_map[] = { 905*607ac485SJiaxin Yu "MTKAIF", "AP_DMIC" 906*607ac485SJiaxin Yu }; 907*607ac485SJiaxin Yu 908*607ac485SJiaxin Yu static int adda_ul_map_value[] = { 909*607ac485SJiaxin Yu ADDA_UL_MUX_MTKAIF, 910*607ac485SJiaxin Yu ADDA_UL_MUX_AP_DMIC, 911*607ac485SJiaxin Yu }; 912*607ac485SJiaxin Yu 913*607ac485SJiaxin Yu static SOC_VALUE_ENUM_SINGLE_DECL(adda_ul_mux_map_enum, 914*607ac485SJiaxin Yu SND_SOC_NOPM, 915*607ac485SJiaxin Yu 0, 916*607ac485SJiaxin Yu ADDA_UL_MUX_MASK, 917*607ac485SJiaxin Yu adda_ul_mux_map, 918*607ac485SJiaxin Yu adda_ul_map_value); 919*607ac485SJiaxin Yu 920*607ac485SJiaxin Yu static const struct snd_kcontrol_new adda_ul_mux_control = 921*607ac485SJiaxin Yu SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum); 922*607ac485SJiaxin Yu 923*607ac485SJiaxin Yu static const struct snd_kcontrol_new adda_ch34_ul_mux_control = 924*607ac485SJiaxin Yu SOC_DAPM_ENUM("ADDA_CH34_UL_MUX Select", adda_ul_mux_map_enum); 925*607ac485SJiaxin Yu 926*607ac485SJiaxin Yu static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = { 927*607ac485SJiaxin Yu /* inter-connections */ 928*607ac485SJiaxin Yu SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0, 929*607ac485SJiaxin Yu mtk_adda_dl_ch1_mix, 930*607ac485SJiaxin Yu ARRAY_SIZE(mtk_adda_dl_ch1_mix)), 931*607ac485SJiaxin Yu SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0, 932*607ac485SJiaxin Yu mtk_adda_dl_ch2_mix, 933*607ac485SJiaxin Yu ARRAY_SIZE(mtk_adda_dl_ch2_mix)), 934*607ac485SJiaxin Yu 935*607ac485SJiaxin Yu SND_SOC_DAPM_MIXER("ADDA_DL_CH3", SND_SOC_NOPM, 0, 0, 936*607ac485SJiaxin Yu mtk_adda_dl_ch3_mix, 937*607ac485SJiaxin Yu ARRAY_SIZE(mtk_adda_dl_ch3_mix)), 938*607ac485SJiaxin Yu SND_SOC_DAPM_MIXER("ADDA_DL_CH4", SND_SOC_NOPM, 0, 0, 939*607ac485SJiaxin Yu mtk_adda_dl_ch4_mix, 940*607ac485SJiaxin Yu ARRAY_SIZE(mtk_adda_dl_ch4_mix)), 941*607ac485SJiaxin Yu 942*607ac485SJiaxin Yu SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON, 943*607ac485SJiaxin Yu AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0, 944*607ac485SJiaxin Yu NULL, 0), 945*607ac485SJiaxin Yu 946*607ac485SJiaxin Yu SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON, 947*607ac485SJiaxin Yu AFE_ADDA_DL_SRC2_CON0, 948*607ac485SJiaxin Yu DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, 949*607ac485SJiaxin Yu mtk_adda_dl_event, 950*607ac485SJiaxin Yu SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 951*607ac485SJiaxin Yu SND_SOC_DAPM_SUPPLY_S("ADDA CH34 Playback Enable", 952*607ac485SJiaxin Yu SUPPLY_SEQ_ADDA_DL_ON, 953*607ac485SJiaxin Yu AFE_ADDA_3RD_DAC_DL_SRC2_CON0, 954*607ac485SJiaxin Yu DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, 955*607ac485SJiaxin Yu mtk_adda_ch34_dl_event, 956*607ac485SJiaxin Yu SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 957*607ac485SJiaxin Yu 958*607ac485SJiaxin Yu SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON, 959*607ac485SJiaxin Yu AFE_ADDA_UL_SRC_CON0, 960*607ac485SJiaxin Yu UL_SRC_ON_TMP_CTL_SFT, 0, 961*607ac485SJiaxin Yu mtk_adda_ul_event, 962*607ac485SJiaxin Yu SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 963*607ac485SJiaxin Yu SND_SOC_DAPM_SUPPLY_S("ADDA CH34 Capture Enable", SUPPLY_SEQ_ADDA_UL_ON, 964*607ac485SJiaxin Yu AFE_ADDA6_UL_SRC_CON0, 965*607ac485SJiaxin Yu UL_SRC_ON_TMP_CTL_SFT, 0, 966*607ac485SJiaxin Yu mtk_adda_ch34_ul_event, 967*607ac485SJiaxin Yu SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 968*607ac485SJiaxin Yu 969*607ac485SJiaxin Yu SND_SOC_DAPM_SUPPLY_S("AUD_PAD_TOP", SUPPLY_SEQ_ADDA_AUD_PAD_TOP, 970*607ac485SJiaxin Yu AFE_AUD_PAD_TOP, 971*607ac485SJiaxin Yu RG_RX_FIFO_ON_SFT, 0, 972*607ac485SJiaxin Yu mtk_adda_pad_top_event, 973*607ac485SJiaxin Yu SND_SOC_DAPM_PRE_PMU), 974*607ac485SJiaxin Yu SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG, 975*607ac485SJiaxin Yu SND_SOC_NOPM, 0, 0, 976*607ac485SJiaxin Yu mtk_adda_mtkaif_cfg_event, 977*607ac485SJiaxin Yu SND_SOC_DAPM_PRE_PMU), 978*607ac485SJiaxin Yu SND_SOC_DAPM_SUPPLY_S("ADDA6_MTKAIF_CFG", SUPPLY_SEQ_ADDA6_MTKAIF_CFG, 979*607ac485SJiaxin Yu SND_SOC_NOPM, 0, 0, 980*607ac485SJiaxin Yu mtk_adda_mtkaif_cfg_event, 981*607ac485SJiaxin Yu SND_SOC_DAPM_PRE_PMU), 982*607ac485SJiaxin Yu 983*607ac485SJiaxin Yu SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC, 984*607ac485SJiaxin Yu AFE_ADDA_UL_SRC_CON0, 985*607ac485SJiaxin Yu UL_AP_DMIC_ON_SFT, 0, 986*607ac485SJiaxin Yu NULL, 0), 987*607ac485SJiaxin Yu SND_SOC_DAPM_SUPPLY_S("AP_DMIC_CH34_EN", SUPPLY_SEQ_ADDA_AP_DMIC, 988*607ac485SJiaxin Yu AFE_ADDA6_UL_SRC_CON0, 989*607ac485SJiaxin Yu UL_AP_DMIC_ON_SFT, 0, 990*607ac485SJiaxin Yu NULL, 0), 991*607ac485SJiaxin Yu 992*607ac485SJiaxin Yu SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO, 993*607ac485SJiaxin Yu AFE_ADDA_UL_DL_CON0, 994*607ac485SJiaxin Yu AFE_ADDA_FIFO_AUTO_RST_SFT, 1, 995*607ac485SJiaxin Yu NULL, 0), 996*607ac485SJiaxin Yu SND_SOC_DAPM_SUPPLY_S("ADDA_CH34_FIFO", SUPPLY_SEQ_ADDA_FIFO, 997*607ac485SJiaxin Yu AFE_ADDA_UL_DL_CON0, 998*607ac485SJiaxin Yu AFE_ADDA6_FIFO_AUTO_RST_SFT, 1, 999*607ac485SJiaxin Yu NULL, 0), 1000*607ac485SJiaxin Yu 1001*607ac485SJiaxin Yu SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0, 1002*607ac485SJiaxin Yu &adda_ul_mux_control), 1003*607ac485SJiaxin Yu SND_SOC_DAPM_MUX("ADDA_CH34_UL_Mux", SND_SOC_NOPM, 0, 0, 1004*607ac485SJiaxin Yu &adda_ch34_ul_mux_control), 1005*607ac485SJiaxin Yu 1006*607ac485SJiaxin Yu SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"), 1007*607ac485SJiaxin Yu SND_SOC_DAPM_INPUT("AP_DMIC_CH34_INPUT"), 1008*607ac485SJiaxin Yu 1009*607ac485SJiaxin Yu /* stf */ 1010*607ac485SJiaxin Yu SND_SOC_DAPM_SWITCH_E("Sidetone Filter", 1011*607ac485SJiaxin Yu AFE_SIDETONE_CON1, SIDE_TONE_ON_SFT, 0, 1012*607ac485SJiaxin Yu &stf_ctl, 1013*607ac485SJiaxin Yu mtk_stf_event, 1014*607ac485SJiaxin Yu SND_SOC_DAPM_PRE_PMU | 1015*607ac485SJiaxin Yu SND_SOC_DAPM_POST_PMD), 1016*607ac485SJiaxin Yu SND_SOC_DAPM_MUX("STF_O19O20_MUX", SND_SOC_NOPM, 0, 0, 1017*607ac485SJiaxin Yu &stf_o19O20_mux_control), 1018*607ac485SJiaxin Yu SND_SOC_DAPM_MUX("STF_ADDA_MUX", SND_SOC_NOPM, 0, 0, 1019*607ac485SJiaxin Yu &stf_adda_mux_control), 1020*607ac485SJiaxin Yu SND_SOC_DAPM_MIXER("STF_CH1", SND_SOC_NOPM, 0, 0, 1021*607ac485SJiaxin Yu mtk_stf_ch1_mix, 1022*607ac485SJiaxin Yu ARRAY_SIZE(mtk_stf_ch1_mix)), 1023*607ac485SJiaxin Yu SND_SOC_DAPM_MIXER("STF_CH2", SND_SOC_NOPM, 0, 0, 1024*607ac485SJiaxin Yu mtk_stf_ch2_mix, 1025*607ac485SJiaxin Yu ARRAY_SIZE(mtk_stf_ch2_mix)), 1026*607ac485SJiaxin Yu SND_SOC_DAPM_OUTPUT("STF_OUTPUT"), 1027*607ac485SJiaxin Yu 1028*607ac485SJiaxin Yu /* clock */ 1029*607ac485SJiaxin Yu SND_SOC_DAPM_CLOCK_SUPPLY("top_mux_audio_h"), 1030*607ac485SJiaxin Yu 1031*607ac485SJiaxin Yu SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"), 1032*607ac485SJiaxin Yu SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"), 1033*607ac485SJiaxin Yu SND_SOC_DAPM_CLOCK_SUPPLY("aud_3rd_dac_clk"), 1034*607ac485SJiaxin Yu SND_SOC_DAPM_CLOCK_SUPPLY("aud_3rd_dac_predis_clk"), 1035*607ac485SJiaxin Yu 1036*607ac485SJiaxin Yu SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"), 1037*607ac485SJiaxin Yu SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc_clk"), 1038*607ac485SJiaxin Yu }; 1039*607ac485SJiaxin Yu 1040*607ac485SJiaxin Yu static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = { 1041*607ac485SJiaxin Yu /* playback */ 1042*607ac485SJiaxin Yu {"ADDA_DL_CH1", "DL1_CH1", "DL1"}, 1043*607ac485SJiaxin Yu {"ADDA_DL_CH2", "DL1_CH1", "DL1"}, 1044*607ac485SJiaxin Yu {"ADDA_DL_CH2", "DL1_CH2", "DL1"}, 1045*607ac485SJiaxin Yu 1046*607ac485SJiaxin Yu {"ADDA_DL_CH1", "DL12_CH1", "DL12"}, 1047*607ac485SJiaxin Yu {"ADDA_DL_CH2", "DL12_CH2", "DL12"}, 1048*607ac485SJiaxin Yu 1049*607ac485SJiaxin Yu {"ADDA_DL_CH1", "DL6_CH1", "DL6"}, 1050*607ac485SJiaxin Yu {"ADDA_DL_CH2", "DL6_CH2", "DL6"}, 1051*607ac485SJiaxin Yu 1052*607ac485SJiaxin Yu {"ADDA_DL_CH1", "DL8_CH1", "DL8"}, 1053*607ac485SJiaxin Yu {"ADDA_DL_CH2", "DL8_CH2", "DL8"}, 1054*607ac485SJiaxin Yu 1055*607ac485SJiaxin Yu {"ADDA_DL_CH1", "DL2_CH1", "DL2"}, 1056*607ac485SJiaxin Yu {"ADDA_DL_CH2", "DL2_CH1", "DL2"}, 1057*607ac485SJiaxin Yu {"ADDA_DL_CH2", "DL2_CH2", "DL2"}, 1058*607ac485SJiaxin Yu 1059*607ac485SJiaxin Yu {"ADDA_DL_CH1", "DL3_CH1", "DL3"}, 1060*607ac485SJiaxin Yu {"ADDA_DL_CH2", "DL3_CH1", "DL3"}, 1061*607ac485SJiaxin Yu {"ADDA_DL_CH2", "DL3_CH2", "DL3"}, 1062*607ac485SJiaxin Yu 1063*607ac485SJiaxin Yu {"ADDA_DL_CH1", "DL4_CH1", "DL4"}, 1064*607ac485SJiaxin Yu {"ADDA_DL_CH2", "DL4_CH2", "DL4"}, 1065*607ac485SJiaxin Yu 1066*607ac485SJiaxin Yu {"ADDA_DL_CH1", "DL5_CH1", "DL5"}, 1067*607ac485SJiaxin Yu {"ADDA_DL_CH2", "DL5_CH2", "DL5"}, 1068*607ac485SJiaxin Yu 1069*607ac485SJiaxin Yu {"ADDA Playback", NULL, "ADDA_DL_CH1"}, 1070*607ac485SJiaxin Yu {"ADDA Playback", NULL, "ADDA_DL_CH2"}, 1071*607ac485SJiaxin Yu 1072*607ac485SJiaxin Yu {"ADDA Playback", NULL, "ADDA Enable"}, 1073*607ac485SJiaxin Yu {"ADDA Playback", NULL, "ADDA Playback Enable"}, 1074*607ac485SJiaxin Yu 1075*607ac485SJiaxin Yu {"ADDA_DL_CH3", "DL1_CH1", "DL1"}, 1076*607ac485SJiaxin Yu {"ADDA_DL_CH4", "DL1_CH1", "DL1"}, 1077*607ac485SJiaxin Yu {"ADDA_DL_CH4", "DL1_CH2", "DL1"}, 1078*607ac485SJiaxin Yu 1079*607ac485SJiaxin Yu {"ADDA_DL_CH3", "DL12_CH1", "DL12"}, 1080*607ac485SJiaxin Yu {"ADDA_DL_CH4", "DL12_CH2", "DL12"}, 1081*607ac485SJiaxin Yu 1082*607ac485SJiaxin Yu {"ADDA_DL_CH3", "DL6_CH1", "DL6"}, 1083*607ac485SJiaxin Yu {"ADDA_DL_CH4", "DL6_CH2", "DL6"}, 1084*607ac485SJiaxin Yu 1085*607ac485SJiaxin Yu {"ADDA_DL_CH3", "DL2_CH1", "DL2"}, 1086*607ac485SJiaxin Yu {"ADDA_DL_CH4", "DL2_CH1", "DL2"}, 1087*607ac485SJiaxin Yu {"ADDA_DL_CH4", "DL2_CH2", "DL2"}, 1088*607ac485SJiaxin Yu 1089*607ac485SJiaxin Yu {"ADDA_DL_CH3", "DL3_CH1", "DL3"}, 1090*607ac485SJiaxin Yu {"ADDA_DL_CH4", "DL3_CH1", "DL3"}, 1091*607ac485SJiaxin Yu {"ADDA_DL_CH4", "DL3_CH2", "DL3"}, 1092*607ac485SJiaxin Yu 1093*607ac485SJiaxin Yu {"ADDA_DL_CH3", "DL4_CH1", "DL4"}, 1094*607ac485SJiaxin Yu {"ADDA_DL_CH4", "DL4_CH2", "DL4"}, 1095*607ac485SJiaxin Yu 1096*607ac485SJiaxin Yu {"ADDA_DL_CH3", "DL5_CH1", "DL5"}, 1097*607ac485SJiaxin Yu {"ADDA_DL_CH4", "DL5_CH2", "DL5"}, 1098*607ac485SJiaxin Yu 1099*607ac485SJiaxin Yu {"ADDA CH34 Playback", NULL, "ADDA_DL_CH3"}, 1100*607ac485SJiaxin Yu {"ADDA CH34 Playback", NULL, "ADDA_DL_CH4"}, 1101*607ac485SJiaxin Yu 1102*607ac485SJiaxin Yu {"ADDA CH34 Playback", NULL, "ADDA Enable"}, 1103*607ac485SJiaxin Yu {"ADDA CH34 Playback", NULL, "ADDA CH34 Playback Enable"}, 1104*607ac485SJiaxin Yu 1105*607ac485SJiaxin Yu /* capture */ 1106*607ac485SJiaxin Yu {"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"}, 1107*607ac485SJiaxin Yu {"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"}, 1108*607ac485SJiaxin Yu 1109*607ac485SJiaxin Yu {"ADDA_CH34_UL_Mux", "MTKAIF", "ADDA CH34 Capture"}, 1110*607ac485SJiaxin Yu {"ADDA_CH34_UL_Mux", "AP_DMIC", "AP DMIC CH34 Capture"}, 1111*607ac485SJiaxin Yu 1112*607ac485SJiaxin Yu {"ADDA Capture", NULL, "ADDA Enable"}, 1113*607ac485SJiaxin Yu {"ADDA Capture", NULL, "ADDA Capture Enable"}, 1114*607ac485SJiaxin Yu {"ADDA Capture", NULL, "AUD_PAD_TOP"}, 1115*607ac485SJiaxin Yu {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"}, 1116*607ac485SJiaxin Yu 1117*607ac485SJiaxin Yu {"AP DMIC Capture", NULL, "ADDA Enable"}, 1118*607ac485SJiaxin Yu {"AP DMIC Capture", NULL, "ADDA Capture Enable"}, 1119*607ac485SJiaxin Yu {"AP DMIC Capture", NULL, "ADDA_FIFO"}, 1120*607ac485SJiaxin Yu {"AP DMIC Capture", NULL, "AP_DMIC_EN"}, 1121*607ac485SJiaxin Yu 1122*607ac485SJiaxin Yu {"ADDA CH34 Capture", NULL, "ADDA Enable"}, 1123*607ac485SJiaxin Yu {"ADDA CH34 Capture", NULL, "ADDA CH34 Capture Enable"}, 1124*607ac485SJiaxin Yu {"ADDA CH34 Capture", NULL, "AUD_PAD_TOP"}, 1125*607ac485SJiaxin Yu {"ADDA CH34 Capture", NULL, "ADDA6_MTKAIF_CFG"}, 1126*607ac485SJiaxin Yu 1127*607ac485SJiaxin Yu {"AP DMIC CH34 Capture", NULL, "ADDA Enable"}, 1128*607ac485SJiaxin Yu {"AP DMIC CH34 Capture", NULL, "ADDA CH34 Capture Enable"}, 1129*607ac485SJiaxin Yu {"AP DMIC CH34 Capture", NULL, "ADDA_CH34_FIFO"}, 1130*607ac485SJiaxin Yu {"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_EN"}, 1131*607ac485SJiaxin Yu 1132*607ac485SJiaxin Yu {"AP DMIC Capture", NULL, "AP_DMIC_INPUT"}, 1133*607ac485SJiaxin Yu {"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_INPUT"}, 1134*607ac485SJiaxin Yu 1135*607ac485SJiaxin Yu /* sidetone filter */ 1136*607ac485SJiaxin Yu {"STF_ADDA_MUX", "ADDA", "ADDA_UL_Mux"}, 1137*607ac485SJiaxin Yu {"STF_ADDA_MUX", "ADDA6", "ADDA_CH34_UL_Mux"}, 1138*607ac485SJiaxin Yu 1139*607ac485SJiaxin Yu {"STF_O19O20_MUX", "ADDA_ADDA6", "STF_ADDA_MUX"}, 1140*607ac485SJiaxin Yu {"STF_O19O20_MUX", "O19O20", "STF_CH1"}, 1141*607ac485SJiaxin Yu {"STF_O19O20_MUX", "O19O20", "STF_CH2"}, 1142*607ac485SJiaxin Yu 1143*607ac485SJiaxin Yu {"Sidetone Filter", "Switch", "STF_O19O20_MUX"}, 1144*607ac485SJiaxin Yu {"STF_OUTPUT", NULL, "Sidetone Filter"}, 1145*607ac485SJiaxin Yu {"ADDA Playback", NULL, "Sidetone Filter"}, 1146*607ac485SJiaxin Yu {"ADDA CH34 Playback", NULL, "Sidetone Filter"}, 1147*607ac485SJiaxin Yu 1148*607ac485SJiaxin Yu /* clk */ 1149*607ac485SJiaxin Yu {"ADDA Playback", NULL, "aud_dac_clk"}, 1150*607ac485SJiaxin Yu {"ADDA Playback", NULL, "aud_dac_predis_clk"}, 1151*607ac485SJiaxin Yu 1152*607ac485SJiaxin Yu {"ADDA CH34 Playback", NULL, "aud_3rd_dac_clk"}, 1153*607ac485SJiaxin Yu {"ADDA CH34 Playback", NULL, "aud_3rd_dac_predis_clk"}, 1154*607ac485SJiaxin Yu 1155*607ac485SJiaxin Yu {"ADDA Capture Enable", NULL, "aud_adc_clk"}, 1156*607ac485SJiaxin Yu {"ADDA CH34 Capture Enable", NULL, "aud_adda6_adc_clk"}, 1157*607ac485SJiaxin Yu }; 1158*607ac485SJiaxin Yu 1159*607ac485SJiaxin Yu /* dai ops */ 1160*607ac485SJiaxin Yu static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream, 1161*607ac485SJiaxin Yu struct snd_pcm_hw_params *params, 1162*607ac485SJiaxin Yu struct snd_soc_dai *dai) 1163*607ac485SJiaxin Yu { 1164*607ac485SJiaxin Yu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1165*607ac485SJiaxin Yu unsigned int rate = params_rate(params); 1166*607ac485SJiaxin Yu int id = dai->id; 1167*607ac485SJiaxin Yu 1168*607ac485SJiaxin Yu dev_info(afe->dev, "%s(), id %d, stream %d, rate %d\n", 1169*607ac485SJiaxin Yu __func__, 1170*607ac485SJiaxin Yu id, 1171*607ac485SJiaxin Yu substream->stream, 1172*607ac485SJiaxin Yu rate); 1173*607ac485SJiaxin Yu 1174*607ac485SJiaxin Yu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1175*607ac485SJiaxin Yu unsigned int dl_src2_con0 = 0; 1176*607ac485SJiaxin Yu unsigned int dl_src2_con1 = 0; 1177*607ac485SJiaxin Yu 1178*607ac485SJiaxin Yu /* set sampling rate */ 1179*607ac485SJiaxin Yu dl_src2_con0 = adda_dl_rate_transform(afe, rate) << 1180*607ac485SJiaxin Yu DL_2_INPUT_MODE_CTL_SFT; 1181*607ac485SJiaxin Yu 1182*607ac485SJiaxin Yu /* set output mode, UP_SAMPLING_RATE_X8 */ 1183*607ac485SJiaxin Yu dl_src2_con0 |= (0x3 << DL_2_OUTPUT_SEL_CTL_SFT); 1184*607ac485SJiaxin Yu 1185*607ac485SJiaxin Yu /* turn off mute function */ 1186*607ac485SJiaxin Yu dl_src2_con0 |= (0x01 << DL_2_MUTE_CH2_OFF_CTL_PRE_SFT); 1187*607ac485SJiaxin Yu dl_src2_con0 |= (0x01 << DL_2_MUTE_CH1_OFF_CTL_PRE_SFT); 1188*607ac485SJiaxin Yu 1189*607ac485SJiaxin Yu /* set voice input data if input sample rate is 8k or 16k */ 1190*607ac485SJiaxin Yu if (rate == 8000 || rate == 16000) 1191*607ac485SJiaxin Yu dl_src2_con0 |= 0x01 << DL_2_VOICE_MODE_CTL_PRE_SFT; 1192*607ac485SJiaxin Yu 1193*607ac485SJiaxin Yu /* SA suggest apply -0.3db to audio/speech path */ 1194*607ac485SJiaxin Yu dl_src2_con1 = MTK_AFE_ADDA_DL_GAIN_NORMAL << 1195*607ac485SJiaxin Yu DL_2_GAIN_CTL_PRE_SFT; 1196*607ac485SJiaxin Yu 1197*607ac485SJiaxin Yu /* turn on down-link gain */ 1198*607ac485SJiaxin Yu dl_src2_con0 |= (0x01 << DL_2_GAIN_ON_CTL_PRE_SFT); 1199*607ac485SJiaxin Yu 1200*607ac485SJiaxin Yu if (id == MT8192_DAI_ADDA) { 1201*607ac485SJiaxin Yu /* clean predistortion */ 1202*607ac485SJiaxin Yu regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0); 1203*607ac485SJiaxin Yu regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0); 1204*607ac485SJiaxin Yu 1205*607ac485SJiaxin Yu regmap_write(afe->regmap, 1206*607ac485SJiaxin Yu AFE_ADDA_DL_SRC2_CON0, dl_src2_con0); 1207*607ac485SJiaxin Yu regmap_write(afe->regmap, 1208*607ac485SJiaxin Yu AFE_ADDA_DL_SRC2_CON1, dl_src2_con1); 1209*607ac485SJiaxin Yu 1210*607ac485SJiaxin Yu /* set sdm gain */ 1211*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 1212*607ac485SJiaxin Yu AFE_ADDA_DL_SDM_DCCOMP_CON, 1213*607ac485SJiaxin Yu ATTGAIN_CTL_MASK_SFT, 1214*607ac485SJiaxin Yu AUDIO_SDM_LEVEL_NORMAL << 1215*607ac485SJiaxin Yu ATTGAIN_CTL_SFT); 1216*607ac485SJiaxin Yu 1217*607ac485SJiaxin Yu /* 2nd sdm */ 1218*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 1219*607ac485SJiaxin Yu AFE_ADDA_DL_SDM_DCCOMP_CON, 1220*607ac485SJiaxin Yu USE_3RD_SDM_MASK_SFT, 1221*607ac485SJiaxin Yu AUDIO_SDM_2ND << USE_3RD_SDM_SFT); 1222*607ac485SJiaxin Yu 1223*607ac485SJiaxin Yu /* sdm auto reset */ 1224*607ac485SJiaxin Yu regmap_write(afe->regmap, 1225*607ac485SJiaxin Yu AFE_ADDA_DL_SDM_AUTO_RESET_CON, 1226*607ac485SJiaxin Yu SDM_AUTO_RESET_THRESHOLD); 1227*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 1228*607ac485SJiaxin Yu AFE_ADDA_DL_SDM_AUTO_RESET_CON, 1229*607ac485SJiaxin Yu ADDA_SDM_AUTO_RESET_ONOFF_MASK_SFT, 1230*607ac485SJiaxin Yu 0x1 << ADDA_SDM_AUTO_RESET_ONOFF_SFT); 1231*607ac485SJiaxin Yu } else { 1232*607ac485SJiaxin Yu /* clean predistortion */ 1233*607ac485SJiaxin Yu regmap_write(afe->regmap, 1234*607ac485SJiaxin Yu AFE_ADDA_3RD_DAC_PREDIS_CON0, 0); 1235*607ac485SJiaxin Yu regmap_write(afe->regmap, 1236*607ac485SJiaxin Yu AFE_ADDA_3RD_DAC_PREDIS_CON1, 0); 1237*607ac485SJiaxin Yu 1238*607ac485SJiaxin Yu regmap_write(afe->regmap, AFE_ADDA_3RD_DAC_DL_SRC2_CON0, 1239*607ac485SJiaxin Yu dl_src2_con0); 1240*607ac485SJiaxin Yu regmap_write(afe->regmap, AFE_ADDA_3RD_DAC_DL_SRC2_CON1, 1241*607ac485SJiaxin Yu dl_src2_con1); 1242*607ac485SJiaxin Yu 1243*607ac485SJiaxin Yu /* set sdm gain */ 1244*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 1245*607ac485SJiaxin Yu AFE_ADDA_3RD_DAC_DL_SDM_DCCOMP_CON, 1246*607ac485SJiaxin Yu ATTGAIN_CTL_MASK_SFT, 1247*607ac485SJiaxin Yu AUDIO_SDM_LEVEL_NORMAL << 1248*607ac485SJiaxin Yu ATTGAIN_CTL_SFT); 1249*607ac485SJiaxin Yu 1250*607ac485SJiaxin Yu /* 2nd sdm */ 1251*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 1252*607ac485SJiaxin Yu AFE_ADDA_3RD_DAC_DL_SDM_DCCOMP_CON, 1253*607ac485SJiaxin Yu USE_3RD_SDM_MASK_SFT, 1254*607ac485SJiaxin Yu AUDIO_SDM_2ND << USE_3RD_SDM_SFT); 1255*607ac485SJiaxin Yu 1256*607ac485SJiaxin Yu /* sdm auto reset */ 1257*607ac485SJiaxin Yu regmap_write(afe->regmap, 1258*607ac485SJiaxin Yu AFE_ADDA_3RD_DAC_DL_SDM_AUTO_RESET_CON, 1259*607ac485SJiaxin Yu SDM_AUTO_RESET_THRESHOLD); 1260*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 1261*607ac485SJiaxin Yu AFE_ADDA_3RD_DAC_DL_SDM_AUTO_RESET_CON, 1262*607ac485SJiaxin Yu ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_MASK_SFT, 1263*607ac485SJiaxin Yu 0x1 << ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_SFT); 1264*607ac485SJiaxin Yu } 1265*607ac485SJiaxin Yu } else { 1266*607ac485SJiaxin Yu unsigned int voice_mode = 0; 1267*607ac485SJiaxin Yu unsigned int ul_src_con0 = 0; /* default value */ 1268*607ac485SJiaxin Yu 1269*607ac485SJiaxin Yu voice_mode = adda_ul_rate_transform(afe, rate); 1270*607ac485SJiaxin Yu 1271*607ac485SJiaxin Yu ul_src_con0 |= (voice_mode << 17) & (0x7 << 17); 1272*607ac485SJiaxin Yu 1273*607ac485SJiaxin Yu /* enable iir */ 1274*607ac485SJiaxin Yu ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) & 1275*607ac485SJiaxin Yu UL_IIR_ON_TMP_CTL_MASK_SFT; 1276*607ac485SJiaxin Yu ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) & 1277*607ac485SJiaxin Yu UL_IIRMODE_CTL_MASK_SFT; 1278*607ac485SJiaxin Yu 1279*607ac485SJiaxin Yu switch (id) { 1280*607ac485SJiaxin Yu case MT8192_DAI_ADDA: 1281*607ac485SJiaxin Yu case MT8192_DAI_AP_DMIC: 1282*607ac485SJiaxin Yu /* 35Hz @ 48k */ 1283*607ac485SJiaxin Yu regmap_write(afe->regmap, 1284*607ac485SJiaxin Yu AFE_ADDA_IIR_COEF_02_01, 0x00000000); 1285*607ac485SJiaxin Yu regmap_write(afe->regmap, 1286*607ac485SJiaxin Yu AFE_ADDA_IIR_COEF_04_03, 0x00003FB8); 1287*607ac485SJiaxin Yu regmap_write(afe->regmap, 1288*607ac485SJiaxin Yu AFE_ADDA_IIR_COEF_06_05, 0x3FB80000); 1289*607ac485SJiaxin Yu regmap_write(afe->regmap, 1290*607ac485SJiaxin Yu AFE_ADDA_IIR_COEF_08_07, 0x3FB80000); 1291*607ac485SJiaxin Yu regmap_write(afe->regmap, 1292*607ac485SJiaxin Yu AFE_ADDA_IIR_COEF_10_09, 0x0000C048); 1293*607ac485SJiaxin Yu 1294*607ac485SJiaxin Yu regmap_write(afe->regmap, 1295*607ac485SJiaxin Yu AFE_ADDA_UL_SRC_CON0, ul_src_con0); 1296*607ac485SJiaxin Yu 1297*607ac485SJiaxin Yu /* Using Internal ADC */ 1298*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 1299*607ac485SJiaxin Yu AFE_ADDA_TOP_CON0, 1300*607ac485SJiaxin Yu 0x1 << 0, 1301*607ac485SJiaxin Yu 0x0 << 0); 1302*607ac485SJiaxin Yu 1303*607ac485SJiaxin Yu /* mtkaif_rxif_data_mode = 0, amic */ 1304*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 1305*607ac485SJiaxin Yu AFE_ADDA_MTKAIF_RX_CFG0, 1306*607ac485SJiaxin Yu 0x1 << 0, 1307*607ac485SJiaxin Yu 0x0 << 0); 1308*607ac485SJiaxin Yu break; 1309*607ac485SJiaxin Yu case MT8192_DAI_ADDA_CH34: 1310*607ac485SJiaxin Yu case MT8192_DAI_AP_DMIC_CH34: 1311*607ac485SJiaxin Yu /* 35Hz @ 48k */ 1312*607ac485SJiaxin Yu regmap_write(afe->regmap, 1313*607ac485SJiaxin Yu AFE_ADDA6_IIR_COEF_02_01, 0x00000000); 1314*607ac485SJiaxin Yu regmap_write(afe->regmap, 1315*607ac485SJiaxin Yu AFE_ADDA6_IIR_COEF_04_03, 0x00003FB8); 1316*607ac485SJiaxin Yu regmap_write(afe->regmap, 1317*607ac485SJiaxin Yu AFE_ADDA6_IIR_COEF_06_05, 0x3FB80000); 1318*607ac485SJiaxin Yu regmap_write(afe->regmap, 1319*607ac485SJiaxin Yu AFE_ADDA6_IIR_COEF_08_07, 0x3FB80000); 1320*607ac485SJiaxin Yu regmap_write(afe->regmap, 1321*607ac485SJiaxin Yu AFE_ADDA6_IIR_COEF_10_09, 0x0000C048); 1322*607ac485SJiaxin Yu 1323*607ac485SJiaxin Yu regmap_write(afe->regmap, 1324*607ac485SJiaxin Yu AFE_ADDA6_UL_SRC_CON0, ul_src_con0); 1325*607ac485SJiaxin Yu 1326*607ac485SJiaxin Yu /* Using Internal ADC */ 1327*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 1328*607ac485SJiaxin Yu AFE_ADDA6_TOP_CON0, 1329*607ac485SJiaxin Yu 0x1 << 0, 1330*607ac485SJiaxin Yu 0x0 << 0); 1331*607ac485SJiaxin Yu 1332*607ac485SJiaxin Yu /* mtkaif_rxif_data_mode = 0, amic */ 1333*607ac485SJiaxin Yu regmap_update_bits(afe->regmap, 1334*607ac485SJiaxin Yu AFE_ADDA6_MTKAIF_RX_CFG0, 1335*607ac485SJiaxin Yu 0x1 << 0, 1336*607ac485SJiaxin Yu 0x0 << 0); 1337*607ac485SJiaxin Yu break; 1338*607ac485SJiaxin Yu default: 1339*607ac485SJiaxin Yu break; 1340*607ac485SJiaxin Yu } 1341*607ac485SJiaxin Yu 1342*607ac485SJiaxin Yu /* ap dmic */ 1343*607ac485SJiaxin Yu switch (id) { 1344*607ac485SJiaxin Yu case MT8192_DAI_AP_DMIC: 1345*607ac485SJiaxin Yu case MT8192_DAI_AP_DMIC_CH34: 1346*607ac485SJiaxin Yu mtk_adda_ul_src_dmic(afe, id); 1347*607ac485SJiaxin Yu break; 1348*607ac485SJiaxin Yu default: 1349*607ac485SJiaxin Yu break; 1350*607ac485SJiaxin Yu } 1351*607ac485SJiaxin Yu } 1352*607ac485SJiaxin Yu 1353*607ac485SJiaxin Yu return 0; 1354*607ac485SJiaxin Yu } 1355*607ac485SJiaxin Yu 1356*607ac485SJiaxin Yu static const struct snd_soc_dai_ops mtk_dai_adda_ops = { 1357*607ac485SJiaxin Yu .hw_params = mtk_dai_adda_hw_params, 1358*607ac485SJiaxin Yu }; 1359*607ac485SJiaxin Yu 1360*607ac485SJiaxin Yu /* dai driver */ 1361*607ac485SJiaxin Yu #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\ 1362*607ac485SJiaxin Yu SNDRV_PCM_RATE_96000 |\ 1363*607ac485SJiaxin Yu SNDRV_PCM_RATE_192000) 1364*607ac485SJiaxin Yu 1365*607ac485SJiaxin Yu #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 1366*607ac485SJiaxin Yu SNDRV_PCM_RATE_16000 |\ 1367*607ac485SJiaxin Yu SNDRV_PCM_RATE_32000 |\ 1368*607ac485SJiaxin Yu SNDRV_PCM_RATE_48000 |\ 1369*607ac485SJiaxin Yu SNDRV_PCM_RATE_96000 |\ 1370*607ac485SJiaxin Yu SNDRV_PCM_RATE_192000) 1371*607ac485SJiaxin Yu 1372*607ac485SJiaxin Yu #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1373*607ac485SJiaxin Yu SNDRV_PCM_FMTBIT_S24_LE |\ 1374*607ac485SJiaxin Yu SNDRV_PCM_FMTBIT_S32_LE) 1375*607ac485SJiaxin Yu 1376*607ac485SJiaxin Yu static struct snd_soc_dai_driver mtk_dai_adda_driver[] = { 1377*607ac485SJiaxin Yu { 1378*607ac485SJiaxin Yu .name = "ADDA", 1379*607ac485SJiaxin Yu .id = MT8192_DAI_ADDA, 1380*607ac485SJiaxin Yu .playback = { 1381*607ac485SJiaxin Yu .stream_name = "ADDA Playback", 1382*607ac485SJiaxin Yu .channels_min = 1, 1383*607ac485SJiaxin Yu .channels_max = 2, 1384*607ac485SJiaxin Yu .rates = MTK_ADDA_PLAYBACK_RATES, 1385*607ac485SJiaxin Yu .formats = MTK_ADDA_FORMATS, 1386*607ac485SJiaxin Yu }, 1387*607ac485SJiaxin Yu .capture = { 1388*607ac485SJiaxin Yu .stream_name = "ADDA Capture", 1389*607ac485SJiaxin Yu .channels_min = 1, 1390*607ac485SJiaxin Yu .channels_max = 2, 1391*607ac485SJiaxin Yu .rates = MTK_ADDA_CAPTURE_RATES, 1392*607ac485SJiaxin Yu .formats = MTK_ADDA_FORMATS, 1393*607ac485SJiaxin Yu }, 1394*607ac485SJiaxin Yu .ops = &mtk_dai_adda_ops, 1395*607ac485SJiaxin Yu }, 1396*607ac485SJiaxin Yu { 1397*607ac485SJiaxin Yu .name = "ADDA_CH34", 1398*607ac485SJiaxin Yu .id = MT8192_DAI_ADDA_CH34, 1399*607ac485SJiaxin Yu .playback = { 1400*607ac485SJiaxin Yu .stream_name = "ADDA CH34 Playback", 1401*607ac485SJiaxin Yu .channels_min = 1, 1402*607ac485SJiaxin Yu .channels_max = 2, 1403*607ac485SJiaxin Yu .rates = MTK_ADDA_PLAYBACK_RATES, 1404*607ac485SJiaxin Yu .formats = MTK_ADDA_FORMATS, 1405*607ac485SJiaxin Yu }, 1406*607ac485SJiaxin Yu .capture = { 1407*607ac485SJiaxin Yu .stream_name = "ADDA CH34 Capture", 1408*607ac485SJiaxin Yu .channels_min = 1, 1409*607ac485SJiaxin Yu .channels_max = 2, 1410*607ac485SJiaxin Yu .rates = MTK_ADDA_CAPTURE_RATES, 1411*607ac485SJiaxin Yu .formats = MTK_ADDA_FORMATS, 1412*607ac485SJiaxin Yu }, 1413*607ac485SJiaxin Yu .ops = &mtk_dai_adda_ops, 1414*607ac485SJiaxin Yu }, 1415*607ac485SJiaxin Yu { 1416*607ac485SJiaxin Yu .name = "AP_DMIC", 1417*607ac485SJiaxin Yu .id = MT8192_DAI_AP_DMIC, 1418*607ac485SJiaxin Yu .capture = { 1419*607ac485SJiaxin Yu .stream_name = "AP DMIC Capture", 1420*607ac485SJiaxin Yu .channels_min = 1, 1421*607ac485SJiaxin Yu .channels_max = 2, 1422*607ac485SJiaxin Yu .rates = MTK_ADDA_CAPTURE_RATES, 1423*607ac485SJiaxin Yu .formats = MTK_ADDA_FORMATS, 1424*607ac485SJiaxin Yu }, 1425*607ac485SJiaxin Yu .ops = &mtk_dai_adda_ops, 1426*607ac485SJiaxin Yu }, 1427*607ac485SJiaxin Yu { 1428*607ac485SJiaxin Yu .name = "AP_DMIC_CH34", 1429*607ac485SJiaxin Yu .id = MT8192_DAI_AP_DMIC_CH34, 1430*607ac485SJiaxin Yu .capture = { 1431*607ac485SJiaxin Yu .stream_name = "AP DMIC CH34 Capture", 1432*607ac485SJiaxin Yu .channels_min = 1, 1433*607ac485SJiaxin Yu .channels_max = 2, 1434*607ac485SJiaxin Yu .rates = MTK_ADDA_CAPTURE_RATES, 1435*607ac485SJiaxin Yu .formats = MTK_ADDA_FORMATS, 1436*607ac485SJiaxin Yu }, 1437*607ac485SJiaxin Yu .ops = &mtk_dai_adda_ops, 1438*607ac485SJiaxin Yu }, 1439*607ac485SJiaxin Yu }; 1440*607ac485SJiaxin Yu 1441*607ac485SJiaxin Yu int mt8192_dai_adda_register(struct mtk_base_afe *afe) 1442*607ac485SJiaxin Yu { 1443*607ac485SJiaxin Yu struct mtk_base_afe_dai *dai; 1444*607ac485SJiaxin Yu struct mt8192_afe_private *afe_priv = afe->platform_priv; 1445*607ac485SJiaxin Yu 1446*607ac485SJiaxin Yu dev_info(afe->dev, "%s()\n", __func__); 1447*607ac485SJiaxin Yu 1448*607ac485SJiaxin Yu dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 1449*607ac485SJiaxin Yu if (!dai) 1450*607ac485SJiaxin Yu return -ENOMEM; 1451*607ac485SJiaxin Yu 1452*607ac485SJiaxin Yu list_add(&dai->list, &afe->sub_dais); 1453*607ac485SJiaxin Yu 1454*607ac485SJiaxin Yu dai->dai_drivers = mtk_dai_adda_driver; 1455*607ac485SJiaxin Yu dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver); 1456*607ac485SJiaxin Yu 1457*607ac485SJiaxin Yu dai->controls = mtk_adda_controls; 1458*607ac485SJiaxin Yu dai->num_controls = ARRAY_SIZE(mtk_adda_controls); 1459*607ac485SJiaxin Yu dai->dapm_widgets = mtk_dai_adda_widgets; 1460*607ac485SJiaxin Yu dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets); 1461*607ac485SJiaxin Yu dai->dapm_routes = mtk_dai_adda_routes; 1462*607ac485SJiaxin Yu dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes); 1463*607ac485SJiaxin Yu 1464*607ac485SJiaxin Yu /* ap dmic priv share with adda */ 1465*607ac485SJiaxin Yu afe_priv->dai_priv[MT8192_DAI_AP_DMIC] = 1466*607ac485SJiaxin Yu afe_priv->dai_priv[MT8192_DAI_ADDA]; 1467*607ac485SJiaxin Yu afe_priv->dai_priv[MT8192_DAI_AP_DMIC_CH34] = 1468*607ac485SJiaxin Yu afe_priv->dai_priv[MT8192_DAI_ADDA_CH34]; 1469*607ac485SJiaxin Yu 1470*607ac485SJiaxin Yu return 0; 1471*607ac485SJiaxin Yu } 1472