1*125ab5d5SJiaxin Yu /* SPDX-License-Identifier: GPL-2.0 */ 2*125ab5d5SJiaxin Yu /* 3*125ab5d5SJiaxin Yu * mt8192-afe-common.h -- Mediatek 8192 audio driver definitions 4*125ab5d5SJiaxin Yu * 5*125ab5d5SJiaxin Yu * Copyright (c) 2020 MediaTek Inc. 6*125ab5d5SJiaxin Yu * Author: Shane Chien <shane.chien@mediatek.com> 7*125ab5d5SJiaxin Yu */ 8*125ab5d5SJiaxin Yu 9*125ab5d5SJiaxin Yu #ifndef _MT_8192_AFE_COMMON_H_ 10*125ab5d5SJiaxin Yu #define _MT_8192_AFE_COMMON_H_ 11*125ab5d5SJiaxin Yu 12*125ab5d5SJiaxin Yu #include <linux/list.h> 13*125ab5d5SJiaxin Yu #include <linux/regmap.h> 14*125ab5d5SJiaxin Yu #include <sound/soc.h> 15*125ab5d5SJiaxin Yu 16*125ab5d5SJiaxin Yu #include "../common/mtk-base-afe.h" 17*125ab5d5SJiaxin Yu #include "mt8192-reg.h" 18*125ab5d5SJiaxin Yu 19*125ab5d5SJiaxin Yu enum { 20*125ab5d5SJiaxin Yu MT8192_MEMIF_DL1, 21*125ab5d5SJiaxin Yu MT8192_MEMIF_DL12, 22*125ab5d5SJiaxin Yu MT8192_MEMIF_DL2, 23*125ab5d5SJiaxin Yu MT8192_MEMIF_DL3, 24*125ab5d5SJiaxin Yu MT8192_MEMIF_DL4, 25*125ab5d5SJiaxin Yu MT8192_MEMIF_DL5, 26*125ab5d5SJiaxin Yu MT8192_MEMIF_DL6, 27*125ab5d5SJiaxin Yu MT8192_MEMIF_DL7, 28*125ab5d5SJiaxin Yu MT8192_MEMIF_DL8, 29*125ab5d5SJiaxin Yu MT8192_MEMIF_DL9, 30*125ab5d5SJiaxin Yu MT8192_MEMIF_DAI, 31*125ab5d5SJiaxin Yu MT8192_MEMIF_DAI2, 32*125ab5d5SJiaxin Yu MT8192_MEMIF_MOD_DAI, 33*125ab5d5SJiaxin Yu MT8192_MEMIF_VUL12, 34*125ab5d5SJiaxin Yu MT8192_MEMIF_VUL2, 35*125ab5d5SJiaxin Yu MT8192_MEMIF_VUL3, 36*125ab5d5SJiaxin Yu MT8192_MEMIF_VUL4, 37*125ab5d5SJiaxin Yu MT8192_MEMIF_VUL5, 38*125ab5d5SJiaxin Yu MT8192_MEMIF_VUL6, 39*125ab5d5SJiaxin Yu MT8192_MEMIF_AWB, 40*125ab5d5SJiaxin Yu MT8192_MEMIF_AWB2, 41*125ab5d5SJiaxin Yu MT8192_MEMIF_HDMI, 42*125ab5d5SJiaxin Yu MT8192_MEMIF_NUM, 43*125ab5d5SJiaxin Yu MT8192_DAI_ADDA = MT8192_MEMIF_NUM, 44*125ab5d5SJiaxin Yu MT8192_DAI_ADDA_CH34, 45*125ab5d5SJiaxin Yu MT8192_DAI_AP_DMIC, 46*125ab5d5SJiaxin Yu MT8192_DAI_AP_DMIC_CH34, 47*125ab5d5SJiaxin Yu MT8192_DAI_VOW, 48*125ab5d5SJiaxin Yu MT8192_DAI_CONNSYS_I2S, 49*125ab5d5SJiaxin Yu MT8192_DAI_I2S_0, 50*125ab5d5SJiaxin Yu MT8192_DAI_I2S_1, 51*125ab5d5SJiaxin Yu MT8192_DAI_I2S_2, 52*125ab5d5SJiaxin Yu MT8192_DAI_I2S_3, 53*125ab5d5SJiaxin Yu MT8192_DAI_I2S_5, 54*125ab5d5SJiaxin Yu MT8192_DAI_I2S_6, 55*125ab5d5SJiaxin Yu MT8192_DAI_I2S_7, 56*125ab5d5SJiaxin Yu MT8192_DAI_I2S_8, 57*125ab5d5SJiaxin Yu MT8192_DAI_I2S_9, 58*125ab5d5SJiaxin Yu MT8192_DAI_HW_GAIN_1, 59*125ab5d5SJiaxin Yu MT8192_DAI_HW_GAIN_2, 60*125ab5d5SJiaxin Yu MT8192_DAI_SRC_1, 61*125ab5d5SJiaxin Yu MT8192_DAI_SRC_2, 62*125ab5d5SJiaxin Yu MT8192_DAI_PCM_1, 63*125ab5d5SJiaxin Yu MT8192_DAI_PCM_2, 64*125ab5d5SJiaxin Yu MT8192_DAI_TDM, 65*125ab5d5SJiaxin Yu MT8192_DAI_NUM, 66*125ab5d5SJiaxin Yu }; 67*125ab5d5SJiaxin Yu 68*125ab5d5SJiaxin Yu enum { 69*125ab5d5SJiaxin Yu MT8192_IRQ_0, 70*125ab5d5SJiaxin Yu MT8192_IRQ_1, 71*125ab5d5SJiaxin Yu MT8192_IRQ_2, 72*125ab5d5SJiaxin Yu MT8192_IRQ_3, 73*125ab5d5SJiaxin Yu MT8192_IRQ_4, 74*125ab5d5SJiaxin Yu MT8192_IRQ_5, 75*125ab5d5SJiaxin Yu MT8192_IRQ_6, 76*125ab5d5SJiaxin Yu MT8192_IRQ_7, 77*125ab5d5SJiaxin Yu MT8192_IRQ_8, 78*125ab5d5SJiaxin Yu MT8192_IRQ_9, 79*125ab5d5SJiaxin Yu MT8192_IRQ_10, 80*125ab5d5SJiaxin Yu MT8192_IRQ_11, 81*125ab5d5SJiaxin Yu MT8192_IRQ_12, 82*125ab5d5SJiaxin Yu MT8192_IRQ_13, 83*125ab5d5SJiaxin Yu MT8192_IRQ_14, 84*125ab5d5SJiaxin Yu MT8192_IRQ_15, 85*125ab5d5SJiaxin Yu MT8192_IRQ_16, 86*125ab5d5SJiaxin Yu MT8192_IRQ_17, 87*125ab5d5SJiaxin Yu MT8192_IRQ_18, 88*125ab5d5SJiaxin Yu MT8192_IRQ_19, 89*125ab5d5SJiaxin Yu MT8192_IRQ_20, 90*125ab5d5SJiaxin Yu MT8192_IRQ_21, 91*125ab5d5SJiaxin Yu MT8192_IRQ_22, 92*125ab5d5SJiaxin Yu MT8192_IRQ_23, 93*125ab5d5SJiaxin Yu MT8192_IRQ_24, 94*125ab5d5SJiaxin Yu MT8192_IRQ_25, 95*125ab5d5SJiaxin Yu MT8192_IRQ_26, 96*125ab5d5SJiaxin Yu MT8192_IRQ_31, /* used only for TDM */ 97*125ab5d5SJiaxin Yu MT8192_IRQ_NUM, 98*125ab5d5SJiaxin Yu }; 99*125ab5d5SJiaxin Yu 100*125ab5d5SJiaxin Yu enum { 101*125ab5d5SJiaxin Yu MTKAIF_PROTOCOL_1 = 0, 102*125ab5d5SJiaxin Yu MTKAIF_PROTOCOL_2, 103*125ab5d5SJiaxin Yu MTKAIF_PROTOCOL_2_CLK_P2, 104*125ab5d5SJiaxin Yu }; 105*125ab5d5SJiaxin Yu 106*125ab5d5SJiaxin Yu enum { 107*125ab5d5SJiaxin Yu MTK_AFE_ADDA_DL_GAIN_MUTE = 0, 108*125ab5d5SJiaxin Yu MTK_AFE_ADDA_DL_GAIN_NORMAL = 0xf74f, 109*125ab5d5SJiaxin Yu /* SA suggest apply -0.3db to audio/speech path */ 110*125ab5d5SJiaxin Yu }; 111*125ab5d5SJiaxin Yu 112*125ab5d5SJiaxin Yu /* MCLK */ 113*125ab5d5SJiaxin Yu enum { 114*125ab5d5SJiaxin Yu MT8192_I2S0_MCK = 0, 115*125ab5d5SJiaxin Yu MT8192_I2S1_MCK, 116*125ab5d5SJiaxin Yu MT8192_I2S2_MCK, 117*125ab5d5SJiaxin Yu MT8192_I2S3_MCK, 118*125ab5d5SJiaxin Yu MT8192_I2S4_MCK, 119*125ab5d5SJiaxin Yu MT8192_I2S4_BCK, 120*125ab5d5SJiaxin Yu MT8192_I2S5_MCK, 121*125ab5d5SJiaxin Yu MT8192_I2S6_MCK, 122*125ab5d5SJiaxin Yu MT8192_I2S7_MCK, 123*125ab5d5SJiaxin Yu MT8192_I2S8_MCK, 124*125ab5d5SJiaxin Yu MT8192_I2S9_MCK, 125*125ab5d5SJiaxin Yu MT8192_MCK_NUM, 126*125ab5d5SJiaxin Yu }; 127*125ab5d5SJiaxin Yu 128*125ab5d5SJiaxin Yu struct clk; 129*125ab5d5SJiaxin Yu 130*125ab5d5SJiaxin Yu struct mt8192_afe_private { 131*125ab5d5SJiaxin Yu struct clk **clk; 132*125ab5d5SJiaxin Yu struct regmap *topckgen; 133*125ab5d5SJiaxin Yu struct regmap *apmixedsys; 134*125ab5d5SJiaxin Yu struct regmap *infracfg; 135*125ab5d5SJiaxin Yu int stf_positive_gain_db; 136*125ab5d5SJiaxin Yu int pm_runtime_bypass_reg_ctl; 137*125ab5d5SJiaxin Yu 138*125ab5d5SJiaxin Yu /* dai */ 139*125ab5d5SJiaxin Yu bool dai_on[MT8192_DAI_NUM]; 140*125ab5d5SJiaxin Yu void *dai_priv[MT8192_DAI_NUM]; 141*125ab5d5SJiaxin Yu 142*125ab5d5SJiaxin Yu /* adda */ 143*125ab5d5SJiaxin Yu int mtkaif_protocol; 144*125ab5d5SJiaxin Yu int mtkaif_chosen_phase[4]; 145*125ab5d5SJiaxin Yu int mtkaif_phase_cycle[4]; 146*125ab5d5SJiaxin Yu int mtkaif_calibration_num_phase; 147*125ab5d5SJiaxin Yu int mtkaif_dmic; 148*125ab5d5SJiaxin Yu int mtkaif_dmic_ch34; 149*125ab5d5SJiaxin Yu int mtkaif_adda6_only; 150*125ab5d5SJiaxin Yu 151*125ab5d5SJiaxin Yu /* mck */ 152*125ab5d5SJiaxin Yu int mck_rate[MT8192_MCK_NUM]; 153*125ab5d5SJiaxin Yu }; 154*125ab5d5SJiaxin Yu 155*125ab5d5SJiaxin Yu int mt8192_dai_adda_register(struct mtk_base_afe *afe); 156*125ab5d5SJiaxin Yu int mt8192_dai_i2s_register(struct mtk_base_afe *afe); 157*125ab5d5SJiaxin Yu int mt8192_dai_hw_gain_register(struct mtk_base_afe *afe); 158*125ab5d5SJiaxin Yu int mt8192_dai_src_register(struct mtk_base_afe *afe); 159*125ab5d5SJiaxin Yu int mt8192_dai_pcm_register(struct mtk_base_afe *afe); 160*125ab5d5SJiaxin Yu int mt8192_dai_tdm_register(struct mtk_base_afe *afe); 161*125ab5d5SJiaxin Yu 162*125ab5d5SJiaxin Yu unsigned int mt8192_general_rate_transform(struct device *dev, 163*125ab5d5SJiaxin Yu unsigned int rate); 164*125ab5d5SJiaxin Yu unsigned int mt8192_rate_transform(struct device *dev, 165*125ab5d5SJiaxin Yu unsigned int rate, int aud_blk); 166*125ab5d5SJiaxin Yu 167*125ab5d5SJiaxin Yu int mt8192_dai_set_priv(struct mtk_base_afe *afe, int id, 168*125ab5d5SJiaxin Yu int priv_size, const void *priv_data); 169*125ab5d5SJiaxin Yu 170*125ab5d5SJiaxin Yu #endif 171