1125ab5d5SJiaxin Yu /* SPDX-License-Identifier: GPL-2.0 */ 2125ab5d5SJiaxin Yu /* 3125ab5d5SJiaxin Yu * mt8192-afe-common.h -- Mediatek 8192 audio driver definitions 4125ab5d5SJiaxin Yu * 5125ab5d5SJiaxin Yu * Copyright (c) 2020 MediaTek Inc. 6125ab5d5SJiaxin Yu * Author: Shane Chien <shane.chien@mediatek.com> 7125ab5d5SJiaxin Yu */ 8125ab5d5SJiaxin Yu 9125ab5d5SJiaxin Yu #ifndef _MT_8192_AFE_COMMON_H_ 10125ab5d5SJiaxin Yu #define _MT_8192_AFE_COMMON_H_ 11125ab5d5SJiaxin Yu 12125ab5d5SJiaxin Yu #include <linux/list.h> 13125ab5d5SJiaxin Yu #include <linux/regmap.h> 14125ab5d5SJiaxin Yu #include <sound/soc.h> 15125ab5d5SJiaxin Yu 16125ab5d5SJiaxin Yu #include "../common/mtk-base-afe.h" 17125ab5d5SJiaxin Yu #include "mt8192-reg.h" 18125ab5d5SJiaxin Yu 19125ab5d5SJiaxin Yu enum { 20125ab5d5SJiaxin Yu MT8192_MEMIF_DL1, 21125ab5d5SJiaxin Yu MT8192_MEMIF_DL12, 22125ab5d5SJiaxin Yu MT8192_MEMIF_DL2, 23125ab5d5SJiaxin Yu MT8192_MEMIF_DL3, 24125ab5d5SJiaxin Yu MT8192_MEMIF_DL4, 25125ab5d5SJiaxin Yu MT8192_MEMIF_DL5, 26125ab5d5SJiaxin Yu MT8192_MEMIF_DL6, 27125ab5d5SJiaxin Yu MT8192_MEMIF_DL7, 28125ab5d5SJiaxin Yu MT8192_MEMIF_DL8, 29125ab5d5SJiaxin Yu MT8192_MEMIF_DL9, 30125ab5d5SJiaxin Yu MT8192_MEMIF_DAI, 31125ab5d5SJiaxin Yu MT8192_MEMIF_DAI2, 32125ab5d5SJiaxin Yu MT8192_MEMIF_MOD_DAI, 33125ab5d5SJiaxin Yu MT8192_MEMIF_VUL12, 34125ab5d5SJiaxin Yu MT8192_MEMIF_VUL2, 35125ab5d5SJiaxin Yu MT8192_MEMIF_VUL3, 36125ab5d5SJiaxin Yu MT8192_MEMIF_VUL4, 37125ab5d5SJiaxin Yu MT8192_MEMIF_VUL5, 38125ab5d5SJiaxin Yu MT8192_MEMIF_VUL6, 39125ab5d5SJiaxin Yu MT8192_MEMIF_AWB, 40125ab5d5SJiaxin Yu MT8192_MEMIF_AWB2, 41125ab5d5SJiaxin Yu MT8192_MEMIF_HDMI, 42125ab5d5SJiaxin Yu MT8192_MEMIF_NUM, 43125ab5d5SJiaxin Yu MT8192_DAI_ADDA = MT8192_MEMIF_NUM, 44125ab5d5SJiaxin Yu MT8192_DAI_ADDA_CH34, 45125ab5d5SJiaxin Yu MT8192_DAI_AP_DMIC, 46125ab5d5SJiaxin Yu MT8192_DAI_AP_DMIC_CH34, 47125ab5d5SJiaxin Yu MT8192_DAI_VOW, 48125ab5d5SJiaxin Yu MT8192_DAI_CONNSYS_I2S, 49125ab5d5SJiaxin Yu MT8192_DAI_I2S_0, 50125ab5d5SJiaxin Yu MT8192_DAI_I2S_1, 51125ab5d5SJiaxin Yu MT8192_DAI_I2S_2, 52125ab5d5SJiaxin Yu MT8192_DAI_I2S_3, 53125ab5d5SJiaxin Yu MT8192_DAI_I2S_5, 54125ab5d5SJiaxin Yu MT8192_DAI_I2S_6, 55125ab5d5SJiaxin Yu MT8192_DAI_I2S_7, 56125ab5d5SJiaxin Yu MT8192_DAI_I2S_8, 57125ab5d5SJiaxin Yu MT8192_DAI_I2S_9, 58125ab5d5SJiaxin Yu MT8192_DAI_HW_GAIN_1, 59125ab5d5SJiaxin Yu MT8192_DAI_HW_GAIN_2, 60125ab5d5SJiaxin Yu MT8192_DAI_SRC_1, 61125ab5d5SJiaxin Yu MT8192_DAI_SRC_2, 62125ab5d5SJiaxin Yu MT8192_DAI_PCM_1, 63125ab5d5SJiaxin Yu MT8192_DAI_PCM_2, 64125ab5d5SJiaxin Yu MT8192_DAI_TDM, 65125ab5d5SJiaxin Yu MT8192_DAI_NUM, 66125ab5d5SJiaxin Yu }; 67125ab5d5SJiaxin Yu 68125ab5d5SJiaxin Yu enum { 69125ab5d5SJiaxin Yu MT8192_IRQ_0, 70125ab5d5SJiaxin Yu MT8192_IRQ_1, 71125ab5d5SJiaxin Yu MT8192_IRQ_2, 72125ab5d5SJiaxin Yu MT8192_IRQ_3, 73125ab5d5SJiaxin Yu MT8192_IRQ_4, 74125ab5d5SJiaxin Yu MT8192_IRQ_5, 75125ab5d5SJiaxin Yu MT8192_IRQ_6, 76125ab5d5SJiaxin Yu MT8192_IRQ_7, 77125ab5d5SJiaxin Yu MT8192_IRQ_8, 78125ab5d5SJiaxin Yu MT8192_IRQ_9, 79125ab5d5SJiaxin Yu MT8192_IRQ_10, 80125ab5d5SJiaxin Yu MT8192_IRQ_11, 81125ab5d5SJiaxin Yu MT8192_IRQ_12, 82125ab5d5SJiaxin Yu MT8192_IRQ_13, 83125ab5d5SJiaxin Yu MT8192_IRQ_14, 84125ab5d5SJiaxin Yu MT8192_IRQ_15, 85125ab5d5SJiaxin Yu MT8192_IRQ_16, 86125ab5d5SJiaxin Yu MT8192_IRQ_17, 87125ab5d5SJiaxin Yu MT8192_IRQ_18, 88125ab5d5SJiaxin Yu MT8192_IRQ_19, 89125ab5d5SJiaxin Yu MT8192_IRQ_20, 90125ab5d5SJiaxin Yu MT8192_IRQ_21, 91125ab5d5SJiaxin Yu MT8192_IRQ_22, 92125ab5d5SJiaxin Yu MT8192_IRQ_23, 93125ab5d5SJiaxin Yu MT8192_IRQ_24, 94125ab5d5SJiaxin Yu MT8192_IRQ_25, 95125ab5d5SJiaxin Yu MT8192_IRQ_26, 96125ab5d5SJiaxin Yu MT8192_IRQ_31, /* used only for TDM */ 97125ab5d5SJiaxin Yu MT8192_IRQ_NUM, 98125ab5d5SJiaxin Yu }; 99125ab5d5SJiaxin Yu 100125ab5d5SJiaxin Yu enum { 101125ab5d5SJiaxin Yu MTKAIF_PROTOCOL_1 = 0, 102125ab5d5SJiaxin Yu MTKAIF_PROTOCOL_2, 103125ab5d5SJiaxin Yu MTKAIF_PROTOCOL_2_CLK_P2, 104125ab5d5SJiaxin Yu }; 105125ab5d5SJiaxin Yu 106125ab5d5SJiaxin Yu enum { 107125ab5d5SJiaxin Yu MTK_AFE_ADDA_DL_GAIN_MUTE = 0, 108125ab5d5SJiaxin Yu MTK_AFE_ADDA_DL_GAIN_NORMAL = 0xf74f, 109125ab5d5SJiaxin Yu /* SA suggest apply -0.3db to audio/speech path */ 110125ab5d5SJiaxin Yu }; 111125ab5d5SJiaxin Yu 112125ab5d5SJiaxin Yu /* MCLK */ 113125ab5d5SJiaxin Yu enum { 114125ab5d5SJiaxin Yu MT8192_I2S0_MCK = 0, 115125ab5d5SJiaxin Yu MT8192_I2S1_MCK, 116125ab5d5SJiaxin Yu MT8192_I2S2_MCK, 117125ab5d5SJiaxin Yu MT8192_I2S3_MCK, 118125ab5d5SJiaxin Yu MT8192_I2S4_MCK, 119125ab5d5SJiaxin Yu MT8192_I2S4_BCK, 120125ab5d5SJiaxin Yu MT8192_I2S5_MCK, 121125ab5d5SJiaxin Yu MT8192_I2S6_MCK, 122125ab5d5SJiaxin Yu MT8192_I2S7_MCK, 123125ab5d5SJiaxin Yu MT8192_I2S8_MCK, 124125ab5d5SJiaxin Yu MT8192_I2S9_MCK, 125125ab5d5SJiaxin Yu MT8192_MCK_NUM, 126125ab5d5SJiaxin Yu }; 127125ab5d5SJiaxin Yu 128125ab5d5SJiaxin Yu struct clk; 129125ab5d5SJiaxin Yu 130125ab5d5SJiaxin Yu struct mt8192_afe_private { 131125ab5d5SJiaxin Yu struct clk **clk; 132125ab5d5SJiaxin Yu struct regmap *topckgen; 133125ab5d5SJiaxin Yu struct regmap *apmixedsys; 134125ab5d5SJiaxin Yu struct regmap *infracfg; 135125ab5d5SJiaxin Yu int stf_positive_gain_db; 136125ab5d5SJiaxin Yu int pm_runtime_bypass_reg_ctl; 137125ab5d5SJiaxin Yu 138125ab5d5SJiaxin Yu /* dai */ 139125ab5d5SJiaxin Yu bool dai_on[MT8192_DAI_NUM]; 140125ab5d5SJiaxin Yu void *dai_priv[MT8192_DAI_NUM]; 141125ab5d5SJiaxin Yu 142125ab5d5SJiaxin Yu /* adda */ 143125ab5d5SJiaxin Yu int mtkaif_protocol; 144125ab5d5SJiaxin Yu int mtkaif_chosen_phase[4]; 145125ab5d5SJiaxin Yu int mtkaif_phase_cycle[4]; 146125ab5d5SJiaxin Yu int mtkaif_calibration_num_phase; 147125ab5d5SJiaxin Yu int mtkaif_dmic; 148125ab5d5SJiaxin Yu int mtkaif_dmic_ch34; 149125ab5d5SJiaxin Yu int mtkaif_adda6_only; 150125ab5d5SJiaxin Yu 151125ab5d5SJiaxin Yu /* mck */ 152125ab5d5SJiaxin Yu int mck_rate[MT8192_MCK_NUM]; 153125ab5d5SJiaxin Yu }; 154125ab5d5SJiaxin Yu 155125ab5d5SJiaxin Yu int mt8192_dai_adda_register(struct mtk_base_afe *afe); 156125ab5d5SJiaxin Yu int mt8192_dai_i2s_register(struct mtk_base_afe *afe); 157125ab5d5SJiaxin Yu int mt8192_dai_hw_gain_register(struct mtk_base_afe *afe); 158125ab5d5SJiaxin Yu int mt8192_dai_src_register(struct mtk_base_afe *afe); 159125ab5d5SJiaxin Yu int mt8192_dai_pcm_register(struct mtk_base_afe *afe); 160125ab5d5SJiaxin Yu int mt8192_dai_tdm_register(struct mtk_base_afe *afe); 161125ab5d5SJiaxin Yu 162*8ae4fcfdSNícolas F. R. A. Prado int mt8192_dai_i2s_set_share(struct mtk_base_afe *afe, const char *main_i2s_name, 163*8ae4fcfdSNícolas F. R. A. Prado const char *secondary_i2s_name); 164*8ae4fcfdSNícolas F. R. A. Prado 165125ab5d5SJiaxin Yu unsigned int mt8192_general_rate_transform(struct device *dev, 166125ab5d5SJiaxin Yu unsigned int rate); 167125ab5d5SJiaxin Yu unsigned int mt8192_rate_transform(struct device *dev, 168125ab5d5SJiaxin Yu unsigned int rate, int aud_blk); 169125ab5d5SJiaxin Yu 170125ab5d5SJiaxin Yu int mt8192_dai_set_priv(struct mtk_base_afe *afe, int id, 171125ab5d5SJiaxin Yu int priv_size, const void *priv_data); 172125ab5d5SJiaxin Yu 173125ab5d5SJiaxin Yu #endif 174