1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek ALSA SoC Audio DAI eTDM Control 4 * 5 * Copyright (c) 2022 MediaTek Inc. 6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 * Trevor Wu <trevor.wu@mediatek.com> 8 * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <sound/pcm_params.h> 15 #include "mt8188-afe-clk.h" 16 #include "mt8188-afe-common.h" 17 #include "mt8188-reg.h" 18 19 #define MT8188_ETDM_MAX_CHANNELS 16 20 #define MT8188_ETDM_NORMAL_MAX_BCK_RATE 24576000 21 #define ETDM_TO_DAI_ID(x) ((x) + MT8188_AFE_IO_ETDM_START) 22 #define ENUM_TO_STR(x) #x 23 24 enum { 25 SUPPLY_SEQ_ETDM_MCLK, 26 SUPPLY_SEQ_ETDM_CG, 27 SUPPLY_SEQ_DPTX_EN, 28 SUPPLY_SEQ_ETDM_EN, 29 }; 30 31 enum { 32 MTK_DAI_ETDM_FORMAT_I2S = 0, 33 MTK_DAI_ETDM_FORMAT_LJ, 34 MTK_DAI_ETDM_FORMAT_RJ, 35 MTK_DAI_ETDM_FORMAT_EIAJ, 36 MTK_DAI_ETDM_FORMAT_DSPA, 37 MTK_DAI_ETDM_FORMAT_DSPB, 38 }; 39 40 enum { 41 MTK_DAI_ETDM_DATA_ONE_PIN = 0, 42 MTK_DAI_ETDM_DATA_MULTI_PIN, 43 }; 44 45 enum { 46 ETDM_IN, 47 ETDM_OUT, 48 }; 49 50 enum { 51 COWORK_ETDM_NONE = 0, 52 COWORK_ETDM_IN1_M = 2, 53 COWORK_ETDM_IN1_S = 3, 54 COWORK_ETDM_IN2_M = 4, 55 COWORK_ETDM_IN2_S = 5, 56 COWORK_ETDM_OUT1_M = 10, 57 COWORK_ETDM_OUT1_S = 11, 58 COWORK_ETDM_OUT2_M = 12, 59 COWORK_ETDM_OUT2_S = 13, 60 COWORK_ETDM_OUT3_M = 14, 61 COWORK_ETDM_OUT3_S = 15, 62 }; 63 64 enum { 65 ETDM_RELATCH_TIMING_A1A2SYS, 66 ETDM_RELATCH_TIMING_A3SYS, 67 ETDM_RELATCH_TIMING_A4SYS, 68 }; 69 70 enum { 71 ETDM_SYNC_NONE, 72 ETDM_SYNC_FROM_IN1 = 2, 73 ETDM_SYNC_FROM_IN2 = 4, 74 ETDM_SYNC_FROM_OUT1 = 10, 75 ETDM_SYNC_FROM_OUT2 = 12, 76 ETDM_SYNC_FROM_OUT3 = 14, 77 }; 78 79 struct etdm_con_reg { 80 unsigned int con0; 81 unsigned int con1; 82 unsigned int con2; 83 unsigned int con3; 84 unsigned int con4; 85 unsigned int con5; 86 }; 87 88 struct mtk_dai_etdm_rate { 89 unsigned int rate; 90 unsigned int reg_value; 91 }; 92 93 struct mtk_dai_etdm_priv { 94 unsigned int data_mode; 95 bool slave_mode; 96 bool lrck_inv; 97 bool bck_inv; 98 unsigned int format; 99 unsigned int slots; 100 unsigned int lrck_width; 101 unsigned int mclk_freq; 102 unsigned int mclk_fixed_apll; 103 unsigned int mclk_apll; 104 unsigned int mclk_dir; 105 int cowork_source_id; //dai id 106 unsigned int cowork_slv_count; 107 int cowork_slv_id[MT8188_AFE_IO_ETDM_NUM - 1]; //dai_id 108 bool in_disable_ch[MT8188_ETDM_MAX_CHANNELS]; 109 }; 110 111 static const struct mtk_dai_etdm_rate mt8188_etdm_rates[] = { 112 { .rate = 8000, .reg_value = 0, }, 113 { .rate = 12000, .reg_value = 1, }, 114 { .rate = 16000, .reg_value = 2, }, 115 { .rate = 24000, .reg_value = 3, }, 116 { .rate = 32000, .reg_value = 4, }, 117 { .rate = 48000, .reg_value = 5, }, 118 { .rate = 96000, .reg_value = 7, }, 119 { .rate = 192000, .reg_value = 9, }, 120 { .rate = 384000, .reg_value = 11, }, 121 { .rate = 11025, .reg_value = 16, }, 122 { .rate = 22050, .reg_value = 17, }, 123 { .rate = 44100, .reg_value = 18, }, 124 { .rate = 88200, .reg_value = 19, }, 125 { .rate = 176400, .reg_value = 20, }, 126 { .rate = 352800, .reg_value = 21, }, 127 }; 128 129 static int get_etdm_fs_timing(unsigned int rate) 130 { 131 int i; 132 133 for (i = 0; i < ARRAY_SIZE(mt8188_etdm_rates); i++) 134 if (mt8188_etdm_rates[i].rate == rate) 135 return mt8188_etdm_rates[i].reg_value; 136 137 return -EINVAL; 138 } 139 140 static unsigned int get_etdm_ch_fixup(unsigned int channels) 141 { 142 if (channels > 16) 143 return 24; 144 else if (channels > 8) 145 return 16; 146 else if (channels > 4) 147 return 8; 148 else if (channels > 2) 149 return 4; 150 else 151 return 2; 152 } 153 154 static int get_etdm_reg(unsigned int dai_id, struct etdm_con_reg *etdm_reg) 155 { 156 switch (dai_id) { 157 case MT8188_AFE_IO_ETDM1_IN: 158 etdm_reg->con0 = ETDM_IN1_CON0; 159 etdm_reg->con1 = ETDM_IN1_CON1; 160 etdm_reg->con2 = ETDM_IN1_CON2; 161 etdm_reg->con3 = ETDM_IN1_CON3; 162 etdm_reg->con4 = ETDM_IN1_CON4; 163 etdm_reg->con5 = ETDM_IN1_CON5; 164 break; 165 case MT8188_AFE_IO_ETDM2_IN: 166 etdm_reg->con0 = ETDM_IN2_CON0; 167 etdm_reg->con1 = ETDM_IN2_CON1; 168 etdm_reg->con2 = ETDM_IN2_CON2; 169 etdm_reg->con3 = ETDM_IN2_CON3; 170 etdm_reg->con4 = ETDM_IN2_CON4; 171 etdm_reg->con5 = ETDM_IN2_CON5; 172 break; 173 case MT8188_AFE_IO_ETDM1_OUT: 174 etdm_reg->con0 = ETDM_OUT1_CON0; 175 etdm_reg->con1 = ETDM_OUT1_CON1; 176 etdm_reg->con2 = ETDM_OUT1_CON2; 177 etdm_reg->con3 = ETDM_OUT1_CON3; 178 etdm_reg->con4 = ETDM_OUT1_CON4; 179 etdm_reg->con5 = ETDM_OUT1_CON5; 180 break; 181 case MT8188_AFE_IO_ETDM2_OUT: 182 etdm_reg->con0 = ETDM_OUT2_CON0; 183 etdm_reg->con1 = ETDM_OUT2_CON1; 184 etdm_reg->con2 = ETDM_OUT2_CON2; 185 etdm_reg->con3 = ETDM_OUT2_CON3; 186 etdm_reg->con4 = ETDM_OUT2_CON4; 187 etdm_reg->con5 = ETDM_OUT2_CON5; 188 break; 189 case MT8188_AFE_IO_ETDM3_OUT: 190 case MT8188_AFE_IO_DPTX: 191 etdm_reg->con0 = ETDM_OUT3_CON0; 192 etdm_reg->con1 = ETDM_OUT3_CON1; 193 etdm_reg->con2 = ETDM_OUT3_CON2; 194 etdm_reg->con3 = ETDM_OUT3_CON3; 195 etdm_reg->con4 = ETDM_OUT3_CON4; 196 etdm_reg->con5 = ETDM_OUT3_CON5; 197 break; 198 default: 199 return -EINVAL; 200 } 201 return 0; 202 } 203 204 static int get_etdm_dir(unsigned int dai_id) 205 { 206 switch (dai_id) { 207 case MT8188_AFE_IO_ETDM1_IN: 208 case MT8188_AFE_IO_ETDM2_IN: 209 return ETDM_IN; 210 case MT8188_AFE_IO_ETDM1_OUT: 211 case MT8188_AFE_IO_ETDM2_OUT: 212 case MT8188_AFE_IO_ETDM3_OUT: 213 return ETDM_OUT; 214 default: 215 return -EINVAL; 216 } 217 } 218 219 static int get_etdm_wlen(unsigned int bitwidth) 220 { 221 return bitwidth <= 16 ? 16 : 32; 222 } 223 224 static bool is_valid_etdm_dai(int dai_id) 225 { 226 switch (dai_id) { 227 case MT8188_AFE_IO_ETDM1_IN: 228 fallthrough; 229 case MT8188_AFE_IO_ETDM2_IN: 230 fallthrough; 231 case MT8188_AFE_IO_ETDM1_OUT: 232 fallthrough; 233 case MT8188_AFE_IO_ETDM2_OUT: 234 fallthrough; 235 case MT8188_AFE_IO_DPTX: 236 fallthrough; 237 case MT8188_AFE_IO_ETDM3_OUT: 238 return true; 239 default: 240 return false; 241 } 242 } 243 244 static int is_cowork_mode(struct snd_soc_dai *dai) 245 { 246 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 247 struct mt8188_afe_private *afe_priv = afe->platform_priv; 248 struct mtk_dai_etdm_priv *etdm_data; 249 250 if (!is_valid_etdm_dai(dai->id)) 251 return -EINVAL; 252 etdm_data = afe_priv->dai_priv[dai->id]; 253 254 return (etdm_data->cowork_slv_count > 0 || 255 etdm_data->cowork_source_id != COWORK_ETDM_NONE); 256 } 257 258 static int sync_to_dai_id(int source_sel) 259 { 260 switch (source_sel) { 261 case ETDM_SYNC_FROM_IN1: 262 return MT8188_AFE_IO_ETDM1_IN; 263 case ETDM_SYNC_FROM_IN2: 264 return MT8188_AFE_IO_ETDM2_IN; 265 case ETDM_SYNC_FROM_OUT1: 266 return MT8188_AFE_IO_ETDM1_OUT; 267 case ETDM_SYNC_FROM_OUT2: 268 return MT8188_AFE_IO_ETDM2_OUT; 269 case ETDM_SYNC_FROM_OUT3: 270 return MT8188_AFE_IO_ETDM3_OUT; 271 default: 272 return 0; 273 } 274 } 275 276 static int get_etdm_cowork_master_id(struct snd_soc_dai *dai) 277 { 278 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 279 struct mt8188_afe_private *afe_priv = afe->platform_priv; 280 struct mtk_dai_etdm_priv *etdm_data; 281 int dai_id; 282 283 if (!is_valid_etdm_dai(dai->id)) 284 return -EINVAL; 285 etdm_data = afe_priv->dai_priv[dai->id]; 286 dai_id = etdm_data->cowork_source_id; 287 288 if (dai_id == COWORK_ETDM_NONE) 289 dai_id = dai->id; 290 291 return dai_id; 292 } 293 294 static int mtk_dai_etdm_get_cg_id_by_dai_id(int dai_id) 295 { 296 switch (dai_id) { 297 case MT8188_AFE_IO_DPTX: 298 return MT8188_CLK_AUD_HDMI_OUT; 299 case MT8188_AFE_IO_ETDM1_IN: 300 return MT8188_CLK_AUD_TDM_IN; 301 case MT8188_AFE_IO_ETDM2_IN: 302 return MT8188_CLK_AUD_I2SIN; 303 case MT8188_AFE_IO_ETDM1_OUT: 304 return MT8188_CLK_AUD_TDM_OUT; 305 case MT8188_AFE_IO_ETDM2_OUT: 306 return MT8188_CLK_AUD_I2S_OUT; 307 case MT8188_AFE_IO_ETDM3_OUT: 308 return MT8188_CLK_AUD_HDMI_OUT; 309 default: 310 return -EINVAL; 311 } 312 } 313 314 static int mtk_dai_etdm_get_clk_id_by_dai_id(int dai_id) 315 { 316 switch (dai_id) { 317 case MT8188_AFE_IO_DPTX: 318 return MT8188_CLK_TOP_DPTX_M_SEL; 319 case MT8188_AFE_IO_ETDM1_IN: 320 return MT8188_CLK_TOP_I2SI1_M_SEL; 321 case MT8188_AFE_IO_ETDM2_IN: 322 return MT8188_CLK_TOP_I2SI2_M_SEL; 323 case MT8188_AFE_IO_ETDM1_OUT: 324 return MT8188_CLK_TOP_I2SO1_M_SEL; 325 case MT8188_AFE_IO_ETDM2_OUT: 326 return MT8188_CLK_TOP_I2SO2_M_SEL; 327 case MT8188_AFE_IO_ETDM3_OUT: 328 default: 329 return -EINVAL; 330 } 331 } 332 333 static int mtk_dai_etdm_get_clkdiv_id_by_dai_id(int dai_id) 334 { 335 switch (dai_id) { 336 case MT8188_AFE_IO_DPTX: 337 return MT8188_CLK_TOP_APLL12_DIV9; 338 case MT8188_AFE_IO_ETDM1_IN: 339 return MT8188_CLK_TOP_APLL12_DIV0; 340 case MT8188_AFE_IO_ETDM2_IN: 341 return MT8188_CLK_TOP_APLL12_DIV1; 342 case MT8188_AFE_IO_ETDM1_OUT: 343 return MT8188_CLK_TOP_APLL12_DIV2; 344 case MT8188_AFE_IO_ETDM2_OUT: 345 return MT8188_CLK_TOP_APLL12_DIV3; 346 case MT8188_AFE_IO_ETDM3_OUT: 347 default: 348 return -EINVAL; 349 } 350 } 351 352 static int get_etdm_id_by_name(struct mtk_base_afe *afe, 353 const char *name) 354 { 355 if (!strncmp(name, "ETDM1_IN", strlen("ETDM1_IN"))) 356 return MT8188_AFE_IO_ETDM1_IN; 357 else if (!strncmp(name, "ETDM2_IN", strlen("ETDM2_IN"))) 358 return MT8188_AFE_IO_ETDM2_IN; 359 else if (!strncmp(name, "ETDM1_OUT", strlen("ETDM1_OUT"))) 360 return MT8188_AFE_IO_ETDM1_OUT; 361 else if (!strncmp(name, "ETDM2_OUT", strlen("ETDM2_OUT"))) 362 return MT8188_AFE_IO_ETDM2_OUT; 363 else 364 return -EINVAL; 365 } 366 367 static struct mtk_dai_etdm_priv *get_etdm_priv_by_name(struct mtk_base_afe *afe, 368 const char *name) 369 { 370 struct mt8188_afe_private *afe_priv = afe->platform_priv; 371 int dai_id = get_etdm_id_by_name(afe, name); 372 373 if (dai_id < MT8188_AFE_IO_ETDM_START || 374 dai_id >= MT8188_AFE_IO_ETDM_END) 375 return NULL; 376 377 return afe_priv->dai_priv[dai_id]; 378 } 379 380 static int mtk_dai_etdm_enable_mclk(struct mtk_base_afe *afe, int dai_id) 381 { 382 struct mt8188_afe_private *afe_priv = afe->platform_priv; 383 struct mtk_dai_etdm_priv *etdm_data; 384 struct etdm_con_reg etdm_reg; 385 unsigned int val = 0; 386 unsigned int mask; 387 int clkmux_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id); 388 int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 389 int apll_clk_id; 390 int apll; 391 int ret; 392 393 if (!is_valid_etdm_dai(dai_id)) 394 return -EINVAL; 395 etdm_data = afe_priv->dai_priv[dai_id]; 396 397 apll = etdm_data->mclk_apll; 398 apll_clk_id = mt8188_afe_get_mclk_source_clk_id(apll); 399 400 if (clkmux_id < 0 || clkdiv_id < 0) 401 return -EINVAL; 402 403 if (apll_clk_id < 0) 404 return apll_clk_id; 405 406 ret = get_etdm_reg(dai_id, &etdm_reg); 407 if (ret < 0) 408 return ret; 409 410 mask = ETDM_CON1_MCLK_OUTPUT; 411 if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 412 val = ETDM_CON1_MCLK_OUTPUT; 413 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 414 415 /* enable parent clock before select apll*/ 416 mt8188_afe_enable_clk(afe, afe_priv->clk[clkmux_id]); 417 418 /* select apll */ 419 ret = mt8188_afe_set_clk_parent(afe, afe_priv->clk[clkmux_id], 420 afe_priv->clk[apll_clk_id]); 421 if (ret) 422 return ret; 423 424 /* set rate */ 425 ret = mt8188_afe_set_clk_rate(afe, afe_priv->clk[clkdiv_id], 426 etdm_data->mclk_freq); 427 428 mt8188_afe_enable_clk(afe, afe_priv->clk[clkdiv_id]); 429 430 return 0; 431 } 432 433 static int mtk_dai_etdm_disable_mclk(struct mtk_base_afe *afe, int dai_id) 434 { 435 struct mt8188_afe_private *afe_priv = afe->platform_priv; 436 int clkmux_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id); 437 int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 438 439 if (clkmux_id < 0 || clkdiv_id < 0) 440 return -EINVAL; 441 442 mt8188_afe_disable_clk(afe, afe_priv->clk[clkdiv_id]); 443 mt8188_afe_disable_clk(afe, afe_priv->clk[clkmux_id]); 444 445 return 0; 446 } 447 448 static int mtk_etdm_mclk_connect(struct snd_soc_dapm_widget *source, 449 struct snd_soc_dapm_widget *sink) 450 { 451 struct snd_soc_dapm_widget *w = sink; 452 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 453 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 454 struct mt8188_afe_private *afe_priv = afe->platform_priv; 455 struct mtk_dai_etdm_priv *etdm_priv; 456 int mclk_id; 457 458 mclk_id = get_etdm_id_by_name(afe, source->name); 459 if (mclk_id < 0) { 460 dev_dbg(afe->dev, "mclk_id < 0\n"); 461 return 0; 462 } 463 464 etdm_priv = get_etdm_priv_by_name(afe, w->name); 465 if (!etdm_priv) { 466 dev_dbg(afe->dev, "etdm_priv == NULL\n"); 467 return 0; 468 } 469 470 if (get_etdm_id_by_name(afe, sink->name) == mclk_id) 471 return !!(etdm_priv->mclk_freq > 0); 472 473 if (etdm_priv->cowork_source_id == mclk_id) { 474 etdm_priv = afe_priv->dai_priv[mclk_id]; 475 return !!(etdm_priv->mclk_freq > 0); 476 } 477 478 return 0; 479 } 480 481 static int mtk_etdm_cowork_connect(struct snd_soc_dapm_widget *source, 482 struct snd_soc_dapm_widget *sink) 483 { 484 struct snd_soc_dapm_widget *w = sink; 485 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 486 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 487 struct mt8188_afe_private *afe_priv = afe->platform_priv; 488 struct mtk_dai_etdm_priv *etdm_priv; 489 int source_id; 490 int i; 491 492 source_id = get_etdm_id_by_name(afe, source->name); 493 if (source_id < 0) { 494 dev_dbg(afe->dev, "%s() source_id < 0\n", __func__); 495 return 0; 496 } 497 498 etdm_priv = get_etdm_priv_by_name(afe, w->name); 499 if (!etdm_priv) { 500 dev_dbg(afe->dev, "%s() etdm_priv == NULL\n", __func__); 501 return 0; 502 } 503 504 if (etdm_priv->cowork_source_id != COWORK_ETDM_NONE) { 505 if (etdm_priv->cowork_source_id == source_id) 506 return 1; 507 508 etdm_priv = afe_priv->dai_priv[etdm_priv->cowork_source_id]; 509 for (i = 0; i < etdm_priv->cowork_slv_count; i++) { 510 if (etdm_priv->cowork_slv_id[i] == source_id) 511 return 1; 512 } 513 } else { 514 for (i = 0; i < etdm_priv->cowork_slv_count; i++) { 515 if (etdm_priv->cowork_slv_id[i] == source_id) 516 return 1; 517 } 518 } 519 520 return 0; 521 } 522 523 static int mtk_etdm_mclk_event(struct snd_soc_dapm_widget *w, 524 struct snd_kcontrol *kcontrol, 525 int event) 526 { 527 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 528 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 529 int mclk_id = get_etdm_id_by_name(afe, w->name); 530 531 if (mclk_id < 0) { 532 dev_dbg(afe->dev, "%s() mclk_id < 0\n", __func__); 533 return 0; 534 } 535 536 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 537 __func__, w->name, event); 538 539 switch (event) { 540 case SND_SOC_DAPM_PRE_PMU: 541 mtk_dai_etdm_enable_mclk(afe, mclk_id); 542 break; 543 case SND_SOC_DAPM_POST_PMD: 544 mtk_dai_etdm_disable_mclk(afe, mclk_id); 545 break; 546 default: 547 break; 548 } 549 550 return 0; 551 } 552 553 static int mtk_dptx_mclk_event(struct snd_soc_dapm_widget *w, 554 struct snd_kcontrol *kcontrol, 555 int event) 556 { 557 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 558 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 559 560 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 561 __func__, w->name, event); 562 563 switch (event) { 564 case SND_SOC_DAPM_PRE_PMU: 565 mtk_dai_etdm_enable_mclk(afe, MT8188_AFE_IO_DPTX); 566 break; 567 case SND_SOC_DAPM_POST_PMD: 568 mtk_dai_etdm_disable_mclk(afe, MT8188_AFE_IO_DPTX); 569 break; 570 default: 571 break; 572 } 573 574 return 0; 575 } 576 577 static int mtk_etdm_cg_event(struct snd_soc_dapm_widget *w, 578 struct snd_kcontrol *kcontrol, 579 int event) 580 { 581 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 582 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 583 struct mt8188_afe_private *afe_priv = afe->platform_priv; 584 int etdm_id; 585 int cg_id; 586 587 etdm_id = get_etdm_id_by_name(afe, w->name); 588 if (etdm_id < 0) { 589 dev_dbg(afe->dev, "%s() etdm_id < 0\n", __func__); 590 return 0; 591 } 592 593 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(etdm_id); 594 if (cg_id < 0) { 595 dev_dbg(afe->dev, "%s() cg_id < 0\n", __func__); 596 return 0; 597 } 598 599 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 600 __func__, w->name, event); 601 602 switch (event) { 603 case SND_SOC_DAPM_PRE_PMU: 604 mt8188_afe_enable_clk(afe, afe_priv->clk[cg_id]); 605 break; 606 case SND_SOC_DAPM_POST_PMD: 607 mt8188_afe_disable_clk(afe, afe_priv->clk[cg_id]); 608 break; 609 default: 610 break; 611 } 612 613 return 0; 614 } 615 616 static int mtk_etdm3_cg_event(struct snd_soc_dapm_widget *w, 617 struct snd_kcontrol *kcontrol, 618 int event) 619 { 620 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 621 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 622 struct mt8188_afe_private *afe_priv = afe->platform_priv; 623 624 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 625 __func__, w->name, event); 626 627 switch (event) { 628 case SND_SOC_DAPM_PRE_PMU: 629 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_HDMI_OUT]); 630 break; 631 case SND_SOC_DAPM_POST_PMD: 632 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_HDMI_OUT]); 633 break; 634 default: 635 break; 636 } 637 638 return 0; 639 } 640 641 static const struct snd_kcontrol_new mtk_dai_etdm_o048_mix[] = { 642 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN48, 20, 1, 0), 643 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN48, 22, 1, 0), 644 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN48_1, 14, 1, 0), 645 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN48_2, 6, 1, 0), 646 }; 647 648 static const struct snd_kcontrol_new mtk_dai_etdm_o049_mix[] = { 649 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN49, 21, 1, 0), 650 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN49, 23, 1, 0), 651 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN49_1, 15, 1, 0), 652 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN49_2, 7, 1, 0), 653 }; 654 655 static const struct snd_kcontrol_new mtk_dai_etdm_o050_mix[] = { 656 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN50, 24, 1, 0), 657 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN50_1, 16, 1, 0), 658 }; 659 660 static const struct snd_kcontrol_new mtk_dai_etdm_o051_mix[] = { 661 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN51, 25, 1, 0), 662 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN51_1, 17, 1, 0), 663 }; 664 665 static const struct snd_kcontrol_new mtk_dai_etdm_o052_mix[] = { 666 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN52, 26, 1, 0), 667 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN52_1, 18, 1, 0), 668 }; 669 670 static const struct snd_kcontrol_new mtk_dai_etdm_o053_mix[] = { 671 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN53, 27, 1, 0), 672 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN53_1, 19, 1, 0), 673 }; 674 675 static const struct snd_kcontrol_new mtk_dai_etdm_o054_mix[] = { 676 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN54, 28, 1, 0), 677 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN54_1, 20, 1, 0), 678 }; 679 680 static const struct snd_kcontrol_new mtk_dai_etdm_o055_mix[] = { 681 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN55, 29, 1, 0), 682 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN55_1, 21, 1, 0), 683 }; 684 685 static const struct snd_kcontrol_new mtk_dai_etdm_o056_mix[] = { 686 SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN56, 30, 1, 0), 687 SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN56_1, 22, 1, 0), 688 }; 689 690 static const struct snd_kcontrol_new mtk_dai_etdm_o057_mix[] = { 691 SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN57, 31, 1, 0), 692 SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN57_1, 23, 1, 0), 693 }; 694 695 static const struct snd_kcontrol_new mtk_dai_etdm_o058_mix[] = { 696 SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN58_1, 0, 1, 0), 697 SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN58_1, 24, 1, 0), 698 }; 699 700 static const struct snd_kcontrol_new mtk_dai_etdm_o059_mix[] = { 701 SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN59_1, 1, 1, 0), 702 SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN59_1, 25, 1, 0), 703 }; 704 705 static const struct snd_kcontrol_new mtk_dai_etdm_o060_mix[] = { 706 SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN60_1, 2, 1, 0), 707 SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN60_1, 26, 1, 0), 708 }; 709 710 static const struct snd_kcontrol_new mtk_dai_etdm_o061_mix[] = { 711 SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN61_1, 3, 1, 0), 712 SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN61_1, 27, 1, 0), 713 }; 714 715 static const struct snd_kcontrol_new mtk_dai_etdm_o062_mix[] = { 716 SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN62_1, 4, 1, 0), 717 SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN62_1, 28, 1, 0), 718 }; 719 720 static const struct snd_kcontrol_new mtk_dai_etdm_o063_mix[] = { 721 SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN63_1, 5, 1, 0), 722 SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN63_1, 29, 1, 0), 723 }; 724 725 static const struct snd_kcontrol_new mtk_dai_etdm_o072_mix[] = { 726 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN72, 20, 1, 0), 727 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN72, 22, 1, 0), 728 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN72_1, 14, 1, 0), 729 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN72_2, 6, 1, 0), 730 }; 731 732 static const struct snd_kcontrol_new mtk_dai_etdm_o073_mix[] = { 733 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN73, 21, 1, 0), 734 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN73, 23, 1, 0), 735 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN73_1, 15, 1, 0), 736 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN73_2, 7, 1, 0), 737 }; 738 739 static const struct snd_kcontrol_new mtk_dai_etdm_o074_mix[] = { 740 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN74, 24, 1, 0), 741 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN74_1, 16, 1, 0), 742 }; 743 744 static const struct snd_kcontrol_new mtk_dai_etdm_o075_mix[] = { 745 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN75, 25, 1, 0), 746 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN75_1, 17, 1, 0), 747 }; 748 749 static const struct snd_kcontrol_new mtk_dai_etdm_o076_mix[] = { 750 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN76, 26, 1, 0), 751 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN76_1, 18, 1, 0), 752 }; 753 754 static const struct snd_kcontrol_new mtk_dai_etdm_o077_mix[] = { 755 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN77, 27, 1, 0), 756 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN77_1, 19, 1, 0), 757 }; 758 759 static const struct snd_kcontrol_new mtk_dai_etdm_o078_mix[] = { 760 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN78, 28, 1, 0), 761 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN78_1, 20, 1, 0), 762 }; 763 764 static const struct snd_kcontrol_new mtk_dai_etdm_o079_mix[] = { 765 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN79, 29, 1, 0), 766 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN79_1, 21, 1, 0), 767 }; 768 769 static const struct snd_kcontrol_new mtk_dai_etdm_o080_mix[] = { 770 SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN80, 30, 1, 0), 771 SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN80_1, 22, 1, 0), 772 }; 773 774 static const struct snd_kcontrol_new mtk_dai_etdm_o081_mix[] = { 775 SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN81, 31, 1, 0), 776 SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN81_1, 23, 1, 0), 777 }; 778 779 static const struct snd_kcontrol_new mtk_dai_etdm_o082_mix[] = { 780 SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN82_1, 0, 1, 0), 781 SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN82_1, 24, 1, 0), 782 }; 783 784 static const struct snd_kcontrol_new mtk_dai_etdm_o083_mix[] = { 785 SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN83_1, 1, 1, 0), 786 SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN83_1, 25, 1, 0), 787 }; 788 789 static const struct snd_kcontrol_new mtk_dai_etdm_o084_mix[] = { 790 SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN84_1, 2, 1, 0), 791 SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN84_1, 26, 1, 0), 792 }; 793 794 static const struct snd_kcontrol_new mtk_dai_etdm_o085_mix[] = { 795 SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN85_1, 3, 1, 0), 796 SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN85_1, 27, 1, 0), 797 }; 798 799 static const struct snd_kcontrol_new mtk_dai_etdm_o086_mix[] = { 800 SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN86_1, 4, 1, 0), 801 SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN86_1, 28, 1, 0), 802 }; 803 804 static const struct snd_kcontrol_new mtk_dai_etdm_o087_mix[] = { 805 SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN87_1, 5, 1, 0), 806 SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN87_1, 29, 1, 0), 807 }; 808 809 static const char * const mt8188_etdm_clk_src_sel_text[] = { 810 "26m", 811 "a1sys_a2sys", 812 "a3sys", 813 "a4sys", 814 }; 815 816 static SOC_ENUM_SINGLE_EXT_DECL(etdmout_clk_src_enum, 817 mt8188_etdm_clk_src_sel_text); 818 819 static const char * const hdmitx_dptx_mux_map[] = { 820 "Disconnect", "Connect", 821 }; 822 823 static int hdmitx_dptx_mux_map_value[] = { 824 0, 1, 825 }; 826 827 /* HDMI_OUT_MUX */ 828 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(hdmi_out_mux_map_enum, 829 SND_SOC_NOPM, 830 0, 831 1, 832 hdmitx_dptx_mux_map, 833 hdmitx_dptx_mux_map_value); 834 835 static const struct snd_kcontrol_new hdmi_out_mux_control = 836 SOC_DAPM_ENUM("HDMI_OUT_MUX", hdmi_out_mux_map_enum); 837 838 /* DPTX_OUT_MUX */ 839 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(dptx_out_mux_map_enum, 840 SND_SOC_NOPM, 841 0, 842 1, 843 hdmitx_dptx_mux_map, 844 hdmitx_dptx_mux_map_value); 845 846 static const struct snd_kcontrol_new dptx_out_mux_control = 847 SOC_DAPM_ENUM("DPTX_OUT_MUX", dptx_out_mux_map_enum); 848 849 /* HDMI_CH0_MUX ~ HDMI_CH7_MUX */ 850 static const char *const afe_conn_hdmi_mux_map[] = { 851 "CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7", 852 }; 853 854 static int afe_conn_hdmi_mux_map_value[] = { 855 0, 1, 2, 3, 4, 5, 6, 7, 856 }; 857 858 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum, 859 AFE_TDMOUT_CONN0, 860 0, 861 0xf, 862 afe_conn_hdmi_mux_map, 863 afe_conn_hdmi_mux_map_value); 864 865 static const struct snd_kcontrol_new hdmi_ch0_mux_control = 866 SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum); 867 868 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum, 869 AFE_TDMOUT_CONN0, 870 4, 871 0xf, 872 afe_conn_hdmi_mux_map, 873 afe_conn_hdmi_mux_map_value); 874 875 static const struct snd_kcontrol_new hdmi_ch1_mux_control = 876 SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum); 877 878 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum, 879 AFE_TDMOUT_CONN0, 880 8, 881 0xf, 882 afe_conn_hdmi_mux_map, 883 afe_conn_hdmi_mux_map_value); 884 885 static const struct snd_kcontrol_new hdmi_ch2_mux_control = 886 SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum); 887 888 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum, 889 AFE_TDMOUT_CONN0, 890 12, 891 0xf, 892 afe_conn_hdmi_mux_map, 893 afe_conn_hdmi_mux_map_value); 894 895 static const struct snd_kcontrol_new hdmi_ch3_mux_control = 896 SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum); 897 898 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum, 899 AFE_TDMOUT_CONN0, 900 16, 901 0xf, 902 afe_conn_hdmi_mux_map, 903 afe_conn_hdmi_mux_map_value); 904 905 static const struct snd_kcontrol_new hdmi_ch4_mux_control = 906 SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum); 907 908 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum, 909 AFE_TDMOUT_CONN0, 910 20, 911 0xf, 912 afe_conn_hdmi_mux_map, 913 afe_conn_hdmi_mux_map_value); 914 915 static const struct snd_kcontrol_new hdmi_ch5_mux_control = 916 SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum); 917 918 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum, 919 AFE_TDMOUT_CONN0, 920 24, 921 0xf, 922 afe_conn_hdmi_mux_map, 923 afe_conn_hdmi_mux_map_value); 924 925 static const struct snd_kcontrol_new hdmi_ch6_mux_control = 926 SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum); 927 928 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum, 929 AFE_TDMOUT_CONN0, 930 28, 931 0xf, 932 afe_conn_hdmi_mux_map, 933 afe_conn_hdmi_mux_map_value); 934 935 static const struct snd_kcontrol_new hdmi_ch7_mux_control = 936 SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum); 937 938 static int mt8188_etdm_clk_src_sel_put(struct snd_kcontrol *kcontrol, 939 struct snd_ctl_elem_value *ucontrol) 940 { 941 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 942 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 943 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 944 unsigned int source = ucontrol->value.enumerated.item[0]; 945 unsigned int val; 946 unsigned int old_val; 947 unsigned int mask; 948 unsigned int reg; 949 950 if (source >= e->items) 951 return -EINVAL; 952 953 if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) { 954 reg = ETDM_OUT1_CON4; 955 mask = ETDM_OUT_CON4_CLOCK_MASK; 956 val = FIELD_PREP(ETDM_OUT_CON4_CLOCK_MASK, source); 957 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) { 958 reg = ETDM_OUT2_CON4; 959 mask = ETDM_OUT_CON4_CLOCK_MASK; 960 val = FIELD_PREP(ETDM_OUT_CON4_CLOCK_MASK, source); 961 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) { 962 reg = ETDM_OUT3_CON4; 963 mask = ETDM_OUT_CON4_CLOCK_MASK; 964 val = FIELD_PREP(ETDM_OUT_CON4_CLOCK_MASK, source); 965 } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) { 966 reg = ETDM_IN1_CON2; 967 mask = ETDM_IN_CON2_CLOCK_MASK; 968 val = FIELD_PREP(ETDM_IN_CON2_CLOCK_MASK, source); 969 } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) { 970 reg = ETDM_IN2_CON2; 971 mask = ETDM_IN_CON2_CLOCK_MASK; 972 val = FIELD_PREP(ETDM_IN_CON2_CLOCK_MASK, source); 973 } else { 974 return -EINVAL; 975 } 976 977 regmap_read(afe->regmap, reg, &old_val); 978 old_val &= mask; 979 if (old_val == val) 980 return 0; 981 982 regmap_update_bits(afe->regmap, reg, mask, val); 983 984 return 1; 985 } 986 987 static int mt8188_etdm_clk_src_sel_get(struct snd_kcontrol *kcontrol, 988 struct snd_ctl_elem_value *ucontrol) 989 { 990 struct snd_soc_component *component = 991 snd_soc_kcontrol_component(kcontrol); 992 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 993 unsigned int value; 994 unsigned int reg; 995 unsigned int mask; 996 unsigned int shift; 997 998 if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) { 999 reg = ETDM_OUT1_CON4; 1000 mask = ETDM_OUT_CON4_CLOCK_MASK; 1001 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 1002 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) { 1003 reg = ETDM_OUT2_CON4; 1004 mask = ETDM_OUT_CON4_CLOCK_MASK; 1005 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 1006 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) { 1007 reg = ETDM_OUT3_CON4; 1008 mask = ETDM_OUT_CON4_CLOCK_MASK; 1009 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 1010 } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) { 1011 reg = ETDM_IN1_CON2; 1012 mask = ETDM_IN_CON2_CLOCK_MASK; 1013 shift = ETDM_IN_CON2_CLOCK_SHIFT; 1014 } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) { 1015 reg = ETDM_IN2_CON2; 1016 mask = ETDM_IN_CON2_CLOCK_MASK; 1017 shift = ETDM_IN_CON2_CLOCK_SHIFT; 1018 } else { 1019 return -EINVAL; 1020 } 1021 1022 regmap_read(afe->regmap, reg, &value); 1023 1024 value &= mask; 1025 value >>= shift; 1026 ucontrol->value.enumerated.item[0] = value; 1027 return 0; 1028 } 1029 1030 static const struct snd_kcontrol_new mtk_dai_etdm_controls[] = { 1031 SOC_ENUM_EXT("ETDM_OUT1_Clock_Source", etdmout_clk_src_enum, 1032 mt8188_etdm_clk_src_sel_get, 1033 mt8188_etdm_clk_src_sel_put), 1034 SOC_ENUM_EXT("ETDM_OUT2_Clock_Source", etdmout_clk_src_enum, 1035 mt8188_etdm_clk_src_sel_get, 1036 mt8188_etdm_clk_src_sel_put), 1037 SOC_ENUM_EXT("ETDM_OUT3_Clock_Source", etdmout_clk_src_enum, 1038 mt8188_etdm_clk_src_sel_get, 1039 mt8188_etdm_clk_src_sel_put), 1040 SOC_ENUM_EXT("ETDM_IN1_Clock_Source", etdmout_clk_src_enum, 1041 mt8188_etdm_clk_src_sel_get, 1042 mt8188_etdm_clk_src_sel_put), 1043 SOC_ENUM_EXT("ETDM_IN2_Clock_Source", etdmout_clk_src_enum, 1044 mt8188_etdm_clk_src_sel_get, 1045 mt8188_etdm_clk_src_sel_put), 1046 }; 1047 1048 static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = { 1049 /* eTDM_IN2 */ 1050 SND_SOC_DAPM_MIXER("I012", SND_SOC_NOPM, 0, 0, NULL, 0), 1051 SND_SOC_DAPM_MIXER("I013", SND_SOC_NOPM, 0, 0, NULL, 0), 1052 SND_SOC_DAPM_MIXER("I014", SND_SOC_NOPM, 0, 0, NULL, 0), 1053 SND_SOC_DAPM_MIXER("I015", SND_SOC_NOPM, 0, 0, NULL, 0), 1054 SND_SOC_DAPM_MIXER("I016", SND_SOC_NOPM, 0, 0, NULL, 0), 1055 SND_SOC_DAPM_MIXER("I017", SND_SOC_NOPM, 0, 0, NULL, 0), 1056 SND_SOC_DAPM_MIXER("I018", SND_SOC_NOPM, 0, 0, NULL, 0), 1057 SND_SOC_DAPM_MIXER("I019", SND_SOC_NOPM, 0, 0, NULL, 0), 1058 SND_SOC_DAPM_MIXER("I188", SND_SOC_NOPM, 0, 0, NULL, 0), 1059 SND_SOC_DAPM_MIXER("I189", SND_SOC_NOPM, 0, 0, NULL, 0), 1060 SND_SOC_DAPM_MIXER("I190", SND_SOC_NOPM, 0, 0, NULL, 0), 1061 SND_SOC_DAPM_MIXER("I191", SND_SOC_NOPM, 0, 0, NULL, 0), 1062 SND_SOC_DAPM_MIXER("I192", SND_SOC_NOPM, 0, 0, NULL, 0), 1063 SND_SOC_DAPM_MIXER("I193", SND_SOC_NOPM, 0, 0, NULL, 0), 1064 SND_SOC_DAPM_MIXER("I194", SND_SOC_NOPM, 0, 0, NULL, 0), 1065 SND_SOC_DAPM_MIXER("I195", SND_SOC_NOPM, 0, 0, NULL, 0), 1066 1067 /* eTDM_IN1 */ 1068 SND_SOC_DAPM_MIXER("I072", SND_SOC_NOPM, 0, 0, NULL, 0), 1069 SND_SOC_DAPM_MIXER("I073", SND_SOC_NOPM, 0, 0, NULL, 0), 1070 SND_SOC_DAPM_MIXER("I074", SND_SOC_NOPM, 0, 0, NULL, 0), 1071 SND_SOC_DAPM_MIXER("I075", SND_SOC_NOPM, 0, 0, NULL, 0), 1072 SND_SOC_DAPM_MIXER("I076", SND_SOC_NOPM, 0, 0, NULL, 0), 1073 SND_SOC_DAPM_MIXER("I077", SND_SOC_NOPM, 0, 0, NULL, 0), 1074 SND_SOC_DAPM_MIXER("I078", SND_SOC_NOPM, 0, 0, NULL, 0), 1075 SND_SOC_DAPM_MIXER("I079", SND_SOC_NOPM, 0, 0, NULL, 0), 1076 SND_SOC_DAPM_MIXER("I080", SND_SOC_NOPM, 0, 0, NULL, 0), 1077 SND_SOC_DAPM_MIXER("I081", SND_SOC_NOPM, 0, 0, NULL, 0), 1078 SND_SOC_DAPM_MIXER("I082", SND_SOC_NOPM, 0, 0, NULL, 0), 1079 SND_SOC_DAPM_MIXER("I083", SND_SOC_NOPM, 0, 0, NULL, 0), 1080 SND_SOC_DAPM_MIXER("I084", SND_SOC_NOPM, 0, 0, NULL, 0), 1081 SND_SOC_DAPM_MIXER("I085", SND_SOC_NOPM, 0, 0, NULL, 0), 1082 SND_SOC_DAPM_MIXER("I086", SND_SOC_NOPM, 0, 0, NULL, 0), 1083 SND_SOC_DAPM_MIXER("I087", SND_SOC_NOPM, 0, 0, NULL, 0), 1084 1085 /* eTDM_OUT2 */ 1086 SND_SOC_DAPM_MIXER("O048", SND_SOC_NOPM, 0, 0, 1087 mtk_dai_etdm_o048_mix, ARRAY_SIZE(mtk_dai_etdm_o048_mix)), 1088 SND_SOC_DAPM_MIXER("O049", SND_SOC_NOPM, 0, 0, 1089 mtk_dai_etdm_o049_mix, ARRAY_SIZE(mtk_dai_etdm_o049_mix)), 1090 SND_SOC_DAPM_MIXER("O050", SND_SOC_NOPM, 0, 0, 1091 mtk_dai_etdm_o050_mix, ARRAY_SIZE(mtk_dai_etdm_o050_mix)), 1092 SND_SOC_DAPM_MIXER("O051", SND_SOC_NOPM, 0, 0, 1093 mtk_dai_etdm_o051_mix, ARRAY_SIZE(mtk_dai_etdm_o051_mix)), 1094 SND_SOC_DAPM_MIXER("O052", SND_SOC_NOPM, 0, 0, 1095 mtk_dai_etdm_o052_mix, ARRAY_SIZE(mtk_dai_etdm_o052_mix)), 1096 SND_SOC_DAPM_MIXER("O053", SND_SOC_NOPM, 0, 0, 1097 mtk_dai_etdm_o053_mix, ARRAY_SIZE(mtk_dai_etdm_o053_mix)), 1098 SND_SOC_DAPM_MIXER("O054", SND_SOC_NOPM, 0, 0, 1099 mtk_dai_etdm_o054_mix, ARRAY_SIZE(mtk_dai_etdm_o054_mix)), 1100 SND_SOC_DAPM_MIXER("O055", SND_SOC_NOPM, 0, 0, 1101 mtk_dai_etdm_o055_mix, ARRAY_SIZE(mtk_dai_etdm_o055_mix)), 1102 SND_SOC_DAPM_MIXER("O056", SND_SOC_NOPM, 0, 0, 1103 mtk_dai_etdm_o056_mix, ARRAY_SIZE(mtk_dai_etdm_o056_mix)), 1104 SND_SOC_DAPM_MIXER("O057", SND_SOC_NOPM, 0, 0, 1105 mtk_dai_etdm_o057_mix, ARRAY_SIZE(mtk_dai_etdm_o057_mix)), 1106 SND_SOC_DAPM_MIXER("O058", SND_SOC_NOPM, 0, 0, 1107 mtk_dai_etdm_o058_mix, ARRAY_SIZE(mtk_dai_etdm_o058_mix)), 1108 SND_SOC_DAPM_MIXER("O059", SND_SOC_NOPM, 0, 0, 1109 mtk_dai_etdm_o059_mix, ARRAY_SIZE(mtk_dai_etdm_o059_mix)), 1110 SND_SOC_DAPM_MIXER("O060", SND_SOC_NOPM, 0, 0, 1111 mtk_dai_etdm_o060_mix, ARRAY_SIZE(mtk_dai_etdm_o060_mix)), 1112 SND_SOC_DAPM_MIXER("O061", SND_SOC_NOPM, 0, 0, 1113 mtk_dai_etdm_o061_mix, ARRAY_SIZE(mtk_dai_etdm_o061_mix)), 1114 SND_SOC_DAPM_MIXER("O062", SND_SOC_NOPM, 0, 0, 1115 mtk_dai_etdm_o062_mix, ARRAY_SIZE(mtk_dai_etdm_o062_mix)), 1116 SND_SOC_DAPM_MIXER("O063", SND_SOC_NOPM, 0, 0, 1117 mtk_dai_etdm_o063_mix, ARRAY_SIZE(mtk_dai_etdm_o063_mix)), 1118 1119 /* eTDM_OUT1 */ 1120 SND_SOC_DAPM_MIXER("O072", SND_SOC_NOPM, 0, 0, 1121 mtk_dai_etdm_o072_mix, ARRAY_SIZE(mtk_dai_etdm_o072_mix)), 1122 SND_SOC_DAPM_MIXER("O073", SND_SOC_NOPM, 0, 0, 1123 mtk_dai_etdm_o073_mix, ARRAY_SIZE(mtk_dai_etdm_o073_mix)), 1124 SND_SOC_DAPM_MIXER("O074", SND_SOC_NOPM, 0, 0, 1125 mtk_dai_etdm_o074_mix, ARRAY_SIZE(mtk_dai_etdm_o074_mix)), 1126 SND_SOC_DAPM_MIXER("O075", SND_SOC_NOPM, 0, 0, 1127 mtk_dai_etdm_o075_mix, ARRAY_SIZE(mtk_dai_etdm_o075_mix)), 1128 SND_SOC_DAPM_MIXER("O076", SND_SOC_NOPM, 0, 0, 1129 mtk_dai_etdm_o076_mix, ARRAY_SIZE(mtk_dai_etdm_o076_mix)), 1130 SND_SOC_DAPM_MIXER("O077", SND_SOC_NOPM, 0, 0, 1131 mtk_dai_etdm_o077_mix, ARRAY_SIZE(mtk_dai_etdm_o077_mix)), 1132 SND_SOC_DAPM_MIXER("O078", SND_SOC_NOPM, 0, 0, 1133 mtk_dai_etdm_o078_mix, ARRAY_SIZE(mtk_dai_etdm_o078_mix)), 1134 SND_SOC_DAPM_MIXER("O079", SND_SOC_NOPM, 0, 0, 1135 mtk_dai_etdm_o079_mix, ARRAY_SIZE(mtk_dai_etdm_o079_mix)), 1136 SND_SOC_DAPM_MIXER("O080", SND_SOC_NOPM, 0, 0, 1137 mtk_dai_etdm_o080_mix, ARRAY_SIZE(mtk_dai_etdm_o080_mix)), 1138 SND_SOC_DAPM_MIXER("O081", SND_SOC_NOPM, 0, 0, 1139 mtk_dai_etdm_o081_mix, ARRAY_SIZE(mtk_dai_etdm_o081_mix)), 1140 SND_SOC_DAPM_MIXER("O082", SND_SOC_NOPM, 0, 0, 1141 mtk_dai_etdm_o082_mix, ARRAY_SIZE(mtk_dai_etdm_o082_mix)), 1142 SND_SOC_DAPM_MIXER("O083", SND_SOC_NOPM, 0, 0, 1143 mtk_dai_etdm_o083_mix, ARRAY_SIZE(mtk_dai_etdm_o083_mix)), 1144 SND_SOC_DAPM_MIXER("O084", SND_SOC_NOPM, 0, 0, 1145 mtk_dai_etdm_o084_mix, ARRAY_SIZE(mtk_dai_etdm_o084_mix)), 1146 SND_SOC_DAPM_MIXER("O085", SND_SOC_NOPM, 0, 0, 1147 mtk_dai_etdm_o085_mix, ARRAY_SIZE(mtk_dai_etdm_o085_mix)), 1148 SND_SOC_DAPM_MIXER("O086", SND_SOC_NOPM, 0, 0, 1149 mtk_dai_etdm_o086_mix, ARRAY_SIZE(mtk_dai_etdm_o086_mix)), 1150 SND_SOC_DAPM_MIXER("O087", SND_SOC_NOPM, 0, 0, 1151 mtk_dai_etdm_o087_mix, ARRAY_SIZE(mtk_dai_etdm_o087_mix)), 1152 1153 /* eTDM_OUT3 */ 1154 SND_SOC_DAPM_MUX("HDMI_OUT_MUX", SND_SOC_NOPM, 0, 0, 1155 &hdmi_out_mux_control), 1156 SND_SOC_DAPM_MUX("DPTX_OUT_MUX", SND_SOC_NOPM, 0, 0, 1157 &dptx_out_mux_control), 1158 1159 SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0, 1160 &hdmi_ch0_mux_control), 1161 SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0, 1162 &hdmi_ch1_mux_control), 1163 SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0, 1164 &hdmi_ch2_mux_control), 1165 SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0, 1166 &hdmi_ch3_mux_control), 1167 SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0, 1168 &hdmi_ch4_mux_control), 1169 SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0, 1170 &hdmi_ch5_mux_control), 1171 SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0, 1172 &hdmi_ch6_mux_control), 1173 SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0, 1174 &hdmi_ch7_mux_control), 1175 1176 /* mclk en */ 1177 SND_SOC_DAPM_SUPPLY_S("ETDM1_IN_MCLK", SUPPLY_SEQ_ETDM_MCLK, 1178 SND_SOC_NOPM, 0, 0, 1179 mtk_etdm_mclk_event, 1180 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1181 SND_SOC_DAPM_SUPPLY_S("ETDM2_IN_MCLK", SUPPLY_SEQ_ETDM_MCLK, 1182 SND_SOC_NOPM, 0, 0, 1183 mtk_etdm_mclk_event, 1184 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1185 SND_SOC_DAPM_SUPPLY_S("ETDM1_OUT_MCLK", SUPPLY_SEQ_ETDM_MCLK, 1186 SND_SOC_NOPM, 0, 0, 1187 mtk_etdm_mclk_event, 1188 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1189 SND_SOC_DAPM_SUPPLY_S("ETDM2_OUT_MCLK", SUPPLY_SEQ_ETDM_MCLK, 1190 SND_SOC_NOPM, 0, 0, 1191 mtk_etdm_mclk_event, 1192 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1193 SND_SOC_DAPM_SUPPLY_S("DPTX_MCLK", SUPPLY_SEQ_ETDM_MCLK, 1194 SND_SOC_NOPM, 0, 0, 1195 mtk_dptx_mclk_event, 1196 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1197 1198 /* cg */ 1199 SND_SOC_DAPM_SUPPLY_S("ETDM1_IN_CG", SUPPLY_SEQ_ETDM_CG, 1200 SND_SOC_NOPM, 0, 0, 1201 mtk_etdm_cg_event, 1202 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1203 SND_SOC_DAPM_SUPPLY_S("ETDM2_IN_CG", SUPPLY_SEQ_ETDM_CG, 1204 SND_SOC_NOPM, 0, 0, 1205 mtk_etdm_cg_event, 1206 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1207 SND_SOC_DAPM_SUPPLY_S("ETDM1_OUT_CG", SUPPLY_SEQ_ETDM_CG, 1208 SND_SOC_NOPM, 0, 0, 1209 mtk_etdm_cg_event, 1210 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1211 SND_SOC_DAPM_SUPPLY_S("ETDM2_OUT_CG", SUPPLY_SEQ_ETDM_CG, 1212 SND_SOC_NOPM, 0, 0, 1213 mtk_etdm_cg_event, 1214 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1215 SND_SOC_DAPM_SUPPLY_S("ETDM3_OUT_CG", SUPPLY_SEQ_ETDM_CG, 1216 SND_SOC_NOPM, 0, 0, 1217 mtk_etdm3_cg_event, 1218 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1219 1220 /* en */ 1221 SND_SOC_DAPM_SUPPLY_S("ETDM1_IN_EN", SUPPLY_SEQ_ETDM_EN, 1222 ETDM_IN1_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0), 1223 SND_SOC_DAPM_SUPPLY_S("ETDM2_IN_EN", SUPPLY_SEQ_ETDM_EN, 1224 ETDM_IN2_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0), 1225 SND_SOC_DAPM_SUPPLY_S("ETDM1_OUT_EN", SUPPLY_SEQ_ETDM_EN, 1226 ETDM_OUT1_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0), 1227 SND_SOC_DAPM_SUPPLY_S("ETDM2_OUT_EN", SUPPLY_SEQ_ETDM_EN, 1228 ETDM_OUT2_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0), 1229 SND_SOC_DAPM_SUPPLY_S("ETDM3_OUT_EN", SUPPLY_SEQ_ETDM_EN, 1230 ETDM_OUT3_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0), 1231 SND_SOC_DAPM_SUPPLY_S("DPTX_EN", SUPPLY_SEQ_DPTX_EN, 1232 AFE_DPTX_CON, AFE_DPTX_CON_ON_SHIFT, 0, NULL, 0), 1233 1234 SND_SOC_DAPM_INPUT("ETDM_INPUT"), 1235 SND_SOC_DAPM_OUTPUT("ETDM_OUTPUT"), 1236 }; 1237 1238 static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = { 1239 /* mclk */ 1240 {"ETDM1_IN", NULL, "ETDM1_IN_MCLK", mtk_etdm_mclk_connect}, 1241 {"ETDM1_IN", NULL, "ETDM2_IN_MCLK", mtk_etdm_mclk_connect}, 1242 {"ETDM1_IN", NULL, "ETDM1_OUT_MCLK", mtk_etdm_mclk_connect}, 1243 {"ETDM1_IN", NULL, "ETDM2_OUT_MCLK", mtk_etdm_mclk_connect}, 1244 1245 {"ETDM2_IN", NULL, "ETDM1_IN_MCLK", mtk_etdm_mclk_connect}, 1246 {"ETDM2_IN", NULL, "ETDM2_IN_MCLK", mtk_etdm_mclk_connect}, 1247 {"ETDM2_IN", NULL, "ETDM1_OUT_MCLK", mtk_etdm_mclk_connect}, 1248 {"ETDM2_IN", NULL, "ETDM2_OUT_MCLK", mtk_etdm_mclk_connect}, 1249 1250 {"ETDM1_OUT", NULL, "ETDM1_IN_MCLK", mtk_etdm_mclk_connect}, 1251 {"ETDM1_OUT", NULL, "ETDM2_IN_MCLK", mtk_etdm_mclk_connect}, 1252 {"ETDM1_OUT", NULL, "ETDM1_OUT_MCLK", mtk_etdm_mclk_connect}, 1253 {"ETDM1_OUT", NULL, "ETDM2_OUT_MCLK", mtk_etdm_mclk_connect}, 1254 1255 {"ETDM2_OUT", NULL, "ETDM1_IN_MCLK", mtk_etdm_mclk_connect}, 1256 {"ETDM2_OUT", NULL, "ETDM2_IN_MCLK", mtk_etdm_mclk_connect}, 1257 {"ETDM2_OUT", NULL, "ETDM1_OUT_MCLK", mtk_etdm_mclk_connect}, 1258 {"ETDM2_OUT", NULL, "ETDM2_OUT_MCLK", mtk_etdm_mclk_connect}, 1259 1260 {"DPTX", NULL, "DPTX_MCLK"}, 1261 1262 /* cg */ 1263 {"ETDM1_IN", NULL, "ETDM1_IN_CG"}, 1264 {"ETDM1_IN", NULL, "ETDM2_IN_CG", mtk_etdm_cowork_connect}, 1265 {"ETDM1_IN", NULL, "ETDM1_OUT_CG", mtk_etdm_cowork_connect}, 1266 {"ETDM1_IN", NULL, "ETDM2_OUT_CG", mtk_etdm_cowork_connect}, 1267 1268 {"ETDM2_IN", NULL, "ETDM1_IN_CG", mtk_etdm_cowork_connect}, 1269 {"ETDM2_IN", NULL, "ETDM2_IN_CG"}, 1270 {"ETDM2_IN", NULL, "ETDM1_OUT_CG", mtk_etdm_cowork_connect}, 1271 {"ETDM2_IN", NULL, "ETDM2_OUT_CG", mtk_etdm_cowork_connect}, 1272 1273 {"ETDM1_OUT", NULL, "ETDM1_IN_CG", mtk_etdm_cowork_connect}, 1274 {"ETDM1_OUT", NULL, "ETDM2_IN_CG", mtk_etdm_cowork_connect}, 1275 {"ETDM1_OUT", NULL, "ETDM1_OUT_CG"}, 1276 {"ETDM1_OUT", NULL, "ETDM2_OUT_CG", mtk_etdm_cowork_connect}, 1277 1278 {"ETDM2_OUT", NULL, "ETDM1_IN_CG", mtk_etdm_cowork_connect}, 1279 {"ETDM2_OUT", NULL, "ETDM2_IN_CG", mtk_etdm_cowork_connect}, 1280 {"ETDM2_OUT", NULL, "ETDM1_OUT_CG", mtk_etdm_cowork_connect}, 1281 {"ETDM2_OUT", NULL, "ETDM2_OUT_CG"}, 1282 1283 {"ETDM3_OUT", NULL, "ETDM3_OUT_CG"}, 1284 {"DPTX", NULL, "ETDM3_OUT_CG"}, 1285 1286 /* en */ 1287 {"ETDM1_IN", NULL, "ETDM1_IN_EN"}, 1288 {"ETDM1_IN", NULL, "ETDM2_IN_EN", mtk_etdm_cowork_connect}, 1289 {"ETDM1_IN", NULL, "ETDM1_OUT_EN", mtk_etdm_cowork_connect}, 1290 {"ETDM1_IN", NULL, "ETDM2_OUT_EN", mtk_etdm_cowork_connect}, 1291 1292 {"ETDM2_IN", NULL, "ETDM1_IN_EN", mtk_etdm_cowork_connect}, 1293 {"ETDM2_IN", NULL, "ETDM2_IN_EN"}, 1294 {"ETDM2_IN", NULL, "ETDM1_OUT_EN", mtk_etdm_cowork_connect}, 1295 {"ETDM2_IN", NULL, "ETDM2_OUT_EN", mtk_etdm_cowork_connect}, 1296 1297 {"ETDM1_OUT", NULL, "ETDM1_IN_EN", mtk_etdm_cowork_connect}, 1298 {"ETDM1_OUT", NULL, "ETDM2_IN_EN", mtk_etdm_cowork_connect}, 1299 {"ETDM1_OUT", NULL, "ETDM1_OUT_EN"}, 1300 {"ETDM1_OUT", NULL, "ETDM2_OUT_EN", mtk_etdm_cowork_connect}, 1301 1302 {"ETDM2_OUT", NULL, "ETDM1_IN_EN", mtk_etdm_cowork_connect}, 1303 {"ETDM2_OUT", NULL, "ETDM2_IN_EN", mtk_etdm_cowork_connect}, 1304 {"ETDM2_OUT", NULL, "ETDM1_OUT_EN", mtk_etdm_cowork_connect}, 1305 {"ETDM2_OUT", NULL, "ETDM2_OUT_EN"}, 1306 1307 {"ETDM3_OUT", NULL, "ETDM3_OUT_EN"}, 1308 {"DPTX", NULL, "ETDM3_OUT_EN"}, 1309 {"DPTX", NULL, "DPTX_EN"}, 1310 1311 {"I012", NULL, "ETDM2_IN"}, 1312 {"I013", NULL, "ETDM2_IN"}, 1313 {"I014", NULL, "ETDM2_IN"}, 1314 {"I015", NULL, "ETDM2_IN"}, 1315 {"I016", NULL, "ETDM2_IN"}, 1316 {"I017", NULL, "ETDM2_IN"}, 1317 {"I018", NULL, "ETDM2_IN"}, 1318 {"I019", NULL, "ETDM2_IN"}, 1319 {"I188", NULL, "ETDM2_IN"}, 1320 {"I189", NULL, "ETDM2_IN"}, 1321 {"I190", NULL, "ETDM2_IN"}, 1322 {"I191", NULL, "ETDM2_IN"}, 1323 {"I192", NULL, "ETDM2_IN"}, 1324 {"I193", NULL, "ETDM2_IN"}, 1325 {"I194", NULL, "ETDM2_IN"}, 1326 {"I195", NULL, "ETDM2_IN"}, 1327 1328 {"I072", NULL, "ETDM1_IN"}, 1329 {"I073", NULL, "ETDM1_IN"}, 1330 {"I074", NULL, "ETDM1_IN"}, 1331 {"I075", NULL, "ETDM1_IN"}, 1332 {"I076", NULL, "ETDM1_IN"}, 1333 {"I077", NULL, "ETDM1_IN"}, 1334 {"I078", NULL, "ETDM1_IN"}, 1335 {"I079", NULL, "ETDM1_IN"}, 1336 {"I080", NULL, "ETDM1_IN"}, 1337 {"I081", NULL, "ETDM1_IN"}, 1338 {"I082", NULL, "ETDM1_IN"}, 1339 {"I083", NULL, "ETDM1_IN"}, 1340 {"I084", NULL, "ETDM1_IN"}, 1341 {"I085", NULL, "ETDM1_IN"}, 1342 {"I086", NULL, "ETDM1_IN"}, 1343 {"I087", NULL, "ETDM1_IN"}, 1344 1345 {"UL8", NULL, "ETDM1_IN"}, 1346 {"UL3", NULL, "ETDM2_IN"}, 1347 1348 {"ETDM2_OUT", NULL, "O048"}, 1349 {"ETDM2_OUT", NULL, "O049"}, 1350 {"ETDM2_OUT", NULL, "O050"}, 1351 {"ETDM2_OUT", NULL, "O051"}, 1352 {"ETDM2_OUT", NULL, "O052"}, 1353 {"ETDM2_OUT", NULL, "O053"}, 1354 {"ETDM2_OUT", NULL, "O054"}, 1355 {"ETDM2_OUT", NULL, "O055"}, 1356 {"ETDM2_OUT", NULL, "O056"}, 1357 {"ETDM2_OUT", NULL, "O057"}, 1358 {"ETDM2_OUT", NULL, "O058"}, 1359 {"ETDM2_OUT", NULL, "O059"}, 1360 {"ETDM2_OUT", NULL, "O060"}, 1361 {"ETDM2_OUT", NULL, "O061"}, 1362 {"ETDM2_OUT", NULL, "O062"}, 1363 {"ETDM2_OUT", NULL, "O063"}, 1364 1365 {"ETDM1_OUT", NULL, "O072"}, 1366 {"ETDM1_OUT", NULL, "O073"}, 1367 {"ETDM1_OUT", NULL, "O074"}, 1368 {"ETDM1_OUT", NULL, "O075"}, 1369 {"ETDM1_OUT", NULL, "O076"}, 1370 {"ETDM1_OUT", NULL, "O077"}, 1371 {"ETDM1_OUT", NULL, "O078"}, 1372 {"ETDM1_OUT", NULL, "O079"}, 1373 {"ETDM1_OUT", NULL, "O080"}, 1374 {"ETDM1_OUT", NULL, "O081"}, 1375 {"ETDM1_OUT", NULL, "O082"}, 1376 {"ETDM1_OUT", NULL, "O083"}, 1377 {"ETDM1_OUT", NULL, "O084"}, 1378 {"ETDM1_OUT", NULL, "O085"}, 1379 {"ETDM1_OUT", NULL, "O086"}, 1380 {"ETDM1_OUT", NULL, "O087"}, 1381 1382 {"O048", "I020 Switch", "I020"}, 1383 {"O049", "I021 Switch", "I021"}, 1384 1385 {"O048", "I022 Switch", "I022"}, 1386 {"O049", "I023 Switch", "I023"}, 1387 {"O050", "I024 Switch", "I024"}, 1388 {"O051", "I025 Switch", "I025"}, 1389 {"O052", "I026 Switch", "I026"}, 1390 {"O053", "I027 Switch", "I027"}, 1391 {"O054", "I028 Switch", "I028"}, 1392 {"O055", "I029 Switch", "I029"}, 1393 {"O056", "I030 Switch", "I030"}, 1394 {"O057", "I031 Switch", "I031"}, 1395 {"O058", "I032 Switch", "I032"}, 1396 {"O059", "I033 Switch", "I033"}, 1397 {"O060", "I034 Switch", "I034"}, 1398 {"O061", "I035 Switch", "I035"}, 1399 {"O062", "I036 Switch", "I036"}, 1400 {"O063", "I037 Switch", "I037"}, 1401 1402 {"O048", "I046 Switch", "I046"}, 1403 {"O049", "I047 Switch", "I047"}, 1404 {"O050", "I048 Switch", "I048"}, 1405 {"O051", "I049 Switch", "I049"}, 1406 {"O052", "I050 Switch", "I050"}, 1407 {"O053", "I051 Switch", "I051"}, 1408 {"O054", "I052 Switch", "I052"}, 1409 {"O055", "I053 Switch", "I053"}, 1410 {"O056", "I054 Switch", "I054"}, 1411 {"O057", "I055 Switch", "I055"}, 1412 {"O058", "I056 Switch", "I056"}, 1413 {"O059", "I057 Switch", "I057"}, 1414 {"O060", "I058 Switch", "I058"}, 1415 {"O061", "I059 Switch", "I059"}, 1416 {"O062", "I060 Switch", "I060"}, 1417 {"O063", "I061 Switch", "I061"}, 1418 1419 {"O048", "I070 Switch", "I070"}, 1420 {"O049", "I071 Switch", "I071"}, 1421 1422 {"O072", "I020 Switch", "I020"}, 1423 {"O073", "I021 Switch", "I021"}, 1424 1425 {"O072", "I022 Switch", "I022"}, 1426 {"O073", "I023 Switch", "I023"}, 1427 {"O074", "I024 Switch", "I024"}, 1428 {"O075", "I025 Switch", "I025"}, 1429 {"O076", "I026 Switch", "I026"}, 1430 {"O077", "I027 Switch", "I027"}, 1431 {"O078", "I028 Switch", "I028"}, 1432 {"O079", "I029 Switch", "I029"}, 1433 {"O080", "I030 Switch", "I030"}, 1434 {"O081", "I031 Switch", "I031"}, 1435 {"O082", "I032 Switch", "I032"}, 1436 {"O083", "I033 Switch", "I033"}, 1437 {"O084", "I034 Switch", "I034"}, 1438 {"O085", "I035 Switch", "I035"}, 1439 {"O086", "I036 Switch", "I036"}, 1440 {"O087", "I037 Switch", "I037"}, 1441 1442 {"O072", "I046 Switch", "I046"}, 1443 {"O073", "I047 Switch", "I047"}, 1444 {"O074", "I048 Switch", "I048"}, 1445 {"O075", "I049 Switch", "I049"}, 1446 {"O076", "I050 Switch", "I050"}, 1447 {"O077", "I051 Switch", "I051"}, 1448 {"O078", "I052 Switch", "I052"}, 1449 {"O079", "I053 Switch", "I053"}, 1450 {"O080", "I054 Switch", "I054"}, 1451 {"O081", "I055 Switch", "I055"}, 1452 {"O082", "I056 Switch", "I056"}, 1453 {"O083", "I057 Switch", "I057"}, 1454 {"O084", "I058 Switch", "I058"}, 1455 {"O085", "I059 Switch", "I059"}, 1456 {"O086", "I060 Switch", "I060"}, 1457 {"O087", "I061 Switch", "I061"}, 1458 1459 {"O072", "I070 Switch", "I070"}, 1460 {"O073", "I071 Switch", "I071"}, 1461 1462 {"HDMI_CH0_MUX", "CH0", "DL10"}, 1463 {"HDMI_CH0_MUX", "CH1", "DL10"}, 1464 {"HDMI_CH0_MUX", "CH2", "DL10"}, 1465 {"HDMI_CH0_MUX", "CH3", "DL10"}, 1466 {"HDMI_CH0_MUX", "CH4", "DL10"}, 1467 {"HDMI_CH0_MUX", "CH5", "DL10"}, 1468 {"HDMI_CH0_MUX", "CH6", "DL10"}, 1469 {"HDMI_CH0_MUX", "CH7", "DL10"}, 1470 1471 {"HDMI_CH1_MUX", "CH0", "DL10"}, 1472 {"HDMI_CH1_MUX", "CH1", "DL10"}, 1473 {"HDMI_CH1_MUX", "CH2", "DL10"}, 1474 {"HDMI_CH1_MUX", "CH3", "DL10"}, 1475 {"HDMI_CH1_MUX", "CH4", "DL10"}, 1476 {"HDMI_CH1_MUX", "CH5", "DL10"}, 1477 {"HDMI_CH1_MUX", "CH6", "DL10"}, 1478 {"HDMI_CH1_MUX", "CH7", "DL10"}, 1479 1480 {"HDMI_CH2_MUX", "CH0", "DL10"}, 1481 {"HDMI_CH2_MUX", "CH1", "DL10"}, 1482 {"HDMI_CH2_MUX", "CH2", "DL10"}, 1483 {"HDMI_CH2_MUX", "CH3", "DL10"}, 1484 {"HDMI_CH2_MUX", "CH4", "DL10"}, 1485 {"HDMI_CH2_MUX", "CH5", "DL10"}, 1486 {"HDMI_CH2_MUX", "CH6", "DL10"}, 1487 {"HDMI_CH2_MUX", "CH7", "DL10"}, 1488 1489 {"HDMI_CH3_MUX", "CH0", "DL10"}, 1490 {"HDMI_CH3_MUX", "CH1", "DL10"}, 1491 {"HDMI_CH3_MUX", "CH2", "DL10"}, 1492 {"HDMI_CH3_MUX", "CH3", "DL10"}, 1493 {"HDMI_CH3_MUX", "CH4", "DL10"}, 1494 {"HDMI_CH3_MUX", "CH5", "DL10"}, 1495 {"HDMI_CH3_MUX", "CH6", "DL10"}, 1496 {"HDMI_CH3_MUX", "CH7", "DL10"}, 1497 1498 {"HDMI_CH4_MUX", "CH0", "DL10"}, 1499 {"HDMI_CH4_MUX", "CH1", "DL10"}, 1500 {"HDMI_CH4_MUX", "CH2", "DL10"}, 1501 {"HDMI_CH4_MUX", "CH3", "DL10"}, 1502 {"HDMI_CH4_MUX", "CH4", "DL10"}, 1503 {"HDMI_CH4_MUX", "CH5", "DL10"}, 1504 {"HDMI_CH4_MUX", "CH6", "DL10"}, 1505 {"HDMI_CH4_MUX", "CH7", "DL10"}, 1506 1507 {"HDMI_CH5_MUX", "CH0", "DL10"}, 1508 {"HDMI_CH5_MUX", "CH1", "DL10"}, 1509 {"HDMI_CH5_MUX", "CH2", "DL10"}, 1510 {"HDMI_CH5_MUX", "CH3", "DL10"}, 1511 {"HDMI_CH5_MUX", "CH4", "DL10"}, 1512 {"HDMI_CH5_MUX", "CH5", "DL10"}, 1513 {"HDMI_CH5_MUX", "CH6", "DL10"}, 1514 {"HDMI_CH5_MUX", "CH7", "DL10"}, 1515 1516 {"HDMI_CH6_MUX", "CH0", "DL10"}, 1517 {"HDMI_CH6_MUX", "CH1", "DL10"}, 1518 {"HDMI_CH6_MUX", "CH2", "DL10"}, 1519 {"HDMI_CH6_MUX", "CH3", "DL10"}, 1520 {"HDMI_CH6_MUX", "CH4", "DL10"}, 1521 {"HDMI_CH6_MUX", "CH5", "DL10"}, 1522 {"HDMI_CH6_MUX", "CH6", "DL10"}, 1523 {"HDMI_CH6_MUX", "CH7", "DL10"}, 1524 1525 {"HDMI_CH7_MUX", "CH0", "DL10"}, 1526 {"HDMI_CH7_MUX", "CH1", "DL10"}, 1527 {"HDMI_CH7_MUX", "CH2", "DL10"}, 1528 {"HDMI_CH7_MUX", "CH3", "DL10"}, 1529 {"HDMI_CH7_MUX", "CH4", "DL10"}, 1530 {"HDMI_CH7_MUX", "CH5", "DL10"}, 1531 {"HDMI_CH7_MUX", "CH6", "DL10"}, 1532 {"HDMI_CH7_MUX", "CH7", "DL10"}, 1533 1534 {"HDMI_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, 1535 {"HDMI_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, 1536 {"HDMI_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, 1537 {"HDMI_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, 1538 {"HDMI_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, 1539 {"HDMI_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, 1540 {"HDMI_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, 1541 {"HDMI_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, 1542 1543 {"DPTX_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, 1544 {"DPTX_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, 1545 {"DPTX_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, 1546 {"DPTX_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, 1547 {"DPTX_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, 1548 {"DPTX_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, 1549 {"DPTX_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, 1550 {"DPTX_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, 1551 1552 {"ETDM3_OUT", NULL, "HDMI_OUT_MUX"}, 1553 {"DPTX", NULL, "DPTX_OUT_MUX"}, 1554 1555 {"ETDM_OUTPUT", NULL, "DPTX"}, 1556 {"ETDM_OUTPUT", NULL, "ETDM1_OUT"}, 1557 {"ETDM_OUTPUT", NULL, "ETDM2_OUT"}, 1558 {"ETDM_OUTPUT", NULL, "ETDM3_OUT"}, 1559 {"ETDM1_IN", NULL, "ETDM_INPUT"}, 1560 {"ETDM2_IN", NULL, "ETDM_INPUT"}, 1561 }; 1562 1563 static int etdm_cowork_slv_sel(int id, int slave_mode) 1564 { 1565 if (slave_mode) { 1566 switch (id) { 1567 case MT8188_AFE_IO_ETDM1_IN: 1568 return COWORK_ETDM_IN1_S; 1569 case MT8188_AFE_IO_ETDM2_IN: 1570 return COWORK_ETDM_IN2_S; 1571 case MT8188_AFE_IO_ETDM1_OUT: 1572 return COWORK_ETDM_OUT1_S; 1573 case MT8188_AFE_IO_ETDM2_OUT: 1574 return COWORK_ETDM_OUT2_S; 1575 case MT8188_AFE_IO_ETDM3_OUT: 1576 return COWORK_ETDM_OUT3_S; 1577 default: 1578 return -EINVAL; 1579 } 1580 } else { 1581 switch (id) { 1582 case MT8188_AFE_IO_ETDM1_IN: 1583 return COWORK_ETDM_IN1_M; 1584 case MT8188_AFE_IO_ETDM2_IN: 1585 return COWORK_ETDM_IN2_M; 1586 case MT8188_AFE_IO_ETDM1_OUT: 1587 return COWORK_ETDM_OUT1_M; 1588 case MT8188_AFE_IO_ETDM2_OUT: 1589 return COWORK_ETDM_OUT2_M; 1590 case MT8188_AFE_IO_ETDM3_OUT: 1591 return COWORK_ETDM_OUT3_M; 1592 default: 1593 return -EINVAL; 1594 } 1595 } 1596 } 1597 1598 static int etdm_cowork_sync_sel(int id) 1599 { 1600 switch (id) { 1601 case MT8188_AFE_IO_ETDM1_IN: 1602 return ETDM_SYNC_FROM_IN1; 1603 case MT8188_AFE_IO_ETDM2_IN: 1604 return ETDM_SYNC_FROM_IN2; 1605 case MT8188_AFE_IO_ETDM1_OUT: 1606 return ETDM_SYNC_FROM_OUT1; 1607 case MT8188_AFE_IO_ETDM2_OUT: 1608 return ETDM_SYNC_FROM_OUT2; 1609 case MT8188_AFE_IO_ETDM3_OUT: 1610 return ETDM_SYNC_FROM_OUT3; 1611 default: 1612 return -EINVAL; 1613 } 1614 } 1615 1616 static int mt8188_etdm_sync_mode_slv(struct mtk_base_afe *afe, int dai_id) 1617 { 1618 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1619 struct mtk_dai_etdm_priv *etdm_data; 1620 unsigned int reg = 0; 1621 unsigned int mask; 1622 unsigned int val; 1623 int cowork_source_sel; 1624 1625 if (!is_valid_etdm_dai(dai_id)) 1626 return -EINVAL; 1627 etdm_data = afe_priv->dai_priv[dai_id]; 1628 1629 cowork_source_sel = etdm_cowork_slv_sel(etdm_data->cowork_source_id, 1630 true); 1631 if (cowork_source_sel < 0) 1632 return cowork_source_sel; 1633 1634 switch (dai_id) { 1635 case MT8188_AFE_IO_ETDM1_IN: 1636 reg = ETDM_COWORK_CON1; 1637 mask = ETDM_IN1_SLAVE_SEL_MASK; 1638 val = FIELD_PREP(ETDM_IN1_SLAVE_SEL_MASK, cowork_source_sel); 1639 break; 1640 case MT8188_AFE_IO_ETDM2_IN: 1641 reg = ETDM_COWORK_CON2; 1642 mask = ETDM_IN2_SLAVE_SEL_MASK; 1643 val = FIELD_PREP(ETDM_IN2_SLAVE_SEL_MASK, cowork_source_sel); 1644 break; 1645 case MT8188_AFE_IO_ETDM1_OUT: 1646 reg = ETDM_COWORK_CON0; 1647 mask = ETDM_OUT1_SLAVE_SEL_MASK; 1648 val = FIELD_PREP(ETDM_OUT1_SLAVE_SEL_MASK, cowork_source_sel); 1649 break; 1650 case MT8188_AFE_IO_ETDM2_OUT: 1651 reg = ETDM_COWORK_CON2; 1652 mask = ETDM_OUT2_SLAVE_SEL_MASK; 1653 val = FIELD_PREP(ETDM_OUT2_SLAVE_SEL_MASK, cowork_source_sel); 1654 break; 1655 case MT8188_AFE_IO_ETDM3_OUT: 1656 reg = ETDM_COWORK_CON2; 1657 mask = ETDM_OUT3_SLAVE_SEL_MASK; 1658 val = FIELD_PREP(ETDM_OUT3_SLAVE_SEL_MASK, cowork_source_sel); 1659 break; 1660 default: 1661 return 0; 1662 } 1663 1664 regmap_update_bits(afe->regmap, reg, mask, val); 1665 1666 return 0; 1667 } 1668 1669 static int mt8188_etdm_sync_mode_mst(struct mtk_base_afe *afe, int dai_id) 1670 { 1671 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1672 struct mtk_dai_etdm_priv *etdm_data; 1673 struct etdm_con_reg etdm_reg; 1674 unsigned int reg = 0; 1675 unsigned int mask; 1676 unsigned int val; 1677 int cowork_source_sel; 1678 int ret; 1679 1680 if (!is_valid_etdm_dai(dai_id)) 1681 return -EINVAL; 1682 etdm_data = afe_priv->dai_priv[dai_id]; 1683 1684 cowork_source_sel = etdm_cowork_sync_sel(etdm_data->cowork_source_id); 1685 if (cowork_source_sel < 0) 1686 return cowork_source_sel; 1687 1688 switch (dai_id) { 1689 case MT8188_AFE_IO_ETDM1_IN: 1690 reg = ETDM_COWORK_CON1; 1691 mask = ETDM_IN1_SYNC_SEL_MASK; 1692 val = FIELD_PREP(ETDM_IN1_SYNC_SEL_MASK, cowork_source_sel); 1693 break; 1694 case MT8188_AFE_IO_ETDM2_IN: 1695 reg = ETDM_COWORK_CON2; 1696 mask = ETDM_IN2_SYNC_SEL_MASK; 1697 val = FIELD_PREP(ETDM_IN2_SYNC_SEL_MASK, cowork_source_sel); 1698 break; 1699 case MT8188_AFE_IO_ETDM1_OUT: 1700 reg = ETDM_COWORK_CON0; 1701 mask = ETDM_OUT1_SYNC_SEL_MASK; 1702 val = FIELD_PREP(ETDM_OUT1_SYNC_SEL_MASK, cowork_source_sel); 1703 break; 1704 case MT8188_AFE_IO_ETDM2_OUT: 1705 reg = ETDM_COWORK_CON2; 1706 mask = ETDM_OUT2_SYNC_SEL_MASK; 1707 val = FIELD_PREP(ETDM_OUT2_SYNC_SEL_MASK, cowork_source_sel); 1708 break; 1709 case MT8188_AFE_IO_ETDM3_OUT: 1710 reg = ETDM_COWORK_CON2; 1711 mask = ETDM_OUT3_SYNC_SEL_MASK; 1712 val = FIELD_PREP(ETDM_OUT3_SYNC_SEL_MASK, cowork_source_sel); 1713 break; 1714 default: 1715 return 0; 1716 } 1717 1718 ret = get_etdm_reg(dai_id, &etdm_reg); 1719 if (ret < 0) 1720 return ret; 1721 1722 regmap_update_bits(afe->regmap, reg, mask, val); 1723 1724 regmap_set_bits(afe->regmap, etdm_reg.con0, ETDM_CON0_SYNC_MODE); 1725 1726 return 0; 1727 } 1728 1729 static int mt8188_etdm_sync_mode_configure(struct mtk_base_afe *afe, int dai_id) 1730 { 1731 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1732 struct mtk_dai_etdm_priv *etdm_data; 1733 1734 if (!is_valid_etdm_dai(dai_id)) 1735 return -EINVAL; 1736 etdm_data = afe_priv->dai_priv[dai_id]; 1737 1738 if (etdm_data->cowork_source_id == COWORK_ETDM_NONE) 1739 return 0; 1740 1741 if (etdm_data->slave_mode) 1742 mt8188_etdm_sync_mode_slv(afe, dai_id); 1743 else 1744 mt8188_etdm_sync_mode_mst(afe, dai_id); 1745 1746 return 0; 1747 } 1748 1749 /* dai ops */ 1750 static int mtk_dai_etdm_fifo_mode(struct mtk_base_afe *afe, 1751 int dai_id, unsigned int rate) 1752 { 1753 unsigned int mode = 0; 1754 unsigned int reg = 0; 1755 unsigned int val = 0; 1756 unsigned int mask = (ETDM_IN_AFIFO_MODE_MASK | ETDM_IN_USE_AFIFO); 1757 1758 if (rate != 0) 1759 mode = mt8188_afe_fs_timing(rate); 1760 1761 switch (dai_id) { 1762 case MT8188_AFE_IO_ETDM1_IN: 1763 reg = ETDM_IN1_AFIFO_CON; 1764 if (rate == 0) 1765 mode = MT8188_ETDM_IN1_1X_EN; 1766 break; 1767 case MT8188_AFE_IO_ETDM2_IN: 1768 reg = ETDM_IN2_AFIFO_CON; 1769 if (rate == 0) 1770 mode = MT8188_ETDM_IN2_1X_EN; 1771 break; 1772 default: 1773 return -EINVAL; 1774 } 1775 1776 val = (mode | ETDM_IN_USE_AFIFO); 1777 1778 regmap_update_bits(afe->regmap, reg, mask, val); 1779 return 0; 1780 } 1781 1782 static int mtk_dai_etdm_in_configure(struct mtk_base_afe *afe, 1783 unsigned int rate, 1784 unsigned int channels, 1785 int dai_id) 1786 { 1787 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1788 struct mtk_dai_etdm_priv *etdm_data; 1789 struct etdm_con_reg etdm_reg; 1790 bool slave_mode; 1791 unsigned int data_mode; 1792 unsigned int lrck_width; 1793 unsigned int val = 0; 1794 unsigned int mask = 0; 1795 int ret; 1796 int i; 1797 1798 if (!is_valid_etdm_dai(dai_id)) 1799 return -EINVAL; 1800 etdm_data = afe_priv->dai_priv[dai_id]; 1801 slave_mode = etdm_data->slave_mode; 1802 data_mode = etdm_data->data_mode; 1803 lrck_width = etdm_data->lrck_width; 1804 1805 dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n", 1806 __func__, rate, channels, dai_id); 1807 1808 ret = get_etdm_reg(dai_id, &etdm_reg); 1809 if (ret < 0) 1810 return ret; 1811 1812 /* afifo */ 1813 if (slave_mode) 1814 mtk_dai_etdm_fifo_mode(afe, dai_id, 0); 1815 else 1816 mtk_dai_etdm_fifo_mode(afe, dai_id, rate); 1817 1818 /* con1 */ 1819 if (lrck_width > 0) { 1820 mask |= (ETDM_IN_CON1_LRCK_AUTO_MODE | 1821 ETDM_IN_CON1_LRCK_WIDTH_MASK); 1822 val |= FIELD_PREP(ETDM_IN_CON1_LRCK_WIDTH_MASK, lrck_width - 1); 1823 } 1824 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 1825 1826 mask = 0; 1827 val = 0; 1828 1829 /* con2 */ 1830 if (!slave_mode) { 1831 mask |= ETDM_IN_CON2_UPDATE_GAP_MASK; 1832 if (rate == 352800 || rate == 384000) 1833 val |= FIELD_PREP(ETDM_IN_CON2_UPDATE_GAP_MASK, 4); 1834 else 1835 val |= FIELD_PREP(ETDM_IN_CON2_UPDATE_GAP_MASK, 3); 1836 } 1837 mask |= (ETDM_IN_CON2_MULTI_IP_2CH_MODE | 1838 ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK); 1839 if (data_mode == MTK_DAI_ETDM_DATA_MULTI_PIN) { 1840 val |= ETDM_IN_CON2_MULTI_IP_2CH_MODE | 1841 FIELD_PREP(ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK, channels - 1); 1842 } 1843 regmap_update_bits(afe->regmap, etdm_reg.con2, mask, val); 1844 1845 mask = 0; 1846 val = 0; 1847 1848 /* con3 */ 1849 mask |= ETDM_IN_CON3_DISABLE_OUT_MASK; 1850 for (i = 0; i < channels; i += 2) { 1851 if (etdm_data->in_disable_ch[i] && 1852 etdm_data->in_disable_ch[i + 1]) 1853 val |= ETDM_IN_CON3_DISABLE_OUT(i >> 1); 1854 } 1855 if (!slave_mode) { 1856 mask |= ETDM_IN_CON3_FS_MASK; 1857 val |= FIELD_PREP(ETDM_IN_CON3_FS_MASK, get_etdm_fs_timing(rate)); 1858 } 1859 regmap_update_bits(afe->regmap, etdm_reg.con3, mask, val); 1860 1861 mask = 0; 1862 val = 0; 1863 1864 /* con4 */ 1865 mask |= (ETDM_IN_CON4_MASTER_LRCK_INV | ETDM_IN_CON4_MASTER_BCK_INV | 1866 ETDM_IN_CON4_SLAVE_LRCK_INV | ETDM_IN_CON4_SLAVE_BCK_INV); 1867 if (slave_mode) { 1868 if (etdm_data->lrck_inv) 1869 val |= ETDM_IN_CON4_SLAVE_LRCK_INV; 1870 if (etdm_data->bck_inv) 1871 val |= ETDM_IN_CON4_SLAVE_BCK_INV; 1872 } else { 1873 if (etdm_data->lrck_inv) 1874 val |= ETDM_IN_CON4_MASTER_LRCK_INV; 1875 if (etdm_data->bck_inv) 1876 val |= ETDM_IN_CON4_MASTER_BCK_INV; 1877 } 1878 regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val); 1879 1880 mask = 0; 1881 val = 0; 1882 1883 /* con5 */ 1884 mask |= ETDM_IN_CON5_LR_SWAP_MASK; 1885 mask |= ETDM_IN_CON5_ENABLE_ODD_MASK; 1886 for (i = 0; i < channels; i += 2) { 1887 if (etdm_data->in_disable_ch[i] && 1888 !etdm_data->in_disable_ch[i + 1]) { 1889 val |= ETDM_IN_CON5_LR_SWAP(i >> 1); 1890 val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1); 1891 } else if (!etdm_data->in_disable_ch[i] && 1892 etdm_data->in_disable_ch[i + 1]) { 1893 val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1); 1894 } 1895 } 1896 regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val); 1897 return 0; 1898 } 1899 1900 static int mtk_dai_etdm_out_configure(struct mtk_base_afe *afe, 1901 unsigned int rate, 1902 unsigned int channels, 1903 int dai_id) 1904 { 1905 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1906 struct mtk_dai_etdm_priv *etdm_data; 1907 struct etdm_con_reg etdm_reg; 1908 bool slave_mode; 1909 unsigned int lrck_width; 1910 unsigned int val = 0; 1911 unsigned int mask = 0; 1912 int fs = 0; 1913 int ret; 1914 1915 if (!is_valid_etdm_dai(dai_id)) 1916 return -EINVAL; 1917 etdm_data = afe_priv->dai_priv[dai_id]; 1918 slave_mode = etdm_data->slave_mode; 1919 lrck_width = etdm_data->lrck_width; 1920 1921 dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n", 1922 __func__, rate, channels, dai_id); 1923 1924 ret = get_etdm_reg(dai_id, &etdm_reg); 1925 if (ret < 0) 1926 return ret; 1927 1928 /* con0 */ 1929 mask = ETDM_OUT_CON0_RELATCH_DOMAIN_MASK; 1930 val = FIELD_PREP(ETDM_OUT_CON0_RELATCH_DOMAIN_MASK, 1931 ETDM_RELATCH_TIMING_A1A2SYS); 1932 regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val); 1933 1934 mask = 0; 1935 val = 0; 1936 1937 /* con1 */ 1938 if (lrck_width > 0) { 1939 mask |= (ETDM_OUT_CON1_LRCK_AUTO_MODE | 1940 ETDM_OUT_CON1_LRCK_WIDTH_MASK); 1941 val |= FIELD_PREP(ETDM_OUT_CON1_LRCK_WIDTH_MASK, lrck_width - 1); 1942 } 1943 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 1944 1945 mask = 0; 1946 val = 0; 1947 1948 if (!slave_mode) { 1949 /* con4 */ 1950 mask |= ETDM_OUT_CON4_FS_MASK; 1951 val |= FIELD_PREP(ETDM_OUT_CON4_FS_MASK, get_etdm_fs_timing(rate)); 1952 } 1953 1954 mask |= ETDM_OUT_CON4_RELATCH_EN_MASK; 1955 if (dai_id == MT8188_AFE_IO_ETDM1_OUT) 1956 fs = MT8188_ETDM_OUT1_1X_EN; 1957 else if (dai_id == MT8188_AFE_IO_ETDM2_OUT) 1958 fs = MT8188_ETDM_OUT2_1X_EN; 1959 1960 val |= FIELD_PREP(ETDM_OUT_CON4_RELATCH_EN_MASK, fs); 1961 1962 regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val); 1963 1964 mask = 0; 1965 val = 0; 1966 1967 /* con5 */ 1968 mask |= (ETDM_OUT_CON5_MASTER_LRCK_INV | ETDM_OUT_CON5_MASTER_BCK_INV | 1969 ETDM_OUT_CON5_SLAVE_LRCK_INV | ETDM_OUT_CON5_SLAVE_BCK_INV); 1970 if (slave_mode) { 1971 if (etdm_data->lrck_inv) 1972 val |= ETDM_OUT_CON5_SLAVE_LRCK_INV; 1973 if (etdm_data->bck_inv) 1974 val |= ETDM_OUT_CON5_SLAVE_BCK_INV; 1975 } else { 1976 if (etdm_data->lrck_inv) 1977 val |= ETDM_OUT_CON5_MASTER_LRCK_INV; 1978 if (etdm_data->bck_inv) 1979 val |= ETDM_OUT_CON5_MASTER_BCK_INV; 1980 } 1981 regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val); 1982 1983 return 0; 1984 } 1985 1986 static int mtk_dai_etdm_configure(struct mtk_base_afe *afe, 1987 unsigned int rate, 1988 unsigned int channels, 1989 unsigned int bit_width, 1990 int dai_id) 1991 { 1992 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1993 struct mtk_dai_etdm_priv *etdm_data; 1994 struct etdm_con_reg etdm_reg; 1995 bool slave_mode; 1996 unsigned int etdm_channels; 1997 unsigned int val = 0; 1998 unsigned int mask = 0; 1999 unsigned int bck; 2000 unsigned int wlen = get_etdm_wlen(bit_width); 2001 int ret; 2002 2003 if (!is_valid_etdm_dai(dai_id)) 2004 return -EINVAL; 2005 etdm_data = afe_priv->dai_priv[dai_id]; 2006 slave_mode = etdm_data->slave_mode; 2007 2008 ret = get_etdm_reg(dai_id, &etdm_reg); 2009 if (ret < 0) 2010 return ret; 2011 2012 dev_dbg(afe->dev, "%s fmt %u data %u lrck %d-%u bck %d, slv %u\n", 2013 __func__, etdm_data->format, etdm_data->data_mode, 2014 etdm_data->lrck_inv, etdm_data->lrck_width, etdm_data->bck_inv, 2015 etdm_data->slave_mode); 2016 dev_dbg(afe->dev, "%s rate %u channels %u bitwidth %u, id %d\n", 2017 __func__, rate, channels, bit_width, dai_id); 2018 2019 etdm_channels = (etdm_data->data_mode == MTK_DAI_ETDM_DATA_ONE_PIN) ? 2020 get_etdm_ch_fixup(channels) : 2; 2021 2022 bck = rate * etdm_channels * wlen; 2023 if (bck > MT8188_ETDM_NORMAL_MAX_BCK_RATE) { 2024 dev_err(afe->dev, "%s bck rate %u not support\n", 2025 __func__, bck); 2026 return -EINVAL; 2027 } 2028 2029 /* con0 */ 2030 mask |= ETDM_CON0_BIT_LEN_MASK; 2031 val |= FIELD_PREP(ETDM_CON0_BIT_LEN_MASK, bit_width - 1); 2032 mask |= ETDM_CON0_WORD_LEN_MASK; 2033 val |= FIELD_PREP(ETDM_CON0_WORD_LEN_MASK, wlen - 1); 2034 mask |= ETDM_CON0_FORMAT_MASK; 2035 val |= FIELD_PREP(ETDM_CON0_FORMAT_MASK, etdm_data->format); 2036 mask |= ETDM_CON0_CH_NUM_MASK; 2037 val |= FIELD_PREP(ETDM_CON0_CH_NUM_MASK, etdm_channels - 1); 2038 2039 mask |= ETDM_CON0_SLAVE_MODE; 2040 if (slave_mode) { 2041 if (dai_id == MT8188_AFE_IO_ETDM1_OUT) { 2042 dev_err(afe->dev, "%s id %d only support master mode\n", 2043 __func__, dai_id); 2044 return -EINVAL; 2045 } 2046 val |= ETDM_CON0_SLAVE_MODE; 2047 } 2048 regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val); 2049 2050 if (get_etdm_dir(dai_id) == ETDM_IN) 2051 mtk_dai_etdm_in_configure(afe, rate, channels, dai_id); 2052 else 2053 mtk_dai_etdm_out_configure(afe, rate, channels, dai_id); 2054 2055 return 0; 2056 } 2057 2058 static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream, 2059 struct snd_pcm_hw_params *params, 2060 struct snd_soc_dai *dai) 2061 { 2062 unsigned int rate = params_rate(params); 2063 unsigned int bit_width = params_width(params); 2064 unsigned int channels = params_channels(params); 2065 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2066 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2067 struct mtk_dai_etdm_priv *mst_etdm_data; 2068 int mst_dai_id; 2069 int slv_dai_id; 2070 int ret; 2071 int i; 2072 2073 dev_dbg(afe->dev, "%s '%s' period %u-%u\n", 2074 __func__, snd_pcm_stream_str(substream), 2075 params_period_size(params), params_periods(params)); 2076 2077 if (is_cowork_mode(dai)) { 2078 mst_dai_id = get_etdm_cowork_master_id(dai); 2079 if (!is_valid_etdm_dai(mst_dai_id)) 2080 return -EINVAL; 2081 2082 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 2083 if (mst_etdm_data->slots) 2084 channels = mst_etdm_data->slots; 2085 2086 ret = mtk_dai_etdm_configure(afe, rate, channels, 2087 bit_width, mst_dai_id); 2088 if (ret) 2089 return ret; 2090 2091 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 2092 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 2093 ret = mtk_dai_etdm_configure(afe, rate, channels, 2094 bit_width, slv_dai_id); 2095 if (ret) 2096 return ret; 2097 2098 ret = mt8188_etdm_sync_mode_configure(afe, slv_dai_id); 2099 if (ret) 2100 return ret; 2101 } 2102 } else { 2103 if (!is_valid_etdm_dai(dai->id)) 2104 return -EINVAL; 2105 mst_etdm_data = afe_priv->dai_priv[dai->id]; 2106 if (mst_etdm_data->slots) 2107 channels = mst_etdm_data->slots; 2108 2109 ret = mtk_dai_etdm_configure(afe, rate, channels, 2110 bit_width, dai->id); 2111 if (ret) 2112 return ret; 2113 } 2114 2115 return 0; 2116 } 2117 2118 static int mtk_dai_etdm_cal_mclk(struct mtk_base_afe *afe, int freq, int dai_id) 2119 { 2120 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2121 struct mtk_dai_etdm_priv *etdm_data; 2122 int apll_rate; 2123 int apll; 2124 2125 if (!is_valid_etdm_dai(dai_id)) 2126 return -EINVAL; 2127 etdm_data = afe_priv->dai_priv[dai_id]; 2128 2129 if (freq == 0) { 2130 etdm_data->mclk_freq = freq; 2131 return 0; 2132 } 2133 2134 if (etdm_data->mclk_fixed_apll == 0) 2135 apll = mt8188_afe_get_default_mclk_source_by_rate(freq); 2136 else 2137 apll = etdm_data->mclk_apll; 2138 2139 apll_rate = mt8188_afe_get_mclk_source_rate(afe, apll); 2140 2141 if (freq > apll_rate) { 2142 dev_err(afe->dev, "freq %d > apll rate %d\n", freq, apll_rate); 2143 return -EINVAL; 2144 } 2145 2146 if (apll_rate % freq != 0) { 2147 dev_err(afe->dev, "APLL%d cannot generate freq Hz\n", apll); 2148 return -EINVAL; 2149 } 2150 2151 if (etdm_data->mclk_fixed_apll == 0) 2152 etdm_data->mclk_apll = apll; 2153 etdm_data->mclk_freq = freq; 2154 2155 return 0; 2156 } 2157 2158 static int mtk_dai_etdm_set_sysclk(struct snd_soc_dai *dai, 2159 int clk_id, unsigned int freq, int dir) 2160 { 2161 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2162 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2163 struct mtk_dai_etdm_priv *etdm_data; 2164 int dai_id; 2165 2166 dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n", 2167 __func__, dai->id, freq, dir); 2168 if (is_cowork_mode(dai)) 2169 dai_id = get_etdm_cowork_master_id(dai); 2170 else 2171 dai_id = dai->id; 2172 2173 if (!is_valid_etdm_dai(dai_id)) 2174 return -EINVAL; 2175 etdm_data = afe_priv->dai_priv[dai_id]; 2176 etdm_data->mclk_dir = dir; 2177 return mtk_dai_etdm_cal_mclk(afe, freq, dai_id); 2178 } 2179 2180 static int mtk_dai_etdm_set_tdm_slot(struct snd_soc_dai *dai, 2181 unsigned int tx_mask, unsigned int rx_mask, 2182 int slots, int slot_width) 2183 { 2184 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2185 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2186 struct mtk_dai_etdm_priv *etdm_data; 2187 int dai_id; 2188 2189 if (is_cowork_mode(dai)) 2190 dai_id = get_etdm_cowork_master_id(dai); 2191 else 2192 dai_id = dai->id; 2193 2194 if (!is_valid_etdm_dai(dai_id)) 2195 return -EINVAL; 2196 etdm_data = afe_priv->dai_priv[dai_id]; 2197 2198 dev_dbg(dai->dev, "%s id %d slot_width %d\n", 2199 __func__, dai->id, slot_width); 2200 2201 etdm_data->slots = slots; 2202 etdm_data->lrck_width = slot_width; 2203 return 0; 2204 } 2205 2206 static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2207 { 2208 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2209 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2210 struct mtk_dai_etdm_priv *etdm_data; 2211 2212 if (!is_valid_etdm_dai(dai->id)) 2213 return -EINVAL; 2214 etdm_data = afe_priv->dai_priv[dai->id]; 2215 2216 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2217 case SND_SOC_DAIFMT_I2S: 2218 etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S; 2219 break; 2220 case SND_SOC_DAIFMT_LEFT_J: 2221 etdm_data->format = MTK_DAI_ETDM_FORMAT_LJ; 2222 break; 2223 case SND_SOC_DAIFMT_RIGHT_J: 2224 etdm_data->format = MTK_DAI_ETDM_FORMAT_RJ; 2225 break; 2226 case SND_SOC_DAIFMT_DSP_A: 2227 etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA; 2228 break; 2229 case SND_SOC_DAIFMT_DSP_B: 2230 etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB; 2231 break; 2232 default: 2233 return -EINVAL; 2234 } 2235 2236 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2237 case SND_SOC_DAIFMT_NB_NF: 2238 etdm_data->bck_inv = false; 2239 etdm_data->lrck_inv = false; 2240 break; 2241 case SND_SOC_DAIFMT_NB_IF: 2242 etdm_data->bck_inv = false; 2243 etdm_data->lrck_inv = true; 2244 break; 2245 case SND_SOC_DAIFMT_IB_NF: 2246 etdm_data->bck_inv = true; 2247 etdm_data->lrck_inv = false; 2248 break; 2249 case SND_SOC_DAIFMT_IB_IF: 2250 etdm_data->bck_inv = true; 2251 etdm_data->lrck_inv = true; 2252 break; 2253 default: 2254 return -EINVAL; 2255 } 2256 2257 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 2258 case SND_SOC_DAIFMT_BC_FC: 2259 etdm_data->slave_mode = true; 2260 break; 2261 case SND_SOC_DAIFMT_BP_FP: 2262 etdm_data->slave_mode = false; 2263 break; 2264 default: 2265 return -EINVAL; 2266 } 2267 2268 return 0; 2269 } 2270 2271 static unsigned int mtk_dai_get_dptx_ch_en(unsigned int channel) 2272 { 2273 switch (channel) { 2274 case 1 ... 2: 2275 return AFE_DPTX_CON_CH_EN_2CH; 2276 case 3 ... 4: 2277 return AFE_DPTX_CON_CH_EN_4CH; 2278 case 5 ... 6: 2279 return AFE_DPTX_CON_CH_EN_6CH; 2280 case 7 ... 8: 2281 return AFE_DPTX_CON_CH_EN_8CH; 2282 default: 2283 return AFE_DPTX_CON_CH_EN_2CH; 2284 } 2285 } 2286 2287 static unsigned int mtk_dai_get_dptx_ch(unsigned int ch) 2288 { 2289 return (ch > 2) ? 2290 AFE_DPTX_CON_CH_NUM_8CH : AFE_DPTX_CON_CH_NUM_2CH; 2291 } 2292 2293 static unsigned int mtk_dai_get_dptx_wlen(snd_pcm_format_t format) 2294 { 2295 return snd_pcm_format_physical_width(format) <= 16 ? 2296 AFE_DPTX_CON_16BIT : AFE_DPTX_CON_24BIT; 2297 } 2298 2299 static int mtk_dai_hdmitx_dptx_hw_params(struct snd_pcm_substream *substream, 2300 struct snd_pcm_hw_params *params, 2301 struct snd_soc_dai *dai) 2302 { 2303 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2304 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2305 struct mtk_dai_etdm_priv *etdm_data; 2306 unsigned int rate = params_rate(params); 2307 unsigned int channels = params_channels(params); 2308 snd_pcm_format_t format = params_format(params); 2309 int width = snd_pcm_format_physical_width(format); 2310 int ret; 2311 2312 if (!is_valid_etdm_dai(dai->id)) 2313 return -EINVAL; 2314 etdm_data = afe_priv->dai_priv[dai->id]; 2315 2316 /* dptx configure */ 2317 if (dai->id == MT8188_AFE_IO_DPTX) { 2318 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2319 AFE_DPTX_CON_CH_EN_MASK, 2320 mtk_dai_get_dptx_ch_en(channels)); 2321 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2322 AFE_DPTX_CON_CH_NUM_MASK, 2323 mtk_dai_get_dptx_ch(channels)); 2324 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2325 AFE_DPTX_CON_16BIT_MASK, 2326 mtk_dai_get_dptx_wlen(format)); 2327 2328 if (mtk_dai_get_dptx_ch(channels) == AFE_DPTX_CON_CH_NUM_8CH) { 2329 etdm_data->data_mode = MTK_DAI_ETDM_DATA_ONE_PIN; 2330 channels = 8; 2331 } else { 2332 channels = 2; 2333 } 2334 } else { 2335 etdm_data->data_mode = MTK_DAI_ETDM_DATA_MULTI_PIN; 2336 } 2337 2338 ret = mtk_dai_etdm_configure(afe, rate, channels, width, dai->id); 2339 2340 return ret; 2341 } 2342 2343 static int mtk_dai_hdmitx_dptx_set_sysclk(struct snd_soc_dai *dai, 2344 int clk_id, 2345 unsigned int freq, 2346 int dir) 2347 { 2348 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2349 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2350 struct mtk_dai_etdm_priv *etdm_data; 2351 2352 if (!is_valid_etdm_dai(dai->id)) 2353 return -EINVAL; 2354 etdm_data = afe_priv->dai_priv[dai->id]; 2355 2356 dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n", 2357 __func__, dai->id, freq, dir); 2358 2359 etdm_data->mclk_dir = dir; 2360 return mtk_dai_etdm_cal_mclk(afe, freq, dai->id); 2361 } 2362 2363 static const struct snd_soc_dai_ops mtk_dai_etdm_ops = { 2364 .hw_params = mtk_dai_etdm_hw_params, 2365 .set_sysclk = mtk_dai_etdm_set_sysclk, 2366 .set_fmt = mtk_dai_etdm_set_fmt, 2367 .set_tdm_slot = mtk_dai_etdm_set_tdm_slot, 2368 }; 2369 2370 static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops = { 2371 .hw_params = mtk_dai_hdmitx_dptx_hw_params, 2372 .set_sysclk = mtk_dai_hdmitx_dptx_set_sysclk, 2373 .set_fmt = mtk_dai_etdm_set_fmt, 2374 }; 2375 2376 /* dai driver */ 2377 #define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_192000) 2378 2379 #define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 2380 SNDRV_PCM_FMTBIT_S24_LE |\ 2381 SNDRV_PCM_FMTBIT_S32_LE) 2382 2383 static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = { 2384 { 2385 .name = "DPTX", 2386 .id = MT8188_AFE_IO_DPTX, 2387 .playback = { 2388 .stream_name = "DPTX", 2389 .channels_min = 1, 2390 .channels_max = 8, 2391 .rates = MTK_ETDM_RATES, 2392 .formats = MTK_ETDM_FORMATS, 2393 }, 2394 .ops = &mtk_dai_hdmitx_dptx_ops, 2395 }, 2396 { 2397 .name = "ETDM1_IN", 2398 .id = MT8188_AFE_IO_ETDM1_IN, 2399 .capture = { 2400 .stream_name = "ETDM1_IN", 2401 .channels_min = 1, 2402 .channels_max = 16, 2403 .rates = MTK_ETDM_RATES, 2404 .formats = MTK_ETDM_FORMATS, 2405 }, 2406 .ops = &mtk_dai_etdm_ops, 2407 }, 2408 { 2409 .name = "ETDM2_IN", 2410 .id = MT8188_AFE_IO_ETDM2_IN, 2411 .capture = { 2412 .stream_name = "ETDM2_IN", 2413 .channels_min = 1, 2414 .channels_max = 16, 2415 .rates = MTK_ETDM_RATES, 2416 .formats = MTK_ETDM_FORMATS, 2417 }, 2418 .ops = &mtk_dai_etdm_ops, 2419 }, 2420 { 2421 .name = "ETDM1_OUT", 2422 .id = MT8188_AFE_IO_ETDM1_OUT, 2423 .playback = { 2424 .stream_name = "ETDM1_OUT", 2425 .channels_min = 1, 2426 .channels_max = 16, 2427 .rates = MTK_ETDM_RATES, 2428 .formats = MTK_ETDM_FORMATS, 2429 }, 2430 .ops = &mtk_dai_etdm_ops, 2431 }, 2432 { 2433 .name = "ETDM2_OUT", 2434 .id = MT8188_AFE_IO_ETDM2_OUT, 2435 .playback = { 2436 .stream_name = "ETDM2_OUT", 2437 .channels_min = 1, 2438 .channels_max = 16, 2439 .rates = MTK_ETDM_RATES, 2440 .formats = MTK_ETDM_FORMATS, 2441 }, 2442 .ops = &mtk_dai_etdm_ops, 2443 }, 2444 { 2445 .name = "ETDM3_OUT", 2446 .id = MT8188_AFE_IO_ETDM3_OUT, 2447 .playback = { 2448 .stream_name = "ETDM3_OUT", 2449 .channels_min = 1, 2450 .channels_max = 8, 2451 .rates = MTK_ETDM_RATES, 2452 .formats = MTK_ETDM_FORMATS, 2453 }, 2454 .ops = &mtk_dai_hdmitx_dptx_ops, 2455 }, 2456 }; 2457 2458 static void mt8188_etdm_update_sync_info(struct mtk_base_afe *afe) 2459 { 2460 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2461 struct mtk_dai_etdm_priv *etdm_data; 2462 struct mtk_dai_etdm_priv *mst_data; 2463 int mst_dai_id; 2464 int i; 2465 2466 for (i = MT8188_AFE_IO_ETDM_START; i < MT8188_AFE_IO_ETDM_END; i++) { 2467 etdm_data = afe_priv->dai_priv[i]; 2468 if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) { 2469 mst_dai_id = etdm_data->cowork_source_id; 2470 mst_data = afe_priv->dai_priv[mst_dai_id]; 2471 if (mst_data->cowork_source_id != COWORK_ETDM_NONE) 2472 dev_err(afe->dev, "%s [%d] wrong sync source\n", 2473 __func__, i); 2474 mst_data->cowork_slv_id[mst_data->cowork_slv_count] = i; 2475 mst_data->cowork_slv_count++; 2476 } 2477 } 2478 } 2479 2480 static void mt8188_dai_etdm_parse_of(struct mtk_base_afe *afe) 2481 { 2482 const struct device_node *of_node = afe->dev->of_node; 2483 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2484 struct mtk_dai_etdm_priv *etdm_data; 2485 char prop[48]; 2486 u8 disable_chn[MT8188_ETDM_MAX_CHANNELS]; 2487 int max_chn = MT8188_ETDM_MAX_CHANNELS; 2488 unsigned int sync_id; 2489 u32 sel; 2490 int ret; 2491 int dai_id; 2492 int i, j; 2493 struct { 2494 const char *name; 2495 const unsigned int sync_id; 2496 } of_afe_etdms[MT8188_AFE_IO_ETDM_NUM] = { 2497 {"etdm-in1", ETDM_SYNC_FROM_IN1}, 2498 {"etdm-in2", ETDM_SYNC_FROM_IN2}, 2499 {"etdm-out1", ETDM_SYNC_FROM_OUT1}, 2500 {"etdm-out2", ETDM_SYNC_FROM_OUT2}, 2501 {"etdm-out3", ETDM_SYNC_FROM_OUT3}, 2502 }; 2503 2504 for (i = 0; i < MT8188_AFE_IO_ETDM_NUM; i++) { 2505 dai_id = ETDM_TO_DAI_ID(i); 2506 etdm_data = afe_priv->dai_priv[dai_id]; 2507 2508 snprintf(prop, sizeof(prop), "mediatek,%s-multi-pin-mode", 2509 of_afe_etdms[i].name); 2510 2511 etdm_data->data_mode = of_property_read_bool(of_node, prop); 2512 2513 snprintf(prop, sizeof(prop), "mediatek,%s-cowork-source", 2514 of_afe_etdms[i].name); 2515 2516 ret = of_property_read_u32(of_node, prop, &sel); 2517 if (ret == 0) { 2518 if (sel >= MT8188_AFE_IO_ETDM_NUM) { 2519 dev_err(afe->dev, "%s invalid id=%d\n", 2520 __func__, sel); 2521 etdm_data->cowork_source_id = COWORK_ETDM_NONE; 2522 } else { 2523 sync_id = of_afe_etdms[sel].sync_id; 2524 etdm_data->cowork_source_id = 2525 sync_to_dai_id(sync_id); 2526 } 2527 } else { 2528 etdm_data->cowork_source_id = COWORK_ETDM_NONE; 2529 } 2530 } 2531 2532 /* etdm in only */ 2533 for (i = 0; i < 2; i++) { 2534 dai_id = ETDM_TO_DAI_ID(i); 2535 etdm_data = afe_priv->dai_priv[dai_id]; 2536 2537 snprintf(prop, sizeof(prop), "mediatek,%s-chn-disabled", 2538 of_afe_etdms[i].name); 2539 2540 ret = of_property_read_variable_u8_array(of_node, prop, 2541 disable_chn, 2542 1, max_chn); 2543 if (ret < 0) 2544 continue; 2545 2546 for (j = 0; j < ret; j++) { 2547 if (disable_chn[j] >= MT8188_ETDM_MAX_CHANNELS) 2548 dev_err(afe->dev, "%s [%d] invalid chn %u\n", 2549 __func__, j, disable_chn[j]); 2550 else 2551 etdm_data->in_disable_ch[disable_chn[j]] = true; 2552 } 2553 } 2554 mt8188_etdm_update_sync_info(afe); 2555 } 2556 2557 static int init_etdm_priv_data(struct mtk_base_afe *afe) 2558 { 2559 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2560 struct mtk_dai_etdm_priv *etdm_priv; 2561 int i; 2562 2563 for (i = MT8188_AFE_IO_ETDM_START; i < MT8188_AFE_IO_ETDM_END; i++) { 2564 etdm_priv = devm_kzalloc(afe->dev, 2565 sizeof(struct mtk_dai_etdm_priv), 2566 GFP_KERNEL); 2567 if (!etdm_priv) 2568 return -ENOMEM; 2569 2570 afe_priv->dai_priv[i] = etdm_priv; 2571 } 2572 2573 afe_priv->dai_priv[MT8188_AFE_IO_DPTX] = 2574 afe_priv->dai_priv[MT8188_AFE_IO_ETDM3_OUT]; 2575 2576 mt8188_dai_etdm_parse_of(afe); 2577 return 0; 2578 } 2579 2580 int mt8188_dai_etdm_register(struct mtk_base_afe *afe) 2581 { 2582 struct mtk_base_afe_dai *dai; 2583 2584 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 2585 if (!dai) 2586 return -ENOMEM; 2587 2588 list_add(&dai->list, &afe->sub_dais); 2589 2590 dai->dai_drivers = mtk_dai_etdm_driver; 2591 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver); 2592 2593 dai->dapm_widgets = mtk_dai_etdm_widgets; 2594 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets); 2595 dai->dapm_routes = mtk_dai_etdm_routes; 2596 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes); 2597 dai->controls = mtk_dai_etdm_controls; 2598 dai->num_controls = ARRAY_SIZE(mtk_dai_etdm_controls); 2599 2600 return init_etdm_priv_data(afe); 2601 } 2602