1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek ALSA SoC Audio DAI eTDM Control 4 * 5 * Copyright (c) 2022 MediaTek Inc. 6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 * Trevor Wu <trevor.wu@mediatek.com> 8 * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <sound/pcm_params.h> 15 #include "mt8188-afe-clk.h" 16 #include "mt8188-afe-common.h" 17 #include "mt8188-reg.h" 18 19 #define MT8188_ETDM_MAX_CHANNELS 16 20 #define MT8188_ETDM_NORMAL_MAX_BCK_RATE 24576000 21 #define ETDM_TO_DAI_ID(x) ((x) + MT8188_AFE_IO_ETDM_START) 22 #define ENUM_TO_STR(x) #x 23 24 enum { 25 MTK_DAI_ETDM_FORMAT_I2S = 0, 26 MTK_DAI_ETDM_FORMAT_LJ, 27 MTK_DAI_ETDM_FORMAT_RJ, 28 MTK_DAI_ETDM_FORMAT_EIAJ, 29 MTK_DAI_ETDM_FORMAT_DSPA, 30 MTK_DAI_ETDM_FORMAT_DSPB, 31 }; 32 33 enum { 34 MTK_DAI_ETDM_DATA_ONE_PIN = 0, 35 MTK_DAI_ETDM_DATA_MULTI_PIN, 36 }; 37 38 enum { 39 ETDM_IN, 40 ETDM_OUT, 41 }; 42 43 enum { 44 COWORK_ETDM_NONE = 0, 45 COWORK_ETDM_IN1_M = 2, 46 COWORK_ETDM_IN1_S = 3, 47 COWORK_ETDM_IN2_M = 4, 48 COWORK_ETDM_IN2_S = 5, 49 COWORK_ETDM_OUT1_M = 10, 50 COWORK_ETDM_OUT1_S = 11, 51 COWORK_ETDM_OUT2_M = 12, 52 COWORK_ETDM_OUT2_S = 13, 53 COWORK_ETDM_OUT3_M = 14, 54 COWORK_ETDM_OUT3_S = 15, 55 }; 56 57 enum { 58 ETDM_RELATCH_TIMING_A1A2SYS, 59 ETDM_RELATCH_TIMING_A3SYS, 60 ETDM_RELATCH_TIMING_A4SYS, 61 }; 62 63 enum { 64 ETDM_SYNC_NONE, 65 ETDM_SYNC_FROM_IN1 = 2, 66 ETDM_SYNC_FROM_IN2 = 4, 67 ETDM_SYNC_FROM_OUT1 = 10, 68 ETDM_SYNC_FROM_OUT2 = 12, 69 ETDM_SYNC_FROM_OUT3 = 14, 70 }; 71 72 struct etdm_con_reg { 73 unsigned int con0; 74 unsigned int con1; 75 unsigned int con2; 76 unsigned int con3; 77 unsigned int con4; 78 unsigned int con5; 79 }; 80 81 struct mtk_dai_etdm_rate { 82 unsigned int rate; 83 unsigned int reg_value; 84 }; 85 86 struct mtk_dai_etdm_priv { 87 unsigned int clock_mode; 88 unsigned int data_mode; 89 bool slave_mode; 90 bool lrck_inv; 91 bool bck_inv; 92 unsigned int format; 93 unsigned int slots; 94 unsigned int lrck_width; 95 unsigned int mclk_freq; 96 unsigned int mclk_fixed_apll; 97 unsigned int mclk_apll; 98 unsigned int mclk_dir; 99 int cowork_source_id; //dai id 100 unsigned int cowork_slv_count; 101 int cowork_slv_id[MT8188_AFE_IO_ETDM_NUM - 1]; //dai_id 102 bool in_disable_ch[MT8188_ETDM_MAX_CHANNELS]; 103 unsigned int en_ref_cnt; 104 bool is_prepared; 105 }; 106 107 static const struct mtk_dai_etdm_rate mt8188_etdm_rates[] = { 108 { .rate = 8000, .reg_value = 0, }, 109 { .rate = 12000, .reg_value = 1, }, 110 { .rate = 16000, .reg_value = 2, }, 111 { .rate = 24000, .reg_value = 3, }, 112 { .rate = 32000, .reg_value = 4, }, 113 { .rate = 48000, .reg_value = 5, }, 114 { .rate = 96000, .reg_value = 7, }, 115 { .rate = 192000, .reg_value = 9, }, 116 { .rate = 384000, .reg_value = 11, }, 117 { .rate = 11025, .reg_value = 16, }, 118 { .rate = 22050, .reg_value = 17, }, 119 { .rate = 44100, .reg_value = 18, }, 120 { .rate = 88200, .reg_value = 19, }, 121 { .rate = 176400, .reg_value = 20, }, 122 { .rate = 352800, .reg_value = 21, }, 123 }; 124 125 static int get_etdm_fs_timing(unsigned int rate) 126 { 127 int i; 128 129 for (i = 0; i < ARRAY_SIZE(mt8188_etdm_rates); i++) 130 if (mt8188_etdm_rates[i].rate == rate) 131 return mt8188_etdm_rates[i].reg_value; 132 133 return -EINVAL; 134 } 135 136 static unsigned int get_etdm_ch_fixup(unsigned int channels) 137 { 138 if (channels > 16) 139 return 24; 140 else if (channels > 8) 141 return 16; 142 else if (channels > 4) 143 return 8; 144 else if (channels > 2) 145 return 4; 146 else 147 return 2; 148 } 149 150 static int get_etdm_reg(unsigned int dai_id, struct etdm_con_reg *etdm_reg) 151 { 152 switch (dai_id) { 153 case MT8188_AFE_IO_ETDM1_IN: 154 etdm_reg->con0 = ETDM_IN1_CON0; 155 etdm_reg->con1 = ETDM_IN1_CON1; 156 etdm_reg->con2 = ETDM_IN1_CON2; 157 etdm_reg->con3 = ETDM_IN1_CON3; 158 etdm_reg->con4 = ETDM_IN1_CON4; 159 etdm_reg->con5 = ETDM_IN1_CON5; 160 break; 161 case MT8188_AFE_IO_ETDM2_IN: 162 etdm_reg->con0 = ETDM_IN2_CON0; 163 etdm_reg->con1 = ETDM_IN2_CON1; 164 etdm_reg->con2 = ETDM_IN2_CON2; 165 etdm_reg->con3 = ETDM_IN2_CON3; 166 etdm_reg->con4 = ETDM_IN2_CON4; 167 etdm_reg->con5 = ETDM_IN2_CON5; 168 break; 169 case MT8188_AFE_IO_ETDM1_OUT: 170 etdm_reg->con0 = ETDM_OUT1_CON0; 171 etdm_reg->con1 = ETDM_OUT1_CON1; 172 etdm_reg->con2 = ETDM_OUT1_CON2; 173 etdm_reg->con3 = ETDM_OUT1_CON3; 174 etdm_reg->con4 = ETDM_OUT1_CON4; 175 etdm_reg->con5 = ETDM_OUT1_CON5; 176 break; 177 case MT8188_AFE_IO_ETDM2_OUT: 178 etdm_reg->con0 = ETDM_OUT2_CON0; 179 etdm_reg->con1 = ETDM_OUT2_CON1; 180 etdm_reg->con2 = ETDM_OUT2_CON2; 181 etdm_reg->con3 = ETDM_OUT2_CON3; 182 etdm_reg->con4 = ETDM_OUT2_CON4; 183 etdm_reg->con5 = ETDM_OUT2_CON5; 184 break; 185 case MT8188_AFE_IO_ETDM3_OUT: 186 case MT8188_AFE_IO_DPTX: 187 etdm_reg->con0 = ETDM_OUT3_CON0; 188 etdm_reg->con1 = ETDM_OUT3_CON1; 189 etdm_reg->con2 = ETDM_OUT3_CON2; 190 etdm_reg->con3 = ETDM_OUT3_CON3; 191 etdm_reg->con4 = ETDM_OUT3_CON4; 192 etdm_reg->con5 = ETDM_OUT3_CON5; 193 break; 194 default: 195 return -EINVAL; 196 } 197 return 0; 198 } 199 200 static int get_etdm_dir(unsigned int dai_id) 201 { 202 switch (dai_id) { 203 case MT8188_AFE_IO_ETDM1_IN: 204 case MT8188_AFE_IO_ETDM2_IN: 205 return ETDM_IN; 206 case MT8188_AFE_IO_ETDM1_OUT: 207 case MT8188_AFE_IO_ETDM2_OUT: 208 case MT8188_AFE_IO_ETDM3_OUT: 209 return ETDM_OUT; 210 default: 211 return -EINVAL; 212 } 213 } 214 215 static int get_etdm_wlen(unsigned int bitwidth) 216 { 217 return bitwidth <= 16 ? 16 : 32; 218 } 219 220 static bool is_valid_etdm_dai(int dai_id) 221 { 222 switch (dai_id) { 223 case MT8188_AFE_IO_ETDM1_IN: 224 fallthrough; 225 case MT8188_AFE_IO_ETDM2_IN: 226 fallthrough; 227 case MT8188_AFE_IO_ETDM1_OUT: 228 fallthrough; 229 case MT8188_AFE_IO_ETDM2_OUT: 230 fallthrough; 231 case MT8188_AFE_IO_DPTX: 232 fallthrough; 233 case MT8188_AFE_IO_ETDM3_OUT: 234 return true; 235 default: 236 return false; 237 } 238 } 239 240 static int is_cowork_mode(struct snd_soc_dai *dai) 241 { 242 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 243 struct mt8188_afe_private *afe_priv = afe->platform_priv; 244 struct mtk_dai_etdm_priv *etdm_data; 245 246 if (!is_valid_etdm_dai(dai->id)) 247 return -EINVAL; 248 etdm_data = afe_priv->dai_priv[dai->id]; 249 250 return (etdm_data->cowork_slv_count > 0 || 251 etdm_data->cowork_source_id != COWORK_ETDM_NONE); 252 } 253 254 static int sync_to_dai_id(int source_sel) 255 { 256 switch (source_sel) { 257 case ETDM_SYNC_FROM_IN1: 258 return MT8188_AFE_IO_ETDM1_IN; 259 case ETDM_SYNC_FROM_IN2: 260 return MT8188_AFE_IO_ETDM2_IN; 261 case ETDM_SYNC_FROM_OUT1: 262 return MT8188_AFE_IO_ETDM1_OUT; 263 case ETDM_SYNC_FROM_OUT2: 264 return MT8188_AFE_IO_ETDM2_OUT; 265 case ETDM_SYNC_FROM_OUT3: 266 return MT8188_AFE_IO_ETDM3_OUT; 267 default: 268 return 0; 269 } 270 } 271 272 static int get_etdm_cowork_master_id(struct snd_soc_dai *dai) 273 { 274 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 275 struct mt8188_afe_private *afe_priv = afe->platform_priv; 276 struct mtk_dai_etdm_priv *etdm_data; 277 int dai_id; 278 279 if (!is_valid_etdm_dai(dai->id)) 280 return -EINVAL; 281 etdm_data = afe_priv->dai_priv[dai->id]; 282 dai_id = etdm_data->cowork_source_id; 283 284 if (dai_id == COWORK_ETDM_NONE) 285 dai_id = dai->id; 286 287 return dai_id; 288 } 289 290 static int mtk_dai_etdm_get_cg_id_by_dai_id(int dai_id) 291 { 292 switch (dai_id) { 293 case MT8188_AFE_IO_DPTX: 294 return MT8188_CLK_AUD_HDMI_OUT; 295 case MT8188_AFE_IO_ETDM1_IN: 296 return MT8188_CLK_AUD_TDM_IN; 297 case MT8188_AFE_IO_ETDM2_IN: 298 return MT8188_CLK_AUD_I2SIN; 299 case MT8188_AFE_IO_ETDM1_OUT: 300 return MT8188_CLK_AUD_TDM_OUT; 301 case MT8188_AFE_IO_ETDM2_OUT: 302 return MT8188_CLK_AUD_I2S_OUT; 303 case MT8188_AFE_IO_ETDM3_OUT: 304 return MT8188_CLK_AUD_HDMI_OUT; 305 default: 306 return -EINVAL; 307 } 308 } 309 310 static int mtk_dai_etdm_get_clk_id_by_dai_id(int dai_id) 311 { 312 switch (dai_id) { 313 case MT8188_AFE_IO_DPTX: 314 return MT8188_CLK_TOP_DPTX_M_SEL; 315 case MT8188_AFE_IO_ETDM1_IN: 316 return MT8188_CLK_TOP_I2SI1_M_SEL; 317 case MT8188_AFE_IO_ETDM2_IN: 318 return MT8188_CLK_TOP_I2SI2_M_SEL; 319 case MT8188_AFE_IO_ETDM1_OUT: 320 return MT8188_CLK_TOP_I2SO1_M_SEL; 321 case MT8188_AFE_IO_ETDM2_OUT: 322 return MT8188_CLK_TOP_I2SO2_M_SEL; 323 case MT8188_AFE_IO_ETDM3_OUT: 324 default: 325 return -EINVAL; 326 } 327 } 328 329 static int mtk_dai_etdm_get_clkdiv_id_by_dai_id(int dai_id) 330 { 331 switch (dai_id) { 332 case MT8188_AFE_IO_DPTX: 333 return MT8188_CLK_TOP_APLL12_DIV9; 334 case MT8188_AFE_IO_ETDM1_IN: 335 return MT8188_CLK_TOP_APLL12_DIV0; 336 case MT8188_AFE_IO_ETDM2_IN: 337 return MT8188_CLK_TOP_APLL12_DIV1; 338 case MT8188_AFE_IO_ETDM1_OUT: 339 return MT8188_CLK_TOP_APLL12_DIV2; 340 case MT8188_AFE_IO_ETDM2_OUT: 341 return MT8188_CLK_TOP_APLL12_DIV3; 342 case MT8188_AFE_IO_ETDM3_OUT: 343 default: 344 return -EINVAL; 345 } 346 } 347 348 static int mtk_dai_etdm_enable_mclk(struct mtk_base_afe *afe, int dai_id) 349 { 350 struct mt8188_afe_private *afe_priv = afe->platform_priv; 351 int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 352 353 if (clkdiv_id < 0) 354 return -EINVAL; 355 356 mt8188_afe_enable_clk(afe, afe_priv->clk[clkdiv_id]); 357 358 return 0; 359 } 360 361 static int mtk_dai_etdm_disable_mclk(struct mtk_base_afe *afe, int dai_id) 362 { 363 struct mt8188_afe_private *afe_priv = afe->platform_priv; 364 int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 365 366 if (clkdiv_id < 0) 367 return -EINVAL; 368 369 mt8188_afe_disable_clk(afe, afe_priv->clk[clkdiv_id]); 370 371 return 0; 372 } 373 374 static const struct snd_kcontrol_new mtk_dai_etdm_o048_mix[] = { 375 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN48, 20, 1, 0), 376 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN48, 22, 1, 0), 377 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN48_1, 14, 1, 0), 378 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN48_2, 6, 1, 0), 379 }; 380 381 static const struct snd_kcontrol_new mtk_dai_etdm_o049_mix[] = { 382 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN49, 21, 1, 0), 383 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN49, 23, 1, 0), 384 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN49_1, 15, 1, 0), 385 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN49_2, 7, 1, 0), 386 }; 387 388 static const struct snd_kcontrol_new mtk_dai_etdm_o050_mix[] = { 389 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN50, 24, 1, 0), 390 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN50_1, 16, 1, 0), 391 }; 392 393 static const struct snd_kcontrol_new mtk_dai_etdm_o051_mix[] = { 394 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN51, 25, 1, 0), 395 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN51_1, 17, 1, 0), 396 }; 397 398 static const struct snd_kcontrol_new mtk_dai_etdm_o052_mix[] = { 399 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN52, 26, 1, 0), 400 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN52_1, 18, 1, 0), 401 }; 402 403 static const struct snd_kcontrol_new mtk_dai_etdm_o053_mix[] = { 404 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN53, 27, 1, 0), 405 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN53_1, 19, 1, 0), 406 }; 407 408 static const struct snd_kcontrol_new mtk_dai_etdm_o054_mix[] = { 409 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN54, 28, 1, 0), 410 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN54_1, 20, 1, 0), 411 }; 412 413 static const struct snd_kcontrol_new mtk_dai_etdm_o055_mix[] = { 414 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN55, 29, 1, 0), 415 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN55_1, 21, 1, 0), 416 }; 417 418 static const struct snd_kcontrol_new mtk_dai_etdm_o056_mix[] = { 419 SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN56, 30, 1, 0), 420 SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN56_1, 22, 1, 0), 421 }; 422 423 static const struct snd_kcontrol_new mtk_dai_etdm_o057_mix[] = { 424 SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN57, 31, 1, 0), 425 SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN57_1, 23, 1, 0), 426 }; 427 428 static const struct snd_kcontrol_new mtk_dai_etdm_o058_mix[] = { 429 SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN58_1, 0, 1, 0), 430 SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN58_1, 24, 1, 0), 431 }; 432 433 static const struct snd_kcontrol_new mtk_dai_etdm_o059_mix[] = { 434 SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN59_1, 1, 1, 0), 435 SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN59_1, 25, 1, 0), 436 }; 437 438 static const struct snd_kcontrol_new mtk_dai_etdm_o060_mix[] = { 439 SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN60_1, 2, 1, 0), 440 SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN60_1, 26, 1, 0), 441 }; 442 443 static const struct snd_kcontrol_new mtk_dai_etdm_o061_mix[] = { 444 SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN61_1, 3, 1, 0), 445 SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN61_1, 27, 1, 0), 446 }; 447 448 static const struct snd_kcontrol_new mtk_dai_etdm_o062_mix[] = { 449 SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN62_1, 4, 1, 0), 450 SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN62_1, 28, 1, 0), 451 }; 452 453 static const struct snd_kcontrol_new mtk_dai_etdm_o063_mix[] = { 454 SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN63_1, 5, 1, 0), 455 SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN63_1, 29, 1, 0), 456 }; 457 458 static const struct snd_kcontrol_new mtk_dai_etdm_o072_mix[] = { 459 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN72, 20, 1, 0), 460 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN72, 22, 1, 0), 461 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN72_1, 14, 1, 0), 462 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN72_2, 6, 1, 0), 463 }; 464 465 static const struct snd_kcontrol_new mtk_dai_etdm_o073_mix[] = { 466 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN73, 21, 1, 0), 467 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN73, 23, 1, 0), 468 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN73_1, 15, 1, 0), 469 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN73_2, 7, 1, 0), 470 }; 471 472 static const struct snd_kcontrol_new mtk_dai_etdm_o074_mix[] = { 473 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN74, 24, 1, 0), 474 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN74_1, 16, 1, 0), 475 }; 476 477 static const struct snd_kcontrol_new mtk_dai_etdm_o075_mix[] = { 478 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN75, 25, 1, 0), 479 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN75_1, 17, 1, 0), 480 }; 481 482 static const struct snd_kcontrol_new mtk_dai_etdm_o076_mix[] = { 483 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN76, 26, 1, 0), 484 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN76_1, 18, 1, 0), 485 }; 486 487 static const struct snd_kcontrol_new mtk_dai_etdm_o077_mix[] = { 488 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN77, 27, 1, 0), 489 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN77_1, 19, 1, 0), 490 }; 491 492 static const struct snd_kcontrol_new mtk_dai_etdm_o078_mix[] = { 493 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN78, 28, 1, 0), 494 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN78_1, 20, 1, 0), 495 }; 496 497 static const struct snd_kcontrol_new mtk_dai_etdm_o079_mix[] = { 498 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN79, 29, 1, 0), 499 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN79_1, 21, 1, 0), 500 }; 501 502 static const struct snd_kcontrol_new mtk_dai_etdm_o080_mix[] = { 503 SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN80, 30, 1, 0), 504 SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN80_1, 22, 1, 0), 505 }; 506 507 static const struct snd_kcontrol_new mtk_dai_etdm_o081_mix[] = { 508 SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN81, 31, 1, 0), 509 SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN81_1, 23, 1, 0), 510 }; 511 512 static const struct snd_kcontrol_new mtk_dai_etdm_o082_mix[] = { 513 SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN82_1, 0, 1, 0), 514 SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN82_1, 24, 1, 0), 515 }; 516 517 static const struct snd_kcontrol_new mtk_dai_etdm_o083_mix[] = { 518 SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN83_1, 1, 1, 0), 519 SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN83_1, 25, 1, 0), 520 }; 521 522 static const struct snd_kcontrol_new mtk_dai_etdm_o084_mix[] = { 523 SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN84_1, 2, 1, 0), 524 SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN84_1, 26, 1, 0), 525 }; 526 527 static const struct snd_kcontrol_new mtk_dai_etdm_o085_mix[] = { 528 SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN85_1, 3, 1, 0), 529 SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN85_1, 27, 1, 0), 530 }; 531 532 static const struct snd_kcontrol_new mtk_dai_etdm_o086_mix[] = { 533 SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN86_1, 4, 1, 0), 534 SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN86_1, 28, 1, 0), 535 }; 536 537 static const struct snd_kcontrol_new mtk_dai_etdm_o087_mix[] = { 538 SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN87_1, 5, 1, 0), 539 SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN87_1, 29, 1, 0), 540 }; 541 542 static const char * const mt8188_etdm_clk_src_sel_text[] = { 543 "26m", 544 "a1sys_a2sys", 545 "a3sys", 546 "a4sys", 547 }; 548 549 static SOC_ENUM_SINGLE_EXT_DECL(etdmout_clk_src_enum, 550 mt8188_etdm_clk_src_sel_text); 551 552 static const char * const hdmitx_dptx_mux_map[] = { 553 "Disconnect", "Connect", 554 }; 555 556 static int hdmitx_dptx_mux_map_value[] = { 557 0, 1, 558 }; 559 560 /* HDMI_OUT_MUX */ 561 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(hdmi_out_mux_map_enum, 562 SND_SOC_NOPM, 563 0, 564 1, 565 hdmitx_dptx_mux_map, 566 hdmitx_dptx_mux_map_value); 567 568 static const struct snd_kcontrol_new hdmi_out_mux_control = 569 SOC_DAPM_ENUM("HDMI_OUT_MUX", hdmi_out_mux_map_enum); 570 571 /* DPTX_OUT_MUX */ 572 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(dptx_out_mux_map_enum, 573 SND_SOC_NOPM, 574 0, 575 1, 576 hdmitx_dptx_mux_map, 577 hdmitx_dptx_mux_map_value); 578 579 static const struct snd_kcontrol_new dptx_out_mux_control = 580 SOC_DAPM_ENUM("DPTX_OUT_MUX", dptx_out_mux_map_enum); 581 582 /* HDMI_CH0_MUX ~ HDMI_CH7_MUX */ 583 static const char *const afe_conn_hdmi_mux_map[] = { 584 "CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7", 585 }; 586 587 static int afe_conn_hdmi_mux_map_value[] = { 588 0, 1, 2, 3, 4, 5, 6, 7, 589 }; 590 591 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum, 592 AFE_TDMOUT_CONN0, 593 0, 594 0xf, 595 afe_conn_hdmi_mux_map, 596 afe_conn_hdmi_mux_map_value); 597 598 static const struct snd_kcontrol_new hdmi_ch0_mux_control = 599 SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum); 600 601 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum, 602 AFE_TDMOUT_CONN0, 603 4, 604 0xf, 605 afe_conn_hdmi_mux_map, 606 afe_conn_hdmi_mux_map_value); 607 608 static const struct snd_kcontrol_new hdmi_ch1_mux_control = 609 SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum); 610 611 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum, 612 AFE_TDMOUT_CONN0, 613 8, 614 0xf, 615 afe_conn_hdmi_mux_map, 616 afe_conn_hdmi_mux_map_value); 617 618 static const struct snd_kcontrol_new hdmi_ch2_mux_control = 619 SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum); 620 621 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum, 622 AFE_TDMOUT_CONN0, 623 12, 624 0xf, 625 afe_conn_hdmi_mux_map, 626 afe_conn_hdmi_mux_map_value); 627 628 static const struct snd_kcontrol_new hdmi_ch3_mux_control = 629 SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum); 630 631 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum, 632 AFE_TDMOUT_CONN0, 633 16, 634 0xf, 635 afe_conn_hdmi_mux_map, 636 afe_conn_hdmi_mux_map_value); 637 638 static const struct snd_kcontrol_new hdmi_ch4_mux_control = 639 SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum); 640 641 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum, 642 AFE_TDMOUT_CONN0, 643 20, 644 0xf, 645 afe_conn_hdmi_mux_map, 646 afe_conn_hdmi_mux_map_value); 647 648 static const struct snd_kcontrol_new hdmi_ch5_mux_control = 649 SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum); 650 651 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum, 652 AFE_TDMOUT_CONN0, 653 24, 654 0xf, 655 afe_conn_hdmi_mux_map, 656 afe_conn_hdmi_mux_map_value); 657 658 static const struct snd_kcontrol_new hdmi_ch6_mux_control = 659 SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum); 660 661 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum, 662 AFE_TDMOUT_CONN0, 663 28, 664 0xf, 665 afe_conn_hdmi_mux_map, 666 afe_conn_hdmi_mux_map_value); 667 668 static const struct snd_kcontrol_new hdmi_ch7_mux_control = 669 SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum); 670 671 static int mt8188_etdm_clk_src_sel_put(struct snd_kcontrol *kcontrol, 672 struct snd_ctl_elem_value *ucontrol) 673 { 674 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 675 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 676 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 677 unsigned int source = ucontrol->value.enumerated.item[0]; 678 unsigned int val; 679 unsigned int old_val; 680 unsigned int mask; 681 unsigned int reg; 682 unsigned int shift; 683 684 if (source >= e->items) 685 return -EINVAL; 686 687 if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) { 688 reg = ETDM_OUT1_CON4; 689 mask = ETDM_OUT_CON4_CLOCK_MASK; 690 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 691 val = FIELD_PREP(ETDM_OUT_CON4_CLOCK_MASK, source); 692 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) { 693 reg = ETDM_OUT2_CON4; 694 mask = ETDM_OUT_CON4_CLOCK_MASK; 695 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 696 val = FIELD_PREP(ETDM_OUT_CON4_CLOCK_MASK, source); 697 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) { 698 reg = ETDM_OUT3_CON4; 699 mask = ETDM_OUT_CON4_CLOCK_MASK; 700 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 701 val = FIELD_PREP(ETDM_OUT_CON4_CLOCK_MASK, source); 702 } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) { 703 reg = ETDM_IN1_CON2; 704 mask = ETDM_IN_CON2_CLOCK_MASK; 705 shift = ETDM_IN_CON2_CLOCK_SHIFT; 706 val = FIELD_PREP(ETDM_IN_CON2_CLOCK_MASK, source); 707 } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) { 708 reg = ETDM_IN2_CON2; 709 mask = ETDM_IN_CON2_CLOCK_MASK; 710 shift = ETDM_IN_CON2_CLOCK_SHIFT; 711 val = FIELD_PREP(ETDM_IN_CON2_CLOCK_MASK, source); 712 } else { 713 return -EINVAL; 714 } 715 716 regmap_read(afe->regmap, reg, &old_val); 717 old_val &= mask; 718 old_val >>= shift; 719 720 if (old_val == val) 721 return 0; 722 723 regmap_update_bits(afe->regmap, reg, mask, val); 724 725 return 1; 726 } 727 728 static int mt8188_etdm_clk_src_sel_get(struct snd_kcontrol *kcontrol, 729 struct snd_ctl_elem_value *ucontrol) 730 { 731 struct snd_soc_component *component = 732 snd_soc_kcontrol_component(kcontrol); 733 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 734 unsigned int value; 735 unsigned int reg; 736 unsigned int mask; 737 unsigned int shift; 738 739 if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) { 740 reg = ETDM_OUT1_CON4; 741 mask = ETDM_OUT_CON4_CLOCK_MASK; 742 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 743 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) { 744 reg = ETDM_OUT2_CON4; 745 mask = ETDM_OUT_CON4_CLOCK_MASK; 746 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 747 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) { 748 reg = ETDM_OUT3_CON4; 749 mask = ETDM_OUT_CON4_CLOCK_MASK; 750 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 751 } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) { 752 reg = ETDM_IN1_CON2; 753 mask = ETDM_IN_CON2_CLOCK_MASK; 754 shift = ETDM_IN_CON2_CLOCK_SHIFT; 755 } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) { 756 reg = ETDM_IN2_CON2; 757 mask = ETDM_IN_CON2_CLOCK_MASK; 758 shift = ETDM_IN_CON2_CLOCK_SHIFT; 759 } else { 760 return -EINVAL; 761 } 762 763 regmap_read(afe->regmap, reg, &value); 764 765 value &= mask; 766 value >>= shift; 767 ucontrol->value.enumerated.item[0] = value; 768 return 0; 769 } 770 771 static const struct snd_kcontrol_new mtk_dai_etdm_controls[] = { 772 SOC_ENUM_EXT("ETDM_OUT1_Clock_Source", etdmout_clk_src_enum, 773 mt8188_etdm_clk_src_sel_get, 774 mt8188_etdm_clk_src_sel_put), 775 SOC_ENUM_EXT("ETDM_OUT2_Clock_Source", etdmout_clk_src_enum, 776 mt8188_etdm_clk_src_sel_get, 777 mt8188_etdm_clk_src_sel_put), 778 SOC_ENUM_EXT("ETDM_OUT3_Clock_Source", etdmout_clk_src_enum, 779 mt8188_etdm_clk_src_sel_get, 780 mt8188_etdm_clk_src_sel_put), 781 SOC_ENUM_EXT("ETDM_IN1_Clock_Source", etdmout_clk_src_enum, 782 mt8188_etdm_clk_src_sel_get, 783 mt8188_etdm_clk_src_sel_put), 784 SOC_ENUM_EXT("ETDM_IN2_Clock_Source", etdmout_clk_src_enum, 785 mt8188_etdm_clk_src_sel_get, 786 mt8188_etdm_clk_src_sel_put), 787 }; 788 789 static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = { 790 /* eTDM_IN2 */ 791 SND_SOC_DAPM_MIXER("I012", SND_SOC_NOPM, 0, 0, NULL, 0), 792 SND_SOC_DAPM_MIXER("I013", SND_SOC_NOPM, 0, 0, NULL, 0), 793 SND_SOC_DAPM_MIXER("I014", SND_SOC_NOPM, 0, 0, NULL, 0), 794 SND_SOC_DAPM_MIXER("I015", SND_SOC_NOPM, 0, 0, NULL, 0), 795 SND_SOC_DAPM_MIXER("I016", SND_SOC_NOPM, 0, 0, NULL, 0), 796 SND_SOC_DAPM_MIXER("I017", SND_SOC_NOPM, 0, 0, NULL, 0), 797 SND_SOC_DAPM_MIXER("I018", SND_SOC_NOPM, 0, 0, NULL, 0), 798 SND_SOC_DAPM_MIXER("I019", SND_SOC_NOPM, 0, 0, NULL, 0), 799 SND_SOC_DAPM_MIXER("I188", SND_SOC_NOPM, 0, 0, NULL, 0), 800 SND_SOC_DAPM_MIXER("I189", SND_SOC_NOPM, 0, 0, NULL, 0), 801 SND_SOC_DAPM_MIXER("I190", SND_SOC_NOPM, 0, 0, NULL, 0), 802 SND_SOC_DAPM_MIXER("I191", SND_SOC_NOPM, 0, 0, NULL, 0), 803 SND_SOC_DAPM_MIXER("I192", SND_SOC_NOPM, 0, 0, NULL, 0), 804 SND_SOC_DAPM_MIXER("I193", SND_SOC_NOPM, 0, 0, NULL, 0), 805 SND_SOC_DAPM_MIXER("I194", SND_SOC_NOPM, 0, 0, NULL, 0), 806 SND_SOC_DAPM_MIXER("I195", SND_SOC_NOPM, 0, 0, NULL, 0), 807 808 /* eTDM_IN1 */ 809 SND_SOC_DAPM_MIXER("I072", SND_SOC_NOPM, 0, 0, NULL, 0), 810 SND_SOC_DAPM_MIXER("I073", SND_SOC_NOPM, 0, 0, NULL, 0), 811 SND_SOC_DAPM_MIXER("I074", SND_SOC_NOPM, 0, 0, NULL, 0), 812 SND_SOC_DAPM_MIXER("I075", SND_SOC_NOPM, 0, 0, NULL, 0), 813 SND_SOC_DAPM_MIXER("I076", SND_SOC_NOPM, 0, 0, NULL, 0), 814 SND_SOC_DAPM_MIXER("I077", SND_SOC_NOPM, 0, 0, NULL, 0), 815 SND_SOC_DAPM_MIXER("I078", SND_SOC_NOPM, 0, 0, NULL, 0), 816 SND_SOC_DAPM_MIXER("I079", SND_SOC_NOPM, 0, 0, NULL, 0), 817 SND_SOC_DAPM_MIXER("I080", SND_SOC_NOPM, 0, 0, NULL, 0), 818 SND_SOC_DAPM_MIXER("I081", SND_SOC_NOPM, 0, 0, NULL, 0), 819 SND_SOC_DAPM_MIXER("I082", SND_SOC_NOPM, 0, 0, NULL, 0), 820 SND_SOC_DAPM_MIXER("I083", SND_SOC_NOPM, 0, 0, NULL, 0), 821 SND_SOC_DAPM_MIXER("I084", SND_SOC_NOPM, 0, 0, NULL, 0), 822 SND_SOC_DAPM_MIXER("I085", SND_SOC_NOPM, 0, 0, NULL, 0), 823 SND_SOC_DAPM_MIXER("I086", SND_SOC_NOPM, 0, 0, NULL, 0), 824 SND_SOC_DAPM_MIXER("I087", SND_SOC_NOPM, 0, 0, NULL, 0), 825 826 /* eTDM_OUT2 */ 827 SND_SOC_DAPM_MIXER("O048", SND_SOC_NOPM, 0, 0, 828 mtk_dai_etdm_o048_mix, ARRAY_SIZE(mtk_dai_etdm_o048_mix)), 829 SND_SOC_DAPM_MIXER("O049", SND_SOC_NOPM, 0, 0, 830 mtk_dai_etdm_o049_mix, ARRAY_SIZE(mtk_dai_etdm_o049_mix)), 831 SND_SOC_DAPM_MIXER("O050", SND_SOC_NOPM, 0, 0, 832 mtk_dai_etdm_o050_mix, ARRAY_SIZE(mtk_dai_etdm_o050_mix)), 833 SND_SOC_DAPM_MIXER("O051", SND_SOC_NOPM, 0, 0, 834 mtk_dai_etdm_o051_mix, ARRAY_SIZE(mtk_dai_etdm_o051_mix)), 835 SND_SOC_DAPM_MIXER("O052", SND_SOC_NOPM, 0, 0, 836 mtk_dai_etdm_o052_mix, ARRAY_SIZE(mtk_dai_etdm_o052_mix)), 837 SND_SOC_DAPM_MIXER("O053", SND_SOC_NOPM, 0, 0, 838 mtk_dai_etdm_o053_mix, ARRAY_SIZE(mtk_dai_etdm_o053_mix)), 839 SND_SOC_DAPM_MIXER("O054", SND_SOC_NOPM, 0, 0, 840 mtk_dai_etdm_o054_mix, ARRAY_SIZE(mtk_dai_etdm_o054_mix)), 841 SND_SOC_DAPM_MIXER("O055", SND_SOC_NOPM, 0, 0, 842 mtk_dai_etdm_o055_mix, ARRAY_SIZE(mtk_dai_etdm_o055_mix)), 843 SND_SOC_DAPM_MIXER("O056", SND_SOC_NOPM, 0, 0, 844 mtk_dai_etdm_o056_mix, ARRAY_SIZE(mtk_dai_etdm_o056_mix)), 845 SND_SOC_DAPM_MIXER("O057", SND_SOC_NOPM, 0, 0, 846 mtk_dai_etdm_o057_mix, ARRAY_SIZE(mtk_dai_etdm_o057_mix)), 847 SND_SOC_DAPM_MIXER("O058", SND_SOC_NOPM, 0, 0, 848 mtk_dai_etdm_o058_mix, ARRAY_SIZE(mtk_dai_etdm_o058_mix)), 849 SND_SOC_DAPM_MIXER("O059", SND_SOC_NOPM, 0, 0, 850 mtk_dai_etdm_o059_mix, ARRAY_SIZE(mtk_dai_etdm_o059_mix)), 851 SND_SOC_DAPM_MIXER("O060", SND_SOC_NOPM, 0, 0, 852 mtk_dai_etdm_o060_mix, ARRAY_SIZE(mtk_dai_etdm_o060_mix)), 853 SND_SOC_DAPM_MIXER("O061", SND_SOC_NOPM, 0, 0, 854 mtk_dai_etdm_o061_mix, ARRAY_SIZE(mtk_dai_etdm_o061_mix)), 855 SND_SOC_DAPM_MIXER("O062", SND_SOC_NOPM, 0, 0, 856 mtk_dai_etdm_o062_mix, ARRAY_SIZE(mtk_dai_etdm_o062_mix)), 857 SND_SOC_DAPM_MIXER("O063", SND_SOC_NOPM, 0, 0, 858 mtk_dai_etdm_o063_mix, ARRAY_SIZE(mtk_dai_etdm_o063_mix)), 859 860 /* eTDM_OUT1 */ 861 SND_SOC_DAPM_MIXER("O072", SND_SOC_NOPM, 0, 0, 862 mtk_dai_etdm_o072_mix, ARRAY_SIZE(mtk_dai_etdm_o072_mix)), 863 SND_SOC_DAPM_MIXER("O073", SND_SOC_NOPM, 0, 0, 864 mtk_dai_etdm_o073_mix, ARRAY_SIZE(mtk_dai_etdm_o073_mix)), 865 SND_SOC_DAPM_MIXER("O074", SND_SOC_NOPM, 0, 0, 866 mtk_dai_etdm_o074_mix, ARRAY_SIZE(mtk_dai_etdm_o074_mix)), 867 SND_SOC_DAPM_MIXER("O075", SND_SOC_NOPM, 0, 0, 868 mtk_dai_etdm_o075_mix, ARRAY_SIZE(mtk_dai_etdm_o075_mix)), 869 SND_SOC_DAPM_MIXER("O076", SND_SOC_NOPM, 0, 0, 870 mtk_dai_etdm_o076_mix, ARRAY_SIZE(mtk_dai_etdm_o076_mix)), 871 SND_SOC_DAPM_MIXER("O077", SND_SOC_NOPM, 0, 0, 872 mtk_dai_etdm_o077_mix, ARRAY_SIZE(mtk_dai_etdm_o077_mix)), 873 SND_SOC_DAPM_MIXER("O078", SND_SOC_NOPM, 0, 0, 874 mtk_dai_etdm_o078_mix, ARRAY_SIZE(mtk_dai_etdm_o078_mix)), 875 SND_SOC_DAPM_MIXER("O079", SND_SOC_NOPM, 0, 0, 876 mtk_dai_etdm_o079_mix, ARRAY_SIZE(mtk_dai_etdm_o079_mix)), 877 SND_SOC_DAPM_MIXER("O080", SND_SOC_NOPM, 0, 0, 878 mtk_dai_etdm_o080_mix, ARRAY_SIZE(mtk_dai_etdm_o080_mix)), 879 SND_SOC_DAPM_MIXER("O081", SND_SOC_NOPM, 0, 0, 880 mtk_dai_etdm_o081_mix, ARRAY_SIZE(mtk_dai_etdm_o081_mix)), 881 SND_SOC_DAPM_MIXER("O082", SND_SOC_NOPM, 0, 0, 882 mtk_dai_etdm_o082_mix, ARRAY_SIZE(mtk_dai_etdm_o082_mix)), 883 SND_SOC_DAPM_MIXER("O083", SND_SOC_NOPM, 0, 0, 884 mtk_dai_etdm_o083_mix, ARRAY_SIZE(mtk_dai_etdm_o083_mix)), 885 SND_SOC_DAPM_MIXER("O084", SND_SOC_NOPM, 0, 0, 886 mtk_dai_etdm_o084_mix, ARRAY_SIZE(mtk_dai_etdm_o084_mix)), 887 SND_SOC_DAPM_MIXER("O085", SND_SOC_NOPM, 0, 0, 888 mtk_dai_etdm_o085_mix, ARRAY_SIZE(mtk_dai_etdm_o085_mix)), 889 SND_SOC_DAPM_MIXER("O086", SND_SOC_NOPM, 0, 0, 890 mtk_dai_etdm_o086_mix, ARRAY_SIZE(mtk_dai_etdm_o086_mix)), 891 SND_SOC_DAPM_MIXER("O087", SND_SOC_NOPM, 0, 0, 892 mtk_dai_etdm_o087_mix, ARRAY_SIZE(mtk_dai_etdm_o087_mix)), 893 894 /* eTDM_OUT3 */ 895 SND_SOC_DAPM_MUX("HDMI_OUT_MUX", SND_SOC_NOPM, 0, 0, 896 &hdmi_out_mux_control), 897 SND_SOC_DAPM_MUX("DPTX_OUT_MUX", SND_SOC_NOPM, 0, 0, 898 &dptx_out_mux_control), 899 900 SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0, 901 &hdmi_ch0_mux_control), 902 SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0, 903 &hdmi_ch1_mux_control), 904 SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0, 905 &hdmi_ch2_mux_control), 906 SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0, 907 &hdmi_ch3_mux_control), 908 SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0, 909 &hdmi_ch4_mux_control), 910 SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0, 911 &hdmi_ch5_mux_control), 912 SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0, 913 &hdmi_ch6_mux_control), 914 SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0, 915 &hdmi_ch7_mux_control), 916 917 SND_SOC_DAPM_INPUT("ETDM_INPUT"), 918 SND_SOC_DAPM_OUTPUT("ETDM_OUTPUT"), 919 }; 920 921 static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = { 922 {"I012", NULL, "ETDM2_IN"}, 923 {"I013", NULL, "ETDM2_IN"}, 924 {"I014", NULL, "ETDM2_IN"}, 925 {"I015", NULL, "ETDM2_IN"}, 926 {"I016", NULL, "ETDM2_IN"}, 927 {"I017", NULL, "ETDM2_IN"}, 928 {"I018", NULL, "ETDM2_IN"}, 929 {"I019", NULL, "ETDM2_IN"}, 930 {"I188", NULL, "ETDM2_IN"}, 931 {"I189", NULL, "ETDM2_IN"}, 932 {"I190", NULL, "ETDM2_IN"}, 933 {"I191", NULL, "ETDM2_IN"}, 934 {"I192", NULL, "ETDM2_IN"}, 935 {"I193", NULL, "ETDM2_IN"}, 936 {"I194", NULL, "ETDM2_IN"}, 937 {"I195", NULL, "ETDM2_IN"}, 938 939 {"I072", NULL, "ETDM1_IN"}, 940 {"I073", NULL, "ETDM1_IN"}, 941 {"I074", NULL, "ETDM1_IN"}, 942 {"I075", NULL, "ETDM1_IN"}, 943 {"I076", NULL, "ETDM1_IN"}, 944 {"I077", NULL, "ETDM1_IN"}, 945 {"I078", NULL, "ETDM1_IN"}, 946 {"I079", NULL, "ETDM1_IN"}, 947 {"I080", NULL, "ETDM1_IN"}, 948 {"I081", NULL, "ETDM1_IN"}, 949 {"I082", NULL, "ETDM1_IN"}, 950 {"I083", NULL, "ETDM1_IN"}, 951 {"I084", NULL, "ETDM1_IN"}, 952 {"I085", NULL, "ETDM1_IN"}, 953 {"I086", NULL, "ETDM1_IN"}, 954 {"I087", NULL, "ETDM1_IN"}, 955 956 {"UL8", NULL, "ETDM1_IN"}, 957 {"UL3", NULL, "ETDM2_IN"}, 958 959 {"ETDM2_OUT", NULL, "O048"}, 960 {"ETDM2_OUT", NULL, "O049"}, 961 {"ETDM2_OUT", NULL, "O050"}, 962 {"ETDM2_OUT", NULL, "O051"}, 963 {"ETDM2_OUT", NULL, "O052"}, 964 {"ETDM2_OUT", NULL, "O053"}, 965 {"ETDM2_OUT", NULL, "O054"}, 966 {"ETDM2_OUT", NULL, "O055"}, 967 {"ETDM2_OUT", NULL, "O056"}, 968 {"ETDM2_OUT", NULL, "O057"}, 969 {"ETDM2_OUT", NULL, "O058"}, 970 {"ETDM2_OUT", NULL, "O059"}, 971 {"ETDM2_OUT", NULL, "O060"}, 972 {"ETDM2_OUT", NULL, "O061"}, 973 {"ETDM2_OUT", NULL, "O062"}, 974 {"ETDM2_OUT", NULL, "O063"}, 975 976 {"ETDM1_OUT", NULL, "O072"}, 977 {"ETDM1_OUT", NULL, "O073"}, 978 {"ETDM1_OUT", NULL, "O074"}, 979 {"ETDM1_OUT", NULL, "O075"}, 980 {"ETDM1_OUT", NULL, "O076"}, 981 {"ETDM1_OUT", NULL, "O077"}, 982 {"ETDM1_OUT", NULL, "O078"}, 983 {"ETDM1_OUT", NULL, "O079"}, 984 {"ETDM1_OUT", NULL, "O080"}, 985 {"ETDM1_OUT", NULL, "O081"}, 986 {"ETDM1_OUT", NULL, "O082"}, 987 {"ETDM1_OUT", NULL, "O083"}, 988 {"ETDM1_OUT", NULL, "O084"}, 989 {"ETDM1_OUT", NULL, "O085"}, 990 {"ETDM1_OUT", NULL, "O086"}, 991 {"ETDM1_OUT", NULL, "O087"}, 992 993 {"O048", "I020 Switch", "I020"}, 994 {"O049", "I021 Switch", "I021"}, 995 996 {"O048", "I022 Switch", "I022"}, 997 {"O049", "I023 Switch", "I023"}, 998 {"O050", "I024 Switch", "I024"}, 999 {"O051", "I025 Switch", "I025"}, 1000 {"O052", "I026 Switch", "I026"}, 1001 {"O053", "I027 Switch", "I027"}, 1002 {"O054", "I028 Switch", "I028"}, 1003 {"O055", "I029 Switch", "I029"}, 1004 {"O056", "I030 Switch", "I030"}, 1005 {"O057", "I031 Switch", "I031"}, 1006 {"O058", "I032 Switch", "I032"}, 1007 {"O059", "I033 Switch", "I033"}, 1008 {"O060", "I034 Switch", "I034"}, 1009 {"O061", "I035 Switch", "I035"}, 1010 {"O062", "I036 Switch", "I036"}, 1011 {"O063", "I037 Switch", "I037"}, 1012 1013 {"O048", "I046 Switch", "I046"}, 1014 {"O049", "I047 Switch", "I047"}, 1015 {"O050", "I048 Switch", "I048"}, 1016 {"O051", "I049 Switch", "I049"}, 1017 {"O052", "I050 Switch", "I050"}, 1018 {"O053", "I051 Switch", "I051"}, 1019 {"O054", "I052 Switch", "I052"}, 1020 {"O055", "I053 Switch", "I053"}, 1021 {"O056", "I054 Switch", "I054"}, 1022 {"O057", "I055 Switch", "I055"}, 1023 {"O058", "I056 Switch", "I056"}, 1024 {"O059", "I057 Switch", "I057"}, 1025 {"O060", "I058 Switch", "I058"}, 1026 {"O061", "I059 Switch", "I059"}, 1027 {"O062", "I060 Switch", "I060"}, 1028 {"O063", "I061 Switch", "I061"}, 1029 1030 {"O048", "I070 Switch", "I070"}, 1031 {"O049", "I071 Switch", "I071"}, 1032 1033 {"O072", "I020 Switch", "I020"}, 1034 {"O073", "I021 Switch", "I021"}, 1035 1036 {"O072", "I022 Switch", "I022"}, 1037 {"O073", "I023 Switch", "I023"}, 1038 {"O074", "I024 Switch", "I024"}, 1039 {"O075", "I025 Switch", "I025"}, 1040 {"O076", "I026 Switch", "I026"}, 1041 {"O077", "I027 Switch", "I027"}, 1042 {"O078", "I028 Switch", "I028"}, 1043 {"O079", "I029 Switch", "I029"}, 1044 {"O080", "I030 Switch", "I030"}, 1045 {"O081", "I031 Switch", "I031"}, 1046 {"O082", "I032 Switch", "I032"}, 1047 {"O083", "I033 Switch", "I033"}, 1048 {"O084", "I034 Switch", "I034"}, 1049 {"O085", "I035 Switch", "I035"}, 1050 {"O086", "I036 Switch", "I036"}, 1051 {"O087", "I037 Switch", "I037"}, 1052 1053 {"O072", "I046 Switch", "I046"}, 1054 {"O073", "I047 Switch", "I047"}, 1055 {"O074", "I048 Switch", "I048"}, 1056 {"O075", "I049 Switch", "I049"}, 1057 {"O076", "I050 Switch", "I050"}, 1058 {"O077", "I051 Switch", "I051"}, 1059 {"O078", "I052 Switch", "I052"}, 1060 {"O079", "I053 Switch", "I053"}, 1061 {"O080", "I054 Switch", "I054"}, 1062 {"O081", "I055 Switch", "I055"}, 1063 {"O082", "I056 Switch", "I056"}, 1064 {"O083", "I057 Switch", "I057"}, 1065 {"O084", "I058 Switch", "I058"}, 1066 {"O085", "I059 Switch", "I059"}, 1067 {"O086", "I060 Switch", "I060"}, 1068 {"O087", "I061 Switch", "I061"}, 1069 1070 {"O072", "I070 Switch", "I070"}, 1071 {"O073", "I071 Switch", "I071"}, 1072 1073 {"HDMI_CH0_MUX", "CH0", "DL10"}, 1074 {"HDMI_CH0_MUX", "CH1", "DL10"}, 1075 {"HDMI_CH0_MUX", "CH2", "DL10"}, 1076 {"HDMI_CH0_MUX", "CH3", "DL10"}, 1077 {"HDMI_CH0_MUX", "CH4", "DL10"}, 1078 {"HDMI_CH0_MUX", "CH5", "DL10"}, 1079 {"HDMI_CH0_MUX", "CH6", "DL10"}, 1080 {"HDMI_CH0_MUX", "CH7", "DL10"}, 1081 1082 {"HDMI_CH1_MUX", "CH0", "DL10"}, 1083 {"HDMI_CH1_MUX", "CH1", "DL10"}, 1084 {"HDMI_CH1_MUX", "CH2", "DL10"}, 1085 {"HDMI_CH1_MUX", "CH3", "DL10"}, 1086 {"HDMI_CH1_MUX", "CH4", "DL10"}, 1087 {"HDMI_CH1_MUX", "CH5", "DL10"}, 1088 {"HDMI_CH1_MUX", "CH6", "DL10"}, 1089 {"HDMI_CH1_MUX", "CH7", "DL10"}, 1090 1091 {"HDMI_CH2_MUX", "CH0", "DL10"}, 1092 {"HDMI_CH2_MUX", "CH1", "DL10"}, 1093 {"HDMI_CH2_MUX", "CH2", "DL10"}, 1094 {"HDMI_CH2_MUX", "CH3", "DL10"}, 1095 {"HDMI_CH2_MUX", "CH4", "DL10"}, 1096 {"HDMI_CH2_MUX", "CH5", "DL10"}, 1097 {"HDMI_CH2_MUX", "CH6", "DL10"}, 1098 {"HDMI_CH2_MUX", "CH7", "DL10"}, 1099 1100 {"HDMI_CH3_MUX", "CH0", "DL10"}, 1101 {"HDMI_CH3_MUX", "CH1", "DL10"}, 1102 {"HDMI_CH3_MUX", "CH2", "DL10"}, 1103 {"HDMI_CH3_MUX", "CH3", "DL10"}, 1104 {"HDMI_CH3_MUX", "CH4", "DL10"}, 1105 {"HDMI_CH3_MUX", "CH5", "DL10"}, 1106 {"HDMI_CH3_MUX", "CH6", "DL10"}, 1107 {"HDMI_CH3_MUX", "CH7", "DL10"}, 1108 1109 {"HDMI_CH4_MUX", "CH0", "DL10"}, 1110 {"HDMI_CH4_MUX", "CH1", "DL10"}, 1111 {"HDMI_CH4_MUX", "CH2", "DL10"}, 1112 {"HDMI_CH4_MUX", "CH3", "DL10"}, 1113 {"HDMI_CH4_MUX", "CH4", "DL10"}, 1114 {"HDMI_CH4_MUX", "CH5", "DL10"}, 1115 {"HDMI_CH4_MUX", "CH6", "DL10"}, 1116 {"HDMI_CH4_MUX", "CH7", "DL10"}, 1117 1118 {"HDMI_CH5_MUX", "CH0", "DL10"}, 1119 {"HDMI_CH5_MUX", "CH1", "DL10"}, 1120 {"HDMI_CH5_MUX", "CH2", "DL10"}, 1121 {"HDMI_CH5_MUX", "CH3", "DL10"}, 1122 {"HDMI_CH5_MUX", "CH4", "DL10"}, 1123 {"HDMI_CH5_MUX", "CH5", "DL10"}, 1124 {"HDMI_CH5_MUX", "CH6", "DL10"}, 1125 {"HDMI_CH5_MUX", "CH7", "DL10"}, 1126 1127 {"HDMI_CH6_MUX", "CH0", "DL10"}, 1128 {"HDMI_CH6_MUX", "CH1", "DL10"}, 1129 {"HDMI_CH6_MUX", "CH2", "DL10"}, 1130 {"HDMI_CH6_MUX", "CH3", "DL10"}, 1131 {"HDMI_CH6_MUX", "CH4", "DL10"}, 1132 {"HDMI_CH6_MUX", "CH5", "DL10"}, 1133 {"HDMI_CH6_MUX", "CH6", "DL10"}, 1134 {"HDMI_CH6_MUX", "CH7", "DL10"}, 1135 1136 {"HDMI_CH7_MUX", "CH0", "DL10"}, 1137 {"HDMI_CH7_MUX", "CH1", "DL10"}, 1138 {"HDMI_CH7_MUX", "CH2", "DL10"}, 1139 {"HDMI_CH7_MUX", "CH3", "DL10"}, 1140 {"HDMI_CH7_MUX", "CH4", "DL10"}, 1141 {"HDMI_CH7_MUX", "CH5", "DL10"}, 1142 {"HDMI_CH7_MUX", "CH6", "DL10"}, 1143 {"HDMI_CH7_MUX", "CH7", "DL10"}, 1144 1145 {"HDMI_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, 1146 {"HDMI_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, 1147 {"HDMI_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, 1148 {"HDMI_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, 1149 {"HDMI_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, 1150 {"HDMI_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, 1151 {"HDMI_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, 1152 {"HDMI_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, 1153 1154 {"DPTX_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, 1155 {"DPTX_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, 1156 {"DPTX_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, 1157 {"DPTX_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, 1158 {"DPTX_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, 1159 {"DPTX_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, 1160 {"DPTX_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, 1161 {"DPTX_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, 1162 1163 {"ETDM3_OUT", NULL, "HDMI_OUT_MUX"}, 1164 {"DPTX", NULL, "DPTX_OUT_MUX"}, 1165 1166 {"ETDM_OUTPUT", NULL, "DPTX"}, 1167 {"ETDM_OUTPUT", NULL, "ETDM1_OUT"}, 1168 {"ETDM_OUTPUT", NULL, "ETDM2_OUT"}, 1169 {"ETDM_OUTPUT", NULL, "ETDM3_OUT"}, 1170 {"ETDM1_IN", NULL, "ETDM_INPUT"}, 1171 {"ETDM2_IN", NULL, "ETDM_INPUT"}, 1172 }; 1173 1174 static int mt8188_afe_enable_etdm(struct mtk_base_afe *afe, int dai_id) 1175 { 1176 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1177 struct mtk_dai_etdm_priv *etdm_data; 1178 struct etdm_con_reg etdm_reg; 1179 unsigned long flags; 1180 int ret = 0; 1181 1182 if (!is_valid_etdm_dai(dai_id)) 1183 return -EINVAL; 1184 etdm_data = afe_priv->dai_priv[dai_id]; 1185 1186 dev_dbg(afe->dev, "%s [%d]%d\n", __func__, dai_id, etdm_data->en_ref_cnt); 1187 spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags); 1188 etdm_data->en_ref_cnt++; 1189 if (etdm_data->en_ref_cnt == 1) { 1190 ret = get_etdm_reg(dai_id, &etdm_reg); 1191 if (ret < 0) 1192 goto out; 1193 1194 regmap_set_bits(afe->regmap, etdm_reg.con0, ETDM_CON0_EN); 1195 } 1196 1197 out: 1198 spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags); 1199 return ret; 1200 } 1201 1202 static int mt8188_afe_disable_etdm(struct mtk_base_afe *afe, int dai_id) 1203 { 1204 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1205 struct mtk_dai_etdm_priv *etdm_data; 1206 struct etdm_con_reg etdm_reg; 1207 unsigned long flags; 1208 int ret = 0; 1209 1210 if (!is_valid_etdm_dai(dai_id)) 1211 return -EINVAL; 1212 etdm_data = afe_priv->dai_priv[dai_id]; 1213 1214 dev_dbg(afe->dev, "%s [%d]%d\n", __func__, dai_id, etdm_data->en_ref_cnt); 1215 spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags); 1216 if (etdm_data->en_ref_cnt > 0) { 1217 etdm_data->en_ref_cnt--; 1218 if (etdm_data->en_ref_cnt == 0) { 1219 ret = get_etdm_reg(dai_id, &etdm_reg); 1220 if (ret < 0) 1221 goto out; 1222 regmap_clear_bits(afe->regmap, etdm_reg.con0, 1223 ETDM_CON0_EN); 1224 } 1225 } 1226 1227 out: 1228 spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags); 1229 return ret; 1230 } 1231 1232 static int etdm_cowork_slv_sel(int id, int slave_mode) 1233 { 1234 if (slave_mode) { 1235 switch (id) { 1236 case MT8188_AFE_IO_ETDM1_IN: 1237 return COWORK_ETDM_IN1_S; 1238 case MT8188_AFE_IO_ETDM2_IN: 1239 return COWORK_ETDM_IN2_S; 1240 case MT8188_AFE_IO_ETDM1_OUT: 1241 return COWORK_ETDM_OUT1_S; 1242 case MT8188_AFE_IO_ETDM2_OUT: 1243 return COWORK_ETDM_OUT2_S; 1244 case MT8188_AFE_IO_ETDM3_OUT: 1245 return COWORK_ETDM_OUT3_S; 1246 default: 1247 return -EINVAL; 1248 } 1249 } else { 1250 switch (id) { 1251 case MT8188_AFE_IO_ETDM1_IN: 1252 return COWORK_ETDM_IN1_M; 1253 case MT8188_AFE_IO_ETDM2_IN: 1254 return COWORK_ETDM_IN2_M; 1255 case MT8188_AFE_IO_ETDM1_OUT: 1256 return COWORK_ETDM_OUT1_M; 1257 case MT8188_AFE_IO_ETDM2_OUT: 1258 return COWORK_ETDM_OUT2_M; 1259 case MT8188_AFE_IO_ETDM3_OUT: 1260 return COWORK_ETDM_OUT3_M; 1261 default: 1262 return -EINVAL; 1263 } 1264 } 1265 } 1266 1267 static int etdm_cowork_sync_sel(int id) 1268 { 1269 switch (id) { 1270 case MT8188_AFE_IO_ETDM1_IN: 1271 return ETDM_SYNC_FROM_IN1; 1272 case MT8188_AFE_IO_ETDM2_IN: 1273 return ETDM_SYNC_FROM_IN2; 1274 case MT8188_AFE_IO_ETDM1_OUT: 1275 return ETDM_SYNC_FROM_OUT1; 1276 case MT8188_AFE_IO_ETDM2_OUT: 1277 return ETDM_SYNC_FROM_OUT2; 1278 case MT8188_AFE_IO_ETDM3_OUT: 1279 return ETDM_SYNC_FROM_OUT3; 1280 default: 1281 return -EINVAL; 1282 } 1283 } 1284 1285 static int mt8188_etdm_sync_mode_slv(struct mtk_base_afe *afe, int dai_id) 1286 { 1287 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1288 struct mtk_dai_etdm_priv *etdm_data; 1289 unsigned int reg = 0; 1290 unsigned int mask; 1291 unsigned int val; 1292 int cowork_source_sel; 1293 1294 if (!is_valid_etdm_dai(dai_id)) 1295 return -EINVAL; 1296 etdm_data = afe_priv->dai_priv[dai_id]; 1297 1298 cowork_source_sel = etdm_cowork_slv_sel(etdm_data->cowork_source_id, 1299 true); 1300 if (cowork_source_sel < 0) 1301 return cowork_source_sel; 1302 1303 switch (dai_id) { 1304 case MT8188_AFE_IO_ETDM1_IN: 1305 reg = ETDM_COWORK_CON1; 1306 mask = ETDM_IN1_SLAVE_SEL_MASK; 1307 val = FIELD_PREP(ETDM_IN1_SLAVE_SEL_MASK, cowork_source_sel); 1308 break; 1309 case MT8188_AFE_IO_ETDM2_IN: 1310 reg = ETDM_COWORK_CON2; 1311 mask = ETDM_IN2_SLAVE_SEL_MASK; 1312 val = FIELD_PREP(ETDM_IN2_SLAVE_SEL_MASK, cowork_source_sel); 1313 break; 1314 case MT8188_AFE_IO_ETDM1_OUT: 1315 reg = ETDM_COWORK_CON0; 1316 mask = ETDM_OUT1_SLAVE_SEL_MASK; 1317 val = FIELD_PREP(ETDM_OUT1_SLAVE_SEL_MASK, cowork_source_sel); 1318 break; 1319 case MT8188_AFE_IO_ETDM2_OUT: 1320 reg = ETDM_COWORK_CON2; 1321 mask = ETDM_OUT2_SLAVE_SEL_MASK; 1322 val = FIELD_PREP(ETDM_OUT2_SLAVE_SEL_MASK, cowork_source_sel); 1323 break; 1324 case MT8188_AFE_IO_ETDM3_OUT: 1325 reg = ETDM_COWORK_CON2; 1326 mask = ETDM_OUT3_SLAVE_SEL_MASK; 1327 val = FIELD_PREP(ETDM_OUT3_SLAVE_SEL_MASK, cowork_source_sel); 1328 break; 1329 default: 1330 return 0; 1331 } 1332 1333 regmap_update_bits(afe->regmap, reg, mask, val); 1334 1335 return 0; 1336 } 1337 1338 static int mt8188_etdm_sync_mode_mst(struct mtk_base_afe *afe, int dai_id) 1339 { 1340 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1341 struct mtk_dai_etdm_priv *etdm_data; 1342 struct etdm_con_reg etdm_reg; 1343 unsigned int reg = 0; 1344 unsigned int mask; 1345 unsigned int val; 1346 int cowork_source_sel; 1347 int ret; 1348 1349 if (!is_valid_etdm_dai(dai_id)) 1350 return -EINVAL; 1351 etdm_data = afe_priv->dai_priv[dai_id]; 1352 1353 cowork_source_sel = etdm_cowork_sync_sel(etdm_data->cowork_source_id); 1354 if (cowork_source_sel < 0) 1355 return cowork_source_sel; 1356 1357 switch (dai_id) { 1358 case MT8188_AFE_IO_ETDM1_IN: 1359 reg = ETDM_COWORK_CON1; 1360 mask = ETDM_IN1_SYNC_SEL_MASK; 1361 val = FIELD_PREP(ETDM_IN1_SYNC_SEL_MASK, cowork_source_sel); 1362 break; 1363 case MT8188_AFE_IO_ETDM2_IN: 1364 reg = ETDM_COWORK_CON2; 1365 mask = ETDM_IN2_SYNC_SEL_MASK; 1366 val = FIELD_PREP(ETDM_IN2_SYNC_SEL_MASK, cowork_source_sel); 1367 break; 1368 case MT8188_AFE_IO_ETDM1_OUT: 1369 reg = ETDM_COWORK_CON0; 1370 mask = ETDM_OUT1_SYNC_SEL_MASK; 1371 val = FIELD_PREP(ETDM_OUT1_SYNC_SEL_MASK, cowork_source_sel); 1372 break; 1373 case MT8188_AFE_IO_ETDM2_OUT: 1374 reg = ETDM_COWORK_CON2; 1375 mask = ETDM_OUT2_SYNC_SEL_MASK; 1376 val = FIELD_PREP(ETDM_OUT2_SYNC_SEL_MASK, cowork_source_sel); 1377 break; 1378 case MT8188_AFE_IO_ETDM3_OUT: 1379 reg = ETDM_COWORK_CON2; 1380 mask = ETDM_OUT3_SYNC_SEL_MASK; 1381 val = FIELD_PREP(ETDM_OUT3_SYNC_SEL_MASK, cowork_source_sel); 1382 break; 1383 default: 1384 return 0; 1385 } 1386 1387 ret = get_etdm_reg(dai_id, &etdm_reg); 1388 if (ret < 0) 1389 return ret; 1390 1391 regmap_update_bits(afe->regmap, reg, mask, val); 1392 1393 regmap_set_bits(afe->regmap, etdm_reg.con0, ETDM_CON0_SYNC_MODE); 1394 1395 return 0; 1396 } 1397 1398 static int mt8188_etdm_sync_mode_configure(struct mtk_base_afe *afe, int dai_id) 1399 { 1400 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1401 struct mtk_dai_etdm_priv *etdm_data; 1402 1403 if (!is_valid_etdm_dai(dai_id)) 1404 return -EINVAL; 1405 etdm_data = afe_priv->dai_priv[dai_id]; 1406 1407 if (etdm_data->cowork_source_id == COWORK_ETDM_NONE) 1408 return 0; 1409 1410 if (etdm_data->slave_mode) 1411 mt8188_etdm_sync_mode_slv(afe, dai_id); 1412 else 1413 mt8188_etdm_sync_mode_mst(afe, dai_id); 1414 1415 return 0; 1416 } 1417 1418 /* dai ops */ 1419 static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream, 1420 struct snd_soc_dai *dai) 1421 { 1422 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1423 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1424 struct mtk_dai_etdm_priv *mst_etdm_data; 1425 int mst_dai_id; 1426 int slv_dai_id; 1427 int cg_id; 1428 int i; 1429 1430 if (is_cowork_mode(dai)) { 1431 mst_dai_id = get_etdm_cowork_master_id(dai); 1432 if (!is_valid_etdm_dai(mst_dai_id)) 1433 return -EINVAL; 1434 mtk_dai_etdm_enable_mclk(afe, mst_dai_id); 1435 1436 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id); 1437 if (cg_id >= 0) 1438 mt8188_afe_enable_clk(afe, afe_priv->clk[cg_id]); 1439 1440 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1441 1442 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1443 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1444 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id); 1445 if (cg_id >= 0) 1446 mt8188_afe_enable_clk(afe, 1447 afe_priv->clk[cg_id]); 1448 } 1449 } else { 1450 mtk_dai_etdm_enable_mclk(afe, dai->id); 1451 1452 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 1453 if (cg_id >= 0) 1454 mt8188_afe_enable_clk(afe, afe_priv->clk[cg_id]); 1455 } 1456 1457 return 0; 1458 } 1459 1460 static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream, 1461 struct snd_soc_dai *dai) 1462 { 1463 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1464 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1465 struct mtk_dai_etdm_priv *mst_etdm_data; 1466 int mst_dai_id; 1467 int slv_dai_id; 1468 int cg_id; 1469 int ret; 1470 int i; 1471 1472 if (!is_valid_etdm_dai(dai->id)) 1473 return; 1474 mst_etdm_data = afe_priv->dai_priv[dai->id]; 1475 1476 dev_dbg(afe->dev, "%s(), dai id %d, prepared %d\n", __func__, dai->id, 1477 mst_etdm_data->is_prepared); 1478 1479 if (mst_etdm_data->is_prepared) { 1480 mst_etdm_data->is_prepared = false; 1481 1482 if (is_cowork_mode(dai)) { 1483 mst_dai_id = get_etdm_cowork_master_id(dai); 1484 if (!is_valid_etdm_dai(mst_dai_id)) 1485 return; 1486 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1487 1488 ret = mt8188_afe_disable_etdm(afe, mst_dai_id); 1489 if (ret) 1490 dev_dbg(afe->dev, "%s disable %d failed\n", 1491 __func__, mst_dai_id); 1492 1493 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1494 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1495 ret = mt8188_afe_disable_etdm(afe, slv_dai_id); 1496 if (ret) 1497 dev_dbg(afe->dev, "%s disable %d failed\n", 1498 __func__, slv_dai_id); 1499 } 1500 } else { 1501 ret = mt8188_afe_disable_etdm(afe, dai->id); 1502 if (ret) 1503 dev_dbg(afe->dev, "%s disable %d failed\n", 1504 __func__, dai->id); 1505 } 1506 } 1507 1508 if (is_cowork_mode(dai)) { 1509 mst_dai_id = get_etdm_cowork_master_id(dai); 1510 if (!is_valid_etdm_dai(mst_dai_id)) 1511 return; 1512 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id); 1513 if (cg_id >= 0) 1514 mt8188_afe_disable_clk(afe, afe_priv->clk[cg_id]); 1515 1516 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1517 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1518 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1519 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id); 1520 if (cg_id >= 0) 1521 mt8188_afe_disable_clk(afe, 1522 afe_priv->clk[cg_id]); 1523 } 1524 mtk_dai_etdm_disable_mclk(afe, mst_dai_id); 1525 } else { 1526 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 1527 if (cg_id >= 0) 1528 mt8188_afe_disable_clk(afe, afe_priv->clk[cg_id]); 1529 1530 mtk_dai_etdm_disable_mclk(afe, dai->id); 1531 } 1532 } 1533 1534 static int mtk_dai_etdm_fifo_mode(struct mtk_base_afe *afe, 1535 int dai_id, unsigned int rate) 1536 { 1537 unsigned int mode = 0; 1538 unsigned int reg = 0; 1539 unsigned int val = 0; 1540 unsigned int mask = (ETDM_IN_AFIFO_MODE_MASK | ETDM_IN_USE_AFIFO); 1541 1542 if (rate != 0) 1543 mode = mt8188_afe_fs_timing(rate); 1544 1545 switch (dai_id) { 1546 case MT8188_AFE_IO_ETDM1_IN: 1547 reg = ETDM_IN1_AFIFO_CON; 1548 if (rate == 0) 1549 mode = MT8188_ETDM_IN1_1X_EN; 1550 break; 1551 case MT8188_AFE_IO_ETDM2_IN: 1552 reg = ETDM_IN2_AFIFO_CON; 1553 if (rate == 0) 1554 mode = MT8188_ETDM_IN2_1X_EN; 1555 break; 1556 default: 1557 return -EINVAL; 1558 } 1559 1560 val = (mode | ETDM_IN_USE_AFIFO); 1561 1562 regmap_update_bits(afe->regmap, reg, mask, val); 1563 return 0; 1564 } 1565 1566 static int mtk_dai_etdm_in_configure(struct mtk_base_afe *afe, 1567 unsigned int rate, 1568 unsigned int channels, 1569 int dai_id) 1570 { 1571 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1572 struct mtk_dai_etdm_priv *etdm_data; 1573 struct etdm_con_reg etdm_reg; 1574 bool slave_mode; 1575 unsigned int data_mode; 1576 unsigned int lrck_width; 1577 unsigned int val = 0; 1578 unsigned int mask = 0; 1579 int ret; 1580 int i; 1581 1582 if (!is_valid_etdm_dai(dai_id)) 1583 return -EINVAL; 1584 etdm_data = afe_priv->dai_priv[dai_id]; 1585 slave_mode = etdm_data->slave_mode; 1586 data_mode = etdm_data->data_mode; 1587 lrck_width = etdm_data->lrck_width; 1588 1589 dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n", 1590 __func__, rate, channels, dai_id); 1591 1592 ret = get_etdm_reg(dai_id, &etdm_reg); 1593 if (ret < 0) 1594 return ret; 1595 1596 /* afifo */ 1597 if (slave_mode) 1598 mtk_dai_etdm_fifo_mode(afe, dai_id, 0); 1599 else 1600 mtk_dai_etdm_fifo_mode(afe, dai_id, rate); 1601 1602 /* con1 */ 1603 if (lrck_width > 0) { 1604 mask |= (ETDM_IN_CON1_LRCK_AUTO_MODE | 1605 ETDM_IN_CON1_LRCK_WIDTH_MASK); 1606 val |= FIELD_PREP(ETDM_IN_CON1_LRCK_WIDTH_MASK, lrck_width - 1); 1607 } 1608 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 1609 1610 mask = 0; 1611 val = 0; 1612 1613 /* con2 */ 1614 if (!slave_mode) { 1615 mask |= ETDM_IN_CON2_UPDATE_GAP_MASK; 1616 if (rate == 352800 || rate == 384000) 1617 val |= FIELD_PREP(ETDM_IN_CON2_UPDATE_GAP_MASK, 4); 1618 else 1619 val |= FIELD_PREP(ETDM_IN_CON2_UPDATE_GAP_MASK, 3); 1620 } 1621 mask |= (ETDM_IN_CON2_MULTI_IP_2CH_MODE | 1622 ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK); 1623 if (data_mode == MTK_DAI_ETDM_DATA_MULTI_PIN) { 1624 val |= ETDM_IN_CON2_MULTI_IP_2CH_MODE | 1625 FIELD_PREP(ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK, channels - 1); 1626 } 1627 regmap_update_bits(afe->regmap, etdm_reg.con2, mask, val); 1628 1629 mask = 0; 1630 val = 0; 1631 1632 /* con3 */ 1633 mask |= ETDM_IN_CON3_DISABLE_OUT_MASK; 1634 for (i = 0; i < channels; i += 2) { 1635 if (etdm_data->in_disable_ch[i] && 1636 etdm_data->in_disable_ch[i + 1]) 1637 val |= ETDM_IN_CON3_DISABLE_OUT(i >> 1); 1638 } 1639 if (!slave_mode) { 1640 mask |= ETDM_IN_CON3_FS_MASK; 1641 val |= FIELD_PREP(ETDM_IN_CON3_FS_MASK, get_etdm_fs_timing(rate)); 1642 } 1643 regmap_update_bits(afe->regmap, etdm_reg.con3, mask, val); 1644 1645 mask = 0; 1646 val = 0; 1647 1648 /* con4 */ 1649 mask |= (ETDM_IN_CON4_MASTER_LRCK_INV | ETDM_IN_CON4_MASTER_BCK_INV | 1650 ETDM_IN_CON4_SLAVE_LRCK_INV | ETDM_IN_CON4_SLAVE_BCK_INV); 1651 if (slave_mode) { 1652 if (etdm_data->lrck_inv) 1653 val |= ETDM_IN_CON4_SLAVE_LRCK_INV; 1654 if (etdm_data->bck_inv) 1655 val |= ETDM_IN_CON4_SLAVE_BCK_INV; 1656 } else { 1657 if (etdm_data->lrck_inv) 1658 val |= ETDM_IN_CON4_MASTER_LRCK_INV; 1659 if (etdm_data->bck_inv) 1660 val |= ETDM_IN_CON4_MASTER_BCK_INV; 1661 } 1662 regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val); 1663 1664 mask = 0; 1665 val = 0; 1666 1667 /* con5 */ 1668 mask |= ETDM_IN_CON5_LR_SWAP_MASK; 1669 mask |= ETDM_IN_CON5_ENABLE_ODD_MASK; 1670 for (i = 0; i < channels; i += 2) { 1671 if (etdm_data->in_disable_ch[i] && 1672 !etdm_data->in_disable_ch[i + 1]) { 1673 val |= ETDM_IN_CON5_LR_SWAP(i >> 1); 1674 val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1); 1675 } else if (!etdm_data->in_disable_ch[i] && 1676 etdm_data->in_disable_ch[i + 1]) { 1677 val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1); 1678 } 1679 } 1680 regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val); 1681 return 0; 1682 } 1683 1684 static int mtk_dai_etdm_out_configure(struct mtk_base_afe *afe, 1685 unsigned int rate, 1686 unsigned int channels, 1687 int dai_id) 1688 { 1689 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1690 struct mtk_dai_etdm_priv *etdm_data; 1691 struct etdm_con_reg etdm_reg; 1692 bool slave_mode; 1693 unsigned int lrck_width; 1694 unsigned int val = 0; 1695 unsigned int mask = 0; 1696 int fs = 0; 1697 int ret; 1698 1699 if (!is_valid_etdm_dai(dai_id)) 1700 return -EINVAL; 1701 etdm_data = afe_priv->dai_priv[dai_id]; 1702 slave_mode = etdm_data->slave_mode; 1703 lrck_width = etdm_data->lrck_width; 1704 1705 dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n", 1706 __func__, rate, channels, dai_id); 1707 1708 ret = get_etdm_reg(dai_id, &etdm_reg); 1709 if (ret < 0) 1710 return ret; 1711 1712 /* con0 */ 1713 mask = ETDM_OUT_CON0_RELATCH_DOMAIN_MASK; 1714 val = FIELD_PREP(ETDM_OUT_CON0_RELATCH_DOMAIN_MASK, 1715 ETDM_RELATCH_TIMING_A1A2SYS); 1716 regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val); 1717 1718 mask = 0; 1719 val = 0; 1720 1721 /* con1 */ 1722 if (lrck_width > 0) { 1723 mask |= (ETDM_OUT_CON1_LRCK_AUTO_MODE | 1724 ETDM_OUT_CON1_LRCK_WIDTH_MASK); 1725 val |= FIELD_PREP(ETDM_OUT_CON1_LRCK_WIDTH_MASK, lrck_width - 1); 1726 } 1727 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 1728 1729 mask = 0; 1730 val = 0; 1731 1732 if (!slave_mode) { 1733 /* con4 */ 1734 mask |= ETDM_OUT_CON4_FS_MASK; 1735 val |= FIELD_PREP(ETDM_OUT_CON4_FS_MASK, get_etdm_fs_timing(rate)); 1736 } 1737 1738 mask |= ETDM_OUT_CON4_RELATCH_EN_MASK; 1739 if (dai_id == MT8188_AFE_IO_ETDM1_OUT) 1740 fs = MT8188_ETDM_OUT1_1X_EN; 1741 else if (dai_id == MT8188_AFE_IO_ETDM2_OUT) 1742 fs = MT8188_ETDM_OUT2_1X_EN; 1743 1744 val |= FIELD_PREP(ETDM_OUT_CON4_RELATCH_EN_MASK, fs); 1745 1746 regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val); 1747 1748 mask = 0; 1749 val = 0; 1750 1751 /* con5 */ 1752 mask |= (ETDM_OUT_CON5_MASTER_LRCK_INV | ETDM_OUT_CON5_MASTER_BCK_INV | 1753 ETDM_OUT_CON5_SLAVE_LRCK_INV | ETDM_OUT_CON5_SLAVE_BCK_INV); 1754 if (slave_mode) { 1755 if (etdm_data->lrck_inv) 1756 val |= ETDM_OUT_CON5_SLAVE_LRCK_INV; 1757 if (etdm_data->bck_inv) 1758 val |= ETDM_OUT_CON5_SLAVE_BCK_INV; 1759 } else { 1760 if (etdm_data->lrck_inv) 1761 val |= ETDM_OUT_CON5_MASTER_LRCK_INV; 1762 if (etdm_data->bck_inv) 1763 val |= ETDM_OUT_CON5_MASTER_BCK_INV; 1764 } 1765 regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val); 1766 1767 return 0; 1768 } 1769 1770 static int mtk_dai_etdm_mclk_configure(struct mtk_base_afe *afe, int dai_id) 1771 { 1772 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1773 struct mtk_dai_etdm_priv *etdm_data; 1774 struct etdm_con_reg etdm_reg; 1775 int clk_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id); 1776 int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 1777 int apll_clk_id; 1778 int apll; 1779 int ret; 1780 1781 if (clk_id < 0 || clkdiv_id < 0) 1782 return -EINVAL; 1783 1784 if (!is_valid_etdm_dai(dai_id)) 1785 return -EINVAL; 1786 etdm_data = afe_priv->dai_priv[dai_id]; 1787 1788 ret = get_etdm_reg(dai_id, &etdm_reg); 1789 if (ret < 0) 1790 return ret; 1791 1792 if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 1793 regmap_set_bits(afe->regmap, etdm_reg.con1, 1794 ETDM_CON1_MCLK_OUTPUT); 1795 else 1796 regmap_clear_bits(afe->regmap, etdm_reg.con1, 1797 ETDM_CON1_MCLK_OUTPUT); 1798 1799 if (etdm_data->mclk_freq) { 1800 apll = etdm_data->mclk_apll; 1801 apll_clk_id = mt8188_afe_get_mclk_source_clk_id(apll); 1802 if (apll_clk_id < 0) 1803 return apll_clk_id; 1804 1805 /* select apll */ 1806 ret = mt8188_afe_set_clk_parent(afe, afe_priv->clk[clk_id], 1807 afe_priv->clk[apll_clk_id]); 1808 if (ret) 1809 return ret; 1810 1811 /* set rate */ 1812 ret = mt8188_afe_set_clk_rate(afe, afe_priv->clk[clkdiv_id], 1813 etdm_data->mclk_freq); 1814 if (ret) 1815 return ret; 1816 } else { 1817 if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 1818 dev_dbg(afe->dev, "%s mclk freq = 0\n", __func__); 1819 } 1820 1821 return 0; 1822 } 1823 1824 static int mtk_dai_etdm_configure(struct mtk_base_afe *afe, 1825 unsigned int rate, 1826 unsigned int channels, 1827 unsigned int bit_width, 1828 int dai_id) 1829 { 1830 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1831 struct mtk_dai_etdm_priv *etdm_data; 1832 struct etdm_con_reg etdm_reg; 1833 bool slave_mode; 1834 unsigned int etdm_channels; 1835 unsigned int val = 0; 1836 unsigned int mask = 0; 1837 unsigned int bck; 1838 unsigned int wlen = get_etdm_wlen(bit_width); 1839 int ret; 1840 1841 if (!is_valid_etdm_dai(dai_id)) 1842 return -EINVAL; 1843 etdm_data = afe_priv->dai_priv[dai_id]; 1844 slave_mode = etdm_data->slave_mode; 1845 1846 ret = get_etdm_reg(dai_id, &etdm_reg); 1847 if (ret < 0) 1848 return ret; 1849 1850 dev_dbg(afe->dev, "%s fmt %u data %u lrck %d-%u bck %d, clock %u slv %u\n", 1851 __func__, etdm_data->format, etdm_data->data_mode, 1852 etdm_data->lrck_inv, etdm_data->lrck_width, etdm_data->bck_inv, 1853 etdm_data->clock_mode, etdm_data->slave_mode); 1854 dev_dbg(afe->dev, "%s rate %u channels %u bitwidth %u, id %d\n", 1855 __func__, rate, channels, bit_width, dai_id); 1856 1857 etdm_channels = (etdm_data->data_mode == MTK_DAI_ETDM_DATA_ONE_PIN) ? 1858 get_etdm_ch_fixup(channels) : 2; 1859 1860 bck = rate * etdm_channels * wlen; 1861 if (bck > MT8188_ETDM_NORMAL_MAX_BCK_RATE) { 1862 dev_err(afe->dev, "%s bck rate %u not support\n", 1863 __func__, bck); 1864 return -EINVAL; 1865 } 1866 1867 /* con0 */ 1868 mask |= ETDM_CON0_BIT_LEN_MASK; 1869 val |= FIELD_PREP(ETDM_CON0_BIT_LEN_MASK, bit_width - 1); 1870 mask |= ETDM_CON0_WORD_LEN_MASK; 1871 val |= FIELD_PREP(ETDM_CON0_WORD_LEN_MASK, wlen - 1); 1872 mask |= ETDM_CON0_FORMAT_MASK; 1873 val |= FIELD_PREP(ETDM_CON0_FORMAT_MASK, etdm_data->format); 1874 mask |= ETDM_CON0_CH_NUM_MASK; 1875 val |= FIELD_PREP(ETDM_CON0_CH_NUM_MASK, etdm_channels - 1); 1876 1877 mask |= ETDM_CON0_SLAVE_MODE; 1878 if (slave_mode) { 1879 if (dai_id == MT8188_AFE_IO_ETDM1_OUT) { 1880 dev_err(afe->dev, "%s id %d only support master mode\n", 1881 __func__, dai_id); 1882 return -EINVAL; 1883 } 1884 val |= ETDM_CON0_SLAVE_MODE; 1885 } 1886 regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val); 1887 1888 if (get_etdm_dir(dai_id) == ETDM_IN) 1889 mtk_dai_etdm_in_configure(afe, rate, channels, dai_id); 1890 else 1891 mtk_dai_etdm_out_configure(afe, rate, channels, dai_id); 1892 1893 return 0; 1894 } 1895 1896 static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream, 1897 struct snd_pcm_hw_params *params, 1898 struct snd_soc_dai *dai) 1899 { 1900 unsigned int rate = params_rate(params); 1901 unsigned int bit_width = params_width(params); 1902 unsigned int channels = params_channels(params); 1903 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1904 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1905 struct mtk_dai_etdm_priv *mst_etdm_data; 1906 int mst_dai_id; 1907 int slv_dai_id; 1908 int ret; 1909 int i; 1910 1911 dev_dbg(afe->dev, "%s '%s' period %u-%u\n", 1912 __func__, snd_pcm_stream_str(substream), 1913 params_period_size(params), params_periods(params)); 1914 1915 if (is_cowork_mode(dai)) { 1916 mst_dai_id = get_etdm_cowork_master_id(dai); 1917 if (!is_valid_etdm_dai(mst_dai_id)) 1918 return -EINVAL; 1919 1920 ret = mtk_dai_etdm_mclk_configure(afe, mst_dai_id); 1921 if (ret) 1922 return ret; 1923 1924 ret = mtk_dai_etdm_configure(afe, rate, channels, 1925 bit_width, mst_dai_id); 1926 if (ret) 1927 return ret; 1928 1929 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1930 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1931 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1932 ret = mtk_dai_etdm_configure(afe, rate, channels, 1933 bit_width, slv_dai_id); 1934 if (ret) 1935 return ret; 1936 1937 ret = mt8188_etdm_sync_mode_configure(afe, slv_dai_id); 1938 if (ret) 1939 return ret; 1940 } 1941 } else { 1942 ret = mtk_dai_etdm_mclk_configure(afe, dai->id); 1943 if (ret) 1944 return ret; 1945 1946 ret = mtk_dai_etdm_configure(afe, rate, channels, 1947 bit_width, dai->id); 1948 if (ret) 1949 return ret; 1950 } 1951 1952 return 0; 1953 } 1954 1955 static int mtk_dai_etdm_prepare(struct snd_pcm_substream *substream, 1956 struct snd_soc_dai *dai) 1957 { 1958 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1959 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1960 struct mtk_dai_etdm_priv *mst_etdm_data; 1961 int mst_dai_id; 1962 int slv_dai_id; 1963 int ret; 1964 int i; 1965 1966 if (!is_valid_etdm_dai(dai->id)) 1967 return -EINVAL; 1968 mst_etdm_data = afe_priv->dai_priv[dai->id]; 1969 1970 dev_dbg(afe->dev, "%s(), dai id %d, prepared %d\n", __func__, dai->id, 1971 mst_etdm_data->is_prepared); 1972 1973 if (mst_etdm_data->is_prepared) 1974 return 0; 1975 1976 mst_etdm_data->is_prepared = true; 1977 1978 if (is_cowork_mode(dai)) { 1979 mst_dai_id = get_etdm_cowork_master_id(dai); 1980 if (!is_valid_etdm_dai(mst_dai_id)) 1981 return -EINVAL; 1982 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1983 1984 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1985 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1986 ret = mt8188_afe_enable_etdm(afe, slv_dai_id); 1987 if (ret) { 1988 dev_dbg(afe->dev, "%s enable %d failed\n", 1989 __func__, slv_dai_id); 1990 1991 return ret; 1992 } 1993 } 1994 1995 ret = mt8188_afe_enable_etdm(afe, mst_dai_id); 1996 if (ret) { 1997 dev_dbg(afe->dev, "%s enable %d failed\n", 1998 __func__, mst_dai_id); 1999 2000 return ret; 2001 } 2002 } else { 2003 ret = mt8188_afe_enable_etdm(afe, dai->id); 2004 if (ret) { 2005 dev_dbg(afe->dev, "%s enable %d failed\n", 2006 __func__, dai->id); 2007 2008 return ret; 2009 } 2010 } 2011 2012 return 0; 2013 } 2014 2015 static int mtk_dai_etdm_cal_mclk(struct mtk_base_afe *afe, int freq, int dai_id) 2016 { 2017 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2018 struct mtk_dai_etdm_priv *etdm_data; 2019 int apll_rate; 2020 int apll; 2021 2022 if (!is_valid_etdm_dai(dai_id)) 2023 return -EINVAL; 2024 etdm_data = afe_priv->dai_priv[dai_id]; 2025 2026 if (freq == 0) { 2027 etdm_data->mclk_freq = freq; 2028 return 0; 2029 } 2030 2031 if (etdm_data->mclk_fixed_apll == 0) 2032 apll = mt8188_afe_get_default_mclk_source_by_rate(freq); 2033 else 2034 apll = etdm_data->mclk_apll; 2035 2036 apll_rate = mt8188_afe_get_mclk_source_rate(afe, apll); 2037 2038 if (freq > apll_rate) { 2039 dev_err(afe->dev, "freq %d > apll rate %d\n", freq, apll_rate); 2040 return -EINVAL; 2041 } 2042 2043 if (apll_rate % freq != 0) { 2044 dev_err(afe->dev, "APLL%d cannot generate freq Hz\n", apll); 2045 return -EINVAL; 2046 } 2047 2048 if (etdm_data->mclk_fixed_apll == 0) 2049 etdm_data->mclk_apll = apll; 2050 etdm_data->mclk_freq = freq; 2051 2052 return 0; 2053 } 2054 2055 static int mtk_dai_etdm_set_sysclk(struct snd_soc_dai *dai, 2056 int clk_id, unsigned int freq, int dir) 2057 { 2058 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2059 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2060 struct mtk_dai_etdm_priv *etdm_data; 2061 int dai_id; 2062 2063 dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n", 2064 __func__, dai->id, freq, dir); 2065 if (is_cowork_mode(dai)) 2066 dai_id = get_etdm_cowork_master_id(dai); 2067 else 2068 dai_id = dai->id; 2069 2070 if (!is_valid_etdm_dai(dai_id)) 2071 return -EINVAL; 2072 etdm_data = afe_priv->dai_priv[dai_id]; 2073 etdm_data->mclk_dir = dir; 2074 return mtk_dai_etdm_cal_mclk(afe, freq, dai_id); 2075 } 2076 2077 static int mtk_dai_etdm_set_tdm_slot(struct snd_soc_dai *dai, 2078 unsigned int tx_mask, unsigned int rx_mask, 2079 int slots, int slot_width) 2080 { 2081 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2082 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2083 struct mtk_dai_etdm_priv *etdm_data; 2084 2085 if (!is_valid_etdm_dai(dai->id)) 2086 return -EINVAL; 2087 etdm_data = afe_priv->dai_priv[dai->id]; 2088 2089 dev_dbg(dai->dev, "%s id %d slot_width %d\n", 2090 __func__, dai->id, slot_width); 2091 2092 etdm_data->slots = slots; 2093 etdm_data->lrck_width = slot_width; 2094 return 0; 2095 } 2096 2097 static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2098 { 2099 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2100 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2101 struct mtk_dai_etdm_priv *etdm_data; 2102 2103 if (!is_valid_etdm_dai(dai->id)) 2104 return -EINVAL; 2105 etdm_data = afe_priv->dai_priv[dai->id]; 2106 2107 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2108 case SND_SOC_DAIFMT_I2S: 2109 etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S; 2110 break; 2111 case SND_SOC_DAIFMT_LEFT_J: 2112 etdm_data->format = MTK_DAI_ETDM_FORMAT_LJ; 2113 break; 2114 case SND_SOC_DAIFMT_RIGHT_J: 2115 etdm_data->format = MTK_DAI_ETDM_FORMAT_RJ; 2116 break; 2117 case SND_SOC_DAIFMT_DSP_A: 2118 etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA; 2119 break; 2120 case SND_SOC_DAIFMT_DSP_B: 2121 etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB; 2122 break; 2123 default: 2124 return -EINVAL; 2125 } 2126 2127 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2128 case SND_SOC_DAIFMT_NB_NF: 2129 etdm_data->bck_inv = false; 2130 etdm_data->lrck_inv = false; 2131 break; 2132 case SND_SOC_DAIFMT_NB_IF: 2133 etdm_data->bck_inv = false; 2134 etdm_data->lrck_inv = true; 2135 break; 2136 case SND_SOC_DAIFMT_IB_NF: 2137 etdm_data->bck_inv = true; 2138 etdm_data->lrck_inv = false; 2139 break; 2140 case SND_SOC_DAIFMT_IB_IF: 2141 etdm_data->bck_inv = true; 2142 etdm_data->lrck_inv = true; 2143 break; 2144 default: 2145 return -EINVAL; 2146 } 2147 2148 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 2149 case SND_SOC_DAIFMT_BC_FC: 2150 etdm_data->slave_mode = true; 2151 break; 2152 case SND_SOC_DAIFMT_BP_FP: 2153 etdm_data->slave_mode = false; 2154 break; 2155 default: 2156 return -EINVAL; 2157 } 2158 2159 return 0; 2160 } 2161 2162 static int mtk_dai_hdmitx_dptx_startup(struct snd_pcm_substream *substream, 2163 struct snd_soc_dai *dai) 2164 { 2165 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2166 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2167 int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 2168 2169 if (cg_id >= 0) 2170 mt8188_afe_enable_clk(afe, afe_priv->clk[cg_id]); 2171 2172 mtk_dai_etdm_enable_mclk(afe, dai->id); 2173 2174 return 0; 2175 } 2176 2177 static void mtk_dai_hdmitx_dptx_shutdown(struct snd_pcm_substream *substream, 2178 struct snd_soc_dai *dai) 2179 { 2180 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2181 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2182 int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 2183 struct mtk_dai_etdm_priv *etdm_data; 2184 int ret; 2185 2186 if (!is_valid_etdm_dai(dai->id)) 2187 return; 2188 etdm_data = afe_priv->dai_priv[dai->id]; 2189 2190 if (etdm_data->is_prepared) { 2191 etdm_data->is_prepared = false; 2192 /* disable etdm_out3 */ 2193 ret = mt8188_afe_disable_etdm(afe, dai->id); 2194 if (ret) 2195 dev_dbg(afe->dev, "%s disable failed\n", __func__); 2196 2197 /* disable dptx interface */ 2198 if (dai->id == MT8188_AFE_IO_DPTX) 2199 regmap_clear_bits(afe->regmap, AFE_DPTX_CON, 2200 AFE_DPTX_CON_ON); 2201 } 2202 2203 mtk_dai_etdm_disable_mclk(afe, dai->id); 2204 2205 if (cg_id >= 0) 2206 mt8188_afe_disable_clk(afe, afe_priv->clk[cg_id]); 2207 } 2208 2209 static unsigned int mtk_dai_get_dptx_ch_en(unsigned int channel) 2210 { 2211 switch (channel) { 2212 case 1 ... 2: 2213 return AFE_DPTX_CON_CH_EN_2CH; 2214 case 3 ... 4: 2215 return AFE_DPTX_CON_CH_EN_4CH; 2216 case 5 ... 6: 2217 return AFE_DPTX_CON_CH_EN_6CH; 2218 case 7 ... 8: 2219 return AFE_DPTX_CON_CH_EN_8CH; 2220 default: 2221 return AFE_DPTX_CON_CH_EN_2CH; 2222 } 2223 } 2224 2225 static unsigned int mtk_dai_get_dptx_ch(unsigned int ch) 2226 { 2227 return (ch > 2) ? 2228 AFE_DPTX_CON_CH_NUM_8CH : AFE_DPTX_CON_CH_NUM_2CH; 2229 } 2230 2231 static unsigned int mtk_dai_get_dptx_wlen(snd_pcm_format_t format) 2232 { 2233 return snd_pcm_format_physical_width(format) <= 16 ? 2234 AFE_DPTX_CON_16BIT : AFE_DPTX_CON_24BIT; 2235 } 2236 2237 static int mtk_dai_hdmitx_dptx_hw_params(struct snd_pcm_substream *substream, 2238 struct snd_pcm_hw_params *params, 2239 struct snd_soc_dai *dai) 2240 { 2241 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2242 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2243 struct mtk_dai_etdm_priv *etdm_data; 2244 unsigned int rate = params_rate(params); 2245 unsigned int channels = params_channels(params); 2246 snd_pcm_format_t format = params_format(params); 2247 int width = snd_pcm_format_physical_width(format); 2248 int ret; 2249 2250 if (!is_valid_etdm_dai(dai->id)) 2251 return -EINVAL; 2252 etdm_data = afe_priv->dai_priv[dai->id]; 2253 2254 /* dptx configure */ 2255 if (dai->id == MT8188_AFE_IO_DPTX) { 2256 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2257 AFE_DPTX_CON_CH_EN_MASK, 2258 mtk_dai_get_dptx_ch_en(channels)); 2259 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2260 AFE_DPTX_CON_CH_NUM_MASK, 2261 mtk_dai_get_dptx_ch(channels)); 2262 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2263 AFE_DPTX_CON_16BIT_MASK, 2264 mtk_dai_get_dptx_wlen(format)); 2265 2266 if (mtk_dai_get_dptx_ch(channels) == AFE_DPTX_CON_CH_NUM_8CH) { 2267 etdm_data->data_mode = MTK_DAI_ETDM_DATA_ONE_PIN; 2268 channels = 8; 2269 } else { 2270 channels = 2; 2271 } 2272 } else { 2273 etdm_data->data_mode = MTK_DAI_ETDM_DATA_MULTI_PIN; 2274 } 2275 2276 ret = mtk_dai_etdm_mclk_configure(afe, dai->id); 2277 if (ret) 2278 return ret; 2279 2280 ret = mtk_dai_etdm_configure(afe, rate, channels, width, dai->id); 2281 2282 return ret; 2283 } 2284 2285 static int mtk_dai_hdmitx_dptx_prepare(struct snd_pcm_substream *substream, 2286 struct snd_soc_dai *dai) 2287 { 2288 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2289 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2290 struct mtk_dai_etdm_priv *etdm_data; 2291 2292 if (!is_valid_etdm_dai(dai->id)) 2293 return -EINVAL; 2294 etdm_data = afe_priv->dai_priv[dai->id]; 2295 2296 dev_dbg(afe->dev, "%s(), dai id %d, prepared %d\n", __func__, dai->id, 2297 etdm_data->is_prepared); 2298 2299 if (etdm_data->is_prepared) 2300 return 0; 2301 2302 etdm_data->is_prepared = true; 2303 2304 /* enable dptx interface */ 2305 if (dai->id == MT8188_AFE_IO_DPTX) 2306 regmap_set_bits(afe->regmap, AFE_DPTX_CON, AFE_DPTX_CON_ON); 2307 2308 /* enable etdm_out3 */ 2309 return mt8188_afe_enable_etdm(afe, dai->id); 2310 } 2311 2312 static int mtk_dai_hdmitx_dptx_set_sysclk(struct snd_soc_dai *dai, 2313 int clk_id, 2314 unsigned int freq, 2315 int dir) 2316 { 2317 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2318 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2319 struct mtk_dai_etdm_priv *etdm_data; 2320 2321 if (!is_valid_etdm_dai(dai->id)) 2322 return -EINVAL; 2323 etdm_data = afe_priv->dai_priv[dai->id]; 2324 2325 dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n", 2326 __func__, dai->id, freq, dir); 2327 2328 etdm_data->mclk_dir = dir; 2329 return mtk_dai_etdm_cal_mclk(afe, freq, dai->id); 2330 } 2331 2332 static const struct snd_soc_dai_ops mtk_dai_etdm_ops = { 2333 .startup = mtk_dai_etdm_startup, 2334 .shutdown = mtk_dai_etdm_shutdown, 2335 .hw_params = mtk_dai_etdm_hw_params, 2336 .prepare = mtk_dai_etdm_prepare, 2337 .set_sysclk = mtk_dai_etdm_set_sysclk, 2338 .set_fmt = mtk_dai_etdm_set_fmt, 2339 .set_tdm_slot = mtk_dai_etdm_set_tdm_slot, 2340 }; 2341 2342 static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops = { 2343 .startup = mtk_dai_hdmitx_dptx_startup, 2344 .shutdown = mtk_dai_hdmitx_dptx_shutdown, 2345 .hw_params = mtk_dai_hdmitx_dptx_hw_params, 2346 .prepare = mtk_dai_hdmitx_dptx_prepare, 2347 .set_sysclk = mtk_dai_hdmitx_dptx_set_sysclk, 2348 .set_fmt = mtk_dai_etdm_set_fmt, 2349 }; 2350 2351 /* dai driver */ 2352 #define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_192000) 2353 2354 #define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 2355 SNDRV_PCM_FMTBIT_S24_LE |\ 2356 SNDRV_PCM_FMTBIT_S32_LE) 2357 2358 static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = { 2359 { 2360 .name = "DPTX", 2361 .id = MT8188_AFE_IO_DPTX, 2362 .playback = { 2363 .stream_name = "DPTX", 2364 .channels_min = 1, 2365 .channels_max = 8, 2366 .rates = MTK_ETDM_RATES, 2367 .formats = MTK_ETDM_FORMATS, 2368 }, 2369 .ops = &mtk_dai_hdmitx_dptx_ops, 2370 }, 2371 { 2372 .name = "ETDM1_IN", 2373 .id = MT8188_AFE_IO_ETDM1_IN, 2374 .capture = { 2375 .stream_name = "ETDM1_IN", 2376 .channels_min = 1, 2377 .channels_max = 16, 2378 .rates = MTK_ETDM_RATES, 2379 .formats = MTK_ETDM_FORMATS, 2380 }, 2381 .ops = &mtk_dai_etdm_ops, 2382 }, 2383 { 2384 .name = "ETDM2_IN", 2385 .id = MT8188_AFE_IO_ETDM2_IN, 2386 .capture = { 2387 .stream_name = "ETDM2_IN", 2388 .channels_min = 1, 2389 .channels_max = 16, 2390 .rates = MTK_ETDM_RATES, 2391 .formats = MTK_ETDM_FORMATS, 2392 }, 2393 .ops = &mtk_dai_etdm_ops, 2394 }, 2395 { 2396 .name = "ETDM1_OUT", 2397 .id = MT8188_AFE_IO_ETDM1_OUT, 2398 .playback = { 2399 .stream_name = "ETDM1_OUT", 2400 .channels_min = 1, 2401 .channels_max = 16, 2402 .rates = MTK_ETDM_RATES, 2403 .formats = MTK_ETDM_FORMATS, 2404 }, 2405 .ops = &mtk_dai_etdm_ops, 2406 }, 2407 { 2408 .name = "ETDM2_OUT", 2409 .id = MT8188_AFE_IO_ETDM2_OUT, 2410 .playback = { 2411 .stream_name = "ETDM2_OUT", 2412 .channels_min = 1, 2413 .channels_max = 16, 2414 .rates = MTK_ETDM_RATES, 2415 .formats = MTK_ETDM_FORMATS, 2416 }, 2417 .ops = &mtk_dai_etdm_ops, 2418 }, 2419 { 2420 .name = "ETDM3_OUT", 2421 .id = MT8188_AFE_IO_ETDM3_OUT, 2422 .playback = { 2423 .stream_name = "ETDM3_OUT", 2424 .channels_min = 1, 2425 .channels_max = 8, 2426 .rates = MTK_ETDM_RATES, 2427 .formats = MTK_ETDM_FORMATS, 2428 }, 2429 .ops = &mtk_dai_hdmitx_dptx_ops, 2430 }, 2431 }; 2432 2433 static void mt8188_etdm_update_sync_info(struct mtk_base_afe *afe) 2434 { 2435 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2436 struct mtk_dai_etdm_priv *etdm_data; 2437 struct mtk_dai_etdm_priv *mst_data; 2438 int mst_dai_id; 2439 int i; 2440 2441 for (i = MT8188_AFE_IO_ETDM_START; i < MT8188_AFE_IO_ETDM_END; i++) { 2442 etdm_data = afe_priv->dai_priv[i]; 2443 if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) { 2444 mst_dai_id = etdm_data->cowork_source_id; 2445 mst_data = afe_priv->dai_priv[mst_dai_id]; 2446 if (mst_data->cowork_source_id != COWORK_ETDM_NONE) 2447 dev_err(afe->dev, "%s [%d] wrong sync source\n", 2448 __func__, i); 2449 mst_data->cowork_slv_id[mst_data->cowork_slv_count] = i; 2450 mst_data->cowork_slv_count++; 2451 } 2452 } 2453 } 2454 2455 static void mt8188_dai_etdm_parse_of(struct mtk_base_afe *afe) 2456 { 2457 const struct device_node *of_node = afe->dev->of_node; 2458 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2459 struct mtk_dai_etdm_priv *etdm_data; 2460 char prop[48]; 2461 u8 disable_chn[MT8188_ETDM_MAX_CHANNELS]; 2462 int max_chn = MT8188_ETDM_MAX_CHANNELS; 2463 unsigned int sync_id; 2464 u32 sel; 2465 int ret; 2466 int dai_id; 2467 int i, j; 2468 struct { 2469 const char *name; 2470 const unsigned int sync_id; 2471 } of_afe_etdms[MT8188_AFE_IO_ETDM_NUM] = { 2472 {"etdm-in1", ETDM_SYNC_FROM_IN1}, 2473 {"etdm-in2", ETDM_SYNC_FROM_IN2}, 2474 {"etdm-out1", ETDM_SYNC_FROM_OUT1}, 2475 {"etdm-out2", ETDM_SYNC_FROM_OUT2}, 2476 {"etdm-out3", ETDM_SYNC_FROM_OUT3}, 2477 }; 2478 2479 for (i = 0; i < MT8188_AFE_IO_ETDM_NUM; i++) { 2480 dai_id = ETDM_TO_DAI_ID(i); 2481 etdm_data = afe_priv->dai_priv[dai_id]; 2482 2483 snprintf(prop, sizeof(prop), "mediatek,%s-multi-pin-mode", 2484 of_afe_etdms[i].name); 2485 2486 etdm_data->data_mode = of_property_read_bool(of_node, prop); 2487 2488 snprintf(prop, sizeof(prop), "mediatek,%s-cowork-source", 2489 of_afe_etdms[i].name); 2490 2491 ret = of_property_read_u32(of_node, prop, &sel); 2492 if (ret == 0) { 2493 if (sel >= MT8188_AFE_IO_ETDM_NUM) { 2494 dev_err(afe->dev, "%s invalid id=%d\n", 2495 __func__, sel); 2496 etdm_data->cowork_source_id = COWORK_ETDM_NONE; 2497 } else { 2498 sync_id = of_afe_etdms[sel].sync_id; 2499 etdm_data->cowork_source_id = 2500 sync_to_dai_id(sync_id); 2501 } 2502 } else { 2503 etdm_data->cowork_source_id = COWORK_ETDM_NONE; 2504 } 2505 } 2506 2507 /* etdm in only */ 2508 for (i = 0; i < 2; i++) { 2509 snprintf(prop, sizeof(prop), "mediatek,%s-chn-disabled", 2510 of_afe_etdms[i].name); 2511 2512 ret = of_property_read_variable_u8_array(of_node, prop, 2513 disable_chn, 2514 1, max_chn); 2515 if (ret < 0) 2516 continue; 2517 2518 for (j = 0; j < ret; j++) { 2519 if (disable_chn[j] >= MT8188_ETDM_MAX_CHANNELS) 2520 dev_err(afe->dev, "%s [%d] invalid chn %u\n", 2521 __func__, j, disable_chn[j]); 2522 else 2523 etdm_data->in_disable_ch[disable_chn[j]] = true; 2524 } 2525 } 2526 mt8188_etdm_update_sync_info(afe); 2527 } 2528 2529 static int init_etdm_priv_data(struct mtk_base_afe *afe) 2530 { 2531 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2532 struct mtk_dai_etdm_priv *etdm_priv; 2533 int i; 2534 2535 for (i = MT8188_AFE_IO_ETDM_START; i < MT8188_AFE_IO_ETDM_END; i++) { 2536 etdm_priv = devm_kzalloc(afe->dev, 2537 sizeof(struct mtk_dai_etdm_priv), 2538 GFP_KERNEL); 2539 if (!etdm_priv) 2540 return -ENOMEM; 2541 2542 afe_priv->dai_priv[i] = etdm_priv; 2543 } 2544 2545 afe_priv->dai_priv[MT8188_AFE_IO_DPTX] = 2546 afe_priv->dai_priv[MT8188_AFE_IO_ETDM3_OUT]; 2547 2548 mt8188_dai_etdm_parse_of(afe); 2549 return 0; 2550 } 2551 2552 int mt8188_dai_etdm_register(struct mtk_base_afe *afe) 2553 { 2554 struct mtk_base_afe_dai *dai; 2555 2556 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 2557 if (!dai) 2558 return -ENOMEM; 2559 2560 list_add(&dai->list, &afe->sub_dais); 2561 2562 dai->dai_drivers = mtk_dai_etdm_driver; 2563 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver); 2564 2565 dai->dapm_widgets = mtk_dai_etdm_widgets; 2566 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets); 2567 dai->dapm_routes = mtk_dai_etdm_routes; 2568 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes); 2569 dai->controls = mtk_dai_etdm_controls; 2570 dai->num_controls = ARRAY_SIZE(mtk_dai_etdm_controls); 2571 2572 return init_etdm_priv_data(afe); 2573 } 2574