1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek ALSA SoC Audio DAI ADDA Control 4 * 5 * Copyright (c) 2022 MediaTek Inc. 6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 * Trevor Wu <trevor.wu@mediatek.com> 8 * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/delay.h> 13 #include <linux/regmap.h> 14 #include "mt8188-afe-clk.h" 15 #include "mt8188-afe-common.h" 16 #include "mt8188-reg.h" 17 18 #define ADDA_HIRES_THRES 48000 19 20 enum { 21 SUPPLY_SEQ_CLOCK_SEL, 22 SUPPLY_SEQ_ADDA_DL_ON, 23 SUPPLY_SEQ_ADDA_MTKAIF_CFG, 24 SUPPLY_SEQ_ADDA_UL_ON, 25 SUPPLY_SEQ_ADDA_AFE_ON, 26 }; 27 28 enum { 29 MTK_AFE_ADDA_DL_RATE_8K = 0, 30 MTK_AFE_ADDA_DL_RATE_11K = 1, 31 MTK_AFE_ADDA_DL_RATE_12K = 2, 32 MTK_AFE_ADDA_DL_RATE_16K = 3, 33 MTK_AFE_ADDA_DL_RATE_22K = 4, 34 MTK_AFE_ADDA_DL_RATE_24K = 5, 35 MTK_AFE_ADDA_DL_RATE_32K = 6, 36 MTK_AFE_ADDA_DL_RATE_44K = 7, 37 MTK_AFE_ADDA_DL_RATE_48K = 8, 38 MTK_AFE_ADDA_DL_RATE_96K = 9, 39 MTK_AFE_ADDA_DL_RATE_192K = 10, 40 }; 41 42 enum { 43 MTK_AFE_ADDA_UL_RATE_8K = 0, 44 MTK_AFE_ADDA_UL_RATE_16K = 1, 45 MTK_AFE_ADDA_UL_RATE_32K = 2, 46 MTK_AFE_ADDA_UL_RATE_48K = 3, 47 MTK_AFE_ADDA_UL_RATE_96K = 4, 48 MTK_AFE_ADDA_UL_RATE_192K = 5, 49 }; 50 51 enum { 52 DELAY_DATA_MISO1 = 0, 53 DELAY_DATA_MISO0 = 1, 54 }; 55 56 struct mtk_dai_adda_priv { 57 unsigned int dl_rate; 58 unsigned int ul_rate; 59 }; 60 61 static unsigned int afe_adda_dl_rate_transform(struct mtk_base_afe *afe, 62 unsigned int rate) 63 { 64 switch (rate) { 65 case 8000: 66 return MTK_AFE_ADDA_DL_RATE_8K; 67 case 11025: 68 return MTK_AFE_ADDA_DL_RATE_11K; 69 case 12000: 70 return MTK_AFE_ADDA_DL_RATE_12K; 71 case 16000: 72 return MTK_AFE_ADDA_DL_RATE_16K; 73 case 22050: 74 return MTK_AFE_ADDA_DL_RATE_22K; 75 case 24000: 76 return MTK_AFE_ADDA_DL_RATE_24K; 77 case 32000: 78 return MTK_AFE_ADDA_DL_RATE_32K; 79 case 44100: 80 return MTK_AFE_ADDA_DL_RATE_44K; 81 case 48000: 82 return MTK_AFE_ADDA_DL_RATE_48K; 83 case 96000: 84 return MTK_AFE_ADDA_DL_RATE_96K; 85 case 192000: 86 return MTK_AFE_ADDA_DL_RATE_192K; 87 default: 88 dev_info(afe->dev, "%s(), rate %u invalid, use 48kHz!!!\n", 89 __func__, rate); 90 return MTK_AFE_ADDA_DL_RATE_48K; 91 } 92 } 93 94 static unsigned int afe_adda_ul_rate_transform(struct mtk_base_afe *afe, 95 unsigned int rate) 96 { 97 switch (rate) { 98 case 8000: 99 return MTK_AFE_ADDA_UL_RATE_8K; 100 case 16000: 101 return MTK_AFE_ADDA_UL_RATE_16K; 102 case 32000: 103 return MTK_AFE_ADDA_UL_RATE_32K; 104 case 48000: 105 return MTK_AFE_ADDA_UL_RATE_48K; 106 case 96000: 107 return MTK_AFE_ADDA_UL_RATE_96K; 108 case 192000: 109 return MTK_AFE_ADDA_UL_RATE_192K; 110 default: 111 dev_info(afe->dev, "%s(), rate %u invalid, use 48kHz!!!\n", 112 __func__, rate); 113 return MTK_AFE_ADDA_UL_RATE_48K; 114 } 115 } 116 117 static int mt8188_adda_mtkaif_init(struct mtk_base_afe *afe) 118 { 119 struct mt8188_afe_private *afe_priv = afe->platform_priv; 120 struct mtkaif_param *param = &afe_priv->mtkaif_params; 121 int delay_data; 122 int delay_cycle; 123 unsigned int mask = 0; 124 unsigned int val = 0; 125 126 /* set rx protocol 2 & mtkaif_rxif_clkinv_adc inverse */ 127 regmap_set_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 128 MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2); 129 130 regmap_set_bits(afe->regmap, AFE_AUD_PAD_TOP, RG_RX_PROTOCOL2); 131 132 if (!param->mtkaif_calibration_ok) { 133 dev_info(afe->dev, "%s(), calibration fail\n", __func__); 134 return 0; 135 } 136 137 /* set delay for ch1, ch2 */ 138 if (param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0] >= 139 param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1]) { 140 delay_data = DELAY_DATA_MISO1; 141 delay_cycle = 142 param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0] - 143 param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1]; 144 } else { 145 delay_data = DELAY_DATA_MISO0; 146 delay_cycle = 147 param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1] - 148 param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0]; 149 } 150 151 val = 0; 152 mask = (MTKAIF_RXIF_DELAY_DATA | MTKAIF_RXIF_DELAY_CYCLE_MASK); 153 val |= FIELD_PREP(MTKAIF_RXIF_DELAY_CYCLE_MASK, delay_cycle); 154 val |= FIELD_PREP(MTKAIF_RXIF_DELAY_DATA, delay_data); 155 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG2, mask, val); 156 157 return 0; 158 } 159 160 static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w, 161 struct snd_kcontrol *kcontrol, 162 int event) 163 { 164 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 165 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 166 167 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 168 __func__, w->name, event); 169 170 switch (event) { 171 case SND_SOC_DAPM_PRE_PMU: 172 mt8188_adda_mtkaif_init(afe); 173 break; 174 default: 175 break; 176 } 177 178 return 0; 179 } 180 181 static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w, 182 struct snd_kcontrol *kcontrol, 183 int event) 184 { 185 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 186 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 187 188 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 189 __func__, w->name, event); 190 191 switch (event) { 192 case SND_SOC_DAPM_POST_PMD: 193 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 194 usleep_range(125, 135); 195 break; 196 default: 197 break; 198 } 199 200 return 0; 201 } 202 203 static void mtk_adda_ul_mictype(struct mtk_base_afe *afe, bool dmic) 204 { 205 unsigned int reg = AFE_ADDA_UL_SRC_CON0; 206 unsigned int val; 207 208 val = (UL_SDM3_LEVEL_CTL | UL_MODE_3P25M_CH1_CTL | 209 UL_MODE_3P25M_CH2_CTL); 210 211 /* turn on dmic, ch1, ch2 */ 212 if (dmic) 213 regmap_set_bits(afe->regmap, reg, val); 214 else 215 regmap_clear_bits(afe->regmap, reg, val); 216 } 217 218 static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w, 219 struct snd_kcontrol *kcontrol, 220 int event) 221 { 222 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 223 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 224 struct mt8188_afe_private *afe_priv = afe->platform_priv; 225 struct mtkaif_param *param = &afe_priv->mtkaif_params; 226 227 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 228 __func__, w->name, event); 229 230 switch (event) { 231 case SND_SOC_DAPM_PRE_PMU: 232 mtk_adda_ul_mictype(afe, param->mtkaif_dmic_on); 233 break; 234 case SND_SOC_DAPM_POST_PMD: 235 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 236 usleep_range(125, 135); 237 break; 238 default: 239 break; 240 } 241 242 return 0; 243 } 244 245 static int mtk_audio_hires_event(struct snd_soc_dapm_widget *w, 246 struct snd_kcontrol *kcontrol, 247 int event) 248 { 249 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 250 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 251 struct mt8188_afe_private *afe_priv = afe->platform_priv; 252 struct clk *clk = afe_priv->clk[MT8188_CLK_TOP_AUDIO_H_SEL]; 253 struct clk *clk_parent; 254 255 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 256 __func__, w->name, event); 257 258 switch (event) { 259 case SND_SOC_DAPM_PRE_PMU: 260 clk_parent = afe_priv->clk[MT8188_CLK_APMIXED_APLL1]; 261 break; 262 case SND_SOC_DAPM_POST_PMD: 263 clk_parent = afe_priv->clk[MT8188_CLK_XTAL_26M]; 264 break; 265 default: 266 return 0; 267 } 268 mt8188_afe_set_clk_parent(afe, clk, clk_parent); 269 270 return 0; 271 } 272 273 static int mtk_afe_adc_hires_connect(struct snd_soc_dapm_widget *source, 274 struct snd_soc_dapm_widget *sink) 275 { 276 struct snd_soc_dapm_widget *w = source; 277 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 278 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 279 struct mt8188_afe_private *afe_priv = afe->platform_priv; 280 struct mtk_dai_adda_priv *adda_priv; 281 282 adda_priv = afe_priv->dai_priv[MT8188_AFE_IO_ADDA]; 283 284 if (!adda_priv) { 285 dev_err(afe->dev, "%s adda_priv == NULL", __func__); 286 return 0; 287 } 288 289 return !!(adda_priv->ul_rate > ADDA_HIRES_THRES); 290 } 291 292 static int mtk_afe_dac_hires_connect(struct snd_soc_dapm_widget *source, 293 struct snd_soc_dapm_widget *sink) 294 { 295 struct snd_soc_dapm_widget *w = source; 296 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 297 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 298 struct mt8188_afe_private *afe_priv = afe->platform_priv; 299 struct mtk_dai_adda_priv *adda_priv; 300 301 adda_priv = afe_priv->dai_priv[MT8188_AFE_IO_ADDA]; 302 303 if (!adda_priv) { 304 dev_err(afe->dev, "%s adda_priv == NULL", __func__); 305 return 0; 306 } 307 308 return !!(adda_priv->dl_rate > ADDA_HIRES_THRES); 309 } 310 311 static const struct snd_kcontrol_new mtk_dai_adda_o176_mix[] = { 312 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN176, 0, 1, 0), 313 SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN176, 2, 1, 0), 314 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN176, 20, 1, 0), 315 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN176, 22, 1, 0), 316 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN176_2, 6, 1, 0), 317 }; 318 319 static const struct snd_kcontrol_new mtk_dai_adda_o177_mix[] = { 320 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN177, 1, 1, 0), 321 SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN177, 3, 1, 0), 322 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN177, 21, 1, 0), 323 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN177, 23, 1, 0), 324 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN177_2, 7, 1, 0), 325 }; 326 327 static const char * const adda_dlgain_mux_map[] = { 328 "Bypass", "Connect", 329 }; 330 331 static SOC_ENUM_SINGLE_DECL(adda_dlgain_mux_map_enum, 332 SND_SOC_NOPM, 0, 333 adda_dlgain_mux_map); 334 335 static const struct snd_kcontrol_new adda_dlgain_mux_control = 336 SOC_DAPM_ENUM("DL_GAIN_MUX", adda_dlgain_mux_map_enum); 337 338 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = { 339 SND_SOC_DAPM_MIXER("I168", SND_SOC_NOPM, 0, 0, NULL, 0), 340 SND_SOC_DAPM_MIXER("I169", SND_SOC_NOPM, 0, 0, NULL, 0), 341 342 SND_SOC_DAPM_MIXER("O176", SND_SOC_NOPM, 0, 0, 343 mtk_dai_adda_o176_mix, 344 ARRAY_SIZE(mtk_dai_adda_o176_mix)), 345 SND_SOC_DAPM_MIXER("O177", SND_SOC_NOPM, 0, 0, 346 mtk_dai_adda_o177_mix, 347 ARRAY_SIZE(mtk_dai_adda_o177_mix)), 348 349 SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON, 350 AFE_ADDA_UL_DL_CON0, 351 ADDA_AFE_ON_SHIFT, 0, 352 NULL, 353 0), 354 355 SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON, 356 AFE_ADDA_DL_SRC2_CON0, 357 DL_2_SRC_ON_TMP_CTRL_PRE_SHIFT, 0, 358 mtk_adda_dl_event, 359 SND_SOC_DAPM_POST_PMD), 360 361 SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON, 362 AFE_ADDA_UL_SRC_CON0, 363 UL_SRC_ON_TMP_CTL_SHIFT, 0, 364 mtk_adda_ul_event, 365 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 366 367 SND_SOC_DAPM_SUPPLY_S("AUDIO_HIRES", SUPPLY_SEQ_CLOCK_SEL, 368 SND_SOC_NOPM, 369 0, 0, 370 mtk_audio_hires_event, 371 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 372 373 SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG, 374 SND_SOC_NOPM, 375 0, 0, 376 mtk_adda_mtkaif_cfg_event, 377 SND_SOC_DAPM_PRE_PMU), 378 379 SND_SOC_DAPM_MUX("DL_GAIN_MUX", SND_SOC_NOPM, 0, 0, 380 &adda_dlgain_mux_control), 381 382 SND_SOC_DAPM_PGA("DL_GAIN", AFE_ADDA_DL_SRC2_CON0, 383 DL_2_GAIN_ON_CTL_PRE_SHIFT, 0, NULL, 0), 384 385 SND_SOC_DAPM_INPUT("ADDA_INPUT"), 386 SND_SOC_DAPM_OUTPUT("ADDA_OUTPUT"), 387 388 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac"), 389 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc"), 390 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_hires"), 391 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_hires"), 392 }; 393 394 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = { 395 {"ADDA Capture", NULL, "ADDA Enable"}, 396 {"ADDA Capture", NULL, "ADDA Capture Enable"}, 397 {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"}, 398 {"ADDA Capture", NULL, "aud_adc"}, 399 {"ADDA Capture", NULL, "aud_adc_hires", mtk_afe_adc_hires_connect}, 400 {"aud_adc_hires", NULL, "AUDIO_HIRES"}, 401 402 {"I168", NULL, "ADDA Capture"}, 403 {"I169", NULL, "ADDA Capture"}, 404 405 {"ADDA Playback", NULL, "ADDA Enable"}, 406 {"ADDA Playback", NULL, "ADDA Playback Enable"}, 407 {"ADDA Playback", NULL, "aud_dac"}, 408 {"ADDA Playback", NULL, "aud_dac_hires", mtk_afe_dac_hires_connect}, 409 {"aud_dac_hires", NULL, "AUDIO_HIRES"}, 410 411 {"DL_GAIN", NULL, "O176"}, 412 {"DL_GAIN", NULL, "O177"}, 413 414 {"DL_GAIN_MUX", "Bypass", "O176"}, 415 {"DL_GAIN_MUX", "Bypass", "O177"}, 416 {"DL_GAIN_MUX", "Connect", "DL_GAIN"}, 417 418 {"ADDA Playback", NULL, "DL_GAIN_MUX"}, 419 420 {"O176", "I000 Switch", "I000"}, 421 {"O177", "I001 Switch", "I001"}, 422 423 {"O176", "I002 Switch", "I002"}, 424 {"O177", "I003 Switch", "I003"}, 425 426 {"O176", "I020 Switch", "I020"}, 427 {"O177", "I021 Switch", "I021"}, 428 429 {"O176", "I022 Switch", "I022"}, 430 {"O177", "I023 Switch", "I023"}, 431 432 {"O176", "I070 Switch", "I070"}, 433 {"O177", "I071 Switch", "I071"}, 434 435 {"ADDA Capture", NULL, "ADDA_INPUT"}, 436 {"ADDA_OUTPUT", NULL, "ADDA Playback"}, 437 }; 438 439 static int mt8188_adda_dmic_get(struct snd_kcontrol *kcontrol, 440 struct snd_ctl_elem_value *ucontrol) 441 { 442 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 443 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 444 struct mt8188_afe_private *afe_priv = afe->platform_priv; 445 struct mtkaif_param *param = &afe_priv->mtkaif_params; 446 447 ucontrol->value.integer.value[0] = param->mtkaif_dmic_on; 448 return 0; 449 } 450 451 static int mt8188_adda_dmic_set(struct snd_kcontrol *kcontrol, 452 struct snd_ctl_elem_value *ucontrol) 453 { 454 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 455 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 456 struct mt8188_afe_private *afe_priv = afe->platform_priv; 457 struct mtkaif_param *param = &afe_priv->mtkaif_params; 458 int dmic_on; 459 460 dmic_on = !!ucontrol->value.integer.value[0]; 461 462 dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n", 463 __func__, kcontrol->id.name, dmic_on); 464 465 if (param->mtkaif_dmic_on == dmic_on) 466 return 0; 467 468 param->mtkaif_dmic_on = dmic_on; 469 return 1; 470 } 471 472 static const struct snd_kcontrol_new mtk_dai_adda_controls[] = { 473 SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1, 474 DL_2_GAIN_CTL_PRE_SHIFT, 65535, 0), 475 SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0, 476 mt8188_adda_dmic_get, mt8188_adda_dmic_set), 477 }; 478 479 static int mtk_dai_da_configure(struct mtk_base_afe *afe, 480 unsigned int rate, int id) 481 { 482 unsigned int val = 0; 483 unsigned int mask = 0; 484 485 /* set sampling rate */ 486 mask |= DL_2_INPUT_MODE_CTL_MASK; 487 val |= FIELD_PREP(DL_2_INPUT_MODE_CTL_MASK, 488 afe_adda_dl_rate_transform(afe, rate)); 489 490 /* turn off saturation */ 491 mask |= DL_2_CH1_SATURATION_EN_CTL; 492 mask |= DL_2_CH2_SATURATION_EN_CTL; 493 494 /* turn off mute function */ 495 mask |= DL_2_MUTE_CH1_OFF_CTL_PRE; 496 mask |= DL_2_MUTE_CH2_OFF_CTL_PRE; 497 val |= DL_2_MUTE_CH1_OFF_CTL_PRE; 498 val |= DL_2_MUTE_CH2_OFF_CTL_PRE; 499 500 /* set voice input data if input sample rate is 8k or 16k */ 501 mask |= DL_2_VOICE_MODE_CTL_PRE; 502 if (rate == 8000 || rate == 16000) 503 val |= DL_2_VOICE_MODE_CTL_PRE; 504 505 regmap_update_bits(afe->regmap, AFE_ADDA_DL_SRC2_CON0, mask, val); 506 507 /* new 2nd sdm */ 508 regmap_set_bits(afe->regmap, AFE_ADDA_DL_SDM_DCCOMP_CON, 509 DL_USE_NEW_2ND_SDM); 510 511 return 0; 512 } 513 514 static int mtk_dai_ad_configure(struct mtk_base_afe *afe, 515 unsigned int rate, int id) 516 { 517 unsigned int val; 518 unsigned int mask; 519 520 mask = UL_VOICE_MODE_CTL_MASK; 521 val = FIELD_PREP(UL_VOICE_MODE_CTL_MASK, 522 afe_adda_ul_rate_transform(afe, rate)); 523 524 regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0, 525 mask, val); 526 return 0; 527 } 528 529 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream, 530 struct snd_pcm_hw_params *params, 531 struct snd_soc_dai *dai) 532 { 533 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 534 struct mt8188_afe_private *afe_priv = afe->platform_priv; 535 struct mtk_dai_adda_priv *adda_priv = afe_priv->dai_priv[dai->id]; 536 unsigned int rate = params_rate(params); 537 int id = dai->id; 538 int ret = 0; 539 540 dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %u\n", 541 __func__, id, substream->stream, rate); 542 543 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 544 adda_priv->dl_rate = rate; 545 ret = mtk_dai_da_configure(afe, rate, id); 546 } else { 547 adda_priv->ul_rate = rate; 548 ret = mtk_dai_ad_configure(afe, rate, id); 549 } 550 551 return ret; 552 } 553 554 static const struct snd_soc_dai_ops mtk_dai_adda_ops = { 555 .hw_params = mtk_dai_adda_hw_params, 556 }; 557 558 /* dai driver */ 559 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\ 560 SNDRV_PCM_RATE_96000 |\ 561 SNDRV_PCM_RATE_192000) 562 563 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 564 SNDRV_PCM_RATE_16000 |\ 565 SNDRV_PCM_RATE_32000 |\ 566 SNDRV_PCM_RATE_48000 |\ 567 SNDRV_PCM_RATE_96000 |\ 568 SNDRV_PCM_RATE_192000) 569 570 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 571 SNDRV_PCM_FMTBIT_S24_LE |\ 572 SNDRV_PCM_FMTBIT_S32_LE) 573 574 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = { 575 { 576 .name = "ADDA", 577 .id = MT8188_AFE_IO_ADDA, 578 .playback = { 579 .stream_name = "ADDA Playback", 580 .channels_min = 1, 581 .channels_max = 2, 582 .rates = MTK_ADDA_PLAYBACK_RATES, 583 .formats = MTK_ADDA_FORMATS, 584 }, 585 .capture = { 586 .stream_name = "ADDA Capture", 587 .channels_min = 1, 588 .channels_max = 2, 589 .rates = MTK_ADDA_CAPTURE_RATES, 590 .formats = MTK_ADDA_FORMATS, 591 }, 592 .ops = &mtk_dai_adda_ops, 593 }, 594 }; 595 596 static int init_adda_priv_data(struct mtk_base_afe *afe) 597 { 598 struct mt8188_afe_private *afe_priv = afe->platform_priv; 599 struct mtk_dai_adda_priv *adda_priv; 600 601 adda_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_adda_priv), 602 GFP_KERNEL); 603 if (!adda_priv) 604 return -ENOMEM; 605 606 afe_priv->dai_priv[MT8188_AFE_IO_ADDA] = adda_priv; 607 608 return 0; 609 } 610 611 int mt8188_dai_adda_register(struct mtk_base_afe *afe) 612 { 613 struct mtk_base_afe_dai *dai; 614 615 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 616 if (!dai) 617 return -ENOMEM; 618 619 list_add(&dai->list, &afe->sub_dais); 620 621 dai->dai_drivers = mtk_dai_adda_driver; 622 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver); 623 624 dai->dapm_widgets = mtk_dai_adda_widgets; 625 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets); 626 dai->dapm_routes = mtk_dai_adda_routes; 627 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes); 628 dai->controls = mtk_dai_adda_controls; 629 dai->num_controls = ARRAY_SIZE(mtk_dai_adda_controls); 630 631 return init_adda_priv_data(afe); 632 } 633