1*fdd4e1a2STrevor Wu /* SPDX-License-Identifier: GPL-2.0 */
2*fdd4e1a2STrevor Wu /*
3*fdd4e1a2STrevor Wu  * mt8188-audsys-clk.h  --  MediaTek 8188 audsys clock definition
4*fdd4e1a2STrevor Wu  *
5*fdd4e1a2STrevor Wu  * Copyright (c) 2022 MediaTek Inc.
6*fdd4e1a2STrevor Wu  * Author: Chun-Chia Chiu <chun-chia.chiu@mediatek.com>
7*fdd4e1a2STrevor Wu  */
8*fdd4e1a2STrevor Wu 
9*fdd4e1a2STrevor Wu #ifndef _MT8188_AUDSYS_CLK_H_
10*fdd4e1a2STrevor Wu #define _MT8188_AUDSYS_CLK_H_
11*fdd4e1a2STrevor Wu 
12*fdd4e1a2STrevor Wu int mt8188_audsys_clk_register(struct mtk_base_afe *afe);
13*fdd4e1a2STrevor Wu 
14*fdd4e1a2STrevor Wu #endif
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