1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek ALSA SoC AFE platform driver for 8188 4 * 5 * Copyright (c) 2022 MediaTek Inc. 6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 * Trevor Wu <trevor.wu@mediatek.com> 8 * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 */ 10 11 #include <linux/arm-smccc.h> 12 #include <linux/delay.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/module.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_platform.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/reset.h> 21 #include <sound/pcm_params.h> 22 #include "mt8188-afe-common.h" 23 #include "mt8188-afe-clk.h" 24 #include "mt8188-reg.h" 25 #include "../common/mtk-afe-platform-driver.h" 26 #include "../common/mtk-afe-fe-dai.h" 27 28 #define MT8188_MEMIF_BUFFER_BYTES_ALIGN (0x40) 29 #define MT8188_MEMIF_DL7_MAX_PERIOD_SIZE (0x3fff) 30 31 #define MEMIF_AXI_MINLEN 9 /* register default value */ 32 33 struct mtk_dai_memif_priv { 34 unsigned int asys_timing_sel; 35 unsigned int fs_timing; 36 }; 37 38 static const struct snd_pcm_hardware mt8188_afe_hardware = { 39 .info = SNDRV_PCM_INFO_MMAP | 40 SNDRV_PCM_INFO_INTERLEAVED | 41 SNDRV_PCM_INFO_MMAP_VALID, 42 .formats = SNDRV_PCM_FMTBIT_S16_LE | 43 SNDRV_PCM_FMTBIT_S24_LE | 44 SNDRV_PCM_FMTBIT_S32_LE, 45 .period_bytes_min = 64, 46 .period_bytes_max = 256 * 1024, 47 .periods_min = 2, 48 .periods_max = 256, 49 .buffer_bytes_max = 256 * 2 * 1024, 50 }; 51 52 struct mt8188_afe_rate { 53 unsigned int rate; 54 unsigned int reg_value; 55 }; 56 57 static const struct mt8188_afe_rate mt8188_afe_rates[] = { 58 { .rate = 8000, .reg_value = 0, }, 59 { .rate = 12000, .reg_value = 1, }, 60 { .rate = 16000, .reg_value = 2, }, 61 { .rate = 24000, .reg_value = 3, }, 62 { .rate = 32000, .reg_value = 4, }, 63 { .rate = 48000, .reg_value = 5, }, 64 { .rate = 96000, .reg_value = 6, }, 65 { .rate = 192000, .reg_value = 7, }, 66 { .rate = 384000, .reg_value = 8, }, 67 { .rate = 7350, .reg_value = 16, }, 68 { .rate = 11025, .reg_value = 17, }, 69 { .rate = 14700, .reg_value = 18, }, 70 { .rate = 22050, .reg_value = 19, }, 71 { .rate = 29400, .reg_value = 20, }, 72 { .rate = 44100, .reg_value = 21, }, 73 { .rate = 88200, .reg_value = 22, }, 74 { .rate = 176400, .reg_value = 23, }, 75 { .rate = 352800, .reg_value = 24, }, 76 }; 77 78 int mt8188_afe_fs_timing(unsigned int rate) 79 { 80 int i; 81 82 for (i = 0; i < ARRAY_SIZE(mt8188_afe_rates); i++) 83 if (mt8188_afe_rates[i].rate == rate) 84 return mt8188_afe_rates[i].reg_value; 85 86 return -EINVAL; 87 } 88 89 static int mt8188_memif_fs(struct snd_pcm_substream *substream, 90 unsigned int rate) 91 { 92 struct snd_soc_pcm_runtime *rtd = substream->private_data; 93 struct snd_soc_component *component = NULL; 94 struct mtk_base_afe *afe = NULL; 95 struct mt8188_afe_private *afe_priv = NULL; 96 struct mtk_base_afe_memif *memif = NULL; 97 struct mtk_dai_memif_priv *memif_priv = NULL; 98 int fs = mt8188_afe_fs_timing(rate); 99 int id = asoc_rtd_to_cpu(rtd, 0)->id; 100 101 if (id < 0) 102 return -EINVAL; 103 104 component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 105 if (!component) 106 return -EINVAL; 107 108 afe = snd_soc_component_get_drvdata(component); 109 memif = &afe->memif[id]; 110 111 switch (memif->data->id) { 112 case MT8188_AFE_MEMIF_DL10: 113 fs = MT8188_ETDM_OUT3_1X_EN; 114 break; 115 case MT8188_AFE_MEMIF_UL8: 116 fs = MT8188_ETDM_IN1_NX_EN; 117 break; 118 case MT8188_AFE_MEMIF_UL3: 119 fs = MT8188_ETDM_IN2_NX_EN; 120 break; 121 default: 122 afe_priv = afe->platform_priv; 123 memif_priv = afe_priv->dai_priv[id]; 124 if (memif_priv->fs_timing) 125 fs = memif_priv->fs_timing; 126 break; 127 } 128 129 return fs; 130 } 131 132 static int mt8188_irq_fs(struct snd_pcm_substream *substream, 133 unsigned int rate) 134 { 135 int fs = mt8188_memif_fs(substream, rate); 136 137 switch (fs) { 138 case MT8188_ETDM_IN1_NX_EN: 139 fs = MT8188_ETDM_IN1_1X_EN; 140 break; 141 case MT8188_ETDM_IN2_NX_EN: 142 fs = MT8188_ETDM_IN2_1X_EN; 143 break; 144 default: 145 break; 146 } 147 148 return fs; 149 } 150 151 enum { 152 MT8188_AFE_CM0, 153 MT8188_AFE_CM1, 154 MT8188_AFE_CM2, 155 MT8188_AFE_CM_NUM, 156 }; 157 158 struct mt8188_afe_channel_merge { 159 int id; 160 int reg; 161 unsigned int sel_shift; 162 unsigned int sel_maskbit; 163 unsigned int sel_default; 164 unsigned int ch_num_shift; 165 unsigned int ch_num_maskbit; 166 unsigned int en_shift; 167 unsigned int en_maskbit; 168 unsigned int update_cnt_shift; 169 unsigned int update_cnt_maskbit; 170 unsigned int update_cnt_default; 171 }; 172 173 static const struct mt8188_afe_channel_merge 174 mt8188_afe_cm[MT8188_AFE_CM_NUM] = { 175 [MT8188_AFE_CM0] = { 176 .id = MT8188_AFE_CM0, 177 .reg = AFE_CM0_CON, 178 .sel_shift = 30, 179 .sel_maskbit = 0x1, 180 .sel_default = 1, 181 .ch_num_shift = 2, 182 .ch_num_maskbit = 0x3f, 183 .en_shift = 0, 184 .en_maskbit = 0x1, 185 .update_cnt_shift = 16, 186 .update_cnt_maskbit = 0x1fff, 187 .update_cnt_default = 0x3, 188 }, 189 [MT8188_AFE_CM1] = { 190 .id = MT8188_AFE_CM1, 191 .reg = AFE_CM1_CON, 192 .sel_shift = 30, 193 .sel_maskbit = 0x1, 194 .sel_default = 1, 195 .ch_num_shift = 2, 196 .ch_num_maskbit = 0x1f, 197 .en_shift = 0, 198 .en_maskbit = 0x1, 199 .update_cnt_shift = 16, 200 .update_cnt_maskbit = 0x1fff, 201 .update_cnt_default = 0x3, 202 }, 203 [MT8188_AFE_CM2] = { 204 .id = MT8188_AFE_CM2, 205 .reg = AFE_CM2_CON, 206 .sel_shift = 30, 207 .sel_maskbit = 0x1, 208 .sel_default = 1, 209 .ch_num_shift = 2, 210 .ch_num_maskbit = 0x1f, 211 .en_shift = 0, 212 .en_maskbit = 0x1, 213 .update_cnt_shift = 16, 214 .update_cnt_maskbit = 0x1fff, 215 .update_cnt_default = 0x3, 216 }, 217 }; 218 219 static int mt8188_afe_memif_is_ul(int id) 220 { 221 if (id >= MT8188_AFE_MEMIF_UL_START && id < MT8188_AFE_MEMIF_END) 222 return 1; 223 else 224 return 0; 225 } 226 227 static const struct mt8188_afe_channel_merge * 228 mt8188_afe_found_cm(struct snd_soc_dai *dai) 229 { 230 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 231 int id = -EINVAL; 232 233 if (mt8188_afe_memif_is_ul(dai->id) == 0) 234 return NULL; 235 236 switch (dai->id) { 237 case MT8188_AFE_MEMIF_UL9: 238 id = MT8188_AFE_CM0; 239 break; 240 case MT8188_AFE_MEMIF_UL2: 241 id = MT8188_AFE_CM1; 242 break; 243 case MT8188_AFE_MEMIF_UL10: 244 id = MT8188_AFE_CM2; 245 break; 246 default: 247 break; 248 } 249 250 if (id < 0) { 251 dev_dbg(afe->dev, "%s, memif %d cannot find CM!\n", __func__, dai->id); 252 return NULL; 253 } 254 255 return &mt8188_afe_cm[id]; 256 } 257 258 static int mt8188_afe_config_cm(struct mtk_base_afe *afe, 259 const struct mt8188_afe_channel_merge *cm, 260 unsigned int channels) 261 { 262 if (!cm) 263 return -EINVAL; 264 265 regmap_update_bits(afe->regmap, 266 cm->reg, 267 cm->sel_maskbit << cm->sel_shift, 268 cm->sel_default << cm->sel_shift); 269 270 regmap_update_bits(afe->regmap, 271 cm->reg, 272 cm->ch_num_maskbit << cm->ch_num_shift, 273 (channels - 1) << cm->ch_num_shift); 274 275 regmap_update_bits(afe->regmap, 276 cm->reg, 277 cm->update_cnt_maskbit << cm->update_cnt_shift, 278 cm->update_cnt_default << cm->update_cnt_shift); 279 280 return 0; 281 } 282 283 static int mt8188_afe_enable_cm(struct mtk_base_afe *afe, 284 const struct mt8188_afe_channel_merge *cm, 285 bool enable) 286 { 287 if (!cm) 288 return -EINVAL; 289 290 regmap_update_bits(afe->regmap, 291 cm->reg, 292 cm->en_maskbit << cm->en_shift, 293 enable << cm->en_shift); 294 295 return 0; 296 } 297 298 static int mt8188_afe_fe_startup(struct snd_pcm_substream *substream, 299 struct snd_soc_dai *dai) 300 { 301 struct snd_soc_pcm_runtime *rtd = substream->private_data; 302 struct snd_pcm_runtime *runtime = substream->runtime; 303 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 304 int id = asoc_rtd_to_cpu(rtd, 0)->id; 305 int ret; 306 307 ret = mtk_afe_fe_startup(substream, dai); 308 309 snd_pcm_hw_constraint_step(runtime, 0, 310 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 311 MT8188_MEMIF_BUFFER_BYTES_ALIGN); 312 313 if (id != MT8188_AFE_MEMIF_DL7) 314 goto out; 315 316 ret = snd_pcm_hw_constraint_minmax(runtime, 317 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 1, 318 MT8188_MEMIF_DL7_MAX_PERIOD_SIZE); 319 if (ret < 0) 320 dev_dbg(afe->dev, "hw_constraint_minmax failed\n"); 321 out: 322 return ret; 323 } 324 325 static void mt8188_afe_fe_shutdown(struct snd_pcm_substream *substream, 326 struct snd_soc_dai *dai) 327 { 328 mtk_afe_fe_shutdown(substream, dai); 329 } 330 331 static int mt8188_afe_fe_hw_params(struct snd_pcm_substream *substream, 332 struct snd_pcm_hw_params *params, 333 struct snd_soc_dai *dai) 334 { 335 struct snd_soc_pcm_runtime *rtd = substream->private_data; 336 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 337 int id = asoc_rtd_to_cpu(rtd, 0)->id; 338 struct mtk_base_afe_memif *memif = &afe->memif[id]; 339 const struct mtk_base_memif_data *data = memif->data; 340 const struct mt8188_afe_channel_merge *cm = mt8188_afe_found_cm(dai); 341 unsigned int channels = params_channels(params); 342 343 mt8188_afe_config_cm(afe, cm, channels); 344 345 if (data->ch_num_reg >= 0) { 346 regmap_update_bits(afe->regmap, data->ch_num_reg, 347 data->ch_num_maskbit << data->ch_num_shift, 348 channels << data->ch_num_shift); 349 } 350 351 return mtk_afe_fe_hw_params(substream, params, dai); 352 } 353 354 static int mt8188_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd, 355 struct snd_soc_dai *dai) 356 { 357 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 358 const struct mt8188_afe_channel_merge *cm = mt8188_afe_found_cm(dai); 359 struct snd_soc_pcm_runtime *rtd = substream->private_data; 360 struct snd_pcm_runtime * const runtime = substream->runtime; 361 int id = asoc_rtd_to_cpu(rtd, 0)->id; 362 struct mtk_base_afe_memif *memif = &afe->memif[id]; 363 struct mtk_base_afe_irq *irqs = &afe->irqs[memif->irq_usage]; 364 const struct mtk_base_irq_data *irq_data = irqs->irq_data; 365 unsigned int counter = runtime->period_size; 366 int fs; 367 int ret; 368 369 switch (cmd) { 370 case SNDRV_PCM_TRIGGER_START: 371 case SNDRV_PCM_TRIGGER_RESUME: 372 mt8188_afe_enable_cm(afe, cm, true); 373 374 ret = mtk_memif_set_enable(afe, id); 375 if (ret) { 376 dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n", 377 __func__, id, ret); 378 return ret; 379 } 380 381 /* set irq counter */ 382 regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg, 383 irq_data->irq_cnt_maskbit << irq_data->irq_cnt_shift, 384 counter << irq_data->irq_cnt_shift); 385 386 /* set irq fs */ 387 fs = afe->irq_fs(substream, runtime->rate); 388 389 if (fs < 0) 390 return -EINVAL; 391 392 if (irq_data->irq_fs_reg >= 0) 393 regmap_update_bits(afe->regmap, irq_data->irq_fs_reg, 394 irq_data->irq_fs_maskbit << irq_data->irq_fs_shift, 395 fs << irq_data->irq_fs_shift); 396 397 /* delay for uplink */ 398 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 399 u32 sample_delay; 400 401 sample_delay = ((MEMIF_AXI_MINLEN + 1) * 64 + 402 (runtime->channels * runtime->sample_bits - 1)) / 403 (runtime->channels * runtime->sample_bits) + 1; 404 405 udelay(sample_delay * 1000000 / runtime->rate); 406 } 407 408 /* enable interrupt */ 409 regmap_set_bits(afe->regmap, irq_data->irq_en_reg, 410 BIT(irq_data->irq_en_shift)); 411 return 0; 412 case SNDRV_PCM_TRIGGER_STOP: 413 case SNDRV_PCM_TRIGGER_SUSPEND: 414 mt8188_afe_enable_cm(afe, cm, false); 415 416 ret = mtk_memif_set_disable(afe, id); 417 if (ret) 418 dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n", 419 __func__, id, ret); 420 421 /* disable interrupt */ 422 423 regmap_clear_bits(afe->regmap, irq_data->irq_en_reg, 424 BIT(irq_data->irq_en_shift)); 425 /* and clear pending IRQ */ 426 regmap_write(afe->regmap, irq_data->irq_clr_reg, 427 BIT(irq_data->irq_clr_shift)); 428 return ret; 429 default: 430 return -EINVAL; 431 } 432 } 433 434 static const struct snd_soc_dai_ops mt8188_afe_fe_dai_ops = { 435 .startup = mt8188_afe_fe_startup, 436 .shutdown = mt8188_afe_fe_shutdown, 437 .hw_params = mt8188_afe_fe_hw_params, 438 .hw_free = mtk_afe_fe_hw_free, 439 .prepare = mtk_afe_fe_prepare, 440 .trigger = mt8188_afe_fe_trigger, 441 }; 442 443 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\ 444 SNDRV_PCM_RATE_88200 |\ 445 SNDRV_PCM_RATE_96000 |\ 446 SNDRV_PCM_RATE_176400 |\ 447 SNDRV_PCM_RATE_192000 |\ 448 SNDRV_PCM_RATE_352800 |\ 449 SNDRV_PCM_RATE_384000) 450 451 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 452 SNDRV_PCM_FMTBIT_S24_LE |\ 453 SNDRV_PCM_FMTBIT_S32_LE) 454 455 static struct snd_soc_dai_driver mt8188_memif_dai_driver[] = { 456 /* FE DAIs: memory intefaces to CPU */ 457 { 458 .name = "DL2", 459 .id = MT8188_AFE_MEMIF_DL2, 460 .playback = { 461 .stream_name = "DL2", 462 .channels_min = 1, 463 .channels_max = 2, 464 .rates = MTK_PCM_RATES, 465 .formats = MTK_PCM_FORMATS, 466 }, 467 .ops = &mt8188_afe_fe_dai_ops, 468 }, 469 { 470 .name = "DL3", 471 .id = MT8188_AFE_MEMIF_DL3, 472 .playback = { 473 .stream_name = "DL3", 474 .channels_min = 1, 475 .channels_max = 2, 476 .rates = MTK_PCM_RATES, 477 .formats = MTK_PCM_FORMATS, 478 }, 479 .ops = &mt8188_afe_fe_dai_ops, 480 }, 481 { 482 .name = "DL6", 483 .id = MT8188_AFE_MEMIF_DL6, 484 .playback = { 485 .stream_name = "DL6", 486 .channels_min = 1, 487 .channels_max = 2, 488 .rates = MTK_PCM_RATES, 489 .formats = MTK_PCM_FORMATS, 490 }, 491 .ops = &mt8188_afe_fe_dai_ops, 492 }, 493 { 494 .name = "DL7", 495 .id = MT8188_AFE_MEMIF_DL7, 496 .playback = { 497 .stream_name = "DL7", 498 .channels_min = 1, 499 .channels_max = 2, 500 .rates = MTK_PCM_RATES, 501 .formats = MTK_PCM_FORMATS, 502 }, 503 .ops = &mt8188_afe_fe_dai_ops, 504 }, 505 { 506 .name = "DL8", 507 .id = MT8188_AFE_MEMIF_DL8, 508 .playback = { 509 .stream_name = "DL8", 510 .channels_min = 1, 511 .channels_max = 16, 512 .rates = MTK_PCM_RATES, 513 .formats = MTK_PCM_FORMATS, 514 }, 515 .ops = &mt8188_afe_fe_dai_ops, 516 }, 517 { 518 .name = "DL10", 519 .id = MT8188_AFE_MEMIF_DL10, 520 .playback = { 521 .stream_name = "DL10", 522 .channels_min = 1, 523 .channels_max = 8, 524 .rates = MTK_PCM_RATES, 525 .formats = MTK_PCM_FORMATS, 526 }, 527 .ops = &mt8188_afe_fe_dai_ops, 528 }, 529 { 530 .name = "DL11", 531 .id = MT8188_AFE_MEMIF_DL11, 532 .playback = { 533 .stream_name = "DL11", 534 .channels_min = 1, 535 .channels_max = 32, 536 .rates = MTK_PCM_RATES, 537 .formats = MTK_PCM_FORMATS, 538 }, 539 .ops = &mt8188_afe_fe_dai_ops, 540 }, 541 { 542 .name = "UL1", 543 .id = MT8188_AFE_MEMIF_UL1, 544 .capture = { 545 .stream_name = "UL1", 546 .channels_min = 1, 547 .channels_max = 8, 548 .rates = MTK_PCM_RATES, 549 .formats = MTK_PCM_FORMATS, 550 }, 551 .ops = &mt8188_afe_fe_dai_ops, 552 }, 553 { 554 .name = "UL2", 555 .id = MT8188_AFE_MEMIF_UL2, 556 .capture = { 557 .stream_name = "UL2", 558 .channels_min = 1, 559 .channels_max = 8, 560 .rates = MTK_PCM_RATES, 561 .formats = MTK_PCM_FORMATS, 562 }, 563 .ops = &mt8188_afe_fe_dai_ops, 564 }, 565 { 566 .name = "UL3", 567 .id = MT8188_AFE_MEMIF_UL3, 568 .capture = { 569 .stream_name = "UL3", 570 .channels_min = 1, 571 .channels_max = 16, 572 .rates = MTK_PCM_RATES, 573 .formats = MTK_PCM_FORMATS, 574 }, 575 .ops = &mt8188_afe_fe_dai_ops, 576 }, 577 { 578 .name = "UL4", 579 .id = MT8188_AFE_MEMIF_UL4, 580 .capture = { 581 .stream_name = "UL4", 582 .channels_min = 1, 583 .channels_max = 2, 584 .rates = MTK_PCM_RATES, 585 .formats = MTK_PCM_FORMATS, 586 }, 587 .ops = &mt8188_afe_fe_dai_ops, 588 }, 589 { 590 .name = "UL5", 591 .id = MT8188_AFE_MEMIF_UL5, 592 .capture = { 593 .stream_name = "UL5", 594 .channels_min = 1, 595 .channels_max = 2, 596 .rates = MTK_PCM_RATES, 597 .formats = MTK_PCM_FORMATS, 598 }, 599 .ops = &mt8188_afe_fe_dai_ops, 600 }, 601 { 602 .name = "UL6", 603 .id = MT8188_AFE_MEMIF_UL6, 604 .capture = { 605 .stream_name = "UL6", 606 .channels_min = 1, 607 .channels_max = 8, 608 .rates = MTK_PCM_RATES, 609 .formats = MTK_PCM_FORMATS, 610 }, 611 .ops = &mt8188_afe_fe_dai_ops, 612 }, 613 { 614 .name = "UL8", 615 .id = MT8188_AFE_MEMIF_UL8, 616 .capture = { 617 .stream_name = "UL8", 618 .channels_min = 1, 619 .channels_max = 24, 620 .rates = MTK_PCM_RATES, 621 .formats = MTK_PCM_FORMATS, 622 }, 623 .ops = &mt8188_afe_fe_dai_ops, 624 }, 625 { 626 .name = "UL9", 627 .id = MT8188_AFE_MEMIF_UL9, 628 .capture = { 629 .stream_name = "UL9", 630 .channels_min = 1, 631 .channels_max = 32, 632 .rates = MTK_PCM_RATES, 633 .formats = MTK_PCM_FORMATS, 634 }, 635 .ops = &mt8188_afe_fe_dai_ops, 636 }, 637 { 638 .name = "UL10", 639 .id = MT8188_AFE_MEMIF_UL10, 640 .capture = { 641 .stream_name = "UL10", 642 .channels_min = 1, 643 .channels_max = 4, 644 .rates = MTK_PCM_RATES, 645 .formats = MTK_PCM_FORMATS, 646 }, 647 .ops = &mt8188_afe_fe_dai_ops, 648 }, 649 }; 650 651 static const struct snd_kcontrol_new o002_mix[] = { 652 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN2, 0, 1, 0), 653 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN2, 12, 1, 0), 654 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN2, 20, 1, 0), 655 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN2, 22, 1, 0), 656 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN2_2, 6, 1, 0), 657 SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN2_2, 8, 1, 0), 658 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN2_5, 8, 1, 0), 659 }; 660 661 static const struct snd_kcontrol_new o003_mix[] = { 662 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN3, 1, 1, 0), 663 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN3, 13, 1, 0), 664 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN3, 21, 1, 0), 665 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN3, 23, 1, 0), 666 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN3_2, 7, 1, 0), 667 SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN3_2, 9, 1, 0), 668 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN3_5, 9, 1, 0), 669 }; 670 671 static const struct snd_kcontrol_new o004_mix[] = { 672 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN4, 0, 1, 0), 673 SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN4, 14, 1, 0), 674 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN4, 24, 1, 0), 675 SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN4_2, 10, 1, 0), 676 }; 677 678 static const struct snd_kcontrol_new o005_mix[] = { 679 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN5, 1, 1, 0), 680 SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN5, 15, 1, 0), 681 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN5, 25, 1, 0), 682 SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN5_2, 11, 1, 0), 683 }; 684 685 static const struct snd_kcontrol_new o006_mix[] = { 686 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN6, 0, 1, 0), 687 SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN6, 16, 1, 0), 688 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN6, 26, 1, 0), 689 SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN6_2, 12, 1, 0), 690 }; 691 692 static const struct snd_kcontrol_new o007_mix[] = { 693 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN7, 1, 1, 0), 694 SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN7, 17, 1, 0), 695 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN7, 27, 1, 0), 696 SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN7_2, 13, 1, 0), 697 }; 698 699 static const struct snd_kcontrol_new o008_mix[] = { 700 SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN8, 18, 1, 0), 701 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN8, 28, 1, 0), 702 SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN8_2, 14, 1, 0), 703 }; 704 705 static const struct snd_kcontrol_new o009_mix[] = { 706 SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN9, 19, 1, 0), 707 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN9, 29, 1, 0), 708 SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN9_2, 15, 1, 0), 709 }; 710 711 static const struct snd_kcontrol_new o010_mix[] = { 712 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN10, 22, 1, 0), 713 SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN10, 30, 1, 0), 714 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN10_1, 14, 1, 0), 715 SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN10_2, 8, 1, 0), 716 SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN10_2, 16, 1, 0), 717 SOC_DAPM_SINGLE_AUTODISABLE("I188 Switch", AFE_CONN10_5, 28, 1, 0), 718 }; 719 720 static const struct snd_kcontrol_new o011_mix[] = { 721 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN11, 23, 1, 0), 722 SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN11, 31, 1, 0), 723 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN11_1, 15, 1, 0), 724 SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN11_2, 9, 1, 0), 725 SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN11_2, 17, 1, 0), 726 SOC_DAPM_SINGLE_AUTODISABLE("I189 Switch", AFE_CONN11_5, 29, 1, 0), 727 }; 728 729 static const struct snd_kcontrol_new o012_mix[] = { 730 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN12, 24, 1, 0), 731 SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN12_1, 0, 1, 0), 732 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN12_1, 16, 1, 0), 733 SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN12_2, 10, 1, 0), 734 SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN12_2, 18, 1, 0), 735 SOC_DAPM_SINGLE_AUTODISABLE("I190 Switch", AFE_CONN12_5, 30, 1, 0), 736 }; 737 738 static const struct snd_kcontrol_new o013_mix[] = { 739 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN13, 25, 1, 0), 740 SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN13_1, 1, 1, 0), 741 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN13_1, 17, 1, 0), 742 SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN13_2, 11, 1, 0), 743 SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN13_2, 19, 1, 0), 744 SOC_DAPM_SINGLE_AUTODISABLE("I191 Switch", AFE_CONN13_5, 31, 1, 0), 745 }; 746 747 static const struct snd_kcontrol_new o014_mix[] = { 748 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN14, 26, 1, 0), 749 SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN14_1, 2, 1, 0), 750 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN14_1, 18, 1, 0), 751 SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN14_2, 12, 1, 0), 752 SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN14_2, 20, 1, 0), 753 SOC_DAPM_SINGLE_AUTODISABLE("I192 Switch", AFE_CONN14_6, 0, 1, 0), 754 }; 755 756 static const struct snd_kcontrol_new o015_mix[] = { 757 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN15, 27, 1, 0), 758 SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN15_1, 3, 1, 0), 759 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN15_1, 19, 1, 0), 760 SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN15_2, 13, 1, 0), 761 SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN15_2, 21, 1, 0), 762 SOC_DAPM_SINGLE_AUTODISABLE("I193 Switch", AFE_CONN15_6, 1, 1, 0), 763 }; 764 765 static const struct snd_kcontrol_new o016_mix[] = { 766 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN16, 28, 1, 0), 767 SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN16_1, 4, 1, 0), 768 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN16_1, 20, 1, 0), 769 SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN16_2, 14, 1, 0), 770 SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN16_2, 22, 1, 0), 771 SOC_DAPM_SINGLE_AUTODISABLE("I194 Switch", AFE_CONN16_6, 2, 1, 0), 772 }; 773 774 static const struct snd_kcontrol_new o017_mix[] = { 775 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN17, 29, 1, 0), 776 SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN17_1, 5, 1, 0), 777 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN17_1, 21, 1, 0), 778 SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN17_2, 15, 1, 0), 779 SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN17_2, 23, 1, 0), 780 SOC_DAPM_SINGLE_AUTODISABLE("I195 Switch", AFE_CONN17_6, 3, 1, 0), 781 }; 782 783 static const struct snd_kcontrol_new o018_mix[] = { 784 SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN18_2, 16, 1, 0), 785 }; 786 787 static const struct snd_kcontrol_new o019_mix[] = { 788 SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN19_2, 17, 1, 0), 789 }; 790 791 static const struct snd_kcontrol_new o020_mix[] = { 792 SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN20_2, 18, 1, 0), 793 }; 794 795 static const struct snd_kcontrol_new o021_mix[] = { 796 SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN21_2, 19, 1, 0), 797 }; 798 799 static const struct snd_kcontrol_new o022_mix[] = { 800 SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN22_2, 20, 1, 0), 801 }; 802 803 static const struct snd_kcontrol_new o023_mix[] = { 804 SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN23_2, 21, 1, 0), 805 }; 806 807 static const struct snd_kcontrol_new o024_mix[] = { 808 SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN24_2, 22, 1, 0), 809 }; 810 811 static const struct snd_kcontrol_new o025_mix[] = { 812 SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN25_2, 23, 1, 0), 813 }; 814 815 static const struct snd_kcontrol_new o026_mix[] = { 816 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN26_1, 14, 1, 0), 817 }; 818 819 static const struct snd_kcontrol_new o027_mix[] = { 820 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN27_1, 15, 1, 0), 821 }; 822 823 static const struct snd_kcontrol_new o028_mix[] = { 824 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN28_1, 16, 1, 0), 825 }; 826 827 static const struct snd_kcontrol_new o029_mix[] = { 828 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN29_1, 17, 1, 0), 829 }; 830 831 static const struct snd_kcontrol_new o030_mix[] = { 832 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN30_1, 18, 1, 0), 833 }; 834 835 static const struct snd_kcontrol_new o031_mix[] = { 836 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN31_1, 19, 1, 0), 837 }; 838 839 static const struct snd_kcontrol_new o032_mix[] = { 840 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN32_1, 20, 1, 0), 841 }; 842 843 static const struct snd_kcontrol_new o033_mix[] = { 844 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN33_1, 21, 1, 0), 845 }; 846 847 static const struct snd_kcontrol_new o034_mix[] = { 848 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN34, 0, 1, 0), 849 SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN34, 2, 1, 0), 850 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN34, 12, 1, 0), 851 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN34, 20, 1, 0), 852 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN34_2, 6, 1, 0), 853 SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN34_2, 8, 1, 0), 854 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN34_5, 8, 1, 0), 855 }; 856 857 static const struct snd_kcontrol_new o035_mix[] = { 858 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN35, 1, 1, 0), 859 SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN35, 3, 1, 0), 860 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN35, 13, 1, 0), 861 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN35, 21, 1, 0), 862 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN35_2, 7, 1, 0), 863 SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN35_2, 9, 1, 0), 864 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN35_5, 8, 1, 0), 865 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN35_5, 9, 1, 0), 866 }; 867 868 static const struct snd_kcontrol_new o036_mix[] = { 869 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN36, 0, 1, 0), 870 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN36, 12, 1, 0), 871 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN36, 20, 1, 0), 872 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN36_2, 6, 1, 0), 873 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN36_5, 8, 1, 0), 874 }; 875 876 static const struct snd_kcontrol_new o037_mix[] = { 877 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN37, 1, 1, 0), 878 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN37, 13, 1, 0), 879 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN37, 21, 1, 0), 880 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN37_2, 7, 1, 0), 881 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN37_5, 9, 1, 0), 882 }; 883 884 static const struct snd_kcontrol_new o038_mix[] = { 885 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN38, 22, 1, 0), 886 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN38_5, 8, 1, 0), 887 }; 888 889 static const struct snd_kcontrol_new o039_mix[] = { 890 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN39, 23, 1, 0), 891 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN39_5, 9, 1, 0), 892 }; 893 894 static const struct snd_kcontrol_new o040_mix[] = { 895 SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN40, 2, 1, 0), 896 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN40, 12, 1, 0), 897 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN40, 22, 1, 0), 898 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN40_5, 8, 1, 0), 899 }; 900 901 static const struct snd_kcontrol_new o041_mix[] = { 902 SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN41, 3, 1, 0), 903 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN41, 13, 1, 0), 904 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN41, 23, 1, 0), 905 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN41_5, 9, 1, 0), 906 }; 907 908 static const struct snd_kcontrol_new o042_mix[] = { 909 SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN42, 14, 1, 0), 910 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN42, 24, 1, 0), 911 }; 912 913 static const struct snd_kcontrol_new o043_mix[] = { 914 SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN43, 15, 1, 0), 915 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN43, 25, 1, 0), 916 }; 917 918 static const struct snd_kcontrol_new o044_mix[] = { 919 SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN44, 16, 1, 0), 920 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN44, 26, 1, 0), 921 }; 922 923 static const struct snd_kcontrol_new o045_mix[] = { 924 SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN45, 17, 1, 0), 925 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN45, 27, 1, 0), 926 }; 927 928 static const struct snd_kcontrol_new o046_mix[] = { 929 SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN46, 18, 1, 0), 930 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN46, 28, 1, 0), 931 }; 932 933 static const struct snd_kcontrol_new o047_mix[] = { 934 SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN47, 19, 1, 0), 935 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN47, 29, 1, 0), 936 }; 937 938 static const struct snd_kcontrol_new o182_mix[] = { 939 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN182, 20, 1, 0), 940 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN182, 22, 1, 0), 941 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN182, 24, 1, 0), 942 }; 943 944 static const struct snd_kcontrol_new o183_mix[] = { 945 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN183, 21, 1, 0), 946 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN183, 23, 1, 0), 947 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN183, 25, 1, 0), 948 }; 949 950 static const char * const dl8_dl11_data_sel_mux_text[] = { 951 "dl8", "dl11", 952 }; 953 954 static SOC_ENUM_SINGLE_DECL(dl8_dl11_data_sel_mux_enum, 955 AFE_DAC_CON2, 0, dl8_dl11_data_sel_mux_text); 956 957 static const struct snd_kcontrol_new dl8_dl11_data_sel_mux = 958 SOC_DAPM_ENUM("DL8_DL11 Sink", 959 dl8_dl11_data_sel_mux_enum); 960 961 static const struct snd_soc_dapm_widget mt8188_memif_widgets[] = { 962 /* DL6 */ 963 SND_SOC_DAPM_MIXER("I000", SND_SOC_NOPM, 0, 0, NULL, 0), 964 SND_SOC_DAPM_MIXER("I001", SND_SOC_NOPM, 0, 0, NULL, 0), 965 966 /* DL3 */ 967 SND_SOC_DAPM_MIXER("I020", SND_SOC_NOPM, 0, 0, NULL, 0), 968 SND_SOC_DAPM_MIXER("I021", SND_SOC_NOPM, 0, 0, NULL, 0), 969 970 /* DL11 */ 971 SND_SOC_DAPM_MIXER("I022", SND_SOC_NOPM, 0, 0, NULL, 0), 972 SND_SOC_DAPM_MIXER("I023", SND_SOC_NOPM, 0, 0, NULL, 0), 973 SND_SOC_DAPM_MIXER("I024", SND_SOC_NOPM, 0, 0, NULL, 0), 974 SND_SOC_DAPM_MIXER("I025", SND_SOC_NOPM, 0, 0, NULL, 0), 975 SND_SOC_DAPM_MIXER("I026", SND_SOC_NOPM, 0, 0, NULL, 0), 976 SND_SOC_DAPM_MIXER("I027", SND_SOC_NOPM, 0, 0, NULL, 0), 977 SND_SOC_DAPM_MIXER("I028", SND_SOC_NOPM, 0, 0, NULL, 0), 978 SND_SOC_DAPM_MIXER("I029", SND_SOC_NOPM, 0, 0, NULL, 0), 979 SND_SOC_DAPM_MIXER("I030", SND_SOC_NOPM, 0, 0, NULL, 0), 980 SND_SOC_DAPM_MIXER("I031", SND_SOC_NOPM, 0, 0, NULL, 0), 981 SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0), 982 SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0), 983 SND_SOC_DAPM_MIXER("I034", SND_SOC_NOPM, 0, 0, NULL, 0), 984 SND_SOC_DAPM_MIXER("I035", SND_SOC_NOPM, 0, 0, NULL, 0), 985 SND_SOC_DAPM_MIXER("I036", SND_SOC_NOPM, 0, 0, NULL, 0), 986 SND_SOC_DAPM_MIXER("I037", SND_SOC_NOPM, 0, 0, NULL, 0), 987 988 /* DL11/DL8 */ 989 SND_SOC_DAPM_MIXER("I046", SND_SOC_NOPM, 0, 0, NULL, 0), 990 SND_SOC_DAPM_MIXER("I047", SND_SOC_NOPM, 0, 0, NULL, 0), 991 SND_SOC_DAPM_MIXER("I048", SND_SOC_NOPM, 0, 0, NULL, 0), 992 SND_SOC_DAPM_MIXER("I049", SND_SOC_NOPM, 0, 0, NULL, 0), 993 SND_SOC_DAPM_MIXER("I050", SND_SOC_NOPM, 0, 0, NULL, 0), 994 SND_SOC_DAPM_MIXER("I051", SND_SOC_NOPM, 0, 0, NULL, 0), 995 SND_SOC_DAPM_MIXER("I052", SND_SOC_NOPM, 0, 0, NULL, 0), 996 SND_SOC_DAPM_MIXER("I053", SND_SOC_NOPM, 0, 0, NULL, 0), 997 SND_SOC_DAPM_MIXER("I054", SND_SOC_NOPM, 0, 0, NULL, 0), 998 SND_SOC_DAPM_MIXER("I055", SND_SOC_NOPM, 0, 0, NULL, 0), 999 SND_SOC_DAPM_MIXER("I056", SND_SOC_NOPM, 0, 0, NULL, 0), 1000 SND_SOC_DAPM_MIXER("I057", SND_SOC_NOPM, 0, 0, NULL, 0), 1001 SND_SOC_DAPM_MIXER("I058", SND_SOC_NOPM, 0, 0, NULL, 0), 1002 SND_SOC_DAPM_MIXER("I059", SND_SOC_NOPM, 0, 0, NULL, 0), 1003 SND_SOC_DAPM_MIXER("I060", SND_SOC_NOPM, 0, 0, NULL, 0), 1004 SND_SOC_DAPM_MIXER("I061", SND_SOC_NOPM, 0, 0, NULL, 0), 1005 1006 /* DL2 */ 1007 SND_SOC_DAPM_MIXER("I070", SND_SOC_NOPM, 0, 0, NULL, 0), 1008 SND_SOC_DAPM_MIXER("I071", SND_SOC_NOPM, 0, 0, NULL, 0), 1009 1010 SND_SOC_DAPM_MUX("DL8_DL11 Mux", 1011 SND_SOC_NOPM, 0, 0, &dl8_dl11_data_sel_mux), 1012 1013 /* UL9 */ 1014 SND_SOC_DAPM_MIXER("O002", SND_SOC_NOPM, 0, 0, 1015 o002_mix, ARRAY_SIZE(o002_mix)), 1016 SND_SOC_DAPM_MIXER("O003", SND_SOC_NOPM, 0, 0, 1017 o003_mix, ARRAY_SIZE(o003_mix)), 1018 SND_SOC_DAPM_MIXER("O004", SND_SOC_NOPM, 0, 0, 1019 o004_mix, ARRAY_SIZE(o004_mix)), 1020 SND_SOC_DAPM_MIXER("O005", SND_SOC_NOPM, 0, 0, 1021 o005_mix, ARRAY_SIZE(o005_mix)), 1022 SND_SOC_DAPM_MIXER("O006", SND_SOC_NOPM, 0, 0, 1023 o006_mix, ARRAY_SIZE(o006_mix)), 1024 SND_SOC_DAPM_MIXER("O007", SND_SOC_NOPM, 0, 0, 1025 o007_mix, ARRAY_SIZE(o007_mix)), 1026 SND_SOC_DAPM_MIXER("O008", SND_SOC_NOPM, 0, 0, 1027 o008_mix, ARRAY_SIZE(o008_mix)), 1028 SND_SOC_DAPM_MIXER("O009", SND_SOC_NOPM, 0, 0, 1029 o009_mix, ARRAY_SIZE(o009_mix)), 1030 SND_SOC_DAPM_MIXER("O010", SND_SOC_NOPM, 0, 0, 1031 o010_mix, ARRAY_SIZE(o010_mix)), 1032 SND_SOC_DAPM_MIXER("O011", SND_SOC_NOPM, 0, 0, 1033 o011_mix, ARRAY_SIZE(o011_mix)), 1034 SND_SOC_DAPM_MIXER("O012", SND_SOC_NOPM, 0, 0, 1035 o012_mix, ARRAY_SIZE(o012_mix)), 1036 SND_SOC_DAPM_MIXER("O013", SND_SOC_NOPM, 0, 0, 1037 o013_mix, ARRAY_SIZE(o013_mix)), 1038 SND_SOC_DAPM_MIXER("O014", SND_SOC_NOPM, 0, 0, 1039 o014_mix, ARRAY_SIZE(o014_mix)), 1040 SND_SOC_DAPM_MIXER("O015", SND_SOC_NOPM, 0, 0, 1041 o015_mix, ARRAY_SIZE(o015_mix)), 1042 SND_SOC_DAPM_MIXER("O016", SND_SOC_NOPM, 0, 0, 1043 o016_mix, ARRAY_SIZE(o016_mix)), 1044 SND_SOC_DAPM_MIXER("O017", SND_SOC_NOPM, 0, 0, 1045 o017_mix, ARRAY_SIZE(o017_mix)), 1046 SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0, 1047 o018_mix, ARRAY_SIZE(o018_mix)), 1048 SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0, 1049 o019_mix, ARRAY_SIZE(o019_mix)), 1050 SND_SOC_DAPM_MIXER("O020", SND_SOC_NOPM, 0, 0, 1051 o020_mix, ARRAY_SIZE(o020_mix)), 1052 SND_SOC_DAPM_MIXER("O021", SND_SOC_NOPM, 0, 0, 1053 o021_mix, ARRAY_SIZE(o021_mix)), 1054 SND_SOC_DAPM_MIXER("O022", SND_SOC_NOPM, 0, 0, 1055 o022_mix, ARRAY_SIZE(o022_mix)), 1056 SND_SOC_DAPM_MIXER("O023", SND_SOC_NOPM, 0, 0, 1057 o023_mix, ARRAY_SIZE(o023_mix)), 1058 SND_SOC_DAPM_MIXER("O024", SND_SOC_NOPM, 0, 0, 1059 o024_mix, ARRAY_SIZE(o024_mix)), 1060 SND_SOC_DAPM_MIXER("O025", SND_SOC_NOPM, 0, 0, 1061 o025_mix, ARRAY_SIZE(o025_mix)), 1062 SND_SOC_DAPM_MIXER("O026", SND_SOC_NOPM, 0, 0, 1063 o026_mix, ARRAY_SIZE(o026_mix)), 1064 SND_SOC_DAPM_MIXER("O027", SND_SOC_NOPM, 0, 0, 1065 o027_mix, ARRAY_SIZE(o027_mix)), 1066 SND_SOC_DAPM_MIXER("O028", SND_SOC_NOPM, 0, 0, 1067 o028_mix, ARRAY_SIZE(o028_mix)), 1068 SND_SOC_DAPM_MIXER("O029", SND_SOC_NOPM, 0, 0, 1069 o029_mix, ARRAY_SIZE(o029_mix)), 1070 SND_SOC_DAPM_MIXER("O030", SND_SOC_NOPM, 0, 0, 1071 o030_mix, ARRAY_SIZE(o030_mix)), 1072 SND_SOC_DAPM_MIXER("O031", SND_SOC_NOPM, 0, 0, 1073 o031_mix, ARRAY_SIZE(o031_mix)), 1074 SND_SOC_DAPM_MIXER("O032", SND_SOC_NOPM, 0, 0, 1075 o032_mix, ARRAY_SIZE(o032_mix)), 1076 SND_SOC_DAPM_MIXER("O033", SND_SOC_NOPM, 0, 0, 1077 o033_mix, ARRAY_SIZE(o033_mix)), 1078 1079 /* UL4 */ 1080 SND_SOC_DAPM_MIXER("O034", SND_SOC_NOPM, 0, 0, 1081 o034_mix, ARRAY_SIZE(o034_mix)), 1082 SND_SOC_DAPM_MIXER("O035", SND_SOC_NOPM, 0, 0, 1083 o035_mix, ARRAY_SIZE(o035_mix)), 1084 1085 /* UL5 */ 1086 SND_SOC_DAPM_MIXER("O036", SND_SOC_NOPM, 0, 0, 1087 o036_mix, ARRAY_SIZE(o036_mix)), 1088 SND_SOC_DAPM_MIXER("O037", SND_SOC_NOPM, 0, 0, 1089 o037_mix, ARRAY_SIZE(o037_mix)), 1090 1091 /* UL10 */ 1092 SND_SOC_DAPM_MIXER("O038", SND_SOC_NOPM, 0, 0, 1093 o038_mix, ARRAY_SIZE(o038_mix)), 1094 SND_SOC_DAPM_MIXER("O039", SND_SOC_NOPM, 0, 0, 1095 o039_mix, ARRAY_SIZE(o039_mix)), 1096 SND_SOC_DAPM_MIXER("O182", SND_SOC_NOPM, 0, 0, 1097 o182_mix, ARRAY_SIZE(o182_mix)), 1098 SND_SOC_DAPM_MIXER("O183", SND_SOC_NOPM, 0, 0, 1099 o183_mix, ARRAY_SIZE(o183_mix)), 1100 1101 /* UL2 */ 1102 SND_SOC_DAPM_MIXER("O040", SND_SOC_NOPM, 0, 0, 1103 o040_mix, ARRAY_SIZE(o040_mix)), 1104 SND_SOC_DAPM_MIXER("O041", SND_SOC_NOPM, 0, 0, 1105 o041_mix, ARRAY_SIZE(o041_mix)), 1106 SND_SOC_DAPM_MIXER("O042", SND_SOC_NOPM, 0, 0, 1107 o042_mix, ARRAY_SIZE(o042_mix)), 1108 SND_SOC_DAPM_MIXER("O043", SND_SOC_NOPM, 0, 0, 1109 o043_mix, ARRAY_SIZE(o043_mix)), 1110 SND_SOC_DAPM_MIXER("O044", SND_SOC_NOPM, 0, 0, 1111 o044_mix, ARRAY_SIZE(o044_mix)), 1112 SND_SOC_DAPM_MIXER("O045", SND_SOC_NOPM, 0, 0, 1113 o045_mix, ARRAY_SIZE(o045_mix)), 1114 SND_SOC_DAPM_MIXER("O046", SND_SOC_NOPM, 0, 0, 1115 o046_mix, ARRAY_SIZE(o046_mix)), 1116 SND_SOC_DAPM_MIXER("O047", SND_SOC_NOPM, 0, 0, 1117 o047_mix, ARRAY_SIZE(o047_mix)), 1118 }; 1119 1120 static const struct snd_soc_dapm_route mt8188_memif_routes[] = { 1121 {"I000", NULL, "DL6"}, 1122 {"I001", NULL, "DL6"}, 1123 1124 {"I020", NULL, "DL3"}, 1125 {"I021", NULL, "DL3"}, 1126 1127 {"I022", NULL, "DL11"}, 1128 {"I023", NULL, "DL11"}, 1129 {"I024", NULL, "DL11"}, 1130 {"I025", NULL, "DL11"}, 1131 {"I026", NULL, "DL11"}, 1132 {"I027", NULL, "DL11"}, 1133 {"I028", NULL, "DL11"}, 1134 {"I029", NULL, "DL11"}, 1135 {"I030", NULL, "DL11"}, 1136 {"I031", NULL, "DL11"}, 1137 {"I032", NULL, "DL11"}, 1138 {"I033", NULL, "DL11"}, 1139 {"I034", NULL, "DL11"}, 1140 {"I035", NULL, "DL11"}, 1141 {"I036", NULL, "DL11"}, 1142 {"I037", NULL, "DL11"}, 1143 1144 {"DL8_DL11 Mux", "dl8", "DL8"}, 1145 {"DL8_DL11 Mux", "dl11", "DL11"}, 1146 1147 {"I046", NULL, "DL8_DL11 Mux"}, 1148 {"I047", NULL, "DL8_DL11 Mux"}, 1149 {"I048", NULL, "DL8_DL11 Mux"}, 1150 {"I049", NULL, "DL8_DL11 Mux"}, 1151 {"I050", NULL, "DL8_DL11 Mux"}, 1152 {"I051", NULL, "DL8_DL11 Mux"}, 1153 {"I052", NULL, "DL8_DL11 Mux"}, 1154 {"I053", NULL, "DL8_DL11 Mux"}, 1155 {"I054", NULL, "DL8_DL11 Mux"}, 1156 {"I055", NULL, "DL8_DL11 Mux"}, 1157 {"I056", NULL, "DL8_DL11 Mux"}, 1158 {"I057", NULL, "DL8_DL11 Mux"}, 1159 {"I058", NULL, "DL8_DL11 Mux"}, 1160 {"I059", NULL, "DL8_DL11 Mux"}, 1161 {"I060", NULL, "DL8_DL11 Mux"}, 1162 {"I061", NULL, "DL8_DL11 Mux"}, 1163 1164 {"I070", NULL, "DL2"}, 1165 {"I071", NULL, "DL2"}, 1166 1167 {"UL9", NULL, "O002"}, 1168 {"UL9", NULL, "O003"}, 1169 {"UL9", NULL, "O004"}, 1170 {"UL9", NULL, "O005"}, 1171 {"UL9", NULL, "O006"}, 1172 {"UL9", NULL, "O007"}, 1173 {"UL9", NULL, "O008"}, 1174 {"UL9", NULL, "O009"}, 1175 {"UL9", NULL, "O010"}, 1176 {"UL9", NULL, "O011"}, 1177 {"UL9", NULL, "O012"}, 1178 {"UL9", NULL, "O013"}, 1179 {"UL9", NULL, "O014"}, 1180 {"UL9", NULL, "O015"}, 1181 {"UL9", NULL, "O016"}, 1182 {"UL9", NULL, "O017"}, 1183 {"UL9", NULL, "O018"}, 1184 {"UL9", NULL, "O019"}, 1185 {"UL9", NULL, "O020"}, 1186 {"UL9", NULL, "O021"}, 1187 {"UL9", NULL, "O022"}, 1188 {"UL9", NULL, "O023"}, 1189 {"UL9", NULL, "O024"}, 1190 {"UL9", NULL, "O025"}, 1191 {"UL9", NULL, "O026"}, 1192 {"UL9", NULL, "O027"}, 1193 {"UL9", NULL, "O028"}, 1194 {"UL9", NULL, "O029"}, 1195 {"UL9", NULL, "O030"}, 1196 {"UL9", NULL, "O031"}, 1197 {"UL9", NULL, "O032"}, 1198 {"UL9", NULL, "O033"}, 1199 1200 {"UL4", NULL, "O034"}, 1201 {"UL4", NULL, "O035"}, 1202 1203 {"UL5", NULL, "O036"}, 1204 {"UL5", NULL, "O037"}, 1205 1206 {"UL10", NULL, "O038"}, 1207 {"UL10", NULL, "O039"}, 1208 {"UL10", NULL, "O182"}, 1209 {"UL10", NULL, "O183"}, 1210 1211 {"UL2", NULL, "O040"}, 1212 {"UL2", NULL, "O041"}, 1213 {"UL2", NULL, "O042"}, 1214 {"UL2", NULL, "O043"}, 1215 {"UL2", NULL, "O044"}, 1216 {"UL2", NULL, "O045"}, 1217 {"UL2", NULL, "O046"}, 1218 {"UL2", NULL, "O047"}, 1219 1220 {"O004", "I000 Switch", "I000"}, 1221 {"O005", "I001 Switch", "I001"}, 1222 1223 {"O006", "I000 Switch", "I000"}, 1224 {"O007", "I001 Switch", "I001"}, 1225 1226 {"O010", "I022 Switch", "I022"}, 1227 {"O011", "I023 Switch", "I023"}, 1228 {"O012", "I024 Switch", "I024"}, 1229 {"O013", "I025 Switch", "I025"}, 1230 {"O014", "I026 Switch", "I026"}, 1231 {"O015", "I027 Switch", "I027"}, 1232 {"O016", "I028 Switch", "I028"}, 1233 {"O017", "I029 Switch", "I029"}, 1234 1235 {"O010", "I046 Switch", "I046"}, 1236 {"O011", "I047 Switch", "I047"}, 1237 {"O012", "I048 Switch", "I048"}, 1238 {"O013", "I049 Switch", "I049"}, 1239 {"O014", "I050 Switch", "I050"}, 1240 {"O015", "I051 Switch", "I051"}, 1241 {"O016", "I052 Switch", "I052"}, 1242 {"O017", "I053 Switch", "I053"}, 1243 1244 {"O002", "I022 Switch", "I022"}, 1245 {"O003", "I023 Switch", "I023"}, 1246 {"O004", "I024 Switch", "I024"}, 1247 {"O005", "I025 Switch", "I025"}, 1248 {"O006", "I026 Switch", "I026"}, 1249 {"O007", "I027 Switch", "I027"}, 1250 {"O008", "I028 Switch", "I028"}, 1251 {"O009", "I029 Switch", "I029"}, 1252 {"O010", "I030 Switch", "I030"}, 1253 {"O011", "I031 Switch", "I031"}, 1254 {"O012", "I032 Switch", "I032"}, 1255 {"O013", "I033 Switch", "I033"}, 1256 {"O014", "I034 Switch", "I034"}, 1257 {"O015", "I035 Switch", "I035"}, 1258 {"O016", "I036 Switch", "I036"}, 1259 {"O017", "I037 Switch", "I037"}, 1260 {"O026", "I046 Switch", "I046"}, 1261 {"O027", "I047 Switch", "I047"}, 1262 {"O028", "I048 Switch", "I048"}, 1263 {"O029", "I049 Switch", "I049"}, 1264 {"O030", "I050 Switch", "I050"}, 1265 {"O031", "I051 Switch", "I051"}, 1266 {"O032", "I052 Switch", "I052"}, 1267 {"O033", "I053 Switch", "I053"}, 1268 1269 {"O002", "I000 Switch", "I000"}, 1270 {"O003", "I001 Switch", "I001"}, 1271 {"O002", "I020 Switch", "I020"}, 1272 {"O003", "I021 Switch", "I021"}, 1273 {"O002", "I070 Switch", "I070"}, 1274 {"O003", "I071 Switch", "I071"}, 1275 1276 {"O034", "I000 Switch", "I000"}, 1277 {"O035", "I001 Switch", "I001"}, 1278 {"O034", "I002 Switch", "I002"}, 1279 {"O035", "I003 Switch", "I003"}, 1280 {"O034", "I012 Switch", "I012"}, 1281 {"O035", "I013 Switch", "I013"}, 1282 {"O034", "I020 Switch", "I020"}, 1283 {"O035", "I021 Switch", "I021"}, 1284 {"O034", "I070 Switch", "I070"}, 1285 {"O035", "I071 Switch", "I071"}, 1286 {"O034", "I072 Switch", "I072"}, 1287 {"O035", "I073 Switch", "I073"}, 1288 1289 {"O036", "I000 Switch", "I000"}, 1290 {"O037", "I001 Switch", "I001"}, 1291 {"O036", "I012 Switch", "I012"}, 1292 {"O037", "I013 Switch", "I013"}, 1293 {"O036", "I020 Switch", "I020"}, 1294 {"O037", "I021 Switch", "I021"}, 1295 {"O036", "I070 Switch", "I070"}, 1296 {"O037", "I071 Switch", "I071"}, 1297 {"O036", "I168 Switch", "I168"}, 1298 {"O037", "I169 Switch", "I169"}, 1299 1300 {"O038", "I022 Switch", "I022"}, 1301 {"O039", "I023 Switch", "I023"}, 1302 {"O182", "I024 Switch", "I024"}, 1303 {"O183", "I025 Switch", "I025"}, 1304 1305 {"O038", "I168 Switch", "I168"}, 1306 {"O039", "I169 Switch", "I169"}, 1307 1308 {"O182", "I020 Switch", "I020"}, 1309 {"O183", "I021 Switch", "I021"}, 1310 1311 {"O182", "I022 Switch", "I022"}, 1312 {"O183", "I023 Switch", "I023"}, 1313 1314 {"O040", "I022 Switch", "I022"}, 1315 {"O041", "I023 Switch", "I023"}, 1316 {"O042", "I024 Switch", "I024"}, 1317 {"O043", "I025 Switch", "I025"}, 1318 {"O044", "I026 Switch", "I026"}, 1319 {"O045", "I027 Switch", "I027"}, 1320 {"O046", "I028 Switch", "I028"}, 1321 {"O047", "I029 Switch", "I029"}, 1322 1323 {"O040", "I002 Switch", "I002"}, 1324 {"O041", "I003 Switch", "I003"}, 1325 1326 {"O002", "I012 Switch", "I012"}, 1327 {"O003", "I013 Switch", "I013"}, 1328 {"O004", "I014 Switch", "I014"}, 1329 {"O005", "I015 Switch", "I015"}, 1330 {"O006", "I016 Switch", "I016"}, 1331 {"O007", "I017 Switch", "I017"}, 1332 {"O008", "I018 Switch", "I018"}, 1333 {"O009", "I019 Switch", "I019"}, 1334 {"O010", "I188 Switch", "I188"}, 1335 {"O011", "I189 Switch", "I189"}, 1336 {"O012", "I190 Switch", "I190"}, 1337 {"O013", "I191 Switch", "I191"}, 1338 {"O014", "I192 Switch", "I192"}, 1339 {"O015", "I193 Switch", "I193"}, 1340 {"O016", "I194 Switch", "I194"}, 1341 {"O017", "I195 Switch", "I195"}, 1342 1343 {"O040", "I012 Switch", "I012"}, 1344 {"O041", "I013 Switch", "I013"}, 1345 {"O042", "I014 Switch", "I014"}, 1346 {"O043", "I015 Switch", "I015"}, 1347 {"O044", "I016 Switch", "I016"}, 1348 {"O045", "I017 Switch", "I017"}, 1349 {"O046", "I018 Switch", "I018"}, 1350 {"O047", "I019 Switch", "I019"}, 1351 1352 {"O002", "I072 Switch", "I072"}, 1353 {"O003", "I073 Switch", "I073"}, 1354 {"O004", "I074 Switch", "I074"}, 1355 {"O005", "I075 Switch", "I075"}, 1356 {"O006", "I076 Switch", "I076"}, 1357 {"O007", "I077 Switch", "I077"}, 1358 {"O008", "I078 Switch", "I078"}, 1359 {"O009", "I079 Switch", "I079"}, 1360 {"O010", "I080 Switch", "I080"}, 1361 {"O011", "I081 Switch", "I081"}, 1362 {"O012", "I082 Switch", "I082"}, 1363 {"O013", "I083 Switch", "I083"}, 1364 {"O014", "I084 Switch", "I084"}, 1365 {"O015", "I085 Switch", "I085"}, 1366 {"O016", "I086 Switch", "I086"}, 1367 {"O017", "I087 Switch", "I087"}, 1368 1369 {"O010", "I072 Switch", "I072"}, 1370 {"O011", "I073 Switch", "I073"}, 1371 {"O012", "I074 Switch", "I074"}, 1372 {"O013", "I075 Switch", "I075"}, 1373 {"O014", "I076 Switch", "I076"}, 1374 {"O015", "I077 Switch", "I077"}, 1375 {"O016", "I078 Switch", "I078"}, 1376 {"O017", "I079 Switch", "I079"}, 1377 {"O018", "I080 Switch", "I080"}, 1378 {"O019", "I081 Switch", "I081"}, 1379 {"O020", "I082 Switch", "I082"}, 1380 {"O021", "I083 Switch", "I083"}, 1381 {"O022", "I084 Switch", "I084"}, 1382 {"O023", "I085 Switch", "I085"}, 1383 {"O024", "I086 Switch", "I086"}, 1384 {"O025", "I087 Switch", "I087"}, 1385 1386 {"O002", "I168 Switch", "I168"}, 1387 {"O003", "I169 Switch", "I169"}, 1388 1389 {"O034", "I168 Switch", "I168"}, 1390 {"O035", "I168 Switch", "I168"}, 1391 {"O035", "I169 Switch", "I169"}, 1392 1393 {"O040", "I168 Switch", "I168"}, 1394 {"O041", "I169 Switch", "I169"}, 1395 }; 1396 1397 static const struct snd_soc_component_driver mt8188_afe_pcm_dai_component = { 1398 .name = "mt8188-afe-pcm-dai", 1399 }; 1400 1401 static const struct mtk_base_memif_data memif_data[MT8188_AFE_MEMIF_NUM] = { 1402 [MT8188_AFE_MEMIF_DL2] = { 1403 .name = "DL2", 1404 .id = MT8188_AFE_MEMIF_DL2, 1405 .reg_ofs_base = AFE_DL2_BASE, 1406 .reg_ofs_cur = AFE_DL2_CUR, 1407 .reg_ofs_end = AFE_DL2_END, 1408 .fs_reg = AFE_MEMIF_AGENT_FS_CON0, 1409 .fs_shift = 10, 1410 .fs_maskbit = 0x1f, 1411 .mono_reg = -1, 1412 .mono_shift = 0, 1413 .int_odd_flag_reg = -1, 1414 .int_odd_flag_shift = 0, 1415 .enable_reg = AFE_DAC_CON0, 1416 .enable_shift = 18, 1417 .hd_reg = AFE_DL2_CON0, 1418 .hd_shift = 5, 1419 .agent_disable_reg = AUDIO_TOP_CON5, 1420 .agent_disable_shift = 18, 1421 .ch_num_reg = AFE_DL2_CON0, 1422 .ch_num_shift = 0, 1423 .ch_num_maskbit = 0x1f, 1424 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1425 .msb_shift = 18, 1426 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1427 .msb_end_shift = 18, 1428 }, 1429 [MT8188_AFE_MEMIF_DL3] = { 1430 .name = "DL3", 1431 .id = MT8188_AFE_MEMIF_DL3, 1432 .reg_ofs_base = AFE_DL3_BASE, 1433 .reg_ofs_cur = AFE_DL3_CUR, 1434 .reg_ofs_end = AFE_DL3_END, 1435 .fs_reg = AFE_MEMIF_AGENT_FS_CON0, 1436 .fs_shift = 15, 1437 .fs_maskbit = 0x1f, 1438 .mono_reg = -1, 1439 .mono_shift = 0, 1440 .int_odd_flag_reg = -1, 1441 .int_odd_flag_shift = 0, 1442 .enable_reg = AFE_DAC_CON0, 1443 .enable_shift = 19, 1444 .hd_reg = AFE_DL3_CON0, 1445 .hd_shift = 5, 1446 .agent_disable_reg = AUDIO_TOP_CON5, 1447 .agent_disable_shift = 19, 1448 .ch_num_reg = AFE_DL3_CON0, 1449 .ch_num_shift = 0, 1450 .ch_num_maskbit = 0x1f, 1451 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1452 .msb_shift = 19, 1453 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1454 .msb_end_shift = 19, 1455 }, 1456 [MT8188_AFE_MEMIF_DL6] = { 1457 .name = "DL6", 1458 .id = MT8188_AFE_MEMIF_DL6, 1459 .reg_ofs_base = AFE_DL6_BASE, 1460 .reg_ofs_cur = AFE_DL6_CUR, 1461 .reg_ofs_end = AFE_DL6_END, 1462 .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 1463 .fs_shift = 0, 1464 .fs_maskbit = 0x1f, 1465 .mono_reg = -1, 1466 .mono_shift = 0, 1467 .int_odd_flag_reg = -1, 1468 .int_odd_flag_shift = 0, 1469 .enable_reg = AFE_DAC_CON0, 1470 .enable_shift = 22, 1471 .hd_reg = AFE_DL6_CON0, 1472 .hd_shift = 5, 1473 .agent_disable_reg = AUDIO_TOP_CON5, 1474 .agent_disable_shift = 22, 1475 .ch_num_reg = AFE_DL6_CON0, 1476 .ch_num_shift = 0, 1477 .ch_num_maskbit = 0x1f, 1478 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1479 .msb_shift = 22, 1480 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1481 .msb_end_shift = 22, 1482 }, 1483 [MT8188_AFE_MEMIF_DL7] = { 1484 .name = "DL7", 1485 .id = MT8188_AFE_MEMIF_DL7, 1486 .reg_ofs_base = AFE_DL7_BASE, 1487 .reg_ofs_cur = AFE_DL7_CUR, 1488 .reg_ofs_end = AFE_DL7_END, 1489 .fs_reg = -1, 1490 .fs_shift = 0, 1491 .fs_maskbit = 0, 1492 .mono_reg = -1, 1493 .mono_shift = 0, 1494 .int_odd_flag_reg = -1, 1495 .int_odd_flag_shift = 0, 1496 .enable_reg = AFE_DAC_CON0, 1497 .enable_shift = 23, 1498 .hd_reg = AFE_DL7_CON0, 1499 .hd_shift = 5, 1500 .agent_disable_reg = AUDIO_TOP_CON5, 1501 .agent_disable_shift = 23, 1502 .ch_num_reg = AFE_DL7_CON0, 1503 .ch_num_shift = 0, 1504 .ch_num_maskbit = 0x1f, 1505 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1506 .msb_shift = 23, 1507 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1508 .msb_end_shift = 23, 1509 }, 1510 [MT8188_AFE_MEMIF_DL8] = { 1511 .name = "DL8", 1512 .id = MT8188_AFE_MEMIF_DL8, 1513 .reg_ofs_base = AFE_DL8_BASE, 1514 .reg_ofs_cur = AFE_DL8_CUR, 1515 .reg_ofs_end = AFE_DL8_END, 1516 .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 1517 .fs_shift = 10, 1518 .fs_maskbit = 0x1f, 1519 .mono_reg = -1, 1520 .mono_shift = 0, 1521 .int_odd_flag_reg = -1, 1522 .int_odd_flag_shift = 0, 1523 .enable_reg = AFE_DAC_CON0, 1524 .enable_shift = 24, 1525 .hd_reg = AFE_DL8_CON0, 1526 .hd_shift = 6, 1527 .agent_disable_reg = AUDIO_TOP_CON5, 1528 .agent_disable_shift = 24, 1529 .ch_num_reg = AFE_DL8_CON0, 1530 .ch_num_shift = 0, 1531 .ch_num_maskbit = 0x3f, 1532 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1533 .msb_shift = 24, 1534 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1535 .msb_end_shift = 24, 1536 }, 1537 [MT8188_AFE_MEMIF_DL10] = { 1538 .name = "DL10", 1539 .id = MT8188_AFE_MEMIF_DL10, 1540 .reg_ofs_base = AFE_DL10_BASE, 1541 .reg_ofs_cur = AFE_DL10_CUR, 1542 .reg_ofs_end = AFE_DL10_END, 1543 .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 1544 .fs_shift = 20, 1545 .fs_maskbit = 0x1f, 1546 .mono_reg = -1, 1547 .mono_shift = 0, 1548 .int_odd_flag_reg = -1, 1549 .int_odd_flag_shift = 0, 1550 .enable_reg = AFE_DAC_CON0, 1551 .enable_shift = 26, 1552 .hd_reg = AFE_DL10_CON0, 1553 .hd_shift = 5, 1554 .agent_disable_reg = AUDIO_TOP_CON5, 1555 .agent_disable_shift = 26, 1556 .ch_num_reg = AFE_DL10_CON0, 1557 .ch_num_shift = 0, 1558 .ch_num_maskbit = 0x1f, 1559 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1560 .msb_shift = 26, 1561 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1562 .msb_end_shift = 26, 1563 }, 1564 [MT8188_AFE_MEMIF_DL11] = { 1565 .name = "DL11", 1566 .id = MT8188_AFE_MEMIF_DL11, 1567 .reg_ofs_base = AFE_DL11_BASE, 1568 .reg_ofs_cur = AFE_DL11_CUR, 1569 .reg_ofs_end = AFE_DL11_END, 1570 .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 1571 .fs_shift = 25, 1572 .fs_maskbit = 0x1f, 1573 .mono_reg = -1, 1574 .mono_shift = 0, 1575 .int_odd_flag_reg = -1, 1576 .int_odd_flag_shift = 0, 1577 .enable_reg = AFE_DAC_CON0, 1578 .enable_shift = 27, 1579 .hd_reg = AFE_DL11_CON0, 1580 .hd_shift = 7, 1581 .agent_disable_reg = AUDIO_TOP_CON5, 1582 .agent_disable_shift = 27, 1583 .ch_num_reg = AFE_DL11_CON0, 1584 .ch_num_shift = 0, 1585 .ch_num_maskbit = 0x7f, 1586 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1587 .msb_shift = 27, 1588 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1589 .msb_end_shift = 27, 1590 }, 1591 [MT8188_AFE_MEMIF_UL1] = { 1592 .name = "UL1", 1593 .id = MT8188_AFE_MEMIF_UL1, 1594 .reg_ofs_base = AFE_UL1_BASE, 1595 .reg_ofs_cur = AFE_UL1_CUR, 1596 .reg_ofs_end = AFE_UL1_END, 1597 .fs_reg = -1, 1598 .fs_shift = 0, 1599 .fs_maskbit = 0, 1600 .mono_reg = AFE_UL1_CON0, 1601 .mono_shift = 1, 1602 .int_odd_flag_reg = AFE_UL1_CON0, 1603 .int_odd_flag_shift = 0, 1604 .enable_reg = AFE_DAC_CON0, 1605 .enable_shift = 1, 1606 .hd_reg = AFE_UL1_CON0, 1607 .hd_shift = 5, 1608 .agent_disable_reg = AUDIO_TOP_CON5, 1609 .agent_disable_shift = 0, 1610 .ch_num_reg = -1, 1611 .ch_num_shift = 0, 1612 .ch_num_maskbit = 0, 1613 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1614 .msb_shift = 0, 1615 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1616 .msb_end_shift = 0, 1617 }, 1618 [MT8188_AFE_MEMIF_UL2] = { 1619 .name = "UL2", 1620 .id = MT8188_AFE_MEMIF_UL2, 1621 .reg_ofs_base = AFE_UL2_BASE, 1622 .reg_ofs_cur = AFE_UL2_CUR, 1623 .reg_ofs_end = AFE_UL2_END, 1624 .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 1625 .fs_shift = 5, 1626 .fs_maskbit = 0x1f, 1627 .mono_reg = AFE_UL2_CON0, 1628 .mono_shift = 1, 1629 .int_odd_flag_reg = AFE_UL2_CON0, 1630 .int_odd_flag_shift = 0, 1631 .enable_reg = AFE_DAC_CON0, 1632 .enable_shift = 2, 1633 .hd_reg = AFE_UL2_CON0, 1634 .hd_shift = 5, 1635 .agent_disable_reg = AUDIO_TOP_CON5, 1636 .agent_disable_shift = 1, 1637 .ch_num_reg = -1, 1638 .ch_num_shift = 0, 1639 .ch_num_maskbit = 0, 1640 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1641 .msb_shift = 1, 1642 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1643 .msb_end_shift = 1, 1644 }, 1645 [MT8188_AFE_MEMIF_UL3] = { 1646 .name = "UL3", 1647 .id = MT8188_AFE_MEMIF_UL3, 1648 .reg_ofs_base = AFE_UL3_BASE, 1649 .reg_ofs_cur = AFE_UL3_CUR, 1650 .reg_ofs_end = AFE_UL3_END, 1651 .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 1652 .fs_shift = 10, 1653 .fs_maskbit = 0x1f, 1654 .mono_reg = AFE_UL3_CON0, 1655 .mono_shift = 1, 1656 .int_odd_flag_reg = AFE_UL3_CON0, 1657 .int_odd_flag_shift = 0, 1658 .enable_reg = AFE_DAC_CON0, 1659 .enable_shift = 3, 1660 .hd_reg = AFE_UL3_CON0, 1661 .hd_shift = 5, 1662 .agent_disable_reg = AUDIO_TOP_CON5, 1663 .agent_disable_shift = 2, 1664 .ch_num_reg = -1, 1665 .ch_num_shift = 0, 1666 .ch_num_maskbit = 0, 1667 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1668 .msb_shift = 2, 1669 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1670 .msb_end_shift = 2, 1671 }, 1672 [MT8188_AFE_MEMIF_UL4] = { 1673 .name = "UL4", 1674 .id = MT8188_AFE_MEMIF_UL4, 1675 .reg_ofs_base = AFE_UL4_BASE, 1676 .reg_ofs_cur = AFE_UL4_CUR, 1677 .reg_ofs_end = AFE_UL4_END, 1678 .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 1679 .fs_shift = 15, 1680 .fs_maskbit = 0x1f, 1681 .mono_reg = AFE_UL4_CON0, 1682 .mono_shift = 1, 1683 .int_odd_flag_reg = AFE_UL4_CON0, 1684 .int_odd_flag_shift = 0, 1685 .enable_reg = AFE_DAC_CON0, 1686 .enable_shift = 4, 1687 .hd_reg = AFE_UL4_CON0, 1688 .hd_shift = 5, 1689 .agent_disable_reg = AUDIO_TOP_CON5, 1690 .agent_disable_shift = 3, 1691 .ch_num_reg = -1, 1692 .ch_num_shift = 0, 1693 .ch_num_maskbit = 0, 1694 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1695 .msb_shift = 3, 1696 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1697 .msb_end_shift = 3, 1698 }, 1699 [MT8188_AFE_MEMIF_UL5] = { 1700 .name = "UL5", 1701 .id = MT8188_AFE_MEMIF_UL5, 1702 .reg_ofs_base = AFE_UL5_BASE, 1703 .reg_ofs_cur = AFE_UL5_CUR, 1704 .reg_ofs_end = AFE_UL5_END, 1705 .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 1706 .fs_shift = 20, 1707 .fs_maskbit = 0x1f, 1708 .mono_reg = AFE_UL5_CON0, 1709 .mono_shift = 1, 1710 .int_odd_flag_reg = AFE_UL5_CON0, 1711 .int_odd_flag_shift = 0, 1712 .enable_reg = AFE_DAC_CON0, 1713 .enable_shift = 5, 1714 .hd_reg = AFE_UL5_CON0, 1715 .hd_shift = 5, 1716 .agent_disable_reg = AUDIO_TOP_CON5, 1717 .agent_disable_shift = 4, 1718 .ch_num_reg = -1, 1719 .ch_num_shift = 0, 1720 .ch_num_maskbit = 0, 1721 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1722 .msb_shift = 4, 1723 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1724 .msb_end_shift = 4, 1725 }, 1726 [MT8188_AFE_MEMIF_UL6] = { 1727 .name = "UL6", 1728 .id = MT8188_AFE_MEMIF_UL6, 1729 .reg_ofs_base = AFE_UL6_BASE, 1730 .reg_ofs_cur = AFE_UL6_CUR, 1731 .reg_ofs_end = AFE_UL6_END, 1732 .fs_reg = -1, 1733 .fs_shift = 0, 1734 .fs_maskbit = 0, 1735 .mono_reg = AFE_UL6_CON0, 1736 .mono_shift = 1, 1737 .int_odd_flag_reg = AFE_UL6_CON0, 1738 .int_odd_flag_shift = 0, 1739 .enable_reg = AFE_DAC_CON0, 1740 .enable_shift = 6, 1741 .hd_reg = AFE_UL6_CON0, 1742 .hd_shift = 5, 1743 .agent_disable_reg = AUDIO_TOP_CON5, 1744 .agent_disable_shift = 5, 1745 .ch_num_reg = -1, 1746 .ch_num_shift = 0, 1747 .ch_num_maskbit = 0, 1748 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1749 .msb_shift = 5, 1750 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1751 .msb_end_shift = 5, 1752 }, 1753 [MT8188_AFE_MEMIF_UL8] = { 1754 .name = "UL8", 1755 .id = MT8188_AFE_MEMIF_UL8, 1756 .reg_ofs_base = AFE_UL8_BASE, 1757 .reg_ofs_cur = AFE_UL8_CUR, 1758 .reg_ofs_end = AFE_UL8_END, 1759 .fs_reg = AFE_MEMIF_AGENT_FS_CON3, 1760 .fs_shift = 5, 1761 .fs_maskbit = 0x1f, 1762 .mono_reg = AFE_UL8_CON0, 1763 .mono_shift = 1, 1764 .int_odd_flag_reg = AFE_UL8_CON0, 1765 .int_odd_flag_shift = 0, 1766 .enable_reg = AFE_DAC_CON0, 1767 .enable_shift = 8, 1768 .hd_reg = AFE_UL8_CON0, 1769 .hd_shift = 5, 1770 .agent_disable_reg = AUDIO_TOP_CON5, 1771 .agent_disable_shift = 7, 1772 .ch_num_reg = -1, 1773 .ch_num_shift = 0, 1774 .ch_num_maskbit = 0, 1775 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1776 .msb_shift = 7, 1777 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1778 .msb_end_shift = 7, 1779 }, 1780 [MT8188_AFE_MEMIF_UL9] = { 1781 .name = "UL9", 1782 .id = MT8188_AFE_MEMIF_UL9, 1783 .reg_ofs_base = AFE_UL9_BASE, 1784 .reg_ofs_cur = AFE_UL9_CUR, 1785 .reg_ofs_end = AFE_UL9_END, 1786 .fs_reg = AFE_MEMIF_AGENT_FS_CON3, 1787 .fs_shift = 10, 1788 .fs_maskbit = 0x1f, 1789 .mono_reg = AFE_UL9_CON0, 1790 .mono_shift = 1, 1791 .int_odd_flag_reg = AFE_UL9_CON0, 1792 .int_odd_flag_shift = 0, 1793 .enable_reg = AFE_DAC_CON0, 1794 .enable_shift = 9, 1795 .hd_reg = AFE_UL9_CON0, 1796 .hd_shift = 5, 1797 .agent_disable_reg = AUDIO_TOP_CON5, 1798 .agent_disable_shift = 8, 1799 .ch_num_reg = -1, 1800 .ch_num_shift = 0, 1801 .ch_num_maskbit = 0, 1802 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1803 .msb_shift = 8, 1804 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1805 .msb_end_shift = 8, 1806 }, 1807 [MT8188_AFE_MEMIF_UL10] = { 1808 .name = "UL10", 1809 .id = MT8188_AFE_MEMIF_UL10, 1810 .reg_ofs_base = AFE_UL10_BASE, 1811 .reg_ofs_cur = AFE_UL10_CUR, 1812 .reg_ofs_end = AFE_UL10_END, 1813 .fs_reg = AFE_MEMIF_AGENT_FS_CON3, 1814 .fs_shift = 15, 1815 .fs_maskbit = 0x1f, 1816 .mono_reg = AFE_UL10_CON0, 1817 .mono_shift = 1, 1818 .int_odd_flag_reg = AFE_UL10_CON0, 1819 .int_odd_flag_shift = 0, 1820 .enable_reg = AFE_DAC_CON0, 1821 .enable_shift = 10, 1822 .hd_reg = AFE_UL10_CON0, 1823 .hd_shift = 5, 1824 .agent_disable_reg = AUDIO_TOP_CON5, 1825 .agent_disable_shift = 9, 1826 .ch_num_reg = -1, 1827 .ch_num_shift = 0, 1828 .ch_num_maskbit = 0, 1829 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1830 .msb_shift = 9, 1831 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1832 .msb_end_shift = 9, 1833 }, 1834 }; 1835 1836 static const struct mtk_base_irq_data irq_data[MT8188_AFE_IRQ_NUM] = { 1837 [MT8188_AFE_IRQ_1] = { 1838 .id = MT8188_AFE_IRQ_1, 1839 .irq_cnt_reg = -1, 1840 .irq_cnt_shift = 0, 1841 .irq_cnt_maskbit = 0, 1842 .irq_fs_reg = -1, 1843 .irq_fs_shift = 0, 1844 .irq_fs_maskbit = 0, 1845 .irq_en_reg = AFE_IRQ1_CON, 1846 .irq_en_shift = 31, 1847 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1848 .irq_clr_shift = 0, 1849 .irq_status_shift = 16, 1850 }, 1851 [MT8188_AFE_IRQ_2] = { 1852 .id = MT8188_AFE_IRQ_2, 1853 .irq_cnt_reg = -1, 1854 .irq_cnt_shift = 0, 1855 .irq_cnt_maskbit = 0, 1856 .irq_fs_reg = -1, 1857 .irq_fs_shift = 0, 1858 .irq_fs_maskbit = 0, 1859 .irq_en_reg = AFE_IRQ2_CON, 1860 .irq_en_shift = 31, 1861 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1862 .irq_clr_shift = 1, 1863 .irq_status_shift = 17, 1864 }, 1865 [MT8188_AFE_IRQ_3] = { 1866 .id = MT8188_AFE_IRQ_3, 1867 .irq_cnt_reg = AFE_IRQ3_CON, 1868 .irq_cnt_shift = 0, 1869 .irq_cnt_maskbit = 0xffffff, 1870 .irq_fs_reg = -1, 1871 .irq_fs_shift = 0, 1872 .irq_fs_maskbit = 0, 1873 .irq_en_reg = AFE_IRQ3_CON, 1874 .irq_en_shift = 31, 1875 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1876 .irq_clr_shift = 2, 1877 .irq_status_shift = 18, 1878 }, 1879 [MT8188_AFE_IRQ_8] = { 1880 .id = MT8188_AFE_IRQ_8, 1881 .irq_cnt_reg = -1, 1882 .irq_cnt_shift = 0, 1883 .irq_cnt_maskbit = 0, 1884 .irq_fs_reg = -1, 1885 .irq_fs_shift = 0, 1886 .irq_fs_maskbit = 0, 1887 .irq_en_reg = AFE_IRQ8_CON, 1888 .irq_en_shift = 31, 1889 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1890 .irq_clr_shift = 7, 1891 .irq_status_shift = 23, 1892 }, 1893 [MT8188_AFE_IRQ_9] = { 1894 .id = MT8188_AFE_IRQ_9, 1895 .irq_cnt_reg = AFE_IRQ9_CON, 1896 .irq_cnt_shift = 0, 1897 .irq_cnt_maskbit = 0xffffff, 1898 .irq_fs_reg = -1, 1899 .irq_fs_shift = 0, 1900 .irq_fs_maskbit = 0, 1901 .irq_en_reg = AFE_IRQ9_CON, 1902 .irq_en_shift = 31, 1903 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1904 .irq_clr_shift = 8, 1905 .irq_status_shift = 24, 1906 }, 1907 [MT8188_AFE_IRQ_10] = { 1908 .id = MT8188_AFE_IRQ_10, 1909 .irq_cnt_reg = -1, 1910 .irq_cnt_shift = 0, 1911 .irq_cnt_maskbit = 0, 1912 .irq_fs_reg = -1, 1913 .irq_fs_shift = 0, 1914 .irq_fs_maskbit = 0, 1915 .irq_en_reg = AFE_IRQ10_CON, 1916 .irq_en_shift = 31, 1917 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1918 .irq_clr_shift = 9, 1919 .irq_status_shift = 25, 1920 }, 1921 [MT8188_AFE_IRQ_13] = { 1922 .id = MT8188_AFE_IRQ_13, 1923 .irq_cnt_reg = ASYS_IRQ1_CON, 1924 .irq_cnt_shift = 0, 1925 .irq_cnt_maskbit = 0xffffff, 1926 .irq_fs_reg = ASYS_IRQ1_CON, 1927 .irq_fs_shift = 24, 1928 .irq_fs_maskbit = 0x1ffff, 1929 .irq_en_reg = ASYS_IRQ1_CON, 1930 .irq_en_shift = 31, 1931 .irq_clr_reg = ASYS_IRQ_CLR, 1932 .irq_clr_shift = 0, 1933 .irq_status_shift = 0, 1934 }, 1935 [MT8188_AFE_IRQ_14] = { 1936 .id = MT8188_AFE_IRQ_14, 1937 .irq_cnt_reg = ASYS_IRQ2_CON, 1938 .irq_cnt_shift = 0, 1939 .irq_cnt_maskbit = 0xffffff, 1940 .irq_fs_reg = ASYS_IRQ2_CON, 1941 .irq_fs_shift = 24, 1942 .irq_fs_maskbit = 0x1ffff, 1943 .irq_en_reg = ASYS_IRQ2_CON, 1944 .irq_en_shift = 31, 1945 .irq_clr_reg = ASYS_IRQ_CLR, 1946 .irq_clr_shift = 1, 1947 .irq_status_shift = 1, 1948 }, 1949 [MT8188_AFE_IRQ_15] = { 1950 .id = MT8188_AFE_IRQ_15, 1951 .irq_cnt_reg = ASYS_IRQ3_CON, 1952 .irq_cnt_shift = 0, 1953 .irq_cnt_maskbit = 0xffffff, 1954 .irq_fs_reg = ASYS_IRQ3_CON, 1955 .irq_fs_shift = 24, 1956 .irq_fs_maskbit = 0x1ffff, 1957 .irq_en_reg = ASYS_IRQ3_CON, 1958 .irq_en_shift = 31, 1959 .irq_clr_reg = ASYS_IRQ_CLR, 1960 .irq_clr_shift = 2, 1961 .irq_status_shift = 2, 1962 }, 1963 [MT8188_AFE_IRQ_16] = { 1964 .id = MT8188_AFE_IRQ_16, 1965 .irq_cnt_reg = ASYS_IRQ4_CON, 1966 .irq_cnt_shift = 0, 1967 .irq_cnt_maskbit = 0xffffff, 1968 .irq_fs_reg = ASYS_IRQ4_CON, 1969 .irq_fs_shift = 24, 1970 .irq_fs_maskbit = 0x1ffff, 1971 .irq_en_reg = ASYS_IRQ4_CON, 1972 .irq_en_shift = 31, 1973 .irq_clr_reg = ASYS_IRQ_CLR, 1974 .irq_clr_shift = 3, 1975 .irq_status_shift = 3, 1976 }, 1977 [MT8188_AFE_IRQ_17] = { 1978 .id = MT8188_AFE_IRQ_17, 1979 .irq_cnt_reg = ASYS_IRQ5_CON, 1980 .irq_cnt_shift = 0, 1981 .irq_cnt_maskbit = 0xffffff, 1982 .irq_fs_reg = ASYS_IRQ5_CON, 1983 .irq_fs_shift = 24, 1984 .irq_fs_maskbit = 0x1ffff, 1985 .irq_en_reg = ASYS_IRQ5_CON, 1986 .irq_en_shift = 31, 1987 .irq_clr_reg = ASYS_IRQ_CLR, 1988 .irq_clr_shift = 4, 1989 .irq_status_shift = 4, 1990 }, 1991 [MT8188_AFE_IRQ_18] = { 1992 .id = MT8188_AFE_IRQ_18, 1993 .irq_cnt_reg = ASYS_IRQ6_CON, 1994 .irq_cnt_shift = 0, 1995 .irq_cnt_maskbit = 0xffffff, 1996 .irq_fs_reg = ASYS_IRQ6_CON, 1997 .irq_fs_shift = 24, 1998 .irq_fs_maskbit = 0x1ffff, 1999 .irq_en_reg = ASYS_IRQ6_CON, 2000 .irq_en_shift = 31, 2001 .irq_clr_reg = ASYS_IRQ_CLR, 2002 .irq_clr_shift = 5, 2003 .irq_status_shift = 5, 2004 }, 2005 [MT8188_AFE_IRQ_19] = { 2006 .id = MT8188_AFE_IRQ_19, 2007 .irq_cnt_reg = ASYS_IRQ7_CON, 2008 .irq_cnt_shift = 0, 2009 .irq_cnt_maskbit = 0xffffff, 2010 .irq_fs_reg = ASYS_IRQ7_CON, 2011 .irq_fs_shift = 24, 2012 .irq_fs_maskbit = 0x1ffff, 2013 .irq_en_reg = ASYS_IRQ7_CON, 2014 .irq_en_shift = 31, 2015 .irq_clr_reg = ASYS_IRQ_CLR, 2016 .irq_clr_shift = 6, 2017 .irq_status_shift = 6, 2018 }, 2019 [MT8188_AFE_IRQ_20] = { 2020 .id = MT8188_AFE_IRQ_20, 2021 .irq_cnt_reg = ASYS_IRQ8_CON, 2022 .irq_cnt_shift = 0, 2023 .irq_cnt_maskbit = 0xffffff, 2024 .irq_fs_reg = ASYS_IRQ8_CON, 2025 .irq_fs_shift = 24, 2026 .irq_fs_maskbit = 0x1ffff, 2027 .irq_en_reg = ASYS_IRQ8_CON, 2028 .irq_en_shift = 31, 2029 .irq_clr_reg = ASYS_IRQ_CLR, 2030 .irq_clr_shift = 7, 2031 .irq_status_shift = 7, 2032 }, 2033 [MT8188_AFE_IRQ_21] = { 2034 .id = MT8188_AFE_IRQ_21, 2035 .irq_cnt_reg = ASYS_IRQ9_CON, 2036 .irq_cnt_shift = 0, 2037 .irq_cnt_maskbit = 0xffffff, 2038 .irq_fs_reg = ASYS_IRQ9_CON, 2039 .irq_fs_shift = 24, 2040 .irq_fs_maskbit = 0x1ffff, 2041 .irq_en_reg = ASYS_IRQ9_CON, 2042 .irq_en_shift = 31, 2043 .irq_clr_reg = ASYS_IRQ_CLR, 2044 .irq_clr_shift = 8, 2045 .irq_status_shift = 8, 2046 }, 2047 [MT8188_AFE_IRQ_22] = { 2048 .id = MT8188_AFE_IRQ_22, 2049 .irq_cnt_reg = ASYS_IRQ10_CON, 2050 .irq_cnt_shift = 0, 2051 .irq_cnt_maskbit = 0xffffff, 2052 .irq_fs_reg = ASYS_IRQ10_CON, 2053 .irq_fs_shift = 24, 2054 .irq_fs_maskbit = 0x1ffff, 2055 .irq_en_reg = ASYS_IRQ10_CON, 2056 .irq_en_shift = 31, 2057 .irq_clr_reg = ASYS_IRQ_CLR, 2058 .irq_clr_shift = 9, 2059 .irq_status_shift = 9, 2060 }, 2061 [MT8188_AFE_IRQ_23] = { 2062 .id = MT8188_AFE_IRQ_23, 2063 .irq_cnt_reg = ASYS_IRQ11_CON, 2064 .irq_cnt_shift = 0, 2065 .irq_cnt_maskbit = 0xffffff, 2066 .irq_fs_reg = ASYS_IRQ11_CON, 2067 .irq_fs_shift = 24, 2068 .irq_fs_maskbit = 0x1ffff, 2069 .irq_en_reg = ASYS_IRQ11_CON, 2070 .irq_en_shift = 31, 2071 .irq_clr_reg = ASYS_IRQ_CLR, 2072 .irq_clr_shift = 10, 2073 .irq_status_shift = 10, 2074 }, 2075 [MT8188_AFE_IRQ_24] = { 2076 .id = MT8188_AFE_IRQ_24, 2077 .irq_cnt_reg = ASYS_IRQ12_CON, 2078 .irq_cnt_shift = 0, 2079 .irq_cnt_maskbit = 0xffffff, 2080 .irq_fs_reg = ASYS_IRQ12_CON, 2081 .irq_fs_shift = 24, 2082 .irq_fs_maskbit = 0x1ffff, 2083 .irq_en_reg = ASYS_IRQ12_CON, 2084 .irq_en_shift = 31, 2085 .irq_clr_reg = ASYS_IRQ_CLR, 2086 .irq_clr_shift = 11, 2087 .irq_status_shift = 11, 2088 }, 2089 [MT8188_AFE_IRQ_25] = { 2090 .id = MT8188_AFE_IRQ_25, 2091 .irq_cnt_reg = ASYS_IRQ13_CON, 2092 .irq_cnt_shift = 0, 2093 .irq_cnt_maskbit = 0xffffff, 2094 .irq_fs_reg = ASYS_IRQ13_CON, 2095 .irq_fs_shift = 24, 2096 .irq_fs_maskbit = 0x1ffff, 2097 .irq_en_reg = ASYS_IRQ13_CON, 2098 .irq_en_shift = 31, 2099 .irq_clr_reg = ASYS_IRQ_CLR, 2100 .irq_clr_shift = 12, 2101 .irq_status_shift = 12, 2102 }, 2103 [MT8188_AFE_IRQ_26] = { 2104 .id = MT8188_AFE_IRQ_26, 2105 .irq_cnt_reg = ASYS_IRQ14_CON, 2106 .irq_cnt_shift = 0, 2107 .irq_cnt_maskbit = 0xffffff, 2108 .irq_fs_reg = ASYS_IRQ14_CON, 2109 .irq_fs_shift = 24, 2110 .irq_fs_maskbit = 0x1ffff, 2111 .irq_en_reg = ASYS_IRQ14_CON, 2112 .irq_en_shift = 31, 2113 .irq_clr_reg = ASYS_IRQ_CLR, 2114 .irq_clr_shift = 13, 2115 .irq_status_shift = 13, 2116 }, 2117 [MT8188_AFE_IRQ_27] = { 2118 .id = MT8188_AFE_IRQ_27, 2119 .irq_cnt_reg = ASYS_IRQ15_CON, 2120 .irq_cnt_shift = 0, 2121 .irq_cnt_maskbit = 0xffffff, 2122 .irq_fs_reg = ASYS_IRQ15_CON, 2123 .irq_fs_shift = 24, 2124 .irq_fs_maskbit = 0x1ffff, 2125 .irq_en_reg = ASYS_IRQ15_CON, 2126 .irq_en_shift = 31, 2127 .irq_clr_reg = ASYS_IRQ_CLR, 2128 .irq_clr_shift = 14, 2129 .irq_status_shift = 14, 2130 }, 2131 [MT8188_AFE_IRQ_28] = { 2132 .id = MT8188_AFE_IRQ_28, 2133 .irq_cnt_reg = ASYS_IRQ16_CON, 2134 .irq_cnt_shift = 0, 2135 .irq_cnt_maskbit = 0xffffff, 2136 .irq_fs_reg = ASYS_IRQ16_CON, 2137 .irq_fs_shift = 24, 2138 .irq_fs_maskbit = 0x1ffff, 2139 .irq_en_reg = ASYS_IRQ16_CON, 2140 .irq_en_shift = 31, 2141 .irq_clr_reg = ASYS_IRQ_CLR, 2142 .irq_clr_shift = 15, 2143 .irq_status_shift = 15, 2144 }, 2145 }; 2146 2147 static const int mt8188_afe_memif_const_irqs[MT8188_AFE_MEMIF_NUM] = { 2148 [MT8188_AFE_MEMIF_DL2] = MT8188_AFE_IRQ_13, 2149 [MT8188_AFE_MEMIF_DL3] = MT8188_AFE_IRQ_14, 2150 [MT8188_AFE_MEMIF_DL6] = MT8188_AFE_IRQ_15, 2151 [MT8188_AFE_MEMIF_DL7] = MT8188_AFE_IRQ_1, 2152 [MT8188_AFE_MEMIF_DL8] = MT8188_AFE_IRQ_16, 2153 [MT8188_AFE_MEMIF_DL10] = MT8188_AFE_IRQ_17, 2154 [MT8188_AFE_MEMIF_DL11] = MT8188_AFE_IRQ_18, 2155 [MT8188_AFE_MEMIF_UL1] = MT8188_AFE_IRQ_3, 2156 [MT8188_AFE_MEMIF_UL2] = MT8188_AFE_IRQ_19, 2157 [MT8188_AFE_MEMIF_UL3] = MT8188_AFE_IRQ_20, 2158 [MT8188_AFE_MEMIF_UL4] = MT8188_AFE_IRQ_21, 2159 [MT8188_AFE_MEMIF_UL5] = MT8188_AFE_IRQ_22, 2160 [MT8188_AFE_MEMIF_UL6] = MT8188_AFE_IRQ_9, 2161 [MT8188_AFE_MEMIF_UL8] = MT8188_AFE_IRQ_23, 2162 [MT8188_AFE_MEMIF_UL9] = MT8188_AFE_IRQ_24, 2163 [MT8188_AFE_MEMIF_UL10] = MT8188_AFE_IRQ_25, 2164 }; 2165 2166 static bool mt8188_is_volatile_reg(struct device *dev, unsigned int reg) 2167 { 2168 /* these auto-gen reg has read-only bit, so put it as volatile */ 2169 /* volatile reg cannot be cached, so cannot be set when power off */ 2170 switch (reg) { 2171 case AUDIO_TOP_CON0: 2172 case AUDIO_TOP_CON1: 2173 case AUDIO_TOP_CON3: 2174 case AUDIO_TOP_CON4: 2175 case AUDIO_TOP_CON5: 2176 case AUDIO_TOP_CON6: 2177 case ASYS_IRQ_CLR: 2178 case ASYS_IRQ_STATUS: 2179 case ASYS_IRQ_MON1: 2180 case ASYS_IRQ_MON2: 2181 case AFE_IRQ_MCU_CLR: 2182 case AFE_IRQ_STATUS: 2183 case AFE_IRQ3_CON_MON: 2184 case AFE_IRQ_MCU_MON2: 2185 case ADSP_IRQ_STATUS: 2186 case AUDIO_TOP_STA0: 2187 case AUDIO_TOP_STA1: 2188 case AFE_GAIN1_CUR: 2189 case AFE_GAIN2_CUR: 2190 case AFE_IEC_BURST_INFO: 2191 case AFE_IEC_CHL_STAT0: 2192 case AFE_IEC_CHL_STAT1: 2193 case AFE_IEC_CHR_STAT0: 2194 case AFE_IEC_CHR_STAT1: 2195 case AFE_SPDIFIN_CHSTS1: 2196 case AFE_SPDIFIN_CHSTS2: 2197 case AFE_SPDIFIN_CHSTS3: 2198 case AFE_SPDIFIN_CHSTS4: 2199 case AFE_SPDIFIN_CHSTS5: 2200 case AFE_SPDIFIN_CHSTS6: 2201 case AFE_SPDIFIN_DEBUG1: 2202 case AFE_SPDIFIN_DEBUG2: 2203 case AFE_SPDIFIN_DEBUG3: 2204 case AFE_SPDIFIN_DEBUG4: 2205 case AFE_SPDIFIN_EC: 2206 case AFE_SPDIFIN_CKLOCK_CFG: 2207 case AFE_SPDIFIN_BR_DBG1: 2208 case AFE_SPDIFIN_CKFBDIV: 2209 case AFE_SPDIFIN_INT_EXT: 2210 case AFE_SPDIFIN_INT_EXT2: 2211 case SPDIFIN_FREQ_STATUS: 2212 case SPDIFIN_USERCODE1: 2213 case SPDIFIN_USERCODE2: 2214 case SPDIFIN_USERCODE3: 2215 case SPDIFIN_USERCODE4: 2216 case SPDIFIN_USERCODE5: 2217 case SPDIFIN_USERCODE6: 2218 case SPDIFIN_USERCODE7: 2219 case SPDIFIN_USERCODE8: 2220 case SPDIFIN_USERCODE9: 2221 case SPDIFIN_USERCODE10: 2222 case SPDIFIN_USERCODE11: 2223 case SPDIFIN_USERCODE12: 2224 case AFE_LINEIN_APLL_TUNER_MON: 2225 case AFE_EARC_APLL_TUNER_MON: 2226 case AFE_CM0_MON: 2227 case AFE_CM1_MON: 2228 case AFE_CM2_MON: 2229 case AFE_MPHONE_MULTI_DET_MON0: 2230 case AFE_MPHONE_MULTI_DET_MON1: 2231 case AFE_MPHONE_MULTI_DET_MON2: 2232 case AFE_MPHONE_MULTI2_DET_MON0: 2233 case AFE_MPHONE_MULTI2_DET_MON1: 2234 case AFE_MPHONE_MULTI2_DET_MON2: 2235 case AFE_ADDA_MTKAIF_MON0: 2236 case AFE_ADDA_MTKAIF_MON1: 2237 case AFE_AUD_PAD_TOP: 2238 case AFE_ADDA6_MTKAIF_MON0: 2239 case AFE_ADDA6_MTKAIF_MON1: 2240 case AFE_ADDA6_SRC_DEBUG_MON0: 2241 case AFE_ADDA6_UL_SRC_MON0: 2242 case AFE_ADDA6_UL_SRC_MON1: 2243 case AFE_ASRC11_NEW_CON8: 2244 case AFE_ASRC11_NEW_CON9: 2245 case AFE_ASRC12_NEW_CON8: 2246 case AFE_ASRC12_NEW_CON9: 2247 case AFE_LRCK_CNT: 2248 case AFE_DAC_MON0: 2249 case AFE_DL2_CUR: 2250 case AFE_DL3_CUR: 2251 case AFE_DL6_CUR: 2252 case AFE_DL7_CUR: 2253 case AFE_DL8_CUR: 2254 case AFE_DL10_CUR: 2255 case AFE_DL11_CUR: 2256 case AFE_UL1_CUR: 2257 case AFE_UL2_CUR: 2258 case AFE_UL3_CUR: 2259 case AFE_UL4_CUR: 2260 case AFE_UL5_CUR: 2261 case AFE_UL6_CUR: 2262 case AFE_UL8_CUR: 2263 case AFE_UL9_CUR: 2264 case AFE_UL10_CUR: 2265 case AFE_DL8_CHK_SUM1: 2266 case AFE_DL8_CHK_SUM2: 2267 case AFE_DL8_CHK_SUM3: 2268 case AFE_DL8_CHK_SUM4: 2269 case AFE_DL8_CHK_SUM5: 2270 case AFE_DL8_CHK_SUM6: 2271 case AFE_DL10_CHK_SUM1: 2272 case AFE_DL10_CHK_SUM2: 2273 case AFE_DL10_CHK_SUM3: 2274 case AFE_DL10_CHK_SUM4: 2275 case AFE_DL10_CHK_SUM5: 2276 case AFE_DL10_CHK_SUM6: 2277 case AFE_DL11_CHK_SUM1: 2278 case AFE_DL11_CHK_SUM2: 2279 case AFE_DL11_CHK_SUM3: 2280 case AFE_DL11_CHK_SUM4: 2281 case AFE_DL11_CHK_SUM5: 2282 case AFE_DL11_CHK_SUM6: 2283 case AFE_UL1_CHK_SUM1: 2284 case AFE_UL1_CHK_SUM2: 2285 case AFE_UL2_CHK_SUM1: 2286 case AFE_UL2_CHK_SUM2: 2287 case AFE_UL3_CHK_SUM1: 2288 case AFE_UL3_CHK_SUM2: 2289 case AFE_UL4_CHK_SUM1: 2290 case AFE_UL4_CHK_SUM2: 2291 case AFE_UL5_CHK_SUM1: 2292 case AFE_UL5_CHK_SUM2: 2293 case AFE_UL6_CHK_SUM1: 2294 case AFE_UL6_CHK_SUM2: 2295 case AFE_UL8_CHK_SUM1: 2296 case AFE_UL8_CHK_SUM2: 2297 case AFE_DL2_CHK_SUM1: 2298 case AFE_DL2_CHK_SUM2: 2299 case AFE_DL3_CHK_SUM1: 2300 case AFE_DL3_CHK_SUM2: 2301 case AFE_DL6_CHK_SUM1: 2302 case AFE_DL6_CHK_SUM2: 2303 case AFE_DL7_CHK_SUM1: 2304 case AFE_DL7_CHK_SUM2: 2305 case AFE_UL9_CHK_SUM1: 2306 case AFE_UL9_CHK_SUM2: 2307 case AFE_BUS_MON1: 2308 case UL1_MOD2AGT_CNT_LAT: 2309 case UL2_MOD2AGT_CNT_LAT: 2310 case UL3_MOD2AGT_CNT_LAT: 2311 case UL4_MOD2AGT_CNT_LAT: 2312 case UL5_MOD2AGT_CNT_LAT: 2313 case UL6_MOD2AGT_CNT_LAT: 2314 case UL8_MOD2AGT_CNT_LAT: 2315 case UL9_MOD2AGT_CNT_LAT: 2316 case UL10_MOD2AGT_CNT_LAT: 2317 case AFE_MEMIF_BUF_FULL_MON: 2318 case AFE_MEMIF_BUF_MON1: 2319 case AFE_MEMIF_BUF_MON3: 2320 case AFE_MEMIF_BUF_MON4: 2321 case AFE_MEMIF_BUF_MON5: 2322 case AFE_MEMIF_BUF_MON6: 2323 case AFE_MEMIF_BUF_MON7: 2324 case AFE_MEMIF_BUF_MON8: 2325 case AFE_MEMIF_BUF_MON9: 2326 case AFE_MEMIF_BUF_MON10: 2327 case DL2_AGENT2MODULE_CNT: 2328 case DL3_AGENT2MODULE_CNT: 2329 case DL6_AGENT2MODULE_CNT: 2330 case DL7_AGENT2MODULE_CNT: 2331 case DL8_AGENT2MODULE_CNT: 2332 case DL10_AGENT2MODULE_CNT: 2333 case DL11_AGENT2MODULE_CNT: 2334 case UL1_MODULE2AGENT_CNT: 2335 case UL2_MODULE2AGENT_CNT: 2336 case UL3_MODULE2AGENT_CNT: 2337 case UL4_MODULE2AGENT_CNT: 2338 case UL5_MODULE2AGENT_CNT: 2339 case UL6_MODULE2AGENT_CNT: 2340 case UL8_MODULE2AGENT_CNT: 2341 case UL9_MODULE2AGENT_CNT: 2342 case UL10_MODULE2AGENT_CNT: 2343 case AFE_DMIC0_SRC_DEBUG_MON0: 2344 case AFE_DMIC0_UL_SRC_MON0: 2345 case AFE_DMIC0_UL_SRC_MON1: 2346 case AFE_DMIC1_SRC_DEBUG_MON0: 2347 case AFE_DMIC1_UL_SRC_MON0: 2348 case AFE_DMIC1_UL_SRC_MON1: 2349 case AFE_DMIC2_SRC_DEBUG_MON0: 2350 case AFE_DMIC2_UL_SRC_MON0: 2351 case AFE_DMIC2_UL_SRC_MON1: 2352 case AFE_DMIC3_SRC_DEBUG_MON0: 2353 case AFE_DMIC3_UL_SRC_MON0: 2354 case AFE_DMIC3_UL_SRC_MON1: 2355 case DMIC_GAIN1_CUR: 2356 case DMIC_GAIN2_CUR: 2357 case DMIC_GAIN3_CUR: 2358 case DMIC_GAIN4_CUR: 2359 case ETDM_IN1_MONITOR: 2360 case ETDM_IN2_MONITOR: 2361 case ETDM_OUT1_MONITOR: 2362 case ETDM_OUT2_MONITOR: 2363 case ETDM_OUT3_MONITOR: 2364 case AFE_ADDA_SRC_DEBUG_MON0: 2365 case AFE_ADDA_SRC_DEBUG_MON1: 2366 case AFE_ADDA_DL_SDM_FIFO_MON: 2367 case AFE_ADDA_DL_SRC_LCH_MON: 2368 case AFE_ADDA_DL_SRC_RCH_MON: 2369 case AFE_ADDA_DL_SDM_OUT_MON: 2370 case AFE_GASRC0_NEW_CON8: 2371 case AFE_GASRC0_NEW_CON9: 2372 case AFE_GASRC0_NEW_CON12: 2373 case AFE_GASRC1_NEW_CON8: 2374 case AFE_GASRC1_NEW_CON9: 2375 case AFE_GASRC1_NEW_CON12: 2376 case AFE_GASRC2_NEW_CON8: 2377 case AFE_GASRC2_NEW_CON9: 2378 case AFE_GASRC2_NEW_CON12: 2379 case AFE_GASRC3_NEW_CON8: 2380 case AFE_GASRC3_NEW_CON9: 2381 case AFE_GASRC3_NEW_CON12: 2382 case AFE_GASRC4_NEW_CON8: 2383 case AFE_GASRC4_NEW_CON9: 2384 case AFE_GASRC4_NEW_CON12: 2385 case AFE_GASRC5_NEW_CON8: 2386 case AFE_GASRC5_NEW_CON9: 2387 case AFE_GASRC5_NEW_CON12: 2388 case AFE_GASRC6_NEW_CON8: 2389 case AFE_GASRC6_NEW_CON9: 2390 case AFE_GASRC6_NEW_CON12: 2391 case AFE_GASRC7_NEW_CON8: 2392 case AFE_GASRC7_NEW_CON9: 2393 case AFE_GASRC7_NEW_CON12: 2394 case AFE_GASRC8_NEW_CON8: 2395 case AFE_GASRC8_NEW_CON9: 2396 case AFE_GASRC8_NEW_CON12: 2397 case AFE_GASRC9_NEW_CON8: 2398 case AFE_GASRC9_NEW_CON9: 2399 case AFE_GASRC9_NEW_CON12: 2400 case AFE_GASRC10_NEW_CON8: 2401 case AFE_GASRC10_NEW_CON9: 2402 case AFE_GASRC10_NEW_CON12: 2403 case AFE_GASRC11_NEW_CON8: 2404 case AFE_GASRC11_NEW_CON9: 2405 case AFE_GASRC11_NEW_CON12: 2406 return true; 2407 default: 2408 return false; 2409 }; 2410 } 2411 2412 static const struct regmap_config mt8188_afe_regmap_config = { 2413 .reg_bits = 32, 2414 .reg_stride = 4, 2415 .val_bits = 32, 2416 .volatile_reg = mt8188_is_volatile_reg, 2417 .max_register = AFE_MAX_REGISTER, 2418 .num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1), 2419 .cache_type = REGCACHE_FLAT, 2420 }; 2421 2422 #define AFE_IRQ_CLR_BITS (0x387) 2423 #define ASYS_IRQ_CLR_BITS (0xffff) 2424 2425 static irqreturn_t mt8188_afe_irq_handler(int irq_id, void *dev_id) 2426 { 2427 struct mtk_base_afe *afe = dev_id; 2428 unsigned int val = 0; 2429 unsigned int asys_irq_clr_bits = 0; 2430 unsigned int afe_irq_clr_bits = 0; 2431 unsigned int irq_status_bits = 0; 2432 unsigned int irq_clr_bits = 0; 2433 unsigned int mcu_irq_mask = 0; 2434 int i = 0; 2435 int ret = 0; 2436 2437 ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &val); 2438 if (ret) { 2439 dev_err(afe->dev, "%s irq status err\n", __func__); 2440 afe_irq_clr_bits = AFE_IRQ_CLR_BITS; 2441 asys_irq_clr_bits = ASYS_IRQ_CLR_BITS; 2442 goto err_irq; 2443 } 2444 2445 ret = regmap_read(afe->regmap, AFE_IRQ_MASK, &mcu_irq_mask); 2446 if (ret) { 2447 dev_err(afe->dev, "%s read irq mask err\n", __func__); 2448 afe_irq_clr_bits = AFE_IRQ_CLR_BITS; 2449 asys_irq_clr_bits = ASYS_IRQ_CLR_BITS; 2450 goto err_irq; 2451 } 2452 2453 /* only clr cpu irq */ 2454 val &= mcu_irq_mask; 2455 2456 for (i = 0; i < MT8188_AFE_MEMIF_NUM; i++) { 2457 struct mtk_base_afe_memif *memif = &afe->memif[i]; 2458 struct mtk_base_irq_data const *irq_data; 2459 2460 if (memif->irq_usage < 0) 2461 continue; 2462 2463 irq_data = afe->irqs[memif->irq_usage].irq_data; 2464 2465 irq_status_bits = BIT(irq_data->irq_status_shift); 2466 irq_clr_bits = BIT(irq_data->irq_clr_shift); 2467 2468 if (!(val & irq_status_bits)) 2469 continue; 2470 2471 if (irq_data->irq_clr_reg == ASYS_IRQ_CLR) 2472 asys_irq_clr_bits |= irq_clr_bits; 2473 else 2474 afe_irq_clr_bits |= irq_clr_bits; 2475 2476 snd_pcm_period_elapsed(memif->substream); 2477 } 2478 2479 err_irq: 2480 /* clear irq */ 2481 if (asys_irq_clr_bits) 2482 regmap_write(afe->regmap, ASYS_IRQ_CLR, asys_irq_clr_bits); 2483 if (afe_irq_clr_bits) 2484 regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, afe_irq_clr_bits); 2485 2486 return IRQ_HANDLED; 2487 } 2488 2489 static int mt8188_afe_runtime_suspend(struct device *dev) 2490 { 2491 struct mtk_base_afe *afe = dev_get_drvdata(dev); 2492 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2493 2494 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) 2495 goto skip_regmap; 2496 2497 mt8188_afe_disable_main_clock(afe); 2498 2499 regcache_cache_only(afe->regmap, true); 2500 regcache_mark_dirty(afe->regmap); 2501 2502 skip_regmap: 2503 mt8188_afe_disable_reg_rw_clk(afe); 2504 2505 return 0; 2506 } 2507 2508 static int mt8188_afe_runtime_resume(struct device *dev) 2509 { 2510 struct mtk_base_afe *afe = dev_get_drvdata(dev); 2511 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2512 struct arm_smccc_res res; 2513 2514 arm_smccc_smc(MTK_SIP_AUDIO_CONTROL, 2515 MTK_AUDIO_SMC_OP_DOMAIN_SIDEBANDS, 2516 0, 0, 0, 0, 0, 0, &res); 2517 2518 mt8188_afe_enable_reg_rw_clk(afe); 2519 2520 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) 2521 goto skip_regmap; 2522 2523 regcache_cache_only(afe->regmap, false); 2524 regcache_sync(afe->regmap); 2525 2526 mt8188_afe_enable_main_clock(afe); 2527 skip_regmap: 2528 return 0; 2529 } 2530 2531 static int mt8188_afe_component_probe(struct snd_soc_component *component) 2532 { 2533 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 2534 int ret; 2535 2536 snd_soc_component_init_regmap(component, afe->regmap); 2537 2538 ret = mtk_afe_add_sub_dai_control(component); 2539 2540 return ret; 2541 } 2542 2543 static const struct snd_soc_component_driver mt8188_afe_component = { 2544 .name = AFE_PCM_NAME, 2545 .pointer = mtk_afe_pcm_pointer, 2546 .pcm_construct = mtk_afe_pcm_new, 2547 .probe = mt8188_afe_component_probe, 2548 }; 2549 2550 static int init_memif_priv_data(struct mtk_base_afe *afe) 2551 { 2552 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2553 struct mtk_dai_memif_priv *memif_priv; 2554 int i; 2555 2556 for (i = MT8188_AFE_MEMIF_START; i < MT8188_AFE_MEMIF_END; i++) { 2557 memif_priv = devm_kzalloc(afe->dev, 2558 sizeof(struct mtk_dai_memif_priv), 2559 GFP_KERNEL); 2560 if (!memif_priv) 2561 return -ENOMEM; 2562 2563 afe_priv->dai_priv[i] = memif_priv; 2564 } 2565 2566 return 0; 2567 } 2568 2569 static int mt8188_dai_memif_register(struct mtk_base_afe *afe) 2570 { 2571 struct mtk_base_afe_dai *dai; 2572 2573 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 2574 if (!dai) 2575 return -ENOMEM; 2576 2577 list_add(&dai->list, &afe->sub_dais); 2578 2579 dai->dai_drivers = mt8188_memif_dai_driver; 2580 dai->num_dai_drivers = ARRAY_SIZE(mt8188_memif_dai_driver); 2581 2582 dai->dapm_widgets = mt8188_memif_widgets; 2583 dai->num_dapm_widgets = ARRAY_SIZE(mt8188_memif_widgets); 2584 dai->dapm_routes = mt8188_memif_routes; 2585 dai->num_dapm_routes = ARRAY_SIZE(mt8188_memif_routes); 2586 2587 return init_memif_priv_data(afe); 2588 } 2589 2590 typedef int (*dai_register_cb)(struct mtk_base_afe *); 2591 static const dai_register_cb dai_register_cbs[] = { 2592 mt8188_dai_adda_register, 2593 mt8188_dai_etdm_register, 2594 mt8188_dai_pcm_register, 2595 mt8188_dai_memif_register, 2596 }; 2597 2598 static const struct reg_sequence mt8188_afe_reg_defaults[] = { 2599 { AFE_IRQ_MASK, 0x387ffff }, 2600 { AFE_IRQ3_CON, BIT(30) }, 2601 { AFE_IRQ9_CON, BIT(30) }, 2602 { ETDM_IN1_CON4, 0x12000100 }, 2603 { ETDM_IN2_CON4, 0x12000100 }, 2604 }; 2605 2606 static const struct reg_sequence mt8188_cg_patch[] = { 2607 { AUDIO_TOP_CON0, 0xfffffffb }, 2608 { AUDIO_TOP_CON1, 0xfffffff8 }, 2609 }; 2610 2611 static int mt8188_afe_init_registers(struct mtk_base_afe *afe) 2612 { 2613 return regmap_multi_reg_write(afe->regmap, 2614 mt8188_afe_reg_defaults, 2615 ARRAY_SIZE(mt8188_afe_reg_defaults)); 2616 } 2617 2618 static int mt8188_afe_parse_of(struct mtk_base_afe *afe, 2619 struct device_node *np) 2620 { 2621 #if IS_ENABLED(CONFIG_SND_SOC_MT6359) 2622 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2623 2624 afe_priv->topckgen = syscon_regmap_lookup_by_phandle(afe->dev->of_node, 2625 "mediatek,topckgen"); 2626 if (IS_ERR(afe_priv->topckgen)) 2627 return dev_err_probe(afe->dev, PTR_ERR(afe_priv->topckgen), 2628 "%s() Cannot find topckgen controller\n", 2629 __func__); 2630 #endif 2631 return 0; 2632 } 2633 2634 static int mt8188_afe_pcm_dev_probe(struct platform_device *pdev) 2635 { 2636 struct mtk_base_afe *afe; 2637 struct mt8188_afe_private *afe_priv; 2638 struct device *dev; 2639 int i, irq_id, ret; 2640 struct snd_soc_component *component; 2641 struct reset_control *rstc; 2642 2643 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33)); 2644 if (ret) 2645 return ret; 2646 2647 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); 2648 if (!afe) 2649 return -ENOMEM; 2650 2651 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv), 2652 GFP_KERNEL); 2653 if (!afe->platform_priv) 2654 return -ENOMEM; 2655 2656 afe_priv = afe->platform_priv; 2657 afe->dev = &pdev->dev; 2658 dev = afe->dev; 2659 2660 afe->base_addr = devm_platform_ioremap_resource(pdev, 0); 2661 if (IS_ERR(afe->base_addr)) 2662 return dev_err_probe(dev, PTR_ERR(afe->base_addr), 2663 "AFE base_addr not found\n"); 2664 2665 /* reset controller to reset audio regs before regmap cache */ 2666 rstc = devm_reset_control_get_exclusive(dev, "audiosys"); 2667 if (IS_ERR(rstc)) 2668 return dev_err_probe(dev, PTR_ERR(rstc), 2669 "could not get audiosys reset\n"); 2670 2671 ret = reset_control_reset(rstc); 2672 if (ret) { 2673 dev_err(dev, "failed to trigger audio reset:%d\n", ret); 2674 return ret; 2675 } 2676 2677 /* initial audio related clock */ 2678 ret = mt8188_afe_init_clock(afe); 2679 if (ret) 2680 return dev_err_probe(dev, ret, "init clock error"); 2681 2682 ret = devm_add_action_or_reset(dev, mt8188_afe_deinit_clock, (void *)afe); 2683 if (ret) 2684 return ret; 2685 2686 spin_lock_init(&afe_priv->afe_ctrl_lock); 2687 2688 mutex_init(&afe->irq_alloc_lock); 2689 2690 /* irq initialize */ 2691 afe->irqs_size = MT8188_AFE_IRQ_NUM; 2692 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), 2693 GFP_KERNEL); 2694 if (!afe->irqs) 2695 return -ENOMEM; 2696 2697 for (i = 0; i < afe->irqs_size; i++) 2698 afe->irqs[i].irq_data = &irq_data[i]; 2699 2700 /* init memif */ 2701 afe->memif_size = MT8188_AFE_MEMIF_NUM; 2702 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), 2703 GFP_KERNEL); 2704 if (!afe->memif) 2705 return -ENOMEM; 2706 2707 for (i = 0; i < afe->memif_size; i++) { 2708 afe->memif[i].data = &memif_data[i]; 2709 afe->memif[i].irq_usage = mt8188_afe_memif_const_irqs[i]; 2710 afe->memif[i].const_irq = 1; 2711 afe->irqs[afe->memif[i].irq_usage].irq_occupyed = true; 2712 } 2713 2714 /* request irq */ 2715 irq_id = platform_get_irq(pdev, 0); 2716 if (irq_id < 0) 2717 return dev_err_probe(dev, irq_id < 0 ? irq_id : -ENXIO, 2718 "no irq found"); 2719 2720 ret = devm_request_irq(dev, irq_id, mt8188_afe_irq_handler, 2721 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe); 2722 if (ret) 2723 return dev_err_probe(dev, ret, "could not request_irq for asys-isr\n"); 2724 2725 /* init sub_dais */ 2726 INIT_LIST_HEAD(&afe->sub_dais); 2727 2728 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) { 2729 ret = dai_register_cbs[i](afe); 2730 if (ret) 2731 return dev_err_probe(dev, ret, "dai register i %d fail\n", i); 2732 } 2733 2734 /* init dai_driver and component_driver */ 2735 ret = mtk_afe_combine_sub_dai(afe); 2736 if (ret) 2737 return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n"); 2738 2739 afe->mtk_afe_hardware = &mt8188_afe_hardware; 2740 afe->memif_fs = mt8188_memif_fs; 2741 afe->irq_fs = mt8188_irq_fs; 2742 2743 afe->runtime_resume = mt8188_afe_runtime_resume; 2744 afe->runtime_suspend = mt8188_afe_runtime_suspend; 2745 2746 platform_set_drvdata(pdev, afe); 2747 2748 ret = mt8188_afe_parse_of(afe, pdev->dev.of_node); 2749 if (ret) 2750 return ret; 2751 2752 ret = devm_pm_runtime_enable(dev); 2753 if (ret) 2754 return ret; 2755 2756 /* enable clock for regcache get default value from hw */ 2757 afe_priv->pm_runtime_bypass_reg_ctl = true; 2758 ret = pm_runtime_resume_and_get(dev); 2759 if (ret) 2760 return dev_err_probe(dev, ret, "failed to resume device\n"); 2761 2762 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr, 2763 &mt8188_afe_regmap_config); 2764 if (IS_ERR(afe->regmap)) { 2765 ret = PTR_ERR(afe->regmap); 2766 goto err_pm_put; 2767 } 2768 2769 ret = regmap_register_patch(afe->regmap, mt8188_cg_patch, 2770 ARRAY_SIZE(mt8188_cg_patch)); 2771 if (ret < 0) { 2772 dev_info(dev, "Failed to apply cg patch\n"); 2773 goto err_pm_put; 2774 } 2775 2776 /* register component */ 2777 ret = devm_snd_soc_register_component(dev, &mt8188_afe_component, 2778 NULL, 0); 2779 if (ret) { 2780 dev_warn(dev, "err_platform\n"); 2781 goto err_pm_put; 2782 } 2783 2784 component = devm_kzalloc(&pdev->dev, sizeof(*component), GFP_KERNEL); 2785 if (!component) { 2786 ret = -ENOMEM; 2787 goto err_pm_put; 2788 } 2789 2790 ret = snd_soc_component_initialize(component, 2791 &mt8188_afe_pcm_dai_component, 2792 &pdev->dev); 2793 if (ret) 2794 goto err_pm_put; 2795 #ifdef CONFIG_DEBUG_FS 2796 component->debugfs_prefix = "pcm"; 2797 #endif 2798 ret = snd_soc_add_component(component, 2799 afe->dai_drivers, 2800 afe->num_dai_drivers); 2801 if (ret) { 2802 dev_warn(dev, "err_add_component\n"); 2803 goto err_pm_put; 2804 } 2805 2806 mt8188_afe_init_registers(afe); 2807 2808 pm_runtime_put_sync(&pdev->dev); 2809 afe_priv->pm_runtime_bypass_reg_ctl = false; 2810 2811 regcache_cache_only(afe->regmap, true); 2812 regcache_mark_dirty(afe->regmap); 2813 2814 return 0; 2815 err_pm_put: 2816 pm_runtime_put_sync(dev); 2817 2818 return ret; 2819 } 2820 2821 static int mt8188_afe_pcm_dev_remove(struct platform_device *pdev) 2822 { 2823 snd_soc_unregister_component(&pdev->dev); 2824 2825 return 0; 2826 } 2827 2828 static const struct of_device_id mt8188_afe_pcm_dt_match[] = { 2829 { .compatible = "mediatek,mt8188-afe", }, 2830 {}, 2831 }; 2832 MODULE_DEVICE_TABLE(of, mt8188_afe_pcm_dt_match); 2833 2834 static const struct dev_pm_ops mt8188_afe_pm_ops = { 2835 SET_RUNTIME_PM_OPS(mt8188_afe_runtime_suspend, 2836 mt8188_afe_runtime_resume, NULL) 2837 }; 2838 2839 static struct platform_driver mt8188_afe_pcm_driver = { 2840 .driver = { 2841 .name = "mt8188-audio", 2842 .of_match_table = mt8188_afe_pcm_dt_match, 2843 .pm = &mt8188_afe_pm_ops, 2844 }, 2845 .probe = mt8188_afe_pcm_dev_probe, 2846 .remove = mt8188_afe_pcm_dev_remove, 2847 }; 2848 2849 module_platform_driver(mt8188_afe_pcm_driver); 2850 2851 MODULE_DESCRIPTION("MediaTek SoC AFE platform driver for ALSA 8188"); 2852 MODULE_AUTHOR("Chun-Chia.Chiu <chun-chia.chiu@mediatek.com>"); 2853 MODULE_LICENSE("GPL"); 2854