1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek ALSA SoC AFE platform driver for 8188 4 * 5 * Copyright (c) 2022 MediaTek Inc. 6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 * Trevor Wu <trevor.wu@mediatek.com> 8 * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 */ 10 11 #include <linux/arm-smccc.h> 12 #include <linux/delay.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/module.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_platform.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/soc/mediatek/infracfg.h> 21 #include <linux/reset.h> 22 #include <sound/pcm_params.h> 23 #include "mt8188-afe-common.h" 24 #include "mt8188-afe-clk.h" 25 #include "mt8188-reg.h" 26 #include "../common/mtk-afe-platform-driver.h" 27 #include "../common/mtk-afe-fe-dai.h" 28 29 #define MT8188_MEMIF_BUFFER_BYTES_ALIGN (0x40) 30 #define MT8188_MEMIF_DL7_MAX_PERIOD_SIZE (0x3fff) 31 32 #define MEMIF_AXI_MINLEN 9 /* register default value */ 33 34 struct mtk_dai_memif_priv { 35 unsigned int asys_timing_sel; 36 unsigned int fs_timing; 37 }; 38 39 static const struct snd_pcm_hardware mt8188_afe_hardware = { 40 .info = SNDRV_PCM_INFO_MMAP | 41 SNDRV_PCM_INFO_INTERLEAVED | 42 SNDRV_PCM_INFO_MMAP_VALID, 43 .formats = SNDRV_PCM_FMTBIT_S16_LE | 44 SNDRV_PCM_FMTBIT_S24_LE | 45 SNDRV_PCM_FMTBIT_S32_LE, 46 .period_bytes_min = 64, 47 .period_bytes_max = 256 * 1024, 48 .periods_min = 2, 49 .periods_max = 256, 50 .buffer_bytes_max = 256 * 2 * 1024, 51 }; 52 53 struct mt8188_afe_rate { 54 unsigned int rate; 55 unsigned int reg_value; 56 }; 57 58 static const struct mt8188_afe_rate mt8188_afe_rates[] = { 59 { .rate = 8000, .reg_value = 0, }, 60 { .rate = 12000, .reg_value = 1, }, 61 { .rate = 16000, .reg_value = 2, }, 62 { .rate = 24000, .reg_value = 3, }, 63 { .rate = 32000, .reg_value = 4, }, 64 { .rate = 48000, .reg_value = 5, }, 65 { .rate = 96000, .reg_value = 6, }, 66 { .rate = 192000, .reg_value = 7, }, 67 { .rate = 384000, .reg_value = 8, }, 68 { .rate = 7350, .reg_value = 16, }, 69 { .rate = 11025, .reg_value = 17, }, 70 { .rate = 14700, .reg_value = 18, }, 71 { .rate = 22050, .reg_value = 19, }, 72 { .rate = 29400, .reg_value = 20, }, 73 { .rate = 44100, .reg_value = 21, }, 74 { .rate = 88200, .reg_value = 22, }, 75 { .rate = 176400, .reg_value = 23, }, 76 { .rate = 352800, .reg_value = 24, }, 77 }; 78 79 int mt8188_afe_fs_timing(unsigned int rate) 80 { 81 int i; 82 83 for (i = 0; i < ARRAY_SIZE(mt8188_afe_rates); i++) 84 if (mt8188_afe_rates[i].rate == rate) 85 return mt8188_afe_rates[i].reg_value; 86 87 return -EINVAL; 88 } 89 90 static int mt8188_memif_fs(struct snd_pcm_substream *substream, 91 unsigned int rate) 92 { 93 struct snd_soc_pcm_runtime *rtd = substream->private_data; 94 struct snd_soc_component *component = NULL; 95 struct mtk_base_afe *afe = NULL; 96 struct mt8188_afe_private *afe_priv = NULL; 97 struct mtk_base_afe_memif *memif = NULL; 98 struct mtk_dai_memif_priv *memif_priv = NULL; 99 int fs = mt8188_afe_fs_timing(rate); 100 int id = asoc_rtd_to_cpu(rtd, 0)->id; 101 102 if (id < 0) 103 return -EINVAL; 104 105 component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 106 if (!component) 107 return -EINVAL; 108 109 afe = snd_soc_component_get_drvdata(component); 110 memif = &afe->memif[id]; 111 112 switch (memif->data->id) { 113 case MT8188_AFE_MEMIF_DL10: 114 fs = MT8188_ETDM_OUT3_1X_EN; 115 break; 116 case MT8188_AFE_MEMIF_UL8: 117 fs = MT8188_ETDM_IN1_NX_EN; 118 break; 119 case MT8188_AFE_MEMIF_UL3: 120 fs = MT8188_ETDM_IN2_NX_EN; 121 break; 122 default: 123 afe_priv = afe->platform_priv; 124 memif_priv = afe_priv->dai_priv[id]; 125 if (memif_priv->fs_timing) 126 fs = memif_priv->fs_timing; 127 break; 128 } 129 130 return fs; 131 } 132 133 static int mt8188_irq_fs(struct snd_pcm_substream *substream, 134 unsigned int rate) 135 { 136 int fs = mt8188_memif_fs(substream, rate); 137 138 switch (fs) { 139 case MT8188_ETDM_IN1_NX_EN: 140 fs = MT8188_ETDM_IN1_1X_EN; 141 break; 142 case MT8188_ETDM_IN2_NX_EN: 143 fs = MT8188_ETDM_IN2_1X_EN; 144 break; 145 default: 146 break; 147 } 148 149 return fs; 150 } 151 152 enum { 153 MT8188_AFE_CM0, 154 MT8188_AFE_CM1, 155 MT8188_AFE_CM2, 156 MT8188_AFE_CM_NUM, 157 }; 158 159 struct mt8188_afe_channel_merge { 160 int id; 161 int reg; 162 unsigned int sel_shift; 163 unsigned int sel_maskbit; 164 unsigned int sel_default; 165 unsigned int ch_num_shift; 166 unsigned int ch_num_maskbit; 167 unsigned int en_shift; 168 unsigned int en_maskbit; 169 unsigned int update_cnt_shift; 170 unsigned int update_cnt_maskbit; 171 unsigned int update_cnt_default; 172 }; 173 174 static const struct mt8188_afe_channel_merge 175 mt8188_afe_cm[MT8188_AFE_CM_NUM] = { 176 [MT8188_AFE_CM0] = { 177 .id = MT8188_AFE_CM0, 178 .reg = AFE_CM0_CON, 179 .sel_shift = 30, 180 .sel_maskbit = 0x1, 181 .sel_default = 1, 182 .ch_num_shift = 2, 183 .ch_num_maskbit = 0x3f, 184 .en_shift = 0, 185 .en_maskbit = 0x1, 186 .update_cnt_shift = 16, 187 .update_cnt_maskbit = 0x1fff, 188 .update_cnt_default = 0x3, 189 }, 190 [MT8188_AFE_CM1] = { 191 .id = MT8188_AFE_CM1, 192 .reg = AFE_CM1_CON, 193 .sel_shift = 30, 194 .sel_maskbit = 0x1, 195 .sel_default = 1, 196 .ch_num_shift = 2, 197 .ch_num_maskbit = 0x1f, 198 .en_shift = 0, 199 .en_maskbit = 0x1, 200 .update_cnt_shift = 16, 201 .update_cnt_maskbit = 0x1fff, 202 .update_cnt_default = 0x3, 203 }, 204 [MT8188_AFE_CM2] = { 205 .id = MT8188_AFE_CM2, 206 .reg = AFE_CM2_CON, 207 .sel_shift = 30, 208 .sel_maskbit = 0x1, 209 .sel_default = 1, 210 .ch_num_shift = 2, 211 .ch_num_maskbit = 0x1f, 212 .en_shift = 0, 213 .en_maskbit = 0x1, 214 .update_cnt_shift = 16, 215 .update_cnt_maskbit = 0x1fff, 216 .update_cnt_default = 0x3, 217 }, 218 }; 219 220 static int mt8188_afe_memif_is_ul(int id) 221 { 222 if (id >= MT8188_AFE_MEMIF_UL_START && id < MT8188_AFE_MEMIF_END) 223 return 1; 224 else 225 return 0; 226 } 227 228 static const struct mt8188_afe_channel_merge * 229 mt8188_afe_found_cm(struct snd_soc_dai *dai) 230 { 231 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 232 int id = -EINVAL; 233 234 if (mt8188_afe_memif_is_ul(dai->id) == 0) 235 return NULL; 236 237 switch (dai->id) { 238 case MT8188_AFE_MEMIF_UL9: 239 id = MT8188_AFE_CM0; 240 break; 241 case MT8188_AFE_MEMIF_UL2: 242 id = MT8188_AFE_CM1; 243 break; 244 case MT8188_AFE_MEMIF_UL10: 245 id = MT8188_AFE_CM2; 246 break; 247 default: 248 break; 249 } 250 251 if (id < 0) { 252 dev_dbg(afe->dev, "%s, memif %d cannot find CM!\n", __func__, dai->id); 253 return NULL; 254 } 255 256 return &mt8188_afe_cm[id]; 257 } 258 259 static int mt8188_afe_config_cm(struct mtk_base_afe *afe, 260 const struct mt8188_afe_channel_merge *cm, 261 unsigned int channels) 262 { 263 if (!cm) 264 return -EINVAL; 265 266 regmap_update_bits(afe->regmap, 267 cm->reg, 268 cm->sel_maskbit << cm->sel_shift, 269 cm->sel_default << cm->sel_shift); 270 271 regmap_update_bits(afe->regmap, 272 cm->reg, 273 cm->ch_num_maskbit << cm->ch_num_shift, 274 (channels - 1) << cm->ch_num_shift); 275 276 regmap_update_bits(afe->regmap, 277 cm->reg, 278 cm->update_cnt_maskbit << cm->update_cnt_shift, 279 cm->update_cnt_default << cm->update_cnt_shift); 280 281 return 0; 282 } 283 284 static int mt8188_afe_enable_cm(struct mtk_base_afe *afe, 285 const struct mt8188_afe_channel_merge *cm, 286 bool enable) 287 { 288 if (!cm) 289 return -EINVAL; 290 291 regmap_update_bits(afe->regmap, 292 cm->reg, 293 cm->en_maskbit << cm->en_shift, 294 enable << cm->en_shift); 295 296 return 0; 297 } 298 299 static int mt8188_afe_fe_startup(struct snd_pcm_substream *substream, 300 struct snd_soc_dai *dai) 301 { 302 struct snd_soc_pcm_runtime *rtd = substream->private_data; 303 struct snd_pcm_runtime *runtime = substream->runtime; 304 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 305 int id = asoc_rtd_to_cpu(rtd, 0)->id; 306 int ret; 307 308 ret = mtk_afe_fe_startup(substream, dai); 309 310 snd_pcm_hw_constraint_step(runtime, 0, 311 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 312 MT8188_MEMIF_BUFFER_BYTES_ALIGN); 313 314 if (id != MT8188_AFE_MEMIF_DL7) 315 goto out; 316 317 ret = snd_pcm_hw_constraint_minmax(runtime, 318 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 1, 319 MT8188_MEMIF_DL7_MAX_PERIOD_SIZE); 320 if (ret < 0) 321 dev_dbg(afe->dev, "hw_constraint_minmax failed\n"); 322 out: 323 return ret; 324 } 325 326 static void mt8188_afe_fe_shutdown(struct snd_pcm_substream *substream, 327 struct snd_soc_dai *dai) 328 { 329 mtk_afe_fe_shutdown(substream, dai); 330 } 331 332 static int mt8188_afe_fe_hw_params(struct snd_pcm_substream *substream, 333 struct snd_pcm_hw_params *params, 334 struct snd_soc_dai *dai) 335 { 336 struct snd_soc_pcm_runtime *rtd = substream->private_data; 337 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 338 int id = asoc_rtd_to_cpu(rtd, 0)->id; 339 struct mtk_base_afe_memif *memif = &afe->memif[id]; 340 const struct mtk_base_memif_data *data = memif->data; 341 const struct mt8188_afe_channel_merge *cm = mt8188_afe_found_cm(dai); 342 unsigned int channels = params_channels(params); 343 344 mt8188_afe_config_cm(afe, cm, channels); 345 346 if (data->ch_num_reg >= 0) { 347 regmap_update_bits(afe->regmap, data->ch_num_reg, 348 data->ch_num_maskbit << data->ch_num_shift, 349 channels << data->ch_num_shift); 350 } 351 352 return mtk_afe_fe_hw_params(substream, params, dai); 353 } 354 355 static int mt8188_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd, 356 struct snd_soc_dai *dai) 357 { 358 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 359 const struct mt8188_afe_channel_merge *cm = mt8188_afe_found_cm(dai); 360 struct snd_soc_pcm_runtime *rtd = substream->private_data; 361 struct snd_pcm_runtime * const runtime = substream->runtime; 362 int id = asoc_rtd_to_cpu(rtd, 0)->id; 363 struct mtk_base_afe_memif *memif = &afe->memif[id]; 364 struct mtk_base_afe_irq *irqs = &afe->irqs[memif->irq_usage]; 365 const struct mtk_base_irq_data *irq_data = irqs->irq_data; 366 unsigned int counter = runtime->period_size; 367 int fs; 368 int ret; 369 370 switch (cmd) { 371 case SNDRV_PCM_TRIGGER_START: 372 case SNDRV_PCM_TRIGGER_RESUME: 373 mt8188_afe_enable_cm(afe, cm, true); 374 375 ret = mtk_memif_set_enable(afe, id); 376 if (ret) { 377 dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n", 378 __func__, id, ret); 379 return ret; 380 } 381 382 /* set irq counter */ 383 regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg, 384 irq_data->irq_cnt_maskbit << irq_data->irq_cnt_shift, 385 counter << irq_data->irq_cnt_shift); 386 387 /* set irq fs */ 388 fs = afe->irq_fs(substream, runtime->rate); 389 390 if (fs < 0) 391 return -EINVAL; 392 393 if (irq_data->irq_fs_reg >= 0) 394 regmap_update_bits(afe->regmap, irq_data->irq_fs_reg, 395 irq_data->irq_fs_maskbit << irq_data->irq_fs_shift, 396 fs << irq_data->irq_fs_shift); 397 398 /* delay for uplink */ 399 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 400 u32 sample_delay; 401 402 sample_delay = ((MEMIF_AXI_MINLEN + 1) * 64 + 403 (runtime->channels * runtime->sample_bits - 1)) / 404 (runtime->channels * runtime->sample_bits) + 1; 405 406 udelay(sample_delay * 1000000 / runtime->rate); 407 } 408 409 /* enable interrupt */ 410 regmap_set_bits(afe->regmap, irq_data->irq_en_reg, 411 BIT(irq_data->irq_en_shift)); 412 return 0; 413 case SNDRV_PCM_TRIGGER_STOP: 414 case SNDRV_PCM_TRIGGER_SUSPEND: 415 mt8188_afe_enable_cm(afe, cm, false); 416 417 ret = mtk_memif_set_disable(afe, id); 418 if (ret) 419 dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n", 420 __func__, id, ret); 421 422 /* disable interrupt */ 423 424 regmap_clear_bits(afe->regmap, irq_data->irq_en_reg, 425 BIT(irq_data->irq_en_shift)); 426 /* and clear pending IRQ */ 427 regmap_write(afe->regmap, irq_data->irq_clr_reg, 428 BIT(irq_data->irq_clr_shift)); 429 return ret; 430 default: 431 return -EINVAL; 432 } 433 } 434 435 static const struct snd_soc_dai_ops mt8188_afe_fe_dai_ops = { 436 .startup = mt8188_afe_fe_startup, 437 .shutdown = mt8188_afe_fe_shutdown, 438 .hw_params = mt8188_afe_fe_hw_params, 439 .hw_free = mtk_afe_fe_hw_free, 440 .prepare = mtk_afe_fe_prepare, 441 .trigger = mt8188_afe_fe_trigger, 442 }; 443 444 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\ 445 SNDRV_PCM_RATE_88200 |\ 446 SNDRV_PCM_RATE_96000 |\ 447 SNDRV_PCM_RATE_176400 |\ 448 SNDRV_PCM_RATE_192000 |\ 449 SNDRV_PCM_RATE_352800 |\ 450 SNDRV_PCM_RATE_384000) 451 452 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 453 SNDRV_PCM_FMTBIT_S24_LE |\ 454 SNDRV_PCM_FMTBIT_S32_LE) 455 456 static struct snd_soc_dai_driver mt8188_memif_dai_driver[] = { 457 /* FE DAIs: memory intefaces to CPU */ 458 { 459 .name = "DL2", 460 .id = MT8188_AFE_MEMIF_DL2, 461 .playback = { 462 .stream_name = "DL2", 463 .channels_min = 1, 464 .channels_max = 2, 465 .rates = MTK_PCM_RATES, 466 .formats = MTK_PCM_FORMATS, 467 }, 468 .ops = &mt8188_afe_fe_dai_ops, 469 }, 470 { 471 .name = "DL3", 472 .id = MT8188_AFE_MEMIF_DL3, 473 .playback = { 474 .stream_name = "DL3", 475 .channels_min = 1, 476 .channels_max = 2, 477 .rates = MTK_PCM_RATES, 478 .formats = MTK_PCM_FORMATS, 479 }, 480 .ops = &mt8188_afe_fe_dai_ops, 481 }, 482 { 483 .name = "DL6", 484 .id = MT8188_AFE_MEMIF_DL6, 485 .playback = { 486 .stream_name = "DL6", 487 .channels_min = 1, 488 .channels_max = 2, 489 .rates = MTK_PCM_RATES, 490 .formats = MTK_PCM_FORMATS, 491 }, 492 .ops = &mt8188_afe_fe_dai_ops, 493 }, 494 { 495 .name = "DL7", 496 .id = MT8188_AFE_MEMIF_DL7, 497 .playback = { 498 .stream_name = "DL7", 499 .channels_min = 1, 500 .channels_max = 2, 501 .rates = MTK_PCM_RATES, 502 .formats = MTK_PCM_FORMATS, 503 }, 504 .ops = &mt8188_afe_fe_dai_ops, 505 }, 506 { 507 .name = "DL8", 508 .id = MT8188_AFE_MEMIF_DL8, 509 .playback = { 510 .stream_name = "DL8", 511 .channels_min = 1, 512 .channels_max = 16, 513 .rates = MTK_PCM_RATES, 514 .formats = MTK_PCM_FORMATS, 515 }, 516 .ops = &mt8188_afe_fe_dai_ops, 517 }, 518 { 519 .name = "DL10", 520 .id = MT8188_AFE_MEMIF_DL10, 521 .playback = { 522 .stream_name = "DL10", 523 .channels_min = 1, 524 .channels_max = 8, 525 .rates = MTK_PCM_RATES, 526 .formats = MTK_PCM_FORMATS, 527 }, 528 .ops = &mt8188_afe_fe_dai_ops, 529 }, 530 { 531 .name = "DL11", 532 .id = MT8188_AFE_MEMIF_DL11, 533 .playback = { 534 .stream_name = "DL11", 535 .channels_min = 1, 536 .channels_max = 32, 537 .rates = MTK_PCM_RATES, 538 .formats = MTK_PCM_FORMATS, 539 }, 540 .ops = &mt8188_afe_fe_dai_ops, 541 }, 542 { 543 .name = "UL1", 544 .id = MT8188_AFE_MEMIF_UL1, 545 .capture = { 546 .stream_name = "UL1", 547 .channels_min = 1, 548 .channels_max = 8, 549 .rates = MTK_PCM_RATES, 550 .formats = MTK_PCM_FORMATS, 551 }, 552 .ops = &mt8188_afe_fe_dai_ops, 553 }, 554 { 555 .name = "UL2", 556 .id = MT8188_AFE_MEMIF_UL2, 557 .capture = { 558 .stream_name = "UL2", 559 .channels_min = 1, 560 .channels_max = 8, 561 .rates = MTK_PCM_RATES, 562 .formats = MTK_PCM_FORMATS, 563 }, 564 .ops = &mt8188_afe_fe_dai_ops, 565 }, 566 { 567 .name = "UL3", 568 .id = MT8188_AFE_MEMIF_UL3, 569 .capture = { 570 .stream_name = "UL3", 571 .channels_min = 1, 572 .channels_max = 16, 573 .rates = MTK_PCM_RATES, 574 .formats = MTK_PCM_FORMATS, 575 }, 576 .ops = &mt8188_afe_fe_dai_ops, 577 }, 578 { 579 .name = "UL4", 580 .id = MT8188_AFE_MEMIF_UL4, 581 .capture = { 582 .stream_name = "UL4", 583 .channels_min = 1, 584 .channels_max = 2, 585 .rates = MTK_PCM_RATES, 586 .formats = MTK_PCM_FORMATS, 587 }, 588 .ops = &mt8188_afe_fe_dai_ops, 589 }, 590 { 591 .name = "UL5", 592 .id = MT8188_AFE_MEMIF_UL5, 593 .capture = { 594 .stream_name = "UL5", 595 .channels_min = 1, 596 .channels_max = 2, 597 .rates = MTK_PCM_RATES, 598 .formats = MTK_PCM_FORMATS, 599 }, 600 .ops = &mt8188_afe_fe_dai_ops, 601 }, 602 { 603 .name = "UL6", 604 .id = MT8188_AFE_MEMIF_UL6, 605 .capture = { 606 .stream_name = "UL6", 607 .channels_min = 1, 608 .channels_max = 8, 609 .rates = MTK_PCM_RATES, 610 .formats = MTK_PCM_FORMATS, 611 }, 612 .ops = &mt8188_afe_fe_dai_ops, 613 }, 614 { 615 .name = "UL8", 616 .id = MT8188_AFE_MEMIF_UL8, 617 .capture = { 618 .stream_name = "UL8", 619 .channels_min = 1, 620 .channels_max = 24, 621 .rates = MTK_PCM_RATES, 622 .formats = MTK_PCM_FORMATS, 623 }, 624 .ops = &mt8188_afe_fe_dai_ops, 625 }, 626 { 627 .name = "UL9", 628 .id = MT8188_AFE_MEMIF_UL9, 629 .capture = { 630 .stream_name = "UL9", 631 .channels_min = 1, 632 .channels_max = 32, 633 .rates = MTK_PCM_RATES, 634 .formats = MTK_PCM_FORMATS, 635 }, 636 .ops = &mt8188_afe_fe_dai_ops, 637 }, 638 { 639 .name = "UL10", 640 .id = MT8188_AFE_MEMIF_UL10, 641 .capture = { 642 .stream_name = "UL10", 643 .channels_min = 1, 644 .channels_max = 4, 645 .rates = MTK_PCM_RATES, 646 .formats = MTK_PCM_FORMATS, 647 }, 648 .ops = &mt8188_afe_fe_dai_ops, 649 }, 650 }; 651 652 static const struct snd_kcontrol_new o002_mix[] = { 653 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN2, 0, 1, 0), 654 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN2, 12, 1, 0), 655 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN2, 20, 1, 0), 656 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN2, 22, 1, 0), 657 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN2_2, 6, 1, 0), 658 SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN2_2, 8, 1, 0), 659 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN2_5, 8, 1, 0), 660 }; 661 662 static const struct snd_kcontrol_new o003_mix[] = { 663 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN3, 1, 1, 0), 664 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN3, 13, 1, 0), 665 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN3, 21, 1, 0), 666 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN3, 23, 1, 0), 667 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN3_2, 7, 1, 0), 668 SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN3_2, 9, 1, 0), 669 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN3_5, 9, 1, 0), 670 }; 671 672 static const struct snd_kcontrol_new o004_mix[] = { 673 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN4, 0, 1, 0), 674 SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN4, 14, 1, 0), 675 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN4, 24, 1, 0), 676 SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN4_2, 10, 1, 0), 677 }; 678 679 static const struct snd_kcontrol_new o005_mix[] = { 680 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN5, 1, 1, 0), 681 SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN5, 15, 1, 0), 682 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN5, 25, 1, 0), 683 SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN5_2, 11, 1, 0), 684 }; 685 686 static const struct snd_kcontrol_new o006_mix[] = { 687 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN6, 0, 1, 0), 688 SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN6, 16, 1, 0), 689 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN6, 26, 1, 0), 690 SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN6_2, 12, 1, 0), 691 }; 692 693 static const struct snd_kcontrol_new o007_mix[] = { 694 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN7, 1, 1, 0), 695 SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN7, 17, 1, 0), 696 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN7, 27, 1, 0), 697 SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN7_2, 13, 1, 0), 698 }; 699 700 static const struct snd_kcontrol_new o008_mix[] = { 701 SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN8, 18, 1, 0), 702 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN8, 28, 1, 0), 703 SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN8_2, 14, 1, 0), 704 }; 705 706 static const struct snd_kcontrol_new o009_mix[] = { 707 SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN9, 19, 1, 0), 708 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN9, 29, 1, 0), 709 SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN9_2, 15, 1, 0), 710 }; 711 712 static const struct snd_kcontrol_new o010_mix[] = { 713 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN10, 22, 1, 0), 714 SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN10, 30, 1, 0), 715 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN10_1, 14, 1, 0), 716 SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN10_2, 8, 1, 0), 717 SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN10_2, 16, 1, 0), 718 SOC_DAPM_SINGLE_AUTODISABLE("I188 Switch", AFE_CONN10_5, 28, 1, 0), 719 }; 720 721 static const struct snd_kcontrol_new o011_mix[] = { 722 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN11, 23, 1, 0), 723 SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN11, 31, 1, 0), 724 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN11_1, 15, 1, 0), 725 SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN11_2, 9, 1, 0), 726 SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN11_2, 17, 1, 0), 727 SOC_DAPM_SINGLE_AUTODISABLE("I189 Switch", AFE_CONN11_5, 29, 1, 0), 728 }; 729 730 static const struct snd_kcontrol_new o012_mix[] = { 731 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN12, 24, 1, 0), 732 SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN12_1, 0, 1, 0), 733 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN12_1, 16, 1, 0), 734 SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN12_2, 10, 1, 0), 735 SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN12_2, 18, 1, 0), 736 SOC_DAPM_SINGLE_AUTODISABLE("I190 Switch", AFE_CONN12_5, 30, 1, 0), 737 }; 738 739 static const struct snd_kcontrol_new o013_mix[] = { 740 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN13, 25, 1, 0), 741 SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN13_1, 1, 1, 0), 742 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN13_1, 17, 1, 0), 743 SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN13_2, 11, 1, 0), 744 SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN13_2, 19, 1, 0), 745 SOC_DAPM_SINGLE_AUTODISABLE("I191 Switch", AFE_CONN13_5, 31, 1, 0), 746 }; 747 748 static const struct snd_kcontrol_new o014_mix[] = { 749 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN14, 26, 1, 0), 750 SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN14_1, 2, 1, 0), 751 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN14_1, 18, 1, 0), 752 SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN14_2, 12, 1, 0), 753 SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN14_2, 20, 1, 0), 754 SOC_DAPM_SINGLE_AUTODISABLE("I192 Switch", AFE_CONN14_6, 0, 1, 0), 755 }; 756 757 static const struct snd_kcontrol_new o015_mix[] = { 758 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN15, 27, 1, 0), 759 SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN15_1, 3, 1, 0), 760 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN15_1, 19, 1, 0), 761 SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN15_2, 13, 1, 0), 762 SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN15_2, 21, 1, 0), 763 SOC_DAPM_SINGLE_AUTODISABLE("I193 Switch", AFE_CONN15_6, 1, 1, 0), 764 }; 765 766 static const struct snd_kcontrol_new o016_mix[] = { 767 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN16, 28, 1, 0), 768 SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN16_1, 4, 1, 0), 769 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN16_1, 20, 1, 0), 770 SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN16_2, 14, 1, 0), 771 SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN16_2, 22, 1, 0), 772 SOC_DAPM_SINGLE_AUTODISABLE("I194 Switch", AFE_CONN16_6, 2, 1, 0), 773 }; 774 775 static const struct snd_kcontrol_new o017_mix[] = { 776 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN17, 29, 1, 0), 777 SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN17_1, 5, 1, 0), 778 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN17_1, 21, 1, 0), 779 SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN17_2, 15, 1, 0), 780 SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN17_2, 23, 1, 0), 781 SOC_DAPM_SINGLE_AUTODISABLE("I195 Switch", AFE_CONN17_6, 3, 1, 0), 782 }; 783 784 static const struct snd_kcontrol_new o018_mix[] = { 785 SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN18_2, 16, 1, 0), 786 }; 787 788 static const struct snd_kcontrol_new o019_mix[] = { 789 SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN19_2, 17, 1, 0), 790 }; 791 792 static const struct snd_kcontrol_new o020_mix[] = { 793 SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN20_2, 18, 1, 0), 794 }; 795 796 static const struct snd_kcontrol_new o021_mix[] = { 797 SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN21_2, 19, 1, 0), 798 }; 799 800 static const struct snd_kcontrol_new o022_mix[] = { 801 SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN22_2, 20, 1, 0), 802 }; 803 804 static const struct snd_kcontrol_new o023_mix[] = { 805 SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN23_2, 21, 1, 0), 806 }; 807 808 static const struct snd_kcontrol_new o024_mix[] = { 809 SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN24_2, 22, 1, 0), 810 }; 811 812 static const struct snd_kcontrol_new o025_mix[] = { 813 SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN25_2, 23, 1, 0), 814 }; 815 816 static const struct snd_kcontrol_new o026_mix[] = { 817 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN26_1, 14, 1, 0), 818 }; 819 820 static const struct snd_kcontrol_new o027_mix[] = { 821 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN27_1, 15, 1, 0), 822 }; 823 824 static const struct snd_kcontrol_new o028_mix[] = { 825 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN28_1, 16, 1, 0), 826 }; 827 828 static const struct snd_kcontrol_new o029_mix[] = { 829 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN29_1, 17, 1, 0), 830 }; 831 832 static const struct snd_kcontrol_new o030_mix[] = { 833 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN30_1, 18, 1, 0), 834 }; 835 836 static const struct snd_kcontrol_new o031_mix[] = { 837 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN31_1, 19, 1, 0), 838 }; 839 840 static const struct snd_kcontrol_new o032_mix[] = { 841 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN32_1, 20, 1, 0), 842 }; 843 844 static const struct snd_kcontrol_new o033_mix[] = { 845 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN33_1, 21, 1, 0), 846 }; 847 848 static const struct snd_kcontrol_new o034_mix[] = { 849 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN34, 0, 1, 0), 850 SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN34, 2, 1, 0), 851 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN34, 12, 1, 0), 852 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN34, 20, 1, 0), 853 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN34_2, 6, 1, 0), 854 SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN34_2, 8, 1, 0), 855 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN34_5, 8, 1, 0), 856 }; 857 858 static const struct snd_kcontrol_new o035_mix[] = { 859 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN35, 1, 1, 0), 860 SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN35, 3, 1, 0), 861 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN35, 13, 1, 0), 862 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN35, 21, 1, 0), 863 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN35_2, 7, 1, 0), 864 SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN35_2, 9, 1, 0), 865 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN35_5, 8, 1, 0), 866 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN35_5, 9, 1, 0), 867 }; 868 869 static const struct snd_kcontrol_new o036_mix[] = { 870 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN36, 0, 1, 0), 871 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN36, 12, 1, 0), 872 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN36, 20, 1, 0), 873 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN36_2, 6, 1, 0), 874 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN36_5, 8, 1, 0), 875 }; 876 877 static const struct snd_kcontrol_new o037_mix[] = { 878 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN37, 1, 1, 0), 879 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN37, 13, 1, 0), 880 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN37, 21, 1, 0), 881 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN37_2, 7, 1, 0), 882 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN37_5, 9, 1, 0), 883 }; 884 885 static const struct snd_kcontrol_new o038_mix[] = { 886 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN38, 22, 1, 0), 887 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN38_5, 8, 1, 0), 888 }; 889 890 static const struct snd_kcontrol_new o039_mix[] = { 891 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN39, 23, 1, 0), 892 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN39_5, 9, 1, 0), 893 }; 894 895 static const struct snd_kcontrol_new o040_mix[] = { 896 SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN40, 2, 1, 0), 897 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN40, 12, 1, 0), 898 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN40, 22, 1, 0), 899 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN40_5, 8, 1, 0), 900 }; 901 902 static const struct snd_kcontrol_new o041_mix[] = { 903 SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN41, 3, 1, 0), 904 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN41, 13, 1, 0), 905 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN41, 23, 1, 0), 906 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN41_5, 9, 1, 0), 907 }; 908 909 static const struct snd_kcontrol_new o042_mix[] = { 910 SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN42, 14, 1, 0), 911 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN42, 24, 1, 0), 912 }; 913 914 static const struct snd_kcontrol_new o043_mix[] = { 915 SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN43, 15, 1, 0), 916 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN43, 25, 1, 0), 917 }; 918 919 static const struct snd_kcontrol_new o044_mix[] = { 920 SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN44, 16, 1, 0), 921 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN44, 26, 1, 0), 922 }; 923 924 static const struct snd_kcontrol_new o045_mix[] = { 925 SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN45, 17, 1, 0), 926 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN45, 27, 1, 0), 927 }; 928 929 static const struct snd_kcontrol_new o046_mix[] = { 930 SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN46, 18, 1, 0), 931 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN46, 28, 1, 0), 932 }; 933 934 static const struct snd_kcontrol_new o047_mix[] = { 935 SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN47, 19, 1, 0), 936 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN47, 29, 1, 0), 937 }; 938 939 static const struct snd_kcontrol_new o182_mix[] = { 940 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN182, 20, 1, 0), 941 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN182, 22, 1, 0), 942 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN182, 24, 1, 0), 943 }; 944 945 static const struct snd_kcontrol_new o183_mix[] = { 946 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN183, 21, 1, 0), 947 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN183, 23, 1, 0), 948 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN183, 25, 1, 0), 949 }; 950 951 static const char * const dl8_dl11_data_sel_mux_text[] = { 952 "dl8", "dl11", 953 }; 954 955 static SOC_ENUM_SINGLE_DECL(dl8_dl11_data_sel_mux_enum, 956 AFE_DAC_CON2, 0, dl8_dl11_data_sel_mux_text); 957 958 static const struct snd_kcontrol_new dl8_dl11_data_sel_mux = 959 SOC_DAPM_ENUM("DL8_DL11 Sink", 960 dl8_dl11_data_sel_mux_enum); 961 962 static const struct snd_soc_dapm_widget mt8188_memif_widgets[] = { 963 /* DL6 */ 964 SND_SOC_DAPM_MIXER("I000", SND_SOC_NOPM, 0, 0, NULL, 0), 965 SND_SOC_DAPM_MIXER("I001", SND_SOC_NOPM, 0, 0, NULL, 0), 966 967 /* DL3 */ 968 SND_SOC_DAPM_MIXER("I020", SND_SOC_NOPM, 0, 0, NULL, 0), 969 SND_SOC_DAPM_MIXER("I021", SND_SOC_NOPM, 0, 0, NULL, 0), 970 971 /* DL11 */ 972 SND_SOC_DAPM_MIXER("I022", SND_SOC_NOPM, 0, 0, NULL, 0), 973 SND_SOC_DAPM_MIXER("I023", SND_SOC_NOPM, 0, 0, NULL, 0), 974 SND_SOC_DAPM_MIXER("I024", SND_SOC_NOPM, 0, 0, NULL, 0), 975 SND_SOC_DAPM_MIXER("I025", SND_SOC_NOPM, 0, 0, NULL, 0), 976 SND_SOC_DAPM_MIXER("I026", SND_SOC_NOPM, 0, 0, NULL, 0), 977 SND_SOC_DAPM_MIXER("I027", SND_SOC_NOPM, 0, 0, NULL, 0), 978 SND_SOC_DAPM_MIXER("I028", SND_SOC_NOPM, 0, 0, NULL, 0), 979 SND_SOC_DAPM_MIXER("I029", SND_SOC_NOPM, 0, 0, NULL, 0), 980 SND_SOC_DAPM_MIXER("I030", SND_SOC_NOPM, 0, 0, NULL, 0), 981 SND_SOC_DAPM_MIXER("I031", SND_SOC_NOPM, 0, 0, NULL, 0), 982 SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0), 983 SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0), 984 SND_SOC_DAPM_MIXER("I034", SND_SOC_NOPM, 0, 0, NULL, 0), 985 SND_SOC_DAPM_MIXER("I035", SND_SOC_NOPM, 0, 0, NULL, 0), 986 SND_SOC_DAPM_MIXER("I036", SND_SOC_NOPM, 0, 0, NULL, 0), 987 SND_SOC_DAPM_MIXER("I037", SND_SOC_NOPM, 0, 0, NULL, 0), 988 989 /* DL11/DL8 */ 990 SND_SOC_DAPM_MIXER("I046", SND_SOC_NOPM, 0, 0, NULL, 0), 991 SND_SOC_DAPM_MIXER("I047", SND_SOC_NOPM, 0, 0, NULL, 0), 992 SND_SOC_DAPM_MIXER("I048", SND_SOC_NOPM, 0, 0, NULL, 0), 993 SND_SOC_DAPM_MIXER("I049", SND_SOC_NOPM, 0, 0, NULL, 0), 994 SND_SOC_DAPM_MIXER("I050", SND_SOC_NOPM, 0, 0, NULL, 0), 995 SND_SOC_DAPM_MIXER("I051", SND_SOC_NOPM, 0, 0, NULL, 0), 996 SND_SOC_DAPM_MIXER("I052", SND_SOC_NOPM, 0, 0, NULL, 0), 997 SND_SOC_DAPM_MIXER("I053", SND_SOC_NOPM, 0, 0, NULL, 0), 998 SND_SOC_DAPM_MIXER("I054", SND_SOC_NOPM, 0, 0, NULL, 0), 999 SND_SOC_DAPM_MIXER("I055", SND_SOC_NOPM, 0, 0, NULL, 0), 1000 SND_SOC_DAPM_MIXER("I056", SND_SOC_NOPM, 0, 0, NULL, 0), 1001 SND_SOC_DAPM_MIXER("I057", SND_SOC_NOPM, 0, 0, NULL, 0), 1002 SND_SOC_DAPM_MIXER("I058", SND_SOC_NOPM, 0, 0, NULL, 0), 1003 SND_SOC_DAPM_MIXER("I059", SND_SOC_NOPM, 0, 0, NULL, 0), 1004 SND_SOC_DAPM_MIXER("I060", SND_SOC_NOPM, 0, 0, NULL, 0), 1005 SND_SOC_DAPM_MIXER("I061", SND_SOC_NOPM, 0, 0, NULL, 0), 1006 1007 /* DL2 */ 1008 SND_SOC_DAPM_MIXER("I070", SND_SOC_NOPM, 0, 0, NULL, 0), 1009 SND_SOC_DAPM_MIXER("I071", SND_SOC_NOPM, 0, 0, NULL, 0), 1010 1011 SND_SOC_DAPM_MUX("DL8_DL11 Mux", 1012 SND_SOC_NOPM, 0, 0, &dl8_dl11_data_sel_mux), 1013 1014 /* UL9 */ 1015 SND_SOC_DAPM_MIXER("O002", SND_SOC_NOPM, 0, 0, 1016 o002_mix, ARRAY_SIZE(o002_mix)), 1017 SND_SOC_DAPM_MIXER("O003", SND_SOC_NOPM, 0, 0, 1018 o003_mix, ARRAY_SIZE(o003_mix)), 1019 SND_SOC_DAPM_MIXER("O004", SND_SOC_NOPM, 0, 0, 1020 o004_mix, ARRAY_SIZE(o004_mix)), 1021 SND_SOC_DAPM_MIXER("O005", SND_SOC_NOPM, 0, 0, 1022 o005_mix, ARRAY_SIZE(o005_mix)), 1023 SND_SOC_DAPM_MIXER("O006", SND_SOC_NOPM, 0, 0, 1024 o006_mix, ARRAY_SIZE(o006_mix)), 1025 SND_SOC_DAPM_MIXER("O007", SND_SOC_NOPM, 0, 0, 1026 o007_mix, ARRAY_SIZE(o007_mix)), 1027 SND_SOC_DAPM_MIXER("O008", SND_SOC_NOPM, 0, 0, 1028 o008_mix, ARRAY_SIZE(o008_mix)), 1029 SND_SOC_DAPM_MIXER("O009", SND_SOC_NOPM, 0, 0, 1030 o009_mix, ARRAY_SIZE(o009_mix)), 1031 SND_SOC_DAPM_MIXER("O010", SND_SOC_NOPM, 0, 0, 1032 o010_mix, ARRAY_SIZE(o010_mix)), 1033 SND_SOC_DAPM_MIXER("O011", SND_SOC_NOPM, 0, 0, 1034 o011_mix, ARRAY_SIZE(o011_mix)), 1035 SND_SOC_DAPM_MIXER("O012", SND_SOC_NOPM, 0, 0, 1036 o012_mix, ARRAY_SIZE(o012_mix)), 1037 SND_SOC_DAPM_MIXER("O013", SND_SOC_NOPM, 0, 0, 1038 o013_mix, ARRAY_SIZE(o013_mix)), 1039 SND_SOC_DAPM_MIXER("O014", SND_SOC_NOPM, 0, 0, 1040 o014_mix, ARRAY_SIZE(o014_mix)), 1041 SND_SOC_DAPM_MIXER("O015", SND_SOC_NOPM, 0, 0, 1042 o015_mix, ARRAY_SIZE(o015_mix)), 1043 SND_SOC_DAPM_MIXER("O016", SND_SOC_NOPM, 0, 0, 1044 o016_mix, ARRAY_SIZE(o016_mix)), 1045 SND_SOC_DAPM_MIXER("O017", SND_SOC_NOPM, 0, 0, 1046 o017_mix, ARRAY_SIZE(o017_mix)), 1047 SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0, 1048 o018_mix, ARRAY_SIZE(o018_mix)), 1049 SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0, 1050 o019_mix, ARRAY_SIZE(o019_mix)), 1051 SND_SOC_DAPM_MIXER("O020", SND_SOC_NOPM, 0, 0, 1052 o020_mix, ARRAY_SIZE(o020_mix)), 1053 SND_SOC_DAPM_MIXER("O021", SND_SOC_NOPM, 0, 0, 1054 o021_mix, ARRAY_SIZE(o021_mix)), 1055 SND_SOC_DAPM_MIXER("O022", SND_SOC_NOPM, 0, 0, 1056 o022_mix, ARRAY_SIZE(o022_mix)), 1057 SND_SOC_DAPM_MIXER("O023", SND_SOC_NOPM, 0, 0, 1058 o023_mix, ARRAY_SIZE(o023_mix)), 1059 SND_SOC_DAPM_MIXER("O024", SND_SOC_NOPM, 0, 0, 1060 o024_mix, ARRAY_SIZE(o024_mix)), 1061 SND_SOC_DAPM_MIXER("O025", SND_SOC_NOPM, 0, 0, 1062 o025_mix, ARRAY_SIZE(o025_mix)), 1063 SND_SOC_DAPM_MIXER("O026", SND_SOC_NOPM, 0, 0, 1064 o026_mix, ARRAY_SIZE(o026_mix)), 1065 SND_SOC_DAPM_MIXER("O027", SND_SOC_NOPM, 0, 0, 1066 o027_mix, ARRAY_SIZE(o027_mix)), 1067 SND_SOC_DAPM_MIXER("O028", SND_SOC_NOPM, 0, 0, 1068 o028_mix, ARRAY_SIZE(o028_mix)), 1069 SND_SOC_DAPM_MIXER("O029", SND_SOC_NOPM, 0, 0, 1070 o029_mix, ARRAY_SIZE(o029_mix)), 1071 SND_SOC_DAPM_MIXER("O030", SND_SOC_NOPM, 0, 0, 1072 o030_mix, ARRAY_SIZE(o030_mix)), 1073 SND_SOC_DAPM_MIXER("O031", SND_SOC_NOPM, 0, 0, 1074 o031_mix, ARRAY_SIZE(o031_mix)), 1075 SND_SOC_DAPM_MIXER("O032", SND_SOC_NOPM, 0, 0, 1076 o032_mix, ARRAY_SIZE(o032_mix)), 1077 SND_SOC_DAPM_MIXER("O033", SND_SOC_NOPM, 0, 0, 1078 o033_mix, ARRAY_SIZE(o033_mix)), 1079 1080 /* UL4 */ 1081 SND_SOC_DAPM_MIXER("O034", SND_SOC_NOPM, 0, 0, 1082 o034_mix, ARRAY_SIZE(o034_mix)), 1083 SND_SOC_DAPM_MIXER("O035", SND_SOC_NOPM, 0, 0, 1084 o035_mix, ARRAY_SIZE(o035_mix)), 1085 1086 /* UL5 */ 1087 SND_SOC_DAPM_MIXER("O036", SND_SOC_NOPM, 0, 0, 1088 o036_mix, ARRAY_SIZE(o036_mix)), 1089 SND_SOC_DAPM_MIXER("O037", SND_SOC_NOPM, 0, 0, 1090 o037_mix, ARRAY_SIZE(o037_mix)), 1091 1092 /* UL10 */ 1093 SND_SOC_DAPM_MIXER("O038", SND_SOC_NOPM, 0, 0, 1094 o038_mix, ARRAY_SIZE(o038_mix)), 1095 SND_SOC_DAPM_MIXER("O039", SND_SOC_NOPM, 0, 0, 1096 o039_mix, ARRAY_SIZE(o039_mix)), 1097 SND_SOC_DAPM_MIXER("O182", SND_SOC_NOPM, 0, 0, 1098 o182_mix, ARRAY_SIZE(o182_mix)), 1099 SND_SOC_DAPM_MIXER("O183", SND_SOC_NOPM, 0, 0, 1100 o183_mix, ARRAY_SIZE(o183_mix)), 1101 1102 /* UL2 */ 1103 SND_SOC_DAPM_MIXER("O040", SND_SOC_NOPM, 0, 0, 1104 o040_mix, ARRAY_SIZE(o040_mix)), 1105 SND_SOC_DAPM_MIXER("O041", SND_SOC_NOPM, 0, 0, 1106 o041_mix, ARRAY_SIZE(o041_mix)), 1107 SND_SOC_DAPM_MIXER("O042", SND_SOC_NOPM, 0, 0, 1108 o042_mix, ARRAY_SIZE(o042_mix)), 1109 SND_SOC_DAPM_MIXER("O043", SND_SOC_NOPM, 0, 0, 1110 o043_mix, ARRAY_SIZE(o043_mix)), 1111 SND_SOC_DAPM_MIXER("O044", SND_SOC_NOPM, 0, 0, 1112 o044_mix, ARRAY_SIZE(o044_mix)), 1113 SND_SOC_DAPM_MIXER("O045", SND_SOC_NOPM, 0, 0, 1114 o045_mix, ARRAY_SIZE(o045_mix)), 1115 SND_SOC_DAPM_MIXER("O046", SND_SOC_NOPM, 0, 0, 1116 o046_mix, ARRAY_SIZE(o046_mix)), 1117 SND_SOC_DAPM_MIXER("O047", SND_SOC_NOPM, 0, 0, 1118 o047_mix, ARRAY_SIZE(o047_mix)), 1119 }; 1120 1121 static const struct snd_soc_dapm_route mt8188_memif_routes[] = { 1122 {"I000", NULL, "DL6"}, 1123 {"I001", NULL, "DL6"}, 1124 1125 {"I020", NULL, "DL3"}, 1126 {"I021", NULL, "DL3"}, 1127 1128 {"I022", NULL, "DL11"}, 1129 {"I023", NULL, "DL11"}, 1130 {"I024", NULL, "DL11"}, 1131 {"I025", NULL, "DL11"}, 1132 {"I026", NULL, "DL11"}, 1133 {"I027", NULL, "DL11"}, 1134 {"I028", NULL, "DL11"}, 1135 {"I029", NULL, "DL11"}, 1136 {"I030", NULL, "DL11"}, 1137 {"I031", NULL, "DL11"}, 1138 {"I032", NULL, "DL11"}, 1139 {"I033", NULL, "DL11"}, 1140 {"I034", NULL, "DL11"}, 1141 {"I035", NULL, "DL11"}, 1142 {"I036", NULL, "DL11"}, 1143 {"I037", NULL, "DL11"}, 1144 1145 {"DL8_DL11 Mux", "dl8", "DL8"}, 1146 {"DL8_DL11 Mux", "dl11", "DL11"}, 1147 1148 {"I046", NULL, "DL8_DL11 Mux"}, 1149 {"I047", NULL, "DL8_DL11 Mux"}, 1150 {"I048", NULL, "DL8_DL11 Mux"}, 1151 {"I049", NULL, "DL8_DL11 Mux"}, 1152 {"I050", NULL, "DL8_DL11 Mux"}, 1153 {"I051", NULL, "DL8_DL11 Mux"}, 1154 {"I052", NULL, "DL8_DL11 Mux"}, 1155 {"I053", NULL, "DL8_DL11 Mux"}, 1156 {"I054", NULL, "DL8_DL11 Mux"}, 1157 {"I055", NULL, "DL8_DL11 Mux"}, 1158 {"I056", NULL, "DL8_DL11 Mux"}, 1159 {"I057", NULL, "DL8_DL11 Mux"}, 1160 {"I058", NULL, "DL8_DL11 Mux"}, 1161 {"I059", NULL, "DL8_DL11 Mux"}, 1162 {"I060", NULL, "DL8_DL11 Mux"}, 1163 {"I061", NULL, "DL8_DL11 Mux"}, 1164 1165 {"I070", NULL, "DL2"}, 1166 {"I071", NULL, "DL2"}, 1167 1168 {"UL9", NULL, "O002"}, 1169 {"UL9", NULL, "O003"}, 1170 {"UL9", NULL, "O004"}, 1171 {"UL9", NULL, "O005"}, 1172 {"UL9", NULL, "O006"}, 1173 {"UL9", NULL, "O007"}, 1174 {"UL9", NULL, "O008"}, 1175 {"UL9", NULL, "O009"}, 1176 {"UL9", NULL, "O010"}, 1177 {"UL9", NULL, "O011"}, 1178 {"UL9", NULL, "O012"}, 1179 {"UL9", NULL, "O013"}, 1180 {"UL9", NULL, "O014"}, 1181 {"UL9", NULL, "O015"}, 1182 {"UL9", NULL, "O016"}, 1183 {"UL9", NULL, "O017"}, 1184 {"UL9", NULL, "O018"}, 1185 {"UL9", NULL, "O019"}, 1186 {"UL9", NULL, "O020"}, 1187 {"UL9", NULL, "O021"}, 1188 {"UL9", NULL, "O022"}, 1189 {"UL9", NULL, "O023"}, 1190 {"UL9", NULL, "O024"}, 1191 {"UL9", NULL, "O025"}, 1192 {"UL9", NULL, "O026"}, 1193 {"UL9", NULL, "O027"}, 1194 {"UL9", NULL, "O028"}, 1195 {"UL9", NULL, "O029"}, 1196 {"UL9", NULL, "O030"}, 1197 {"UL9", NULL, "O031"}, 1198 {"UL9", NULL, "O032"}, 1199 {"UL9", NULL, "O033"}, 1200 1201 {"UL4", NULL, "O034"}, 1202 {"UL4", NULL, "O035"}, 1203 1204 {"UL5", NULL, "O036"}, 1205 {"UL5", NULL, "O037"}, 1206 1207 {"UL10", NULL, "O038"}, 1208 {"UL10", NULL, "O039"}, 1209 {"UL10", NULL, "O182"}, 1210 {"UL10", NULL, "O183"}, 1211 1212 {"UL2", NULL, "O040"}, 1213 {"UL2", NULL, "O041"}, 1214 {"UL2", NULL, "O042"}, 1215 {"UL2", NULL, "O043"}, 1216 {"UL2", NULL, "O044"}, 1217 {"UL2", NULL, "O045"}, 1218 {"UL2", NULL, "O046"}, 1219 {"UL2", NULL, "O047"}, 1220 1221 {"O004", "I000 Switch", "I000"}, 1222 {"O005", "I001 Switch", "I001"}, 1223 1224 {"O006", "I000 Switch", "I000"}, 1225 {"O007", "I001 Switch", "I001"}, 1226 1227 {"O010", "I022 Switch", "I022"}, 1228 {"O011", "I023 Switch", "I023"}, 1229 {"O012", "I024 Switch", "I024"}, 1230 {"O013", "I025 Switch", "I025"}, 1231 {"O014", "I026 Switch", "I026"}, 1232 {"O015", "I027 Switch", "I027"}, 1233 {"O016", "I028 Switch", "I028"}, 1234 {"O017", "I029 Switch", "I029"}, 1235 1236 {"O010", "I046 Switch", "I046"}, 1237 {"O011", "I047 Switch", "I047"}, 1238 {"O012", "I048 Switch", "I048"}, 1239 {"O013", "I049 Switch", "I049"}, 1240 {"O014", "I050 Switch", "I050"}, 1241 {"O015", "I051 Switch", "I051"}, 1242 {"O016", "I052 Switch", "I052"}, 1243 {"O017", "I053 Switch", "I053"}, 1244 1245 {"O002", "I022 Switch", "I022"}, 1246 {"O003", "I023 Switch", "I023"}, 1247 {"O004", "I024 Switch", "I024"}, 1248 {"O005", "I025 Switch", "I025"}, 1249 {"O006", "I026 Switch", "I026"}, 1250 {"O007", "I027 Switch", "I027"}, 1251 {"O008", "I028 Switch", "I028"}, 1252 {"O009", "I029 Switch", "I029"}, 1253 {"O010", "I030 Switch", "I030"}, 1254 {"O011", "I031 Switch", "I031"}, 1255 {"O012", "I032 Switch", "I032"}, 1256 {"O013", "I033 Switch", "I033"}, 1257 {"O014", "I034 Switch", "I034"}, 1258 {"O015", "I035 Switch", "I035"}, 1259 {"O016", "I036 Switch", "I036"}, 1260 {"O017", "I037 Switch", "I037"}, 1261 {"O026", "I046 Switch", "I046"}, 1262 {"O027", "I047 Switch", "I047"}, 1263 {"O028", "I048 Switch", "I048"}, 1264 {"O029", "I049 Switch", "I049"}, 1265 {"O030", "I050 Switch", "I050"}, 1266 {"O031", "I051 Switch", "I051"}, 1267 {"O032", "I052 Switch", "I052"}, 1268 {"O033", "I053 Switch", "I053"}, 1269 1270 {"O002", "I000 Switch", "I000"}, 1271 {"O003", "I001 Switch", "I001"}, 1272 {"O002", "I020 Switch", "I020"}, 1273 {"O003", "I021 Switch", "I021"}, 1274 {"O002", "I070 Switch", "I070"}, 1275 {"O003", "I071 Switch", "I071"}, 1276 1277 {"O034", "I000 Switch", "I000"}, 1278 {"O035", "I001 Switch", "I001"}, 1279 {"O034", "I002 Switch", "I002"}, 1280 {"O035", "I003 Switch", "I003"}, 1281 {"O034", "I012 Switch", "I012"}, 1282 {"O035", "I013 Switch", "I013"}, 1283 {"O034", "I020 Switch", "I020"}, 1284 {"O035", "I021 Switch", "I021"}, 1285 {"O034", "I070 Switch", "I070"}, 1286 {"O035", "I071 Switch", "I071"}, 1287 {"O034", "I072 Switch", "I072"}, 1288 {"O035", "I073 Switch", "I073"}, 1289 1290 {"O036", "I000 Switch", "I000"}, 1291 {"O037", "I001 Switch", "I001"}, 1292 {"O036", "I012 Switch", "I012"}, 1293 {"O037", "I013 Switch", "I013"}, 1294 {"O036", "I020 Switch", "I020"}, 1295 {"O037", "I021 Switch", "I021"}, 1296 {"O036", "I070 Switch", "I070"}, 1297 {"O037", "I071 Switch", "I071"}, 1298 {"O036", "I168 Switch", "I168"}, 1299 {"O037", "I169 Switch", "I169"}, 1300 1301 {"O038", "I022 Switch", "I022"}, 1302 {"O039", "I023 Switch", "I023"}, 1303 {"O182", "I024 Switch", "I024"}, 1304 {"O183", "I025 Switch", "I025"}, 1305 1306 {"O038", "I168 Switch", "I168"}, 1307 {"O039", "I169 Switch", "I169"}, 1308 1309 {"O182", "I020 Switch", "I020"}, 1310 {"O183", "I021 Switch", "I021"}, 1311 1312 {"O182", "I022 Switch", "I022"}, 1313 {"O183", "I023 Switch", "I023"}, 1314 1315 {"O040", "I022 Switch", "I022"}, 1316 {"O041", "I023 Switch", "I023"}, 1317 {"O042", "I024 Switch", "I024"}, 1318 {"O043", "I025 Switch", "I025"}, 1319 {"O044", "I026 Switch", "I026"}, 1320 {"O045", "I027 Switch", "I027"}, 1321 {"O046", "I028 Switch", "I028"}, 1322 {"O047", "I029 Switch", "I029"}, 1323 1324 {"O040", "I002 Switch", "I002"}, 1325 {"O041", "I003 Switch", "I003"}, 1326 1327 {"O002", "I012 Switch", "I012"}, 1328 {"O003", "I013 Switch", "I013"}, 1329 {"O004", "I014 Switch", "I014"}, 1330 {"O005", "I015 Switch", "I015"}, 1331 {"O006", "I016 Switch", "I016"}, 1332 {"O007", "I017 Switch", "I017"}, 1333 {"O008", "I018 Switch", "I018"}, 1334 {"O009", "I019 Switch", "I019"}, 1335 {"O010", "I188 Switch", "I188"}, 1336 {"O011", "I189 Switch", "I189"}, 1337 {"O012", "I190 Switch", "I190"}, 1338 {"O013", "I191 Switch", "I191"}, 1339 {"O014", "I192 Switch", "I192"}, 1340 {"O015", "I193 Switch", "I193"}, 1341 {"O016", "I194 Switch", "I194"}, 1342 {"O017", "I195 Switch", "I195"}, 1343 1344 {"O040", "I012 Switch", "I012"}, 1345 {"O041", "I013 Switch", "I013"}, 1346 {"O042", "I014 Switch", "I014"}, 1347 {"O043", "I015 Switch", "I015"}, 1348 {"O044", "I016 Switch", "I016"}, 1349 {"O045", "I017 Switch", "I017"}, 1350 {"O046", "I018 Switch", "I018"}, 1351 {"O047", "I019 Switch", "I019"}, 1352 1353 {"O002", "I072 Switch", "I072"}, 1354 {"O003", "I073 Switch", "I073"}, 1355 {"O004", "I074 Switch", "I074"}, 1356 {"O005", "I075 Switch", "I075"}, 1357 {"O006", "I076 Switch", "I076"}, 1358 {"O007", "I077 Switch", "I077"}, 1359 {"O008", "I078 Switch", "I078"}, 1360 {"O009", "I079 Switch", "I079"}, 1361 {"O010", "I080 Switch", "I080"}, 1362 {"O011", "I081 Switch", "I081"}, 1363 {"O012", "I082 Switch", "I082"}, 1364 {"O013", "I083 Switch", "I083"}, 1365 {"O014", "I084 Switch", "I084"}, 1366 {"O015", "I085 Switch", "I085"}, 1367 {"O016", "I086 Switch", "I086"}, 1368 {"O017", "I087 Switch", "I087"}, 1369 1370 {"O010", "I072 Switch", "I072"}, 1371 {"O011", "I073 Switch", "I073"}, 1372 {"O012", "I074 Switch", "I074"}, 1373 {"O013", "I075 Switch", "I075"}, 1374 {"O014", "I076 Switch", "I076"}, 1375 {"O015", "I077 Switch", "I077"}, 1376 {"O016", "I078 Switch", "I078"}, 1377 {"O017", "I079 Switch", "I079"}, 1378 {"O018", "I080 Switch", "I080"}, 1379 {"O019", "I081 Switch", "I081"}, 1380 {"O020", "I082 Switch", "I082"}, 1381 {"O021", "I083 Switch", "I083"}, 1382 {"O022", "I084 Switch", "I084"}, 1383 {"O023", "I085 Switch", "I085"}, 1384 {"O024", "I086 Switch", "I086"}, 1385 {"O025", "I087 Switch", "I087"}, 1386 1387 {"O002", "I168 Switch", "I168"}, 1388 {"O003", "I169 Switch", "I169"}, 1389 1390 {"O034", "I168 Switch", "I168"}, 1391 {"O035", "I168 Switch", "I168"}, 1392 {"O035", "I169 Switch", "I169"}, 1393 1394 {"O040", "I168 Switch", "I168"}, 1395 {"O041", "I169 Switch", "I169"}, 1396 }; 1397 1398 static const char * const mt8188_afe_1x_en_sel_text[] = { 1399 "a1sys_a2sys", "a3sys", "a4sys", 1400 }; 1401 1402 static const unsigned int mt8188_afe_1x_en_sel_values[] = { 1403 0, 1, 2, 1404 }; 1405 1406 static SOC_VALUE_ENUM_SINGLE_DECL(dl2_1x_en_sel_enum, 1407 A3_A4_TIMING_SEL1, 18, 0x3, 1408 mt8188_afe_1x_en_sel_text, 1409 mt8188_afe_1x_en_sel_values); 1410 static SOC_VALUE_ENUM_SINGLE_DECL(dl3_1x_en_sel_enum, 1411 A3_A4_TIMING_SEL1, 20, 0x3, 1412 mt8188_afe_1x_en_sel_text, 1413 mt8188_afe_1x_en_sel_values); 1414 static SOC_VALUE_ENUM_SINGLE_DECL(dl6_1x_en_sel_enum, 1415 A3_A4_TIMING_SEL1, 22, 0x3, 1416 mt8188_afe_1x_en_sel_text, 1417 mt8188_afe_1x_en_sel_values); 1418 static SOC_VALUE_ENUM_SINGLE_DECL(dl7_1x_en_sel_enum, 1419 A3_A4_TIMING_SEL1, 24, 0x3, 1420 mt8188_afe_1x_en_sel_text, 1421 mt8188_afe_1x_en_sel_values); 1422 static SOC_VALUE_ENUM_SINGLE_DECL(dl8_1x_en_sel_enum, 1423 A3_A4_TIMING_SEL1, 26, 0x3, 1424 mt8188_afe_1x_en_sel_text, 1425 mt8188_afe_1x_en_sel_values); 1426 static SOC_VALUE_ENUM_SINGLE_DECL(dl10_1x_en_sel_enum, 1427 A3_A4_TIMING_SEL1, 28, 0x3, 1428 mt8188_afe_1x_en_sel_text, 1429 mt8188_afe_1x_en_sel_values); 1430 static SOC_VALUE_ENUM_SINGLE_DECL(dl11_1x_en_sel_enum, 1431 A3_A4_TIMING_SEL1, 30, 0x3, 1432 mt8188_afe_1x_en_sel_text, 1433 mt8188_afe_1x_en_sel_values); 1434 static SOC_VALUE_ENUM_SINGLE_DECL(ul1_1x_en_sel_enum, 1435 A3_A4_TIMING_SEL1, 0, 0x3, 1436 mt8188_afe_1x_en_sel_text, 1437 mt8188_afe_1x_en_sel_values); 1438 static SOC_VALUE_ENUM_SINGLE_DECL(ul2_1x_en_sel_enum, 1439 A3_A4_TIMING_SEL1, 2, 0x3, 1440 mt8188_afe_1x_en_sel_text, 1441 mt8188_afe_1x_en_sel_values); 1442 static SOC_VALUE_ENUM_SINGLE_DECL(ul3_1x_en_sel_enum, 1443 A3_A4_TIMING_SEL1, 4, 0x3, 1444 mt8188_afe_1x_en_sel_text, 1445 mt8188_afe_1x_en_sel_values); 1446 static SOC_VALUE_ENUM_SINGLE_DECL(ul4_1x_en_sel_enum, 1447 A3_A4_TIMING_SEL1, 6, 0x3, 1448 mt8188_afe_1x_en_sel_text, 1449 mt8188_afe_1x_en_sel_values); 1450 static SOC_VALUE_ENUM_SINGLE_DECL(ul5_1x_en_sel_enum, 1451 A3_A4_TIMING_SEL1, 8, 0x3, 1452 mt8188_afe_1x_en_sel_text, 1453 mt8188_afe_1x_en_sel_values); 1454 static SOC_VALUE_ENUM_SINGLE_DECL(ul6_1x_en_sel_enum, 1455 A3_A4_TIMING_SEL1, 10, 0x3, 1456 mt8188_afe_1x_en_sel_text, 1457 mt8188_afe_1x_en_sel_values); 1458 static SOC_VALUE_ENUM_SINGLE_DECL(ul8_1x_en_sel_enum, 1459 A3_A4_TIMING_SEL1, 12, 0x3, 1460 mt8188_afe_1x_en_sel_text, 1461 mt8188_afe_1x_en_sel_values); 1462 static SOC_VALUE_ENUM_SINGLE_DECL(ul9_1x_en_sel_enum, 1463 A3_A4_TIMING_SEL1, 14, 0x3, 1464 mt8188_afe_1x_en_sel_text, 1465 mt8188_afe_1x_en_sel_values); 1466 static SOC_VALUE_ENUM_SINGLE_DECL(ul10_1x_en_sel_enum, 1467 A3_A4_TIMING_SEL1, 16, 0x3, 1468 mt8188_afe_1x_en_sel_text, 1469 mt8188_afe_1x_en_sel_values); 1470 1471 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq1_1x_en_sel_enum, 1472 A3_A4_TIMING_SEL6, 0, 0x3, 1473 mt8188_afe_1x_en_sel_text, 1474 mt8188_afe_1x_en_sel_values); 1475 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq2_1x_en_sel_enum, 1476 A3_A4_TIMING_SEL6, 2, 0x3, 1477 mt8188_afe_1x_en_sel_text, 1478 mt8188_afe_1x_en_sel_values); 1479 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq3_1x_en_sel_enum, 1480 A3_A4_TIMING_SEL6, 4, 0x3, 1481 mt8188_afe_1x_en_sel_text, 1482 mt8188_afe_1x_en_sel_values); 1483 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq4_1x_en_sel_enum, 1484 A3_A4_TIMING_SEL6, 6, 0x3, 1485 mt8188_afe_1x_en_sel_text, 1486 mt8188_afe_1x_en_sel_values); 1487 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq5_1x_en_sel_enum, 1488 A3_A4_TIMING_SEL6, 8, 0x3, 1489 mt8188_afe_1x_en_sel_text, 1490 mt8188_afe_1x_en_sel_values); 1491 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq6_1x_en_sel_enum, 1492 A3_A4_TIMING_SEL6, 10, 0x3, 1493 mt8188_afe_1x_en_sel_text, 1494 mt8188_afe_1x_en_sel_values); 1495 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq7_1x_en_sel_enum, 1496 A3_A4_TIMING_SEL6, 12, 0x3, 1497 mt8188_afe_1x_en_sel_text, 1498 mt8188_afe_1x_en_sel_values); 1499 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq8_1x_en_sel_enum, 1500 A3_A4_TIMING_SEL6, 14, 0x3, 1501 mt8188_afe_1x_en_sel_text, 1502 mt8188_afe_1x_en_sel_values); 1503 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq9_1x_en_sel_enum, 1504 A3_A4_TIMING_SEL6, 16, 0x3, 1505 mt8188_afe_1x_en_sel_text, 1506 mt8188_afe_1x_en_sel_values); 1507 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq10_1x_en_sel_enum, 1508 A3_A4_TIMING_SEL6, 18, 0x3, 1509 mt8188_afe_1x_en_sel_text, 1510 mt8188_afe_1x_en_sel_values); 1511 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq11_1x_en_sel_enum, 1512 A3_A4_TIMING_SEL6, 20, 0x3, 1513 mt8188_afe_1x_en_sel_text, 1514 mt8188_afe_1x_en_sel_values); 1515 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq12_1x_en_sel_enum, 1516 A3_A4_TIMING_SEL6, 22, 0x3, 1517 mt8188_afe_1x_en_sel_text, 1518 mt8188_afe_1x_en_sel_values); 1519 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq13_1x_en_sel_enum, 1520 A3_A4_TIMING_SEL6, 24, 0x3, 1521 mt8188_afe_1x_en_sel_text, 1522 mt8188_afe_1x_en_sel_values); 1523 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq14_1x_en_sel_enum, 1524 A3_A4_TIMING_SEL6, 26, 0x3, 1525 mt8188_afe_1x_en_sel_text, 1526 mt8188_afe_1x_en_sel_values); 1527 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq15_1x_en_sel_enum, 1528 A3_A4_TIMING_SEL6, 28, 0x3, 1529 mt8188_afe_1x_en_sel_text, 1530 mt8188_afe_1x_en_sel_values); 1531 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq16_1x_en_sel_enum, 1532 A3_A4_TIMING_SEL6, 30, 0x3, 1533 mt8188_afe_1x_en_sel_text, 1534 mt8188_afe_1x_en_sel_values); 1535 1536 static const char * const mt8188_afe_fs_timing_sel_text[] = { 1537 "asys", 1538 "etdmout1_1x_en", 1539 "etdmout2_1x_en", 1540 "etdmout3_1x_en", 1541 "etdmin1_1x_en", 1542 "etdmin2_1x_en", 1543 "etdmin1_nx_en", 1544 "etdmin2_nx_en", 1545 }; 1546 1547 static const unsigned int mt8188_afe_fs_timing_sel_values[] = { 1548 0, 1549 MT8188_ETDM_OUT1_1X_EN, 1550 MT8188_ETDM_OUT2_1X_EN, 1551 MT8188_ETDM_OUT3_1X_EN, 1552 MT8188_ETDM_IN1_1X_EN, 1553 MT8188_ETDM_IN2_1X_EN, 1554 MT8188_ETDM_IN1_NX_EN, 1555 MT8188_ETDM_IN2_NX_EN, 1556 }; 1557 1558 static SOC_VALUE_ENUM_SINGLE_DECL(dl2_fs_timing_sel_enum, 1559 SND_SOC_NOPM, 0, 0, 1560 mt8188_afe_fs_timing_sel_text, 1561 mt8188_afe_fs_timing_sel_values); 1562 static SOC_VALUE_ENUM_SINGLE_DECL(dl3_fs_timing_sel_enum, 1563 SND_SOC_NOPM, 0, 0, 1564 mt8188_afe_fs_timing_sel_text, 1565 mt8188_afe_fs_timing_sel_values); 1566 static SOC_VALUE_ENUM_SINGLE_DECL(dl6_fs_timing_sel_enum, 1567 SND_SOC_NOPM, 0, 0, 1568 mt8188_afe_fs_timing_sel_text, 1569 mt8188_afe_fs_timing_sel_values); 1570 static SOC_VALUE_ENUM_SINGLE_DECL(dl8_fs_timing_sel_enum, 1571 SND_SOC_NOPM, 0, 0, 1572 mt8188_afe_fs_timing_sel_text, 1573 mt8188_afe_fs_timing_sel_values); 1574 static SOC_VALUE_ENUM_SINGLE_DECL(dl11_fs_timing_sel_enum, 1575 SND_SOC_NOPM, 0, 0, 1576 mt8188_afe_fs_timing_sel_text, 1577 mt8188_afe_fs_timing_sel_values); 1578 static SOC_VALUE_ENUM_SINGLE_DECL(ul2_fs_timing_sel_enum, 1579 SND_SOC_NOPM, 0, 0, 1580 mt8188_afe_fs_timing_sel_text, 1581 mt8188_afe_fs_timing_sel_values); 1582 static SOC_VALUE_ENUM_SINGLE_DECL(ul4_fs_timing_sel_enum, 1583 SND_SOC_NOPM, 0, 0, 1584 mt8188_afe_fs_timing_sel_text, 1585 mt8188_afe_fs_timing_sel_values); 1586 static SOC_VALUE_ENUM_SINGLE_DECL(ul5_fs_timing_sel_enum, 1587 SND_SOC_NOPM, 0, 0, 1588 mt8188_afe_fs_timing_sel_text, 1589 mt8188_afe_fs_timing_sel_values); 1590 static SOC_VALUE_ENUM_SINGLE_DECL(ul9_fs_timing_sel_enum, 1591 SND_SOC_NOPM, 0, 0, 1592 mt8188_afe_fs_timing_sel_text, 1593 mt8188_afe_fs_timing_sel_values); 1594 static SOC_VALUE_ENUM_SINGLE_DECL(ul10_fs_timing_sel_enum, 1595 SND_SOC_NOPM, 0, 0, 1596 mt8188_afe_fs_timing_sel_text, 1597 mt8188_afe_fs_timing_sel_values); 1598 1599 static int mt8188_memif_1x_en_sel_put(struct snd_kcontrol *kcontrol, 1600 struct snd_ctl_elem_value *ucontrol) 1601 { 1602 struct snd_soc_component *component = 1603 snd_soc_kcontrol_component(kcontrol); 1604 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 1605 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1606 struct mtk_dai_memif_priv *memif_priv; 1607 unsigned int dai_id = kcontrol->id.device; 1608 long val = ucontrol->value.integer.value[0]; 1609 int ret = 0; 1610 1611 memif_priv = afe_priv->dai_priv[dai_id]; 1612 1613 if (val == memif_priv->asys_timing_sel) 1614 return 0; 1615 1616 ret = snd_soc_put_enum_double(kcontrol, ucontrol); 1617 1618 memif_priv->asys_timing_sel = val; 1619 1620 return ret; 1621 } 1622 1623 static int mt8188_asys_irq_1x_en_sel_put(struct snd_kcontrol *kcontrol, 1624 struct snd_ctl_elem_value *ucontrol) 1625 { 1626 struct snd_soc_component *component = 1627 snd_soc_kcontrol_component(kcontrol); 1628 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 1629 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1630 unsigned int id = kcontrol->id.device; 1631 long val = ucontrol->value.integer.value[0]; 1632 int ret = 0; 1633 1634 if (val == afe_priv->irq_priv[id].asys_timing_sel) 1635 return 0; 1636 1637 ret = snd_soc_put_enum_double(kcontrol, ucontrol); 1638 1639 afe_priv->irq_priv[id].asys_timing_sel = val; 1640 1641 return ret; 1642 } 1643 1644 static int mt8188_memif_fs_timing_sel_get(struct snd_kcontrol *kcontrol, 1645 struct snd_ctl_elem_value *ucontrol) 1646 { 1647 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1648 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 1649 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1650 struct mtk_dai_memif_priv *memif_priv; 1651 unsigned int dai_id = kcontrol->id.device; 1652 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1653 1654 memif_priv = afe_priv->dai_priv[dai_id]; 1655 1656 ucontrol->value.enumerated.item[0] = 1657 snd_soc_enum_val_to_item(e, memif_priv->fs_timing); 1658 1659 return 0; 1660 } 1661 1662 static int mt8188_memif_fs_timing_sel_put(struct snd_kcontrol *kcontrol, 1663 struct snd_ctl_elem_value *ucontrol) 1664 { 1665 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1666 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 1667 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1668 struct mtk_dai_memif_priv *memif_priv; 1669 unsigned int dai_id = kcontrol->id.device; 1670 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1671 unsigned int *item = ucontrol->value.enumerated.item; 1672 unsigned int prev_item = 0; 1673 1674 if (item[0] >= e->items) 1675 return -EINVAL; 1676 1677 memif_priv = afe_priv->dai_priv[dai_id]; 1678 1679 prev_item = snd_soc_enum_val_to_item(e, memif_priv->fs_timing); 1680 1681 if (item[0] == prev_item) 1682 return 0; 1683 1684 memif_priv->fs_timing = snd_soc_enum_item_to_val(e, item[0]); 1685 1686 return 1; 1687 } 1688 1689 static const struct snd_kcontrol_new mt8188_memif_controls[] = { 1690 MT8188_SOC_ENUM_EXT("dl2_1x_en_sel", 1691 dl2_1x_en_sel_enum, 1692 snd_soc_get_enum_double, 1693 mt8188_memif_1x_en_sel_put, 1694 MT8188_AFE_MEMIF_DL2), 1695 MT8188_SOC_ENUM_EXT("dl3_1x_en_sel", 1696 dl3_1x_en_sel_enum, 1697 snd_soc_get_enum_double, 1698 mt8188_memif_1x_en_sel_put, 1699 MT8188_AFE_MEMIF_DL3), 1700 MT8188_SOC_ENUM_EXT("dl6_1x_en_sel", 1701 dl6_1x_en_sel_enum, 1702 snd_soc_get_enum_double, 1703 mt8188_memif_1x_en_sel_put, 1704 MT8188_AFE_MEMIF_DL6), 1705 MT8188_SOC_ENUM_EXT("dl7_1x_en_sel", 1706 dl7_1x_en_sel_enum, 1707 snd_soc_get_enum_double, 1708 mt8188_memif_1x_en_sel_put, 1709 MT8188_AFE_MEMIF_DL7), 1710 MT8188_SOC_ENUM_EXT("dl8_1x_en_sel", 1711 dl8_1x_en_sel_enum, 1712 snd_soc_get_enum_double, 1713 mt8188_memif_1x_en_sel_put, 1714 MT8188_AFE_MEMIF_DL8), 1715 MT8188_SOC_ENUM_EXT("dl10_1x_en_sel", 1716 dl10_1x_en_sel_enum, 1717 snd_soc_get_enum_double, 1718 mt8188_memif_1x_en_sel_put, 1719 MT8188_AFE_MEMIF_DL10), 1720 MT8188_SOC_ENUM_EXT("dl11_1x_en_sel", 1721 dl11_1x_en_sel_enum, 1722 snd_soc_get_enum_double, 1723 mt8188_memif_1x_en_sel_put, 1724 MT8188_AFE_MEMIF_DL11), 1725 MT8188_SOC_ENUM_EXT("ul1_1x_en_sel", 1726 ul1_1x_en_sel_enum, 1727 snd_soc_get_enum_double, 1728 mt8188_memif_1x_en_sel_put, 1729 MT8188_AFE_MEMIF_UL1), 1730 MT8188_SOC_ENUM_EXT("ul2_1x_en_sel", 1731 ul2_1x_en_sel_enum, 1732 snd_soc_get_enum_double, 1733 mt8188_memif_1x_en_sel_put, 1734 MT8188_AFE_MEMIF_UL2), 1735 MT8188_SOC_ENUM_EXT("ul3_1x_en_sel", 1736 ul3_1x_en_sel_enum, 1737 snd_soc_get_enum_double, 1738 mt8188_memif_1x_en_sel_put, 1739 MT8188_AFE_MEMIF_UL3), 1740 MT8188_SOC_ENUM_EXT("ul4_1x_en_sel", 1741 ul4_1x_en_sel_enum, 1742 snd_soc_get_enum_double, 1743 mt8188_memif_1x_en_sel_put, 1744 MT8188_AFE_MEMIF_UL4), 1745 MT8188_SOC_ENUM_EXT("ul5_1x_en_sel", 1746 ul5_1x_en_sel_enum, 1747 snd_soc_get_enum_double, 1748 mt8188_memif_1x_en_sel_put, 1749 MT8188_AFE_MEMIF_UL5), 1750 MT8188_SOC_ENUM_EXT("ul6_1x_en_sel", 1751 ul6_1x_en_sel_enum, 1752 snd_soc_get_enum_double, 1753 mt8188_memif_1x_en_sel_put, 1754 MT8188_AFE_MEMIF_UL6), 1755 MT8188_SOC_ENUM_EXT("ul8_1x_en_sel", 1756 ul8_1x_en_sel_enum, 1757 snd_soc_get_enum_double, 1758 mt8188_memif_1x_en_sel_put, 1759 MT8188_AFE_MEMIF_UL8), 1760 MT8188_SOC_ENUM_EXT("ul9_1x_en_sel", 1761 ul9_1x_en_sel_enum, 1762 snd_soc_get_enum_double, 1763 mt8188_memif_1x_en_sel_put, 1764 MT8188_AFE_MEMIF_UL9), 1765 MT8188_SOC_ENUM_EXT("ul10_1x_en_sel", 1766 ul10_1x_en_sel_enum, 1767 snd_soc_get_enum_double, 1768 mt8188_memif_1x_en_sel_put, 1769 MT8188_AFE_MEMIF_UL10), 1770 MT8188_SOC_ENUM_EXT("asys_irq1_1x_en_sel", 1771 asys_irq1_1x_en_sel_enum, 1772 snd_soc_get_enum_double, 1773 mt8188_asys_irq_1x_en_sel_put, 1774 MT8188_AFE_IRQ_13), 1775 MT8188_SOC_ENUM_EXT("asys_irq2_1x_en_sel", 1776 asys_irq2_1x_en_sel_enum, 1777 snd_soc_get_enum_double, 1778 mt8188_asys_irq_1x_en_sel_put, 1779 MT8188_AFE_IRQ_14), 1780 MT8188_SOC_ENUM_EXT("asys_irq3_1x_en_sel", 1781 asys_irq3_1x_en_sel_enum, 1782 snd_soc_get_enum_double, 1783 mt8188_asys_irq_1x_en_sel_put, 1784 MT8188_AFE_IRQ_15), 1785 MT8188_SOC_ENUM_EXT("asys_irq4_1x_en_sel", 1786 asys_irq4_1x_en_sel_enum, 1787 snd_soc_get_enum_double, 1788 mt8188_asys_irq_1x_en_sel_put, 1789 MT8188_AFE_IRQ_16), 1790 MT8188_SOC_ENUM_EXT("asys_irq5_1x_en_sel", 1791 asys_irq5_1x_en_sel_enum, 1792 snd_soc_get_enum_double, 1793 mt8188_asys_irq_1x_en_sel_put, 1794 MT8188_AFE_IRQ_17), 1795 MT8188_SOC_ENUM_EXT("asys_irq6_1x_en_sel", 1796 asys_irq6_1x_en_sel_enum, 1797 snd_soc_get_enum_double, 1798 mt8188_asys_irq_1x_en_sel_put, 1799 MT8188_AFE_IRQ_18), 1800 MT8188_SOC_ENUM_EXT("asys_irq7_1x_en_sel", 1801 asys_irq7_1x_en_sel_enum, 1802 snd_soc_get_enum_double, 1803 mt8188_asys_irq_1x_en_sel_put, 1804 MT8188_AFE_IRQ_19), 1805 MT8188_SOC_ENUM_EXT("asys_irq8_1x_en_sel", 1806 asys_irq8_1x_en_sel_enum, 1807 snd_soc_get_enum_double, 1808 mt8188_asys_irq_1x_en_sel_put, 1809 MT8188_AFE_IRQ_20), 1810 MT8188_SOC_ENUM_EXT("asys_irq9_1x_en_sel", 1811 asys_irq9_1x_en_sel_enum, 1812 snd_soc_get_enum_double, 1813 mt8188_asys_irq_1x_en_sel_put, 1814 MT8188_AFE_IRQ_21), 1815 MT8188_SOC_ENUM_EXT("asys_irq10_1x_en_sel", 1816 asys_irq10_1x_en_sel_enum, 1817 snd_soc_get_enum_double, 1818 mt8188_asys_irq_1x_en_sel_put, 1819 MT8188_AFE_IRQ_22), 1820 MT8188_SOC_ENUM_EXT("asys_irq11_1x_en_sel", 1821 asys_irq11_1x_en_sel_enum, 1822 snd_soc_get_enum_double, 1823 mt8188_asys_irq_1x_en_sel_put, 1824 MT8188_AFE_IRQ_23), 1825 MT8188_SOC_ENUM_EXT("asys_irq12_1x_en_sel", 1826 asys_irq12_1x_en_sel_enum, 1827 snd_soc_get_enum_double, 1828 mt8188_asys_irq_1x_en_sel_put, 1829 MT8188_AFE_IRQ_24), 1830 MT8188_SOC_ENUM_EXT("asys_irq13_1x_en_sel", 1831 asys_irq13_1x_en_sel_enum, 1832 snd_soc_get_enum_double, 1833 mt8188_asys_irq_1x_en_sel_put, 1834 MT8188_AFE_IRQ_25), 1835 MT8188_SOC_ENUM_EXT("asys_irq14_1x_en_sel", 1836 asys_irq14_1x_en_sel_enum, 1837 snd_soc_get_enum_double, 1838 mt8188_asys_irq_1x_en_sel_put, 1839 MT8188_AFE_IRQ_26), 1840 MT8188_SOC_ENUM_EXT("asys_irq15_1x_en_sel", 1841 asys_irq15_1x_en_sel_enum, 1842 snd_soc_get_enum_double, 1843 mt8188_asys_irq_1x_en_sel_put, 1844 MT8188_AFE_IRQ_27), 1845 MT8188_SOC_ENUM_EXT("asys_irq16_1x_en_sel", 1846 asys_irq16_1x_en_sel_enum, 1847 snd_soc_get_enum_double, 1848 mt8188_asys_irq_1x_en_sel_put, 1849 MT8188_AFE_IRQ_28), 1850 MT8188_SOC_ENUM_EXT("dl2_fs_timing_sel", 1851 dl2_fs_timing_sel_enum, 1852 mt8188_memif_fs_timing_sel_get, 1853 mt8188_memif_fs_timing_sel_put, 1854 MT8188_AFE_MEMIF_DL2), 1855 MT8188_SOC_ENUM_EXT("dl3_fs_timing_sel", 1856 dl3_fs_timing_sel_enum, 1857 mt8188_memif_fs_timing_sel_get, 1858 mt8188_memif_fs_timing_sel_put, 1859 MT8188_AFE_MEMIF_DL3), 1860 MT8188_SOC_ENUM_EXT("dl6_fs_timing_sel", 1861 dl6_fs_timing_sel_enum, 1862 mt8188_memif_fs_timing_sel_get, 1863 mt8188_memif_fs_timing_sel_put, 1864 MT8188_AFE_MEMIF_DL6), 1865 MT8188_SOC_ENUM_EXT("dl8_fs_timing_sel", 1866 dl8_fs_timing_sel_enum, 1867 mt8188_memif_fs_timing_sel_get, 1868 mt8188_memif_fs_timing_sel_put, 1869 MT8188_AFE_MEMIF_DL8), 1870 MT8188_SOC_ENUM_EXT("dl11_fs_timing_sel", 1871 dl11_fs_timing_sel_enum, 1872 mt8188_memif_fs_timing_sel_get, 1873 mt8188_memif_fs_timing_sel_put, 1874 MT8188_AFE_MEMIF_DL11), 1875 MT8188_SOC_ENUM_EXT("ul2_fs_timing_sel", 1876 ul2_fs_timing_sel_enum, 1877 mt8188_memif_fs_timing_sel_get, 1878 mt8188_memif_fs_timing_sel_put, 1879 MT8188_AFE_MEMIF_UL2), 1880 MT8188_SOC_ENUM_EXT("ul4_fs_timing_sel", 1881 ul4_fs_timing_sel_enum, 1882 mt8188_memif_fs_timing_sel_get, 1883 mt8188_memif_fs_timing_sel_put, 1884 MT8188_AFE_MEMIF_UL4), 1885 MT8188_SOC_ENUM_EXT("ul5_fs_timing_sel", 1886 ul5_fs_timing_sel_enum, 1887 mt8188_memif_fs_timing_sel_get, 1888 mt8188_memif_fs_timing_sel_put, 1889 MT8188_AFE_MEMIF_UL5), 1890 MT8188_SOC_ENUM_EXT("ul9_fs_timing_sel", 1891 ul9_fs_timing_sel_enum, 1892 mt8188_memif_fs_timing_sel_get, 1893 mt8188_memif_fs_timing_sel_put, 1894 MT8188_AFE_MEMIF_UL9), 1895 MT8188_SOC_ENUM_EXT("ul10_fs_timing_sel", 1896 ul10_fs_timing_sel_enum, 1897 mt8188_memif_fs_timing_sel_get, 1898 mt8188_memif_fs_timing_sel_put, 1899 MT8188_AFE_MEMIF_UL10), 1900 }; 1901 1902 static const struct mtk_base_memif_data memif_data[MT8188_AFE_MEMIF_NUM] = { 1903 [MT8188_AFE_MEMIF_DL2] = { 1904 .name = "DL2", 1905 .id = MT8188_AFE_MEMIF_DL2, 1906 .reg_ofs_base = AFE_DL2_BASE, 1907 .reg_ofs_cur = AFE_DL2_CUR, 1908 .reg_ofs_end = AFE_DL2_END, 1909 .fs_reg = AFE_MEMIF_AGENT_FS_CON0, 1910 .fs_shift = 10, 1911 .fs_maskbit = 0x1f, 1912 .mono_reg = -1, 1913 .mono_shift = 0, 1914 .int_odd_flag_reg = -1, 1915 .int_odd_flag_shift = 0, 1916 .enable_reg = AFE_DAC_CON0, 1917 .enable_shift = 18, 1918 .hd_reg = AFE_DL2_CON0, 1919 .hd_shift = 5, 1920 .agent_disable_reg = AUDIO_TOP_CON5, 1921 .agent_disable_shift = 18, 1922 .ch_num_reg = AFE_DL2_CON0, 1923 .ch_num_shift = 0, 1924 .ch_num_maskbit = 0x1f, 1925 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1926 .msb_shift = 18, 1927 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1928 .msb_end_shift = 18, 1929 }, 1930 [MT8188_AFE_MEMIF_DL3] = { 1931 .name = "DL3", 1932 .id = MT8188_AFE_MEMIF_DL3, 1933 .reg_ofs_base = AFE_DL3_BASE, 1934 .reg_ofs_cur = AFE_DL3_CUR, 1935 .reg_ofs_end = AFE_DL3_END, 1936 .fs_reg = AFE_MEMIF_AGENT_FS_CON0, 1937 .fs_shift = 15, 1938 .fs_maskbit = 0x1f, 1939 .mono_reg = -1, 1940 .mono_shift = 0, 1941 .int_odd_flag_reg = -1, 1942 .int_odd_flag_shift = 0, 1943 .enable_reg = AFE_DAC_CON0, 1944 .enable_shift = 19, 1945 .hd_reg = AFE_DL3_CON0, 1946 .hd_shift = 5, 1947 .agent_disable_reg = AUDIO_TOP_CON5, 1948 .agent_disable_shift = 19, 1949 .ch_num_reg = AFE_DL3_CON0, 1950 .ch_num_shift = 0, 1951 .ch_num_maskbit = 0x1f, 1952 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1953 .msb_shift = 19, 1954 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1955 .msb_end_shift = 19, 1956 }, 1957 [MT8188_AFE_MEMIF_DL6] = { 1958 .name = "DL6", 1959 .id = MT8188_AFE_MEMIF_DL6, 1960 .reg_ofs_base = AFE_DL6_BASE, 1961 .reg_ofs_cur = AFE_DL6_CUR, 1962 .reg_ofs_end = AFE_DL6_END, 1963 .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 1964 .fs_shift = 0, 1965 .fs_maskbit = 0x1f, 1966 .mono_reg = -1, 1967 .mono_shift = 0, 1968 .int_odd_flag_reg = -1, 1969 .int_odd_flag_shift = 0, 1970 .enable_reg = AFE_DAC_CON0, 1971 .enable_shift = 22, 1972 .hd_reg = AFE_DL6_CON0, 1973 .hd_shift = 5, 1974 .agent_disable_reg = AUDIO_TOP_CON5, 1975 .agent_disable_shift = 22, 1976 .ch_num_reg = AFE_DL6_CON0, 1977 .ch_num_shift = 0, 1978 .ch_num_maskbit = 0x1f, 1979 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1980 .msb_shift = 22, 1981 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1982 .msb_end_shift = 22, 1983 }, 1984 [MT8188_AFE_MEMIF_DL7] = { 1985 .name = "DL7", 1986 .id = MT8188_AFE_MEMIF_DL7, 1987 .reg_ofs_base = AFE_DL7_BASE, 1988 .reg_ofs_cur = AFE_DL7_CUR, 1989 .reg_ofs_end = AFE_DL7_END, 1990 .fs_reg = -1, 1991 .fs_shift = 0, 1992 .fs_maskbit = 0, 1993 .mono_reg = -1, 1994 .mono_shift = 0, 1995 .int_odd_flag_reg = -1, 1996 .int_odd_flag_shift = 0, 1997 .enable_reg = AFE_DAC_CON0, 1998 .enable_shift = 23, 1999 .hd_reg = AFE_DL7_CON0, 2000 .hd_shift = 5, 2001 .agent_disable_reg = AUDIO_TOP_CON5, 2002 .agent_disable_shift = 23, 2003 .ch_num_reg = AFE_DL7_CON0, 2004 .ch_num_shift = 0, 2005 .ch_num_maskbit = 0x1f, 2006 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2007 .msb_shift = 23, 2008 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2009 .msb_end_shift = 23, 2010 }, 2011 [MT8188_AFE_MEMIF_DL8] = { 2012 .name = "DL8", 2013 .id = MT8188_AFE_MEMIF_DL8, 2014 .reg_ofs_base = AFE_DL8_BASE, 2015 .reg_ofs_cur = AFE_DL8_CUR, 2016 .reg_ofs_end = AFE_DL8_END, 2017 .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 2018 .fs_shift = 10, 2019 .fs_maskbit = 0x1f, 2020 .mono_reg = -1, 2021 .mono_shift = 0, 2022 .int_odd_flag_reg = -1, 2023 .int_odd_flag_shift = 0, 2024 .enable_reg = AFE_DAC_CON0, 2025 .enable_shift = 24, 2026 .hd_reg = AFE_DL8_CON0, 2027 .hd_shift = 6, 2028 .agent_disable_reg = AUDIO_TOP_CON5, 2029 .agent_disable_shift = 24, 2030 .ch_num_reg = AFE_DL8_CON0, 2031 .ch_num_shift = 0, 2032 .ch_num_maskbit = 0x3f, 2033 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2034 .msb_shift = 24, 2035 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2036 .msb_end_shift = 24, 2037 }, 2038 [MT8188_AFE_MEMIF_DL10] = { 2039 .name = "DL10", 2040 .id = MT8188_AFE_MEMIF_DL10, 2041 .reg_ofs_base = AFE_DL10_BASE, 2042 .reg_ofs_cur = AFE_DL10_CUR, 2043 .reg_ofs_end = AFE_DL10_END, 2044 .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 2045 .fs_shift = 20, 2046 .fs_maskbit = 0x1f, 2047 .mono_reg = -1, 2048 .mono_shift = 0, 2049 .int_odd_flag_reg = -1, 2050 .int_odd_flag_shift = 0, 2051 .enable_reg = AFE_DAC_CON0, 2052 .enable_shift = 26, 2053 .hd_reg = AFE_DL10_CON0, 2054 .hd_shift = 5, 2055 .agent_disable_reg = AUDIO_TOP_CON5, 2056 .agent_disable_shift = 26, 2057 .ch_num_reg = AFE_DL10_CON0, 2058 .ch_num_shift = 0, 2059 .ch_num_maskbit = 0x1f, 2060 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2061 .msb_shift = 26, 2062 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2063 .msb_end_shift = 26, 2064 }, 2065 [MT8188_AFE_MEMIF_DL11] = { 2066 .name = "DL11", 2067 .id = MT8188_AFE_MEMIF_DL11, 2068 .reg_ofs_base = AFE_DL11_BASE, 2069 .reg_ofs_cur = AFE_DL11_CUR, 2070 .reg_ofs_end = AFE_DL11_END, 2071 .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 2072 .fs_shift = 25, 2073 .fs_maskbit = 0x1f, 2074 .mono_reg = -1, 2075 .mono_shift = 0, 2076 .int_odd_flag_reg = -1, 2077 .int_odd_flag_shift = 0, 2078 .enable_reg = AFE_DAC_CON0, 2079 .enable_shift = 27, 2080 .hd_reg = AFE_DL11_CON0, 2081 .hd_shift = 7, 2082 .agent_disable_reg = AUDIO_TOP_CON5, 2083 .agent_disable_shift = 27, 2084 .ch_num_reg = AFE_DL11_CON0, 2085 .ch_num_shift = 0, 2086 .ch_num_maskbit = 0x7f, 2087 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2088 .msb_shift = 27, 2089 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2090 .msb_end_shift = 27, 2091 }, 2092 [MT8188_AFE_MEMIF_UL1] = { 2093 .name = "UL1", 2094 .id = MT8188_AFE_MEMIF_UL1, 2095 .reg_ofs_base = AFE_UL1_BASE, 2096 .reg_ofs_cur = AFE_UL1_CUR, 2097 .reg_ofs_end = AFE_UL1_END, 2098 .fs_reg = -1, 2099 .fs_shift = 0, 2100 .fs_maskbit = 0, 2101 .mono_reg = AFE_UL1_CON0, 2102 .mono_shift = 1, 2103 .int_odd_flag_reg = AFE_UL1_CON0, 2104 .int_odd_flag_shift = 0, 2105 .enable_reg = AFE_DAC_CON0, 2106 .enable_shift = 1, 2107 .hd_reg = AFE_UL1_CON0, 2108 .hd_shift = 5, 2109 .agent_disable_reg = AUDIO_TOP_CON5, 2110 .agent_disable_shift = 0, 2111 .ch_num_reg = -1, 2112 .ch_num_shift = 0, 2113 .ch_num_maskbit = 0, 2114 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2115 .msb_shift = 0, 2116 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2117 .msb_end_shift = 0, 2118 }, 2119 [MT8188_AFE_MEMIF_UL2] = { 2120 .name = "UL2", 2121 .id = MT8188_AFE_MEMIF_UL2, 2122 .reg_ofs_base = AFE_UL2_BASE, 2123 .reg_ofs_cur = AFE_UL2_CUR, 2124 .reg_ofs_end = AFE_UL2_END, 2125 .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 2126 .fs_shift = 5, 2127 .fs_maskbit = 0x1f, 2128 .mono_reg = AFE_UL2_CON0, 2129 .mono_shift = 1, 2130 .int_odd_flag_reg = AFE_UL2_CON0, 2131 .int_odd_flag_shift = 0, 2132 .enable_reg = AFE_DAC_CON0, 2133 .enable_shift = 2, 2134 .hd_reg = AFE_UL2_CON0, 2135 .hd_shift = 5, 2136 .agent_disable_reg = AUDIO_TOP_CON5, 2137 .agent_disable_shift = 1, 2138 .ch_num_reg = -1, 2139 .ch_num_shift = 0, 2140 .ch_num_maskbit = 0, 2141 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2142 .msb_shift = 1, 2143 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2144 .msb_end_shift = 1, 2145 }, 2146 [MT8188_AFE_MEMIF_UL3] = { 2147 .name = "UL3", 2148 .id = MT8188_AFE_MEMIF_UL3, 2149 .reg_ofs_base = AFE_UL3_BASE, 2150 .reg_ofs_cur = AFE_UL3_CUR, 2151 .reg_ofs_end = AFE_UL3_END, 2152 .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 2153 .fs_shift = 10, 2154 .fs_maskbit = 0x1f, 2155 .mono_reg = AFE_UL3_CON0, 2156 .mono_shift = 1, 2157 .int_odd_flag_reg = AFE_UL3_CON0, 2158 .int_odd_flag_shift = 0, 2159 .enable_reg = AFE_DAC_CON0, 2160 .enable_shift = 3, 2161 .hd_reg = AFE_UL3_CON0, 2162 .hd_shift = 5, 2163 .agent_disable_reg = AUDIO_TOP_CON5, 2164 .agent_disable_shift = 2, 2165 .ch_num_reg = -1, 2166 .ch_num_shift = 0, 2167 .ch_num_maskbit = 0, 2168 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2169 .msb_shift = 2, 2170 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2171 .msb_end_shift = 2, 2172 }, 2173 [MT8188_AFE_MEMIF_UL4] = { 2174 .name = "UL4", 2175 .id = MT8188_AFE_MEMIF_UL4, 2176 .reg_ofs_base = AFE_UL4_BASE, 2177 .reg_ofs_cur = AFE_UL4_CUR, 2178 .reg_ofs_end = AFE_UL4_END, 2179 .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 2180 .fs_shift = 15, 2181 .fs_maskbit = 0x1f, 2182 .mono_reg = AFE_UL4_CON0, 2183 .mono_shift = 1, 2184 .int_odd_flag_reg = AFE_UL4_CON0, 2185 .int_odd_flag_shift = 0, 2186 .enable_reg = AFE_DAC_CON0, 2187 .enable_shift = 4, 2188 .hd_reg = AFE_UL4_CON0, 2189 .hd_shift = 5, 2190 .agent_disable_reg = AUDIO_TOP_CON5, 2191 .agent_disable_shift = 3, 2192 .ch_num_reg = -1, 2193 .ch_num_shift = 0, 2194 .ch_num_maskbit = 0, 2195 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2196 .msb_shift = 3, 2197 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2198 .msb_end_shift = 3, 2199 }, 2200 [MT8188_AFE_MEMIF_UL5] = { 2201 .name = "UL5", 2202 .id = MT8188_AFE_MEMIF_UL5, 2203 .reg_ofs_base = AFE_UL5_BASE, 2204 .reg_ofs_cur = AFE_UL5_CUR, 2205 .reg_ofs_end = AFE_UL5_END, 2206 .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 2207 .fs_shift = 20, 2208 .fs_maskbit = 0x1f, 2209 .mono_reg = AFE_UL5_CON0, 2210 .mono_shift = 1, 2211 .int_odd_flag_reg = AFE_UL5_CON0, 2212 .int_odd_flag_shift = 0, 2213 .enable_reg = AFE_DAC_CON0, 2214 .enable_shift = 5, 2215 .hd_reg = AFE_UL5_CON0, 2216 .hd_shift = 5, 2217 .agent_disable_reg = AUDIO_TOP_CON5, 2218 .agent_disable_shift = 4, 2219 .ch_num_reg = -1, 2220 .ch_num_shift = 0, 2221 .ch_num_maskbit = 0, 2222 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2223 .msb_shift = 4, 2224 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2225 .msb_end_shift = 4, 2226 }, 2227 [MT8188_AFE_MEMIF_UL6] = { 2228 .name = "UL6", 2229 .id = MT8188_AFE_MEMIF_UL6, 2230 .reg_ofs_base = AFE_UL6_BASE, 2231 .reg_ofs_cur = AFE_UL6_CUR, 2232 .reg_ofs_end = AFE_UL6_END, 2233 .fs_reg = -1, 2234 .fs_shift = 0, 2235 .fs_maskbit = 0, 2236 .mono_reg = AFE_UL6_CON0, 2237 .mono_shift = 1, 2238 .int_odd_flag_reg = AFE_UL6_CON0, 2239 .int_odd_flag_shift = 0, 2240 .enable_reg = AFE_DAC_CON0, 2241 .enable_shift = 6, 2242 .hd_reg = AFE_UL6_CON0, 2243 .hd_shift = 5, 2244 .agent_disable_reg = AUDIO_TOP_CON5, 2245 .agent_disable_shift = 5, 2246 .ch_num_reg = -1, 2247 .ch_num_shift = 0, 2248 .ch_num_maskbit = 0, 2249 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2250 .msb_shift = 5, 2251 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2252 .msb_end_shift = 5, 2253 }, 2254 [MT8188_AFE_MEMIF_UL8] = { 2255 .name = "UL8", 2256 .id = MT8188_AFE_MEMIF_UL8, 2257 .reg_ofs_base = AFE_UL8_BASE, 2258 .reg_ofs_cur = AFE_UL8_CUR, 2259 .reg_ofs_end = AFE_UL8_END, 2260 .fs_reg = AFE_MEMIF_AGENT_FS_CON3, 2261 .fs_shift = 5, 2262 .fs_maskbit = 0x1f, 2263 .mono_reg = AFE_UL8_CON0, 2264 .mono_shift = 1, 2265 .int_odd_flag_reg = AFE_UL8_CON0, 2266 .int_odd_flag_shift = 0, 2267 .enable_reg = AFE_DAC_CON0, 2268 .enable_shift = 8, 2269 .hd_reg = AFE_UL8_CON0, 2270 .hd_shift = 5, 2271 .agent_disable_reg = AUDIO_TOP_CON5, 2272 .agent_disable_shift = 7, 2273 .ch_num_reg = -1, 2274 .ch_num_shift = 0, 2275 .ch_num_maskbit = 0, 2276 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2277 .msb_shift = 7, 2278 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2279 .msb_end_shift = 7, 2280 }, 2281 [MT8188_AFE_MEMIF_UL9] = { 2282 .name = "UL9", 2283 .id = MT8188_AFE_MEMIF_UL9, 2284 .reg_ofs_base = AFE_UL9_BASE, 2285 .reg_ofs_cur = AFE_UL9_CUR, 2286 .reg_ofs_end = AFE_UL9_END, 2287 .fs_reg = AFE_MEMIF_AGENT_FS_CON3, 2288 .fs_shift = 10, 2289 .fs_maskbit = 0x1f, 2290 .mono_reg = AFE_UL9_CON0, 2291 .mono_shift = 1, 2292 .int_odd_flag_reg = AFE_UL9_CON0, 2293 .int_odd_flag_shift = 0, 2294 .enable_reg = AFE_DAC_CON0, 2295 .enable_shift = 9, 2296 .hd_reg = AFE_UL9_CON0, 2297 .hd_shift = 5, 2298 .agent_disable_reg = AUDIO_TOP_CON5, 2299 .agent_disable_shift = 8, 2300 .ch_num_reg = -1, 2301 .ch_num_shift = 0, 2302 .ch_num_maskbit = 0, 2303 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2304 .msb_shift = 8, 2305 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2306 .msb_end_shift = 8, 2307 }, 2308 [MT8188_AFE_MEMIF_UL10] = { 2309 .name = "UL10", 2310 .id = MT8188_AFE_MEMIF_UL10, 2311 .reg_ofs_base = AFE_UL10_BASE, 2312 .reg_ofs_cur = AFE_UL10_CUR, 2313 .reg_ofs_end = AFE_UL10_END, 2314 .fs_reg = AFE_MEMIF_AGENT_FS_CON3, 2315 .fs_shift = 15, 2316 .fs_maskbit = 0x1f, 2317 .mono_reg = AFE_UL10_CON0, 2318 .mono_shift = 1, 2319 .int_odd_flag_reg = AFE_UL10_CON0, 2320 .int_odd_flag_shift = 0, 2321 .enable_reg = AFE_DAC_CON0, 2322 .enable_shift = 10, 2323 .hd_reg = AFE_UL10_CON0, 2324 .hd_shift = 5, 2325 .agent_disable_reg = AUDIO_TOP_CON5, 2326 .agent_disable_shift = 9, 2327 .ch_num_reg = -1, 2328 .ch_num_shift = 0, 2329 .ch_num_maskbit = 0, 2330 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2331 .msb_shift = 9, 2332 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2333 .msb_end_shift = 9, 2334 }, 2335 }; 2336 2337 static const struct mtk_base_irq_data irq_data[MT8188_AFE_IRQ_NUM] = { 2338 [MT8188_AFE_IRQ_1] = { 2339 .id = MT8188_AFE_IRQ_1, 2340 .irq_cnt_reg = -1, 2341 .irq_cnt_shift = 0, 2342 .irq_cnt_maskbit = 0, 2343 .irq_fs_reg = -1, 2344 .irq_fs_shift = 0, 2345 .irq_fs_maskbit = 0, 2346 .irq_en_reg = AFE_IRQ1_CON, 2347 .irq_en_shift = 31, 2348 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2349 .irq_clr_shift = 0, 2350 .irq_status_shift = 16, 2351 }, 2352 [MT8188_AFE_IRQ_2] = { 2353 .id = MT8188_AFE_IRQ_2, 2354 .irq_cnt_reg = -1, 2355 .irq_cnt_shift = 0, 2356 .irq_cnt_maskbit = 0, 2357 .irq_fs_reg = -1, 2358 .irq_fs_shift = 0, 2359 .irq_fs_maskbit = 0, 2360 .irq_en_reg = AFE_IRQ2_CON, 2361 .irq_en_shift = 31, 2362 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2363 .irq_clr_shift = 1, 2364 .irq_status_shift = 17, 2365 }, 2366 [MT8188_AFE_IRQ_3] = { 2367 .id = MT8188_AFE_IRQ_3, 2368 .irq_cnt_reg = AFE_IRQ3_CON, 2369 .irq_cnt_shift = 0, 2370 .irq_cnt_maskbit = 0xffffff, 2371 .irq_fs_reg = -1, 2372 .irq_fs_shift = 0, 2373 .irq_fs_maskbit = 0, 2374 .irq_en_reg = AFE_IRQ3_CON, 2375 .irq_en_shift = 31, 2376 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2377 .irq_clr_shift = 2, 2378 .irq_status_shift = 18, 2379 }, 2380 [MT8188_AFE_IRQ_8] = { 2381 .id = MT8188_AFE_IRQ_8, 2382 .irq_cnt_reg = -1, 2383 .irq_cnt_shift = 0, 2384 .irq_cnt_maskbit = 0, 2385 .irq_fs_reg = -1, 2386 .irq_fs_shift = 0, 2387 .irq_fs_maskbit = 0, 2388 .irq_en_reg = AFE_IRQ8_CON, 2389 .irq_en_shift = 31, 2390 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2391 .irq_clr_shift = 7, 2392 .irq_status_shift = 23, 2393 }, 2394 [MT8188_AFE_IRQ_9] = { 2395 .id = MT8188_AFE_IRQ_9, 2396 .irq_cnt_reg = AFE_IRQ9_CON, 2397 .irq_cnt_shift = 0, 2398 .irq_cnt_maskbit = 0xffffff, 2399 .irq_fs_reg = -1, 2400 .irq_fs_shift = 0, 2401 .irq_fs_maskbit = 0, 2402 .irq_en_reg = AFE_IRQ9_CON, 2403 .irq_en_shift = 31, 2404 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2405 .irq_clr_shift = 8, 2406 .irq_status_shift = 24, 2407 }, 2408 [MT8188_AFE_IRQ_10] = { 2409 .id = MT8188_AFE_IRQ_10, 2410 .irq_cnt_reg = -1, 2411 .irq_cnt_shift = 0, 2412 .irq_cnt_maskbit = 0, 2413 .irq_fs_reg = -1, 2414 .irq_fs_shift = 0, 2415 .irq_fs_maskbit = 0, 2416 .irq_en_reg = AFE_IRQ10_CON, 2417 .irq_en_shift = 31, 2418 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2419 .irq_clr_shift = 9, 2420 .irq_status_shift = 25, 2421 }, 2422 [MT8188_AFE_IRQ_13] = { 2423 .id = MT8188_AFE_IRQ_13, 2424 .irq_cnt_reg = ASYS_IRQ1_CON, 2425 .irq_cnt_shift = 0, 2426 .irq_cnt_maskbit = 0xffffff, 2427 .irq_fs_reg = ASYS_IRQ1_CON, 2428 .irq_fs_shift = 24, 2429 .irq_fs_maskbit = 0x1ffff, 2430 .irq_en_reg = ASYS_IRQ1_CON, 2431 .irq_en_shift = 31, 2432 .irq_clr_reg = ASYS_IRQ_CLR, 2433 .irq_clr_shift = 0, 2434 .irq_status_shift = 0, 2435 }, 2436 [MT8188_AFE_IRQ_14] = { 2437 .id = MT8188_AFE_IRQ_14, 2438 .irq_cnt_reg = ASYS_IRQ2_CON, 2439 .irq_cnt_shift = 0, 2440 .irq_cnt_maskbit = 0xffffff, 2441 .irq_fs_reg = ASYS_IRQ2_CON, 2442 .irq_fs_shift = 24, 2443 .irq_fs_maskbit = 0x1ffff, 2444 .irq_en_reg = ASYS_IRQ2_CON, 2445 .irq_en_shift = 31, 2446 .irq_clr_reg = ASYS_IRQ_CLR, 2447 .irq_clr_shift = 1, 2448 .irq_status_shift = 1, 2449 }, 2450 [MT8188_AFE_IRQ_15] = { 2451 .id = MT8188_AFE_IRQ_15, 2452 .irq_cnt_reg = ASYS_IRQ3_CON, 2453 .irq_cnt_shift = 0, 2454 .irq_cnt_maskbit = 0xffffff, 2455 .irq_fs_reg = ASYS_IRQ3_CON, 2456 .irq_fs_shift = 24, 2457 .irq_fs_maskbit = 0x1ffff, 2458 .irq_en_reg = ASYS_IRQ3_CON, 2459 .irq_en_shift = 31, 2460 .irq_clr_reg = ASYS_IRQ_CLR, 2461 .irq_clr_shift = 2, 2462 .irq_status_shift = 2, 2463 }, 2464 [MT8188_AFE_IRQ_16] = { 2465 .id = MT8188_AFE_IRQ_16, 2466 .irq_cnt_reg = ASYS_IRQ4_CON, 2467 .irq_cnt_shift = 0, 2468 .irq_cnt_maskbit = 0xffffff, 2469 .irq_fs_reg = ASYS_IRQ4_CON, 2470 .irq_fs_shift = 24, 2471 .irq_fs_maskbit = 0x1ffff, 2472 .irq_en_reg = ASYS_IRQ4_CON, 2473 .irq_en_shift = 31, 2474 .irq_clr_reg = ASYS_IRQ_CLR, 2475 .irq_clr_shift = 3, 2476 .irq_status_shift = 3, 2477 }, 2478 [MT8188_AFE_IRQ_17] = { 2479 .id = MT8188_AFE_IRQ_17, 2480 .irq_cnt_reg = ASYS_IRQ5_CON, 2481 .irq_cnt_shift = 0, 2482 .irq_cnt_maskbit = 0xffffff, 2483 .irq_fs_reg = ASYS_IRQ5_CON, 2484 .irq_fs_shift = 24, 2485 .irq_fs_maskbit = 0x1ffff, 2486 .irq_en_reg = ASYS_IRQ5_CON, 2487 .irq_en_shift = 31, 2488 .irq_clr_reg = ASYS_IRQ_CLR, 2489 .irq_clr_shift = 4, 2490 .irq_status_shift = 4, 2491 }, 2492 [MT8188_AFE_IRQ_18] = { 2493 .id = MT8188_AFE_IRQ_18, 2494 .irq_cnt_reg = ASYS_IRQ6_CON, 2495 .irq_cnt_shift = 0, 2496 .irq_cnt_maskbit = 0xffffff, 2497 .irq_fs_reg = ASYS_IRQ6_CON, 2498 .irq_fs_shift = 24, 2499 .irq_fs_maskbit = 0x1ffff, 2500 .irq_en_reg = ASYS_IRQ6_CON, 2501 .irq_en_shift = 31, 2502 .irq_clr_reg = ASYS_IRQ_CLR, 2503 .irq_clr_shift = 5, 2504 .irq_status_shift = 5, 2505 }, 2506 [MT8188_AFE_IRQ_19] = { 2507 .id = MT8188_AFE_IRQ_19, 2508 .irq_cnt_reg = ASYS_IRQ7_CON, 2509 .irq_cnt_shift = 0, 2510 .irq_cnt_maskbit = 0xffffff, 2511 .irq_fs_reg = ASYS_IRQ7_CON, 2512 .irq_fs_shift = 24, 2513 .irq_fs_maskbit = 0x1ffff, 2514 .irq_en_reg = ASYS_IRQ7_CON, 2515 .irq_en_shift = 31, 2516 .irq_clr_reg = ASYS_IRQ_CLR, 2517 .irq_clr_shift = 6, 2518 .irq_status_shift = 6, 2519 }, 2520 [MT8188_AFE_IRQ_20] = { 2521 .id = MT8188_AFE_IRQ_20, 2522 .irq_cnt_reg = ASYS_IRQ8_CON, 2523 .irq_cnt_shift = 0, 2524 .irq_cnt_maskbit = 0xffffff, 2525 .irq_fs_reg = ASYS_IRQ8_CON, 2526 .irq_fs_shift = 24, 2527 .irq_fs_maskbit = 0x1ffff, 2528 .irq_en_reg = ASYS_IRQ8_CON, 2529 .irq_en_shift = 31, 2530 .irq_clr_reg = ASYS_IRQ_CLR, 2531 .irq_clr_shift = 7, 2532 .irq_status_shift = 7, 2533 }, 2534 [MT8188_AFE_IRQ_21] = { 2535 .id = MT8188_AFE_IRQ_21, 2536 .irq_cnt_reg = ASYS_IRQ9_CON, 2537 .irq_cnt_shift = 0, 2538 .irq_cnt_maskbit = 0xffffff, 2539 .irq_fs_reg = ASYS_IRQ9_CON, 2540 .irq_fs_shift = 24, 2541 .irq_fs_maskbit = 0x1ffff, 2542 .irq_en_reg = ASYS_IRQ9_CON, 2543 .irq_en_shift = 31, 2544 .irq_clr_reg = ASYS_IRQ_CLR, 2545 .irq_clr_shift = 8, 2546 .irq_status_shift = 8, 2547 }, 2548 [MT8188_AFE_IRQ_22] = { 2549 .id = MT8188_AFE_IRQ_22, 2550 .irq_cnt_reg = ASYS_IRQ10_CON, 2551 .irq_cnt_shift = 0, 2552 .irq_cnt_maskbit = 0xffffff, 2553 .irq_fs_reg = ASYS_IRQ10_CON, 2554 .irq_fs_shift = 24, 2555 .irq_fs_maskbit = 0x1ffff, 2556 .irq_en_reg = ASYS_IRQ10_CON, 2557 .irq_en_shift = 31, 2558 .irq_clr_reg = ASYS_IRQ_CLR, 2559 .irq_clr_shift = 9, 2560 .irq_status_shift = 9, 2561 }, 2562 [MT8188_AFE_IRQ_23] = { 2563 .id = MT8188_AFE_IRQ_23, 2564 .irq_cnt_reg = ASYS_IRQ11_CON, 2565 .irq_cnt_shift = 0, 2566 .irq_cnt_maskbit = 0xffffff, 2567 .irq_fs_reg = ASYS_IRQ11_CON, 2568 .irq_fs_shift = 24, 2569 .irq_fs_maskbit = 0x1ffff, 2570 .irq_en_reg = ASYS_IRQ11_CON, 2571 .irq_en_shift = 31, 2572 .irq_clr_reg = ASYS_IRQ_CLR, 2573 .irq_clr_shift = 10, 2574 .irq_status_shift = 10, 2575 }, 2576 [MT8188_AFE_IRQ_24] = { 2577 .id = MT8188_AFE_IRQ_24, 2578 .irq_cnt_reg = ASYS_IRQ12_CON, 2579 .irq_cnt_shift = 0, 2580 .irq_cnt_maskbit = 0xffffff, 2581 .irq_fs_reg = ASYS_IRQ12_CON, 2582 .irq_fs_shift = 24, 2583 .irq_fs_maskbit = 0x1ffff, 2584 .irq_en_reg = ASYS_IRQ12_CON, 2585 .irq_en_shift = 31, 2586 .irq_clr_reg = ASYS_IRQ_CLR, 2587 .irq_clr_shift = 11, 2588 .irq_status_shift = 11, 2589 }, 2590 [MT8188_AFE_IRQ_25] = { 2591 .id = MT8188_AFE_IRQ_25, 2592 .irq_cnt_reg = ASYS_IRQ13_CON, 2593 .irq_cnt_shift = 0, 2594 .irq_cnt_maskbit = 0xffffff, 2595 .irq_fs_reg = ASYS_IRQ13_CON, 2596 .irq_fs_shift = 24, 2597 .irq_fs_maskbit = 0x1ffff, 2598 .irq_en_reg = ASYS_IRQ13_CON, 2599 .irq_en_shift = 31, 2600 .irq_clr_reg = ASYS_IRQ_CLR, 2601 .irq_clr_shift = 12, 2602 .irq_status_shift = 12, 2603 }, 2604 [MT8188_AFE_IRQ_26] = { 2605 .id = MT8188_AFE_IRQ_26, 2606 .irq_cnt_reg = ASYS_IRQ14_CON, 2607 .irq_cnt_shift = 0, 2608 .irq_cnt_maskbit = 0xffffff, 2609 .irq_fs_reg = ASYS_IRQ14_CON, 2610 .irq_fs_shift = 24, 2611 .irq_fs_maskbit = 0x1ffff, 2612 .irq_en_reg = ASYS_IRQ14_CON, 2613 .irq_en_shift = 31, 2614 .irq_clr_reg = ASYS_IRQ_CLR, 2615 .irq_clr_shift = 13, 2616 .irq_status_shift = 13, 2617 }, 2618 [MT8188_AFE_IRQ_27] = { 2619 .id = MT8188_AFE_IRQ_27, 2620 .irq_cnt_reg = ASYS_IRQ15_CON, 2621 .irq_cnt_shift = 0, 2622 .irq_cnt_maskbit = 0xffffff, 2623 .irq_fs_reg = ASYS_IRQ15_CON, 2624 .irq_fs_shift = 24, 2625 .irq_fs_maskbit = 0x1ffff, 2626 .irq_en_reg = ASYS_IRQ15_CON, 2627 .irq_en_shift = 31, 2628 .irq_clr_reg = ASYS_IRQ_CLR, 2629 .irq_clr_shift = 14, 2630 .irq_status_shift = 14, 2631 }, 2632 [MT8188_AFE_IRQ_28] = { 2633 .id = MT8188_AFE_IRQ_28, 2634 .irq_cnt_reg = ASYS_IRQ16_CON, 2635 .irq_cnt_shift = 0, 2636 .irq_cnt_maskbit = 0xffffff, 2637 .irq_fs_reg = ASYS_IRQ16_CON, 2638 .irq_fs_shift = 24, 2639 .irq_fs_maskbit = 0x1ffff, 2640 .irq_en_reg = ASYS_IRQ16_CON, 2641 .irq_en_shift = 31, 2642 .irq_clr_reg = ASYS_IRQ_CLR, 2643 .irq_clr_shift = 15, 2644 .irq_status_shift = 15, 2645 }, 2646 }; 2647 2648 static const int mt8188_afe_memif_const_irqs[MT8188_AFE_MEMIF_NUM] = { 2649 [MT8188_AFE_MEMIF_DL2] = MT8188_AFE_IRQ_13, 2650 [MT8188_AFE_MEMIF_DL3] = MT8188_AFE_IRQ_14, 2651 [MT8188_AFE_MEMIF_DL6] = MT8188_AFE_IRQ_15, 2652 [MT8188_AFE_MEMIF_DL7] = MT8188_AFE_IRQ_1, 2653 [MT8188_AFE_MEMIF_DL8] = MT8188_AFE_IRQ_16, 2654 [MT8188_AFE_MEMIF_DL10] = MT8188_AFE_IRQ_17, 2655 [MT8188_AFE_MEMIF_DL11] = MT8188_AFE_IRQ_18, 2656 [MT8188_AFE_MEMIF_UL1] = MT8188_AFE_IRQ_3, 2657 [MT8188_AFE_MEMIF_UL2] = MT8188_AFE_IRQ_19, 2658 [MT8188_AFE_MEMIF_UL3] = MT8188_AFE_IRQ_20, 2659 [MT8188_AFE_MEMIF_UL4] = MT8188_AFE_IRQ_21, 2660 [MT8188_AFE_MEMIF_UL5] = MT8188_AFE_IRQ_22, 2661 [MT8188_AFE_MEMIF_UL6] = MT8188_AFE_IRQ_9, 2662 [MT8188_AFE_MEMIF_UL8] = MT8188_AFE_IRQ_23, 2663 [MT8188_AFE_MEMIF_UL9] = MT8188_AFE_IRQ_24, 2664 [MT8188_AFE_MEMIF_UL10] = MT8188_AFE_IRQ_25, 2665 }; 2666 2667 static bool mt8188_is_volatile_reg(struct device *dev, unsigned int reg) 2668 { 2669 /* these auto-gen reg has read-only bit, so put it as volatile */ 2670 /* volatile reg cannot be cached, so cannot be set when power off */ 2671 switch (reg) { 2672 case AUDIO_TOP_CON0: 2673 case AUDIO_TOP_CON1: 2674 case AUDIO_TOP_CON3: 2675 case AUDIO_TOP_CON4: 2676 case AUDIO_TOP_CON5: 2677 case AUDIO_TOP_CON6: 2678 case ASYS_IRQ_CLR: 2679 case ASYS_IRQ_STATUS: 2680 case ASYS_IRQ_MON1: 2681 case ASYS_IRQ_MON2: 2682 case AFE_IRQ_MCU_CLR: 2683 case AFE_IRQ_STATUS: 2684 case AFE_IRQ3_CON_MON: 2685 case AFE_IRQ_MCU_MON2: 2686 case ADSP_IRQ_STATUS: 2687 case AUDIO_TOP_STA0: 2688 case AUDIO_TOP_STA1: 2689 case AFE_GAIN1_CUR: 2690 case AFE_GAIN2_CUR: 2691 case AFE_IEC_BURST_INFO: 2692 case AFE_IEC_CHL_STAT0: 2693 case AFE_IEC_CHL_STAT1: 2694 case AFE_IEC_CHR_STAT0: 2695 case AFE_IEC_CHR_STAT1: 2696 case AFE_SPDIFIN_CHSTS1: 2697 case AFE_SPDIFIN_CHSTS2: 2698 case AFE_SPDIFIN_CHSTS3: 2699 case AFE_SPDIFIN_CHSTS4: 2700 case AFE_SPDIFIN_CHSTS5: 2701 case AFE_SPDIFIN_CHSTS6: 2702 case AFE_SPDIFIN_DEBUG1: 2703 case AFE_SPDIFIN_DEBUG2: 2704 case AFE_SPDIFIN_DEBUG3: 2705 case AFE_SPDIFIN_DEBUG4: 2706 case AFE_SPDIFIN_EC: 2707 case AFE_SPDIFIN_CKLOCK_CFG: 2708 case AFE_SPDIFIN_BR_DBG1: 2709 case AFE_SPDIFIN_CKFBDIV: 2710 case AFE_SPDIFIN_INT_EXT: 2711 case AFE_SPDIFIN_INT_EXT2: 2712 case SPDIFIN_FREQ_STATUS: 2713 case SPDIFIN_USERCODE1: 2714 case SPDIFIN_USERCODE2: 2715 case SPDIFIN_USERCODE3: 2716 case SPDIFIN_USERCODE4: 2717 case SPDIFIN_USERCODE5: 2718 case SPDIFIN_USERCODE6: 2719 case SPDIFIN_USERCODE7: 2720 case SPDIFIN_USERCODE8: 2721 case SPDIFIN_USERCODE9: 2722 case SPDIFIN_USERCODE10: 2723 case SPDIFIN_USERCODE11: 2724 case SPDIFIN_USERCODE12: 2725 case AFE_LINEIN_APLL_TUNER_MON: 2726 case AFE_EARC_APLL_TUNER_MON: 2727 case AFE_CM0_MON: 2728 case AFE_CM1_MON: 2729 case AFE_CM2_MON: 2730 case AFE_MPHONE_MULTI_DET_MON0: 2731 case AFE_MPHONE_MULTI_DET_MON1: 2732 case AFE_MPHONE_MULTI_DET_MON2: 2733 case AFE_MPHONE_MULTI2_DET_MON0: 2734 case AFE_MPHONE_MULTI2_DET_MON1: 2735 case AFE_MPHONE_MULTI2_DET_MON2: 2736 case AFE_ADDA_MTKAIF_MON0: 2737 case AFE_ADDA_MTKAIF_MON1: 2738 case AFE_AUD_PAD_TOP: 2739 case AFE_ADDA6_MTKAIF_MON0: 2740 case AFE_ADDA6_MTKAIF_MON1: 2741 case AFE_ADDA6_SRC_DEBUG_MON0: 2742 case AFE_ADDA6_UL_SRC_MON0: 2743 case AFE_ADDA6_UL_SRC_MON1: 2744 case AFE_ASRC11_NEW_CON8: 2745 case AFE_ASRC11_NEW_CON9: 2746 case AFE_ASRC12_NEW_CON8: 2747 case AFE_ASRC12_NEW_CON9: 2748 case AFE_LRCK_CNT: 2749 case AFE_DAC_MON0: 2750 case AFE_DL2_CUR: 2751 case AFE_DL3_CUR: 2752 case AFE_DL6_CUR: 2753 case AFE_DL7_CUR: 2754 case AFE_DL8_CUR: 2755 case AFE_DL10_CUR: 2756 case AFE_DL11_CUR: 2757 case AFE_UL1_CUR: 2758 case AFE_UL2_CUR: 2759 case AFE_UL3_CUR: 2760 case AFE_UL4_CUR: 2761 case AFE_UL5_CUR: 2762 case AFE_UL6_CUR: 2763 case AFE_UL8_CUR: 2764 case AFE_UL9_CUR: 2765 case AFE_UL10_CUR: 2766 case AFE_DL8_CHK_SUM1: 2767 case AFE_DL8_CHK_SUM2: 2768 case AFE_DL8_CHK_SUM3: 2769 case AFE_DL8_CHK_SUM4: 2770 case AFE_DL8_CHK_SUM5: 2771 case AFE_DL8_CHK_SUM6: 2772 case AFE_DL10_CHK_SUM1: 2773 case AFE_DL10_CHK_SUM2: 2774 case AFE_DL10_CHK_SUM3: 2775 case AFE_DL10_CHK_SUM4: 2776 case AFE_DL10_CHK_SUM5: 2777 case AFE_DL10_CHK_SUM6: 2778 case AFE_DL11_CHK_SUM1: 2779 case AFE_DL11_CHK_SUM2: 2780 case AFE_DL11_CHK_SUM3: 2781 case AFE_DL11_CHK_SUM4: 2782 case AFE_DL11_CHK_SUM5: 2783 case AFE_DL11_CHK_SUM6: 2784 case AFE_UL1_CHK_SUM1: 2785 case AFE_UL1_CHK_SUM2: 2786 case AFE_UL2_CHK_SUM1: 2787 case AFE_UL2_CHK_SUM2: 2788 case AFE_UL3_CHK_SUM1: 2789 case AFE_UL3_CHK_SUM2: 2790 case AFE_UL4_CHK_SUM1: 2791 case AFE_UL4_CHK_SUM2: 2792 case AFE_UL5_CHK_SUM1: 2793 case AFE_UL5_CHK_SUM2: 2794 case AFE_UL6_CHK_SUM1: 2795 case AFE_UL6_CHK_SUM2: 2796 case AFE_UL8_CHK_SUM1: 2797 case AFE_UL8_CHK_SUM2: 2798 case AFE_DL2_CHK_SUM1: 2799 case AFE_DL2_CHK_SUM2: 2800 case AFE_DL3_CHK_SUM1: 2801 case AFE_DL3_CHK_SUM2: 2802 case AFE_DL6_CHK_SUM1: 2803 case AFE_DL6_CHK_SUM2: 2804 case AFE_DL7_CHK_SUM1: 2805 case AFE_DL7_CHK_SUM2: 2806 case AFE_UL9_CHK_SUM1: 2807 case AFE_UL9_CHK_SUM2: 2808 case AFE_BUS_MON1: 2809 case UL1_MOD2AGT_CNT_LAT: 2810 case UL2_MOD2AGT_CNT_LAT: 2811 case UL3_MOD2AGT_CNT_LAT: 2812 case UL4_MOD2AGT_CNT_LAT: 2813 case UL5_MOD2AGT_CNT_LAT: 2814 case UL6_MOD2AGT_CNT_LAT: 2815 case UL8_MOD2AGT_CNT_LAT: 2816 case UL9_MOD2AGT_CNT_LAT: 2817 case UL10_MOD2AGT_CNT_LAT: 2818 case AFE_MEMIF_BUF_FULL_MON: 2819 case AFE_MEMIF_BUF_MON1: 2820 case AFE_MEMIF_BUF_MON3: 2821 case AFE_MEMIF_BUF_MON4: 2822 case AFE_MEMIF_BUF_MON5: 2823 case AFE_MEMIF_BUF_MON6: 2824 case AFE_MEMIF_BUF_MON7: 2825 case AFE_MEMIF_BUF_MON8: 2826 case AFE_MEMIF_BUF_MON9: 2827 case AFE_MEMIF_BUF_MON10: 2828 case DL2_AGENT2MODULE_CNT: 2829 case DL3_AGENT2MODULE_CNT: 2830 case DL6_AGENT2MODULE_CNT: 2831 case DL7_AGENT2MODULE_CNT: 2832 case DL8_AGENT2MODULE_CNT: 2833 case DL10_AGENT2MODULE_CNT: 2834 case DL11_AGENT2MODULE_CNT: 2835 case UL1_MODULE2AGENT_CNT: 2836 case UL2_MODULE2AGENT_CNT: 2837 case UL3_MODULE2AGENT_CNT: 2838 case UL4_MODULE2AGENT_CNT: 2839 case UL5_MODULE2AGENT_CNT: 2840 case UL6_MODULE2AGENT_CNT: 2841 case UL8_MODULE2AGENT_CNT: 2842 case UL9_MODULE2AGENT_CNT: 2843 case UL10_MODULE2AGENT_CNT: 2844 case AFE_DMIC0_SRC_DEBUG_MON0: 2845 case AFE_DMIC0_UL_SRC_MON0: 2846 case AFE_DMIC0_UL_SRC_MON1: 2847 case AFE_DMIC1_SRC_DEBUG_MON0: 2848 case AFE_DMIC1_UL_SRC_MON0: 2849 case AFE_DMIC1_UL_SRC_MON1: 2850 case AFE_DMIC2_SRC_DEBUG_MON0: 2851 case AFE_DMIC2_UL_SRC_MON0: 2852 case AFE_DMIC2_UL_SRC_MON1: 2853 case AFE_DMIC3_SRC_DEBUG_MON0: 2854 case AFE_DMIC3_UL_SRC_MON0: 2855 case AFE_DMIC3_UL_SRC_MON1: 2856 case DMIC_GAIN1_CUR: 2857 case DMIC_GAIN2_CUR: 2858 case DMIC_GAIN3_CUR: 2859 case DMIC_GAIN4_CUR: 2860 case ETDM_IN1_MONITOR: 2861 case ETDM_IN2_MONITOR: 2862 case ETDM_OUT1_MONITOR: 2863 case ETDM_OUT2_MONITOR: 2864 case ETDM_OUT3_MONITOR: 2865 case AFE_ADDA_SRC_DEBUG_MON0: 2866 case AFE_ADDA_SRC_DEBUG_MON1: 2867 case AFE_ADDA_DL_SDM_FIFO_MON: 2868 case AFE_ADDA_DL_SRC_LCH_MON: 2869 case AFE_ADDA_DL_SRC_RCH_MON: 2870 case AFE_ADDA_DL_SDM_OUT_MON: 2871 case AFE_GASRC0_NEW_CON8: 2872 case AFE_GASRC0_NEW_CON9: 2873 case AFE_GASRC0_NEW_CON12: 2874 case AFE_GASRC1_NEW_CON8: 2875 case AFE_GASRC1_NEW_CON9: 2876 case AFE_GASRC1_NEW_CON12: 2877 case AFE_GASRC2_NEW_CON8: 2878 case AFE_GASRC2_NEW_CON9: 2879 case AFE_GASRC2_NEW_CON12: 2880 case AFE_GASRC3_NEW_CON8: 2881 case AFE_GASRC3_NEW_CON9: 2882 case AFE_GASRC3_NEW_CON12: 2883 case AFE_GASRC4_NEW_CON8: 2884 case AFE_GASRC4_NEW_CON9: 2885 case AFE_GASRC4_NEW_CON12: 2886 case AFE_GASRC5_NEW_CON8: 2887 case AFE_GASRC5_NEW_CON9: 2888 case AFE_GASRC5_NEW_CON12: 2889 case AFE_GASRC6_NEW_CON8: 2890 case AFE_GASRC6_NEW_CON9: 2891 case AFE_GASRC6_NEW_CON12: 2892 case AFE_GASRC7_NEW_CON8: 2893 case AFE_GASRC7_NEW_CON9: 2894 case AFE_GASRC7_NEW_CON12: 2895 case AFE_GASRC8_NEW_CON8: 2896 case AFE_GASRC8_NEW_CON9: 2897 case AFE_GASRC8_NEW_CON12: 2898 case AFE_GASRC9_NEW_CON8: 2899 case AFE_GASRC9_NEW_CON9: 2900 case AFE_GASRC9_NEW_CON12: 2901 case AFE_GASRC10_NEW_CON8: 2902 case AFE_GASRC10_NEW_CON9: 2903 case AFE_GASRC10_NEW_CON12: 2904 case AFE_GASRC11_NEW_CON8: 2905 case AFE_GASRC11_NEW_CON9: 2906 case AFE_GASRC11_NEW_CON12: 2907 return true; 2908 default: 2909 return false; 2910 }; 2911 } 2912 2913 static const struct regmap_config mt8188_afe_regmap_config = { 2914 .reg_bits = 32, 2915 .reg_stride = 4, 2916 .val_bits = 32, 2917 .volatile_reg = mt8188_is_volatile_reg, 2918 .max_register = AFE_MAX_REGISTER, 2919 .num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1), 2920 .cache_type = REGCACHE_FLAT, 2921 }; 2922 2923 #define AFE_IRQ_CLR_BITS (0x387) 2924 #define ASYS_IRQ_CLR_BITS (0xffff) 2925 2926 static irqreturn_t mt8188_afe_irq_handler(int irq_id, void *dev_id) 2927 { 2928 struct mtk_base_afe *afe = dev_id; 2929 unsigned int val = 0; 2930 unsigned int asys_irq_clr_bits = 0; 2931 unsigned int afe_irq_clr_bits = 0; 2932 unsigned int irq_status_bits = 0; 2933 unsigned int irq_clr_bits = 0; 2934 unsigned int mcu_irq_mask = 0; 2935 int i = 0; 2936 int ret = 0; 2937 2938 ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &val); 2939 if (ret) { 2940 dev_err(afe->dev, "%s irq status err\n", __func__); 2941 afe_irq_clr_bits = AFE_IRQ_CLR_BITS; 2942 asys_irq_clr_bits = ASYS_IRQ_CLR_BITS; 2943 goto err_irq; 2944 } 2945 2946 ret = regmap_read(afe->regmap, AFE_IRQ_MASK, &mcu_irq_mask); 2947 if (ret) { 2948 dev_err(afe->dev, "%s read irq mask err\n", __func__); 2949 afe_irq_clr_bits = AFE_IRQ_CLR_BITS; 2950 asys_irq_clr_bits = ASYS_IRQ_CLR_BITS; 2951 goto err_irq; 2952 } 2953 2954 /* only clr cpu irq */ 2955 val &= mcu_irq_mask; 2956 2957 for (i = 0; i < MT8188_AFE_MEMIF_NUM; i++) { 2958 struct mtk_base_afe_memif *memif = &afe->memif[i]; 2959 struct mtk_base_irq_data const *irq_data; 2960 2961 if (memif->irq_usage < 0) 2962 continue; 2963 2964 irq_data = afe->irqs[memif->irq_usage].irq_data; 2965 2966 irq_status_bits = BIT(irq_data->irq_status_shift); 2967 irq_clr_bits = BIT(irq_data->irq_clr_shift); 2968 2969 if (!(val & irq_status_bits)) 2970 continue; 2971 2972 if (irq_data->irq_clr_reg == ASYS_IRQ_CLR) 2973 asys_irq_clr_bits |= irq_clr_bits; 2974 else 2975 afe_irq_clr_bits |= irq_clr_bits; 2976 2977 snd_pcm_period_elapsed(memif->substream); 2978 } 2979 2980 err_irq: 2981 /* clear irq */ 2982 if (asys_irq_clr_bits) 2983 regmap_write(afe->regmap, ASYS_IRQ_CLR, asys_irq_clr_bits); 2984 if (afe_irq_clr_bits) 2985 regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, afe_irq_clr_bits); 2986 2987 return IRQ_HANDLED; 2988 } 2989 2990 static int mt8188_afe_runtime_suspend(struct device *dev) 2991 { 2992 struct mtk_base_afe *afe = dev_get_drvdata(dev); 2993 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2994 2995 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) 2996 goto skip_regmap; 2997 2998 mt8188_afe_disable_main_clock(afe); 2999 3000 regcache_cache_only(afe->regmap, true); 3001 regcache_mark_dirty(afe->regmap); 3002 3003 skip_regmap: 3004 mt8188_afe_disable_reg_rw_clk(afe); 3005 3006 return 0; 3007 } 3008 3009 static int mt8188_afe_runtime_resume(struct device *dev) 3010 { 3011 struct mtk_base_afe *afe = dev_get_drvdata(dev); 3012 struct mt8188_afe_private *afe_priv = afe->platform_priv; 3013 struct arm_smccc_res res; 3014 3015 arm_smccc_smc(MTK_SIP_AUDIO_CONTROL, 3016 MTK_AUDIO_SMC_OP_DOMAIN_SIDEBANDS, 3017 0, 0, 0, 0, 0, 0, &res); 3018 3019 mt8188_afe_enable_reg_rw_clk(afe); 3020 3021 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) 3022 goto skip_regmap; 3023 3024 regcache_cache_only(afe->regmap, false); 3025 regcache_sync(afe->regmap); 3026 3027 mt8188_afe_enable_main_clock(afe); 3028 skip_regmap: 3029 return 0; 3030 } 3031 3032 static int mt8188_afe_component_probe(struct snd_soc_component *component) 3033 { 3034 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 3035 int ret; 3036 3037 snd_soc_component_init_regmap(component, afe->regmap); 3038 3039 ret = mtk_afe_add_sub_dai_control(component); 3040 3041 return ret; 3042 } 3043 3044 static const struct snd_soc_component_driver mt8188_afe_component = { 3045 .name = AFE_PCM_NAME, 3046 .pointer = mtk_afe_pcm_pointer, 3047 .pcm_construct = mtk_afe_pcm_new, 3048 .probe = mt8188_afe_component_probe, 3049 }; 3050 3051 static int init_memif_priv_data(struct mtk_base_afe *afe) 3052 { 3053 struct mt8188_afe_private *afe_priv = afe->platform_priv; 3054 struct mtk_dai_memif_priv *memif_priv; 3055 int i; 3056 3057 for (i = MT8188_AFE_MEMIF_START; i < MT8188_AFE_MEMIF_END; i++) { 3058 memif_priv = devm_kzalloc(afe->dev, 3059 sizeof(struct mtk_dai_memif_priv), 3060 GFP_KERNEL); 3061 if (!memif_priv) 3062 return -ENOMEM; 3063 3064 afe_priv->dai_priv[i] = memif_priv; 3065 } 3066 3067 return 0; 3068 } 3069 3070 static int mt8188_dai_memif_register(struct mtk_base_afe *afe) 3071 { 3072 struct mtk_base_afe_dai *dai; 3073 3074 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 3075 if (!dai) 3076 return -ENOMEM; 3077 3078 list_add(&dai->list, &afe->sub_dais); 3079 3080 dai->dai_drivers = mt8188_memif_dai_driver; 3081 dai->num_dai_drivers = ARRAY_SIZE(mt8188_memif_dai_driver); 3082 3083 dai->dapm_widgets = mt8188_memif_widgets; 3084 dai->num_dapm_widgets = ARRAY_SIZE(mt8188_memif_widgets); 3085 dai->dapm_routes = mt8188_memif_routes; 3086 dai->num_dapm_routes = ARRAY_SIZE(mt8188_memif_routes); 3087 dai->controls = mt8188_memif_controls; 3088 dai->num_controls = ARRAY_SIZE(mt8188_memif_controls); 3089 3090 return init_memif_priv_data(afe); 3091 } 3092 3093 typedef int (*dai_register_cb)(struct mtk_base_afe *); 3094 static const dai_register_cb dai_register_cbs[] = { 3095 mt8188_dai_adda_register, 3096 mt8188_dai_etdm_register, 3097 mt8188_dai_pcm_register, 3098 mt8188_dai_memif_register, 3099 }; 3100 3101 static const struct reg_sequence mt8188_afe_reg_defaults[] = { 3102 { AFE_IRQ_MASK, 0x387ffff }, 3103 { AFE_IRQ3_CON, BIT(30) }, 3104 { AFE_IRQ9_CON, BIT(30) }, 3105 { ETDM_IN1_CON4, 0x12000100 }, 3106 { ETDM_IN2_CON4, 0x12000100 }, 3107 }; 3108 3109 static const struct reg_sequence mt8188_cg_patch[] = { 3110 { AUDIO_TOP_CON0, 0xfffffffb }, 3111 { AUDIO_TOP_CON1, 0xfffffff8 }, 3112 }; 3113 3114 static int mt8188_afe_init_registers(struct mtk_base_afe *afe) 3115 { 3116 return regmap_multi_reg_write(afe->regmap, 3117 mt8188_afe_reg_defaults, 3118 ARRAY_SIZE(mt8188_afe_reg_defaults)); 3119 } 3120 3121 static int mt8188_afe_parse_of(struct mtk_base_afe *afe, 3122 struct device_node *np) 3123 { 3124 #if IS_ENABLED(CONFIG_SND_SOC_MT6359) 3125 struct mt8188_afe_private *afe_priv = afe->platform_priv; 3126 3127 afe_priv->topckgen = syscon_regmap_lookup_by_phandle(afe->dev->of_node, 3128 "mediatek,topckgen"); 3129 if (IS_ERR(afe_priv->topckgen)) 3130 return dev_err_probe(afe->dev, PTR_ERR(afe_priv->topckgen), 3131 "%s() Cannot find topckgen controller\n", 3132 __func__); 3133 #endif 3134 return 0; 3135 } 3136 3137 #define MT8188_DELAY_US 10 3138 #define MT8188_TIMEOUT_US USEC_PER_SEC 3139 3140 static int bus_protect_enable(struct regmap *regmap) 3141 { 3142 int ret; 3143 u32 val; 3144 u32 mask; 3145 3146 val = 0; 3147 mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1; 3148 regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_SET, mask); 3149 3150 ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA, 3151 val, (val & mask) == mask, 3152 MT8188_DELAY_US, MT8188_TIMEOUT_US); 3153 if (ret) 3154 return ret; 3155 3156 val = 0; 3157 mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2; 3158 regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_SET, mask); 3159 3160 ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA, 3161 val, (val & mask) == mask, 3162 MT8188_DELAY_US, MT8188_TIMEOUT_US); 3163 return ret; 3164 } 3165 3166 static int bus_protect_disable(struct regmap *regmap) 3167 { 3168 int ret; 3169 u32 val; 3170 u32 mask; 3171 3172 val = 0; 3173 mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2; 3174 regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_CLR, mask); 3175 3176 ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA, 3177 val, !(val & mask), 3178 MT8188_DELAY_US, MT8188_TIMEOUT_US); 3179 if (ret) 3180 return ret; 3181 3182 val = 0; 3183 mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1; 3184 regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_CLR, mask); 3185 3186 ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA, 3187 val, !(val & mask), 3188 MT8188_DELAY_US, MT8188_TIMEOUT_US); 3189 return ret; 3190 } 3191 3192 static int mt8188_afe_pcm_dev_probe(struct platform_device *pdev) 3193 { 3194 struct mtk_base_afe *afe; 3195 struct mt8188_afe_private *afe_priv; 3196 struct device *dev; 3197 struct reset_control *rstc; 3198 struct regmap *infra_ao; 3199 int i, irq_id, ret; 3200 3201 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33)); 3202 if (ret) 3203 return ret; 3204 3205 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); 3206 if (!afe) 3207 return -ENOMEM; 3208 3209 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv), 3210 GFP_KERNEL); 3211 if (!afe->platform_priv) 3212 return -ENOMEM; 3213 3214 afe_priv = afe->platform_priv; 3215 afe->dev = &pdev->dev; 3216 dev = afe->dev; 3217 3218 afe->base_addr = devm_platform_ioremap_resource(pdev, 0); 3219 if (IS_ERR(afe->base_addr)) 3220 return dev_err_probe(dev, PTR_ERR(afe->base_addr), 3221 "AFE base_addr not found\n"); 3222 3223 infra_ao = syscon_regmap_lookup_by_phandle(dev->of_node, 3224 "mediatek,infracfg"); 3225 if (IS_ERR(infra_ao)) 3226 return dev_err_probe(dev, PTR_ERR(infra_ao), 3227 "%s() Cannot find infra_ao controller\n", 3228 __func__); 3229 3230 /* reset controller to reset audio regs before regmap cache */ 3231 rstc = devm_reset_control_get_exclusive(dev, "audiosys"); 3232 if (IS_ERR(rstc)) 3233 return dev_err_probe(dev, PTR_ERR(rstc), 3234 "could not get audiosys reset\n"); 3235 3236 ret = bus_protect_enable(infra_ao); 3237 if (ret) { 3238 dev_err(dev, "bus_protect_enable failed\n"); 3239 return ret; 3240 } 3241 3242 ret = reset_control_reset(rstc); 3243 if (ret) { 3244 dev_err(dev, "failed to trigger audio reset:%d\n", ret); 3245 return ret; 3246 } 3247 3248 ret = bus_protect_disable(infra_ao); 3249 if (ret) { 3250 dev_err(dev, "bus_protect_disable failed\n"); 3251 return ret; 3252 } 3253 3254 /* initial audio related clock */ 3255 ret = mt8188_afe_init_clock(afe); 3256 if (ret) 3257 return dev_err_probe(dev, ret, "init clock error"); 3258 3259 spin_lock_init(&afe_priv->afe_ctrl_lock); 3260 3261 mutex_init(&afe->irq_alloc_lock); 3262 3263 /* irq initialize */ 3264 afe->irqs_size = MT8188_AFE_IRQ_NUM; 3265 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), 3266 GFP_KERNEL); 3267 if (!afe->irqs) 3268 return -ENOMEM; 3269 3270 for (i = 0; i < afe->irqs_size; i++) 3271 afe->irqs[i].irq_data = &irq_data[i]; 3272 3273 /* init memif */ 3274 afe->memif_size = MT8188_AFE_MEMIF_NUM; 3275 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), 3276 GFP_KERNEL); 3277 if (!afe->memif) 3278 return -ENOMEM; 3279 3280 for (i = 0; i < afe->memif_size; i++) { 3281 afe->memif[i].data = &memif_data[i]; 3282 afe->memif[i].irq_usage = mt8188_afe_memif_const_irqs[i]; 3283 afe->memif[i].const_irq = 1; 3284 afe->irqs[afe->memif[i].irq_usage].irq_occupyed = true; 3285 } 3286 3287 /* request irq */ 3288 irq_id = platform_get_irq(pdev, 0); 3289 if (irq_id < 0) 3290 return dev_err_probe(dev, irq_id, "no irq found"); 3291 3292 ret = devm_request_irq(dev, irq_id, mt8188_afe_irq_handler, 3293 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe); 3294 if (ret) 3295 return dev_err_probe(dev, ret, "could not request_irq for asys-isr\n"); 3296 3297 /* init sub_dais */ 3298 INIT_LIST_HEAD(&afe->sub_dais); 3299 3300 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) { 3301 ret = dai_register_cbs[i](afe); 3302 if (ret) 3303 return dev_err_probe(dev, ret, "dai register i %d fail\n", i); 3304 } 3305 3306 /* init dai_driver and component_driver */ 3307 ret = mtk_afe_combine_sub_dai(afe); 3308 if (ret) 3309 return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n"); 3310 3311 afe->mtk_afe_hardware = &mt8188_afe_hardware; 3312 afe->memif_fs = mt8188_memif_fs; 3313 afe->irq_fs = mt8188_irq_fs; 3314 3315 afe->runtime_resume = mt8188_afe_runtime_resume; 3316 afe->runtime_suspend = mt8188_afe_runtime_suspend; 3317 3318 platform_set_drvdata(pdev, afe); 3319 3320 ret = mt8188_afe_parse_of(afe, pdev->dev.of_node); 3321 if (ret) 3322 return ret; 3323 3324 ret = devm_pm_runtime_enable(dev); 3325 if (ret) 3326 return ret; 3327 3328 /* enable clock for regcache get default value from hw */ 3329 afe_priv->pm_runtime_bypass_reg_ctl = true; 3330 ret = pm_runtime_resume_and_get(dev); 3331 if (ret) 3332 return dev_err_probe(dev, ret, "failed to resume device\n"); 3333 3334 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr, 3335 &mt8188_afe_regmap_config); 3336 if (IS_ERR(afe->regmap)) { 3337 ret = PTR_ERR(afe->regmap); 3338 goto err_pm_put; 3339 } 3340 3341 ret = regmap_register_patch(afe->regmap, mt8188_cg_patch, 3342 ARRAY_SIZE(mt8188_cg_patch)); 3343 if (ret < 0) { 3344 dev_info(dev, "Failed to apply cg patch\n"); 3345 goto err_pm_put; 3346 } 3347 3348 /* register component */ 3349 ret = devm_snd_soc_register_component(dev, &mt8188_afe_component, 3350 afe->dai_drivers, afe->num_dai_drivers); 3351 if (ret) { 3352 dev_warn(dev, "err_platform\n"); 3353 goto err_pm_put; 3354 } 3355 3356 mt8188_afe_init_registers(afe); 3357 3358 pm_runtime_put_sync(&pdev->dev); 3359 afe_priv->pm_runtime_bypass_reg_ctl = false; 3360 3361 regcache_cache_only(afe->regmap, true); 3362 regcache_mark_dirty(afe->regmap); 3363 3364 return 0; 3365 err_pm_put: 3366 pm_runtime_put_sync(dev); 3367 3368 return ret; 3369 } 3370 3371 static const struct of_device_id mt8188_afe_pcm_dt_match[] = { 3372 { .compatible = "mediatek,mt8188-afe", }, 3373 {}, 3374 }; 3375 MODULE_DEVICE_TABLE(of, mt8188_afe_pcm_dt_match); 3376 3377 static const struct dev_pm_ops mt8188_afe_pm_ops = { 3378 SET_RUNTIME_PM_OPS(mt8188_afe_runtime_suspend, 3379 mt8188_afe_runtime_resume, NULL) 3380 }; 3381 3382 static struct platform_driver mt8188_afe_pcm_driver = { 3383 .driver = { 3384 .name = "mt8188-audio", 3385 .of_match_table = mt8188_afe_pcm_dt_match, 3386 .pm = &mt8188_afe_pm_ops, 3387 }, 3388 .probe = mt8188_afe_pcm_dev_probe, 3389 }; 3390 3391 module_platform_driver(mt8188_afe_pcm_driver); 3392 3393 MODULE_DESCRIPTION("MediaTek SoC AFE platform driver for ALSA 8188"); 3394 MODULE_AUTHOR("Chun-Chia.Chiu <chun-chia.chiu@mediatek.com>"); 3395 MODULE_LICENSE("GPL"); 3396