1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * mt8188-afe-clk.c  --  MediaTek 8188 afe clock ctrl
4  *
5  * Copyright (c) 2022 MediaTek Inc.
6  * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
7  *         Trevor Wu <trevor.wu@mediatek.com>
8  *         Chun-Chia Chiu <chun-chia.chiu@mediatek.com>
9  */
10 
11 #include <linux/clk.h>
12 
13 #include "mt8188-afe-common.h"
14 #include "mt8188-afe-clk.h"
15 #include "mt8188-audsys-clk.h"
16 #include "mt8188-reg.h"
17 
18 static const char *aud_clks[MT8188_CLK_NUM] = {
19 	/* xtal */
20 	[MT8188_CLK_XTAL_26M] = "clk26m",
21 
22 	/* pll */
23 	[MT8188_CLK_APMIXED_APLL1] = "apll1",
24 	[MT8188_CLK_APMIXED_APLL2] = "apll2",
25 
26 	/* divider */
27 	[MT8188_CLK_TOP_APLL12_DIV0] = "apll12_div0",
28 	[MT8188_CLK_TOP_APLL12_DIV1] = "apll12_div1",
29 	[MT8188_CLK_TOP_APLL12_DIV2] = "apll12_div2",
30 	[MT8188_CLK_TOP_APLL12_DIV3] = "apll12_div3",
31 	[MT8188_CLK_TOP_APLL12_DIV9] = "apll12_div9",
32 
33 	/* mux */
34 	[MT8188_CLK_TOP_A1SYS_HP_SEL] = "top_a1sys_hp",
35 	[MT8188_CLK_TOP_AUD_INTBUS_SEL] = "top_aud_intbus",
36 	[MT8188_CLK_TOP_AUDIO_H_SEL] = "top_audio_h",
37 	[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "top_audio_local_bus",
38 	[MT8188_CLK_TOP_DPTX_M_SEL] = "top_dptx",
39 	[MT8188_CLK_TOP_I2SO1_M_SEL] = "top_i2so1",
40 	[MT8188_CLK_TOP_I2SO2_M_SEL] = "top_i2so2",
41 	[MT8188_CLK_TOP_I2SI1_M_SEL] = "top_i2si1",
42 	[MT8188_CLK_TOP_I2SI2_M_SEL] = "top_i2si2",
43 
44 	/* clock gate */
45 	[MT8188_CLK_ADSP_AUDIO_26M] = "adsp_audio_26m",
46 	/* afe clock gate */
47 	[MT8188_CLK_AUD_AFE] = "aud_afe",
48 	[MT8188_CLK_AUD_APLL1_TUNER] = "aud_apll1_tuner",
49 	[MT8188_CLK_AUD_APLL2_TUNER] = "aud_apll2_tuner",
50 	[MT8188_CLK_AUD_APLL] = "aud_apll",
51 	[MT8188_CLK_AUD_APLL2] = "aud_apll2",
52 	[MT8188_CLK_AUD_DAC] = "aud_dac",
53 	[MT8188_CLK_AUD_ADC] = "aud_adc",
54 	[MT8188_CLK_AUD_DAC_HIRES] = "aud_dac_hires",
55 	[MT8188_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp",
56 	[MT8188_CLK_AUD_ADC_HIRES] = "aud_adc_hires",
57 	[MT8188_CLK_AUD_I2SIN] = "aud_i2sin",
58 	[MT8188_CLK_AUD_TDM_IN] = "aud_tdm_in",
59 	[MT8188_CLK_AUD_I2S_OUT] = "aud_i2s_out",
60 	[MT8188_CLK_AUD_TDM_OUT] = "aud_tdm_out",
61 	[MT8188_CLK_AUD_HDMI_OUT] = "aud_hdmi_out",
62 	[MT8188_CLK_AUD_ASRC11] = "aud_asrc11",
63 	[MT8188_CLK_AUD_ASRC12] = "aud_asrc12",
64 	[MT8188_CLK_AUD_A1SYS] = "aud_a1sys",
65 	[MT8188_CLK_AUD_A2SYS] = "aud_a2sys",
66 	[MT8188_CLK_AUD_PCMIF] = "aud_pcmif",
67 	[MT8188_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1",
68 	[MT8188_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2",
69 	[MT8188_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3",
70 	[MT8188_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4",
71 	[MT8188_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5",
72 	[MT8188_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6",
73 	[MT8188_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8",
74 	[MT8188_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9",
75 	[MT8188_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10",
76 	[MT8188_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2",
77 	[MT8188_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3",
78 	[MT8188_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6",
79 	[MT8188_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7",
80 	[MT8188_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8",
81 	[MT8188_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10",
82 	[MT8188_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11",
83 };
84 
85 struct mt8188_afe_tuner_cfg {
86 	unsigned int id;
87 	int apll_div_reg;
88 	unsigned int apll_div_shift;
89 	unsigned int apll_div_maskbit;
90 	unsigned int apll_div_default;
91 	int ref_ck_sel_reg;
92 	unsigned int ref_ck_sel_shift;
93 	unsigned int ref_ck_sel_maskbit;
94 	unsigned int ref_ck_sel_default;
95 	int tuner_en_reg;
96 	unsigned int tuner_en_shift;
97 	unsigned int tuner_en_maskbit;
98 	int upper_bound_reg;
99 	unsigned int upper_bound_shift;
100 	unsigned int upper_bound_maskbit;
101 	unsigned int upper_bound_default;
102 	spinlock_t ctrl_lock; /* lock for apll tuner ctrl*/
103 	int ref_cnt;
104 };
105 
106 static struct mt8188_afe_tuner_cfg
107 	mt8188_afe_tuner_cfgs[MT8188_AUD_PLL_NUM] = {
108 	[MT8188_AUD_PLL1] = {
109 		.id = MT8188_AUD_PLL1,
110 		.apll_div_reg = AFE_APLL_TUNER_CFG,
111 		.apll_div_shift = 4,
112 		.apll_div_maskbit = 0xf,
113 		.apll_div_default = 0x7,
114 		.ref_ck_sel_reg = AFE_APLL_TUNER_CFG,
115 		.ref_ck_sel_shift = 1,
116 		.ref_ck_sel_maskbit = 0x3,
117 		.ref_ck_sel_default = 0x2,
118 		.tuner_en_reg = AFE_APLL_TUNER_CFG,
119 		.tuner_en_shift = 0,
120 		.tuner_en_maskbit = 0x1,
121 		.upper_bound_reg = AFE_APLL_TUNER_CFG,
122 		.upper_bound_shift = 8,
123 		.upper_bound_maskbit = 0xff,
124 		.upper_bound_default = 0x3,
125 	},
126 	[MT8188_AUD_PLL2] = {
127 		.id = MT8188_AUD_PLL2,
128 		.apll_div_reg = AFE_APLL_TUNER_CFG1,
129 		.apll_div_shift = 4,
130 		.apll_div_maskbit = 0xf,
131 		.apll_div_default = 0x7,
132 		.ref_ck_sel_reg = AFE_APLL_TUNER_CFG1,
133 		.ref_ck_sel_shift = 1,
134 		.ref_ck_sel_maskbit = 0x3,
135 		.ref_ck_sel_default = 0x1,
136 		.tuner_en_reg = AFE_APLL_TUNER_CFG1,
137 		.tuner_en_shift = 0,
138 		.tuner_en_maskbit = 0x1,
139 		.upper_bound_reg = AFE_APLL_TUNER_CFG1,
140 		.upper_bound_shift = 8,
141 		.upper_bound_maskbit = 0xff,
142 		.upper_bound_default = 0x3,
143 	},
144 	[MT8188_AUD_PLL3] = {
145 		.id = MT8188_AUD_PLL3,
146 		.apll_div_reg = AFE_EARC_APLL_TUNER_CFG,
147 		.apll_div_shift = 4,
148 		.apll_div_maskbit = 0x3f,
149 		.apll_div_default = 0x3,
150 		.ref_ck_sel_reg = AFE_EARC_APLL_TUNER_CFG,
151 		.ref_ck_sel_shift = 24,
152 		.ref_ck_sel_maskbit = 0x3,
153 		.ref_ck_sel_default = 0x0,
154 		.tuner_en_reg = AFE_EARC_APLL_TUNER_CFG,
155 		.tuner_en_shift = 0,
156 		.tuner_en_maskbit = 0x1,
157 		.upper_bound_reg = AFE_EARC_APLL_TUNER_CFG,
158 		.upper_bound_shift = 12,
159 		.upper_bound_maskbit = 0xff,
160 		.upper_bound_default = 0x4,
161 	},
162 	[MT8188_AUD_PLL4] = {
163 		.id = MT8188_AUD_PLL4,
164 		.apll_div_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
165 		.apll_div_shift = 4,
166 		.apll_div_maskbit = 0x3f,
167 		.apll_div_default = 0x7,
168 		.ref_ck_sel_reg = AFE_SPDIFIN_APLL_TUNER_CFG1,
169 		.ref_ck_sel_shift = 8,
170 		.ref_ck_sel_maskbit = 0x1,
171 		.ref_ck_sel_default = 0,
172 		.tuner_en_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
173 		.tuner_en_shift = 0,
174 		.tuner_en_maskbit = 0x1,
175 		.upper_bound_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
176 		.upper_bound_shift = 12,
177 		.upper_bound_maskbit = 0xff,
178 		.upper_bound_default = 0x4,
179 	},
180 	[MT8188_AUD_PLL5] = {
181 		.id = MT8188_AUD_PLL5,
182 		.apll_div_reg = AFE_LINEIN_APLL_TUNER_CFG,
183 		.apll_div_shift = 4,
184 		.apll_div_maskbit = 0x3f,
185 		.apll_div_default = 0x3,
186 		.ref_ck_sel_reg = AFE_LINEIN_APLL_TUNER_CFG,
187 		.ref_ck_sel_shift = 24,
188 		.ref_ck_sel_maskbit = 0x1,
189 		.ref_ck_sel_default = 0,
190 		.tuner_en_reg = AFE_LINEIN_APLL_TUNER_CFG,
191 		.tuner_en_shift = 0,
192 		.tuner_en_maskbit = 0x1,
193 		.upper_bound_reg = AFE_LINEIN_APLL_TUNER_CFG,
194 		.upper_bound_shift = 12,
195 		.upper_bound_maskbit = 0xff,
196 		.upper_bound_default = 0x4,
197 	},
198 };
199 
200 static struct mt8188_afe_tuner_cfg *mt8188_afe_found_apll_tuner(unsigned int id)
201 {
202 	if (id >= MT8188_AUD_PLL_NUM)
203 		return NULL;
204 
205 	return &mt8188_afe_tuner_cfgs[id];
206 }
207 
208 static int mt8188_afe_init_apll_tuner(unsigned int id)
209 {
210 	struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);
211 
212 	if (!cfg)
213 		return -EINVAL;
214 
215 	cfg->ref_cnt = 0;
216 	spin_lock_init(&cfg->ctrl_lock);
217 
218 	return 0;
219 }
220 
221 static int mt8188_afe_setup_apll_tuner(struct mtk_base_afe *afe, unsigned int id)
222 {
223 	const struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);
224 
225 	if (!cfg)
226 		return -EINVAL;
227 
228 	regmap_update_bits(afe->regmap,
229 			   cfg->apll_div_reg,
230 			   cfg->apll_div_maskbit << cfg->apll_div_shift,
231 			   cfg->apll_div_default << cfg->apll_div_shift);
232 
233 	regmap_update_bits(afe->regmap,
234 			   cfg->ref_ck_sel_reg,
235 			   cfg->ref_ck_sel_maskbit << cfg->ref_ck_sel_shift,
236 			   cfg->ref_ck_sel_default << cfg->ref_ck_sel_shift);
237 
238 	regmap_update_bits(afe->regmap,
239 			   cfg->upper_bound_reg,
240 			   cfg->upper_bound_maskbit << cfg->upper_bound_shift,
241 			   cfg->upper_bound_default << cfg->upper_bound_shift);
242 
243 	return 0;
244 }
245 
246 static int mt8188_afe_enable_tuner_clk(struct mtk_base_afe *afe,
247 				       unsigned int id)
248 {
249 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
250 
251 	switch (id) {
252 	case MT8188_AUD_PLL1:
253 		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]);
254 		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]);
255 		break;
256 	case MT8188_AUD_PLL2:
257 		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]);
258 		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]);
259 		break;
260 	default:
261 		return -EINVAL;
262 	}
263 
264 	return 0;
265 }
266 
267 static int mt8188_afe_disable_tuner_clk(struct mtk_base_afe *afe,
268 					unsigned int id)
269 {
270 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
271 
272 	switch (id) {
273 	case MT8188_AUD_PLL1:
274 		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]);
275 		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]);
276 		break;
277 	case MT8188_AUD_PLL2:
278 		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]);
279 		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]);
280 		break;
281 	default:
282 		return -EINVAL;
283 	}
284 
285 	return 0;
286 }
287 
288 static int mt8188_afe_enable_apll_tuner(struct mtk_base_afe *afe, unsigned int id)
289 {
290 	struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);
291 	unsigned long flags;
292 	int ret;
293 
294 	if (!cfg)
295 		return -EINVAL;
296 
297 	ret = mt8188_afe_setup_apll_tuner(afe, id);
298 	if (ret)
299 		return ret;
300 
301 	ret = mt8188_afe_enable_tuner_clk(afe, id);
302 	if (ret)
303 		return ret;
304 
305 	spin_lock_irqsave(&cfg->ctrl_lock, flags);
306 
307 	cfg->ref_cnt++;
308 	if (cfg->ref_cnt == 1)
309 		regmap_update_bits(afe->regmap,
310 				   cfg->tuner_en_reg,
311 				   cfg->tuner_en_maskbit << cfg->tuner_en_shift,
312 				   BIT(cfg->tuner_en_shift));
313 
314 	spin_unlock_irqrestore(&cfg->ctrl_lock, flags);
315 
316 	return 0;
317 }
318 
319 static int mt8188_afe_disable_apll_tuner(struct mtk_base_afe *afe, unsigned int id)
320 {
321 	struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);
322 	unsigned long flags;
323 	int ret;
324 
325 	if (!cfg)
326 		return -EINVAL;
327 
328 	spin_lock_irqsave(&cfg->ctrl_lock, flags);
329 
330 	cfg->ref_cnt--;
331 	if (cfg->ref_cnt == 0)
332 		regmap_update_bits(afe->regmap,
333 				   cfg->tuner_en_reg,
334 				   cfg->tuner_en_maskbit << cfg->tuner_en_shift,
335 				   0 << cfg->tuner_en_shift);
336 	else if (cfg->ref_cnt < 0)
337 		cfg->ref_cnt = 0;
338 
339 	spin_unlock_irqrestore(&cfg->ctrl_lock, flags);
340 
341 	ret = mt8188_afe_disable_tuner_clk(afe, id);
342 	if (ret)
343 		return ret;
344 
345 	return 0;
346 }
347 
348 int mt8188_afe_get_mclk_source_clk_id(int sel)
349 {
350 	switch (sel) {
351 	case MT8188_MCK_SEL_26M:
352 		return MT8188_CLK_XTAL_26M;
353 	case MT8188_MCK_SEL_APLL1:
354 		return MT8188_CLK_APMIXED_APLL1;
355 	case MT8188_MCK_SEL_APLL2:
356 		return MT8188_CLK_APMIXED_APLL2;
357 	default:
358 		return -EINVAL;
359 	}
360 }
361 
362 int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll)
363 {
364 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
365 	int clk_id = mt8188_afe_get_mclk_source_clk_id(apll);
366 
367 	if (clk_id < 0) {
368 		dev_dbg(afe->dev, "invalid clk id\n");
369 		return 0;
370 	}
371 
372 	return clk_get_rate(afe_priv->clk[clk_id]);
373 }
374 
375 int mt8188_afe_get_default_mclk_source_by_rate(int rate)
376 {
377 	return ((rate % 8000) == 0) ?
378 		MT8188_MCK_SEL_APLL1 : MT8188_MCK_SEL_APLL2;
379 }
380 
381 int mt8188_afe_init_clock(struct mtk_base_afe *afe)
382 {
383 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
384 	int i, ret;
385 
386 	ret = mt8188_audsys_clk_register(afe);
387 	if (ret) {
388 		dev_err(afe->dev, "register audsys clk fail %d\n", ret);
389 		return ret;
390 	}
391 
392 	afe_priv->clk =
393 		devm_kcalloc(afe->dev, MT8188_CLK_NUM, sizeof(*afe_priv->clk),
394 			     GFP_KERNEL);
395 	if (!afe_priv->clk)
396 		return -ENOMEM;
397 
398 	for (i = 0; i < MT8188_CLK_NUM; i++) {
399 		afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
400 		if (IS_ERR(afe_priv->clk[i])) {
401 			dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
402 				__func__, aud_clks[i],
403 				PTR_ERR(afe_priv->clk[i]));
404 			return PTR_ERR(afe_priv->clk[i]);
405 		}
406 	}
407 
408 	/* initial tuner */
409 	for (i = 0; i < MT8188_AUD_PLL_NUM; i++) {
410 		ret = mt8188_afe_init_apll_tuner(i);
411 		if (ret) {
412 			dev_info(afe->dev, "%s(), init apll_tuner%d failed",
413 				 __func__, (i + 1));
414 			return -EINVAL;
415 		}
416 	}
417 
418 	return 0;
419 }
420 
421 void mt8188_afe_deinit_clock(void *priv)
422 {
423 	struct mtk_base_afe *afe = priv;
424 
425 	mt8188_audsys_clk_unregister(afe);
426 }
427 
428 int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
429 {
430 	int ret;
431 
432 	if (clk) {
433 		ret = clk_prepare_enable(clk);
434 		if (ret) {
435 			dev_dbg(afe->dev, "%s(), failed to enable clk\n",
436 				__func__);
437 			return ret;
438 		}
439 	} else {
440 		dev_dbg(afe->dev, "NULL clk\n");
441 	}
442 	return 0;
443 }
444 EXPORT_SYMBOL_GPL(mt8188_afe_enable_clk);
445 
446 void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
447 {
448 	if (clk)
449 		clk_disable_unprepare(clk);
450 	else
451 		dev_dbg(afe->dev, "NULL clk\n");
452 }
453 EXPORT_SYMBOL_GPL(mt8188_afe_disable_clk);
454 
455 int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
456 			    unsigned int rate)
457 {
458 	int ret;
459 
460 	if (clk) {
461 		ret = clk_set_rate(clk, rate);
462 		if (ret) {
463 			dev_dbg(afe->dev, "%s(), failed to set clk rate\n",
464 				__func__);
465 			return ret;
466 		}
467 	}
468 
469 	return 0;
470 }
471 
472 int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
473 			      struct clk *parent)
474 {
475 	int ret;
476 
477 	if (clk && parent) {
478 		ret = clk_set_parent(clk, parent);
479 		if (ret) {
480 			dev_dbg(afe->dev, "%s(), failed to set clk parent\n",
481 				__func__);
482 			return ret;
483 		}
484 	}
485 
486 	return 0;
487 }
488 
489 static unsigned int get_top_cg_reg(unsigned int cg_type)
490 {
491 	switch (cg_type) {
492 	case MT8188_TOP_CG_A1SYS_TIMING:
493 	case MT8188_TOP_CG_A2SYS_TIMING:
494 	case MT8188_TOP_CG_26M_TIMING:
495 		return ASYS_TOP_CON;
496 	default:
497 		return 0;
498 	}
499 }
500 
501 static unsigned int get_top_cg_mask(unsigned int cg_type)
502 {
503 	switch (cg_type) {
504 	case MT8188_TOP_CG_A1SYS_TIMING:
505 		return ASYS_TOP_CON_A1SYS_TIMING_ON;
506 	case MT8188_TOP_CG_A2SYS_TIMING:
507 		return ASYS_TOP_CON_A2SYS_TIMING_ON;
508 	case MT8188_TOP_CG_26M_TIMING:
509 		return ASYS_TOP_CON_26M_TIMING_ON;
510 	default:
511 		return 0;
512 	}
513 }
514 
515 static unsigned int get_top_cg_on_val(unsigned int cg_type)
516 {
517 	switch (cg_type) {
518 	case MT8188_TOP_CG_A1SYS_TIMING:
519 	case MT8188_TOP_CG_A2SYS_TIMING:
520 	case MT8188_TOP_CG_26M_TIMING:
521 		return get_top_cg_mask(cg_type);
522 	default:
523 		return 0;
524 	}
525 }
526 
527 static unsigned int get_top_cg_off_val(unsigned int cg_type)
528 {
529 	switch (cg_type) {
530 	case MT8188_TOP_CG_A1SYS_TIMING:
531 	case MT8188_TOP_CG_A2SYS_TIMING:
532 	case MT8188_TOP_CG_26M_TIMING:
533 		return 0;
534 	default:
535 		return get_top_cg_mask(cg_type);
536 	}
537 }
538 
539 static int mt8188_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
540 {
541 	unsigned int reg = get_top_cg_reg(cg_type);
542 	unsigned int mask = get_top_cg_mask(cg_type);
543 	unsigned int val = get_top_cg_on_val(cg_type);
544 
545 	regmap_update_bits(afe->regmap, reg, mask, val);
546 
547 	return 0;
548 }
549 
550 static int mt8188_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
551 {
552 	unsigned int reg = get_top_cg_reg(cg_type);
553 	unsigned int mask = get_top_cg_mask(cg_type);
554 	unsigned int val = get_top_cg_off_val(cg_type);
555 
556 	regmap_update_bits(afe->regmap, reg, mask, val);
557 
558 	return 0;
559 }
560 
561 int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
562 {
563 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
564 
565 	/* bus clock for AFE external access, like DRAM */
566 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]);
567 
568 	/* bus clock for AFE internal access, like AFE SRAM */
569 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]);
570 
571 	/* audio 26m clock source */
572 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]);
573 
574 	/* AFE hw clock */
575 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);
576 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]);
577 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
578 
579 	return 0;
580 }
581 
582 int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
583 {
584 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
585 
586 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
587 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]);
588 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);
589 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]);
590 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]);
591 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]);
592 
593 	return 0;
594 }
595 
596 static int mt8188_afe_enable_afe_on(struct mtk_base_afe *afe)
597 {
598 	regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
599 	return 0;
600 }
601 
602 static int mt8188_afe_disable_afe_on(struct mtk_base_afe *afe)
603 {
604 	regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
605 	return 0;
606 }
607 
608 static int mt8188_afe_enable_timing_sys(struct mtk_base_afe *afe)
609 {
610 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
611 
612 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
613 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);
614 
615 	mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);
616 	mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);
617 	mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);
618 
619 	return 0;
620 }
621 
622 static int mt8188_afe_disable_timing_sys(struct mtk_base_afe *afe)
623 {
624 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
625 
626 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
627 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);
628 
629 	mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);
630 	mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);
631 	mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);
632 
633 	return 0;
634 }
635 
636 int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe)
637 {
638 	mt8188_afe_enable_timing_sys(afe);
639 
640 	mt8188_afe_enable_afe_on(afe);
641 
642 	mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL1);
643 	mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL2);
644 
645 	return 0;
646 }
647 
648 int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe)
649 {
650 	mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2);
651 	mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1);
652 
653 	mt8188_afe_disable_afe_on(afe);
654 
655 	mt8188_afe_disable_timing_sys(afe);
656 
657 	return 0;
658 }
659