1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // MediaTek ALSA SoC Audio DAI I2S Control 4 // 5 // Copyright (c) 2022 MediaTek Inc. 6 // Author: Jiaxin Yu <jiaxin.yu@mediatek.com> 7 8 #include <linux/bitops.h> 9 #include <linux/regmap.h> 10 #include <sound/pcm_params.h> 11 #include "mt8186-afe-clk.h" 12 #include "mt8186-afe-common.h" 13 #include "mt8186-afe-gpio.h" 14 #include "mt8186-interconnection.h" 15 16 enum { 17 I2S_FMT_EIAJ = 0, 18 I2S_FMT_I2S = 1, 19 }; 20 21 enum { 22 I2S_WLEN_16_BIT = 0, 23 I2S_WLEN_32_BIT = 1, 24 }; 25 26 enum { 27 I2S_HD_NORMAL = 0, 28 I2S_HD_LOW_JITTER = 1, 29 }; 30 31 enum { 32 I2S1_SEL_O28_O29 = 0, 33 I2S1_SEL_O03_O04 = 1, 34 }; 35 36 enum { 37 I2S_IN_PAD_CONNSYS = 0, 38 I2S_IN_PAD_IO_MUX = 1, 39 }; 40 41 struct mtk_afe_i2s_priv { 42 int id; 43 int rate; /* for determine which apll to use */ 44 int low_jitter_en; 45 int master; /* only i2s0 has slave mode*/ 46 47 const char *share_property_name; 48 int share_i2s_id; 49 50 int mclk_id; 51 int mclk_rate; 52 int mclk_apll; 53 }; 54 55 static unsigned int get_i2s_wlen(snd_pcm_format_t format) 56 { 57 return snd_pcm_format_physical_width(format) <= 16 ? 58 I2S_WLEN_16_BIT : I2S_WLEN_32_BIT; 59 } 60 61 #define MTK_AFE_I2S0_KCONTROL_NAME "I2S0_HD_Mux" 62 #define MTK_AFE_I2S1_KCONTROL_NAME "I2S1_HD_Mux" 63 #define MTK_AFE_I2S2_KCONTROL_NAME "I2S2_HD_Mux" 64 #define MTK_AFE_I2S3_KCONTROL_NAME "I2S3_HD_Mux" 65 #define MTK_AFE_I2S0_SRC_KCONTROL_NAME "I2S0_SRC_Mux" 66 67 #define I2S0_HD_EN_W_NAME "I2S0_HD_EN" 68 #define I2S1_HD_EN_W_NAME "I2S1_HD_EN" 69 #define I2S2_HD_EN_W_NAME "I2S2_HD_EN" 70 #define I2S3_HD_EN_W_NAME "I2S3_HD_EN" 71 72 #define I2S0_MCLK_EN_W_NAME "I2S0_MCLK_EN" 73 #define I2S1_MCLK_EN_W_NAME "I2S1_MCLK_EN" 74 #define I2S2_MCLK_EN_W_NAME "I2S2_MCLK_EN" 75 #define I2S3_MCLK_EN_W_NAME "I2S3_MCLK_EN" 76 77 static int get_i2s_id_by_name(struct mtk_base_afe *afe, 78 const char *name) 79 { 80 if (strncmp(name, "I2S0", 4) == 0) 81 return MT8186_DAI_I2S_0; 82 else if (strncmp(name, "I2S1", 4) == 0) 83 return MT8186_DAI_I2S_1; 84 else if (strncmp(name, "I2S2", 4) == 0) 85 return MT8186_DAI_I2S_2; 86 else if (strncmp(name, "I2S3", 4) == 0) 87 return MT8186_DAI_I2S_3; 88 89 return -EINVAL; 90 } 91 92 static struct mtk_afe_i2s_priv *get_i2s_priv_by_name(struct mtk_base_afe *afe, 93 const char *name) 94 { 95 struct mt8186_afe_private *afe_priv = afe->platform_priv; 96 int dai_id = get_i2s_id_by_name(afe, name); 97 98 if (dai_id < 0) 99 return NULL; 100 101 return afe_priv->dai_priv[dai_id]; 102 } 103 104 /* low jitter control */ 105 static const char * const mt8186_i2s_hd_str[] = { 106 "Normal", "Low_Jitter" 107 }; 108 109 static const struct soc_enum mt8186_i2s_enum[] = { 110 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8186_i2s_hd_str), 111 mt8186_i2s_hd_str), 112 }; 113 114 static int mt8186_i2s_hd_get(struct snd_kcontrol *kcontrol, 115 struct snd_ctl_elem_value *ucontrol) 116 { 117 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 118 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 119 struct mtk_afe_i2s_priv *i2s_priv; 120 121 i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name); 122 ucontrol->value.integer.value[0] = i2s_priv->low_jitter_en; 123 124 return 0; 125 } 126 127 static int mt8186_i2s_hd_set(struct snd_kcontrol *kcontrol, 128 struct snd_ctl_elem_value *ucontrol) 129 { 130 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 131 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 132 struct mtk_afe_i2s_priv *i2s_priv; 133 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 134 int hd_en; 135 136 if (ucontrol->value.enumerated.item[0] >= e->items) 137 return -EINVAL; 138 139 hd_en = ucontrol->value.integer.value[0]; 140 141 dev_dbg(afe->dev, "%s(), kcontrol name %s, hd_en %d\n", 142 __func__, kcontrol->id.name, hd_en); 143 144 i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name); 145 if (i2s_priv->low_jitter_en == hd_en) 146 return 0; 147 148 i2s_priv->low_jitter_en = hd_en; 149 150 return 1; 151 } 152 153 static const struct snd_kcontrol_new mtk_dai_i2s_controls[] = { 154 SOC_ENUM_EXT(MTK_AFE_I2S0_KCONTROL_NAME, mt8186_i2s_enum[0], 155 mt8186_i2s_hd_get, mt8186_i2s_hd_set), 156 SOC_ENUM_EXT(MTK_AFE_I2S1_KCONTROL_NAME, mt8186_i2s_enum[0], 157 mt8186_i2s_hd_get, mt8186_i2s_hd_set), 158 SOC_ENUM_EXT(MTK_AFE_I2S2_KCONTROL_NAME, mt8186_i2s_enum[0], 159 mt8186_i2s_hd_get, mt8186_i2s_hd_set), 160 SOC_ENUM_EXT(MTK_AFE_I2S3_KCONTROL_NAME, mt8186_i2s_enum[0], 161 mt8186_i2s_hd_get, mt8186_i2s_hd_set), 162 }; 163 164 /* dai component */ 165 /* i2s virtual mux to output widget */ 166 static const char * const i2s_mux_map[] = { 167 "Normal", "Dummy_Widget", 168 }; 169 170 static int i2s_mux_map_value[] = { 171 0, 1, 172 }; 173 174 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s_mux_map_enum, 175 SND_SOC_NOPM, 176 0, 177 1, 178 i2s_mux_map, 179 i2s_mux_map_value); 180 181 static const struct snd_kcontrol_new i2s0_in_mux_control = 182 SOC_DAPM_ENUM("I2S0 In Select", i2s_mux_map_enum); 183 184 static const struct snd_kcontrol_new i2s1_out_mux_control = 185 SOC_DAPM_ENUM("I2S1 Out Select", i2s_mux_map_enum); 186 187 static const struct snd_kcontrol_new i2s2_in_mux_control = 188 SOC_DAPM_ENUM("I2S2 In Select", i2s_mux_map_enum); 189 190 static const struct snd_kcontrol_new i2s3_out_mux_control = 191 SOC_DAPM_ENUM("I2S3 Out Select", i2s_mux_map_enum); 192 193 /* i2s in lpbk */ 194 static const char * const i2s_lpbk_mux_map[] = { 195 "Normal", "Lpbk", 196 }; 197 198 static int i2s_lpbk_mux_map_value[] = { 199 0, 1, 200 }; 201 202 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s0_lpbk_mux_map_enum, 203 AFE_I2S_CON, 204 I2S_LOOPBACK_SFT, 205 1, 206 i2s_lpbk_mux_map, 207 i2s_lpbk_mux_map_value); 208 209 static const struct snd_kcontrol_new i2s0_lpbk_mux_control = 210 SOC_DAPM_ENUM("I2S Lpbk Select", i2s0_lpbk_mux_map_enum); 211 212 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s2_lpbk_mux_map_enum, 213 AFE_I2S_CON2, 214 I2S3_LOOPBACK_SFT, 215 1, 216 i2s_lpbk_mux_map, 217 i2s_lpbk_mux_map_value); 218 219 static const struct snd_kcontrol_new i2s2_lpbk_mux_control = 220 SOC_DAPM_ENUM("I2S Lpbk Select", i2s2_lpbk_mux_map_enum); 221 222 /* interconnection */ 223 static const struct snd_kcontrol_new mtk_i2s3_ch1_mix[] = { 224 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN0, 225 I_DL1_CH1, 1, 0), 226 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN0, 227 I_DL2_CH1, 1, 0), 228 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN0, 229 I_DL3_CH1, 1, 0), 230 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN0, 231 I_DL12_CH1, 1, 0), 232 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN0, 233 I_DL12_CH3, 1, 0), 234 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN0_1, 235 I_DL6_CH1, 1, 0), 236 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN0_1, 237 I_DL4_CH1, 1, 0), 238 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN0_1, 239 I_DL5_CH1, 1, 0), 240 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1 Switch", AFE_CONN0_1, 241 I_DL8_CH1, 1, 0), 242 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN0, 243 I_GAIN1_OUT_CH1, 1, 0), 244 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN0, 245 I_ADDA_UL_CH1, 1, 0), 246 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN0, 247 I_ADDA_UL_CH2, 1, 0), 248 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN0, 249 I_ADDA_UL_CH3, 1, 0), 250 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN0, 251 I_PCM_1_CAP_CH1, 1, 0), 252 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN0_1, 253 I_SRC_1_OUT_CH1, 1, 0), 254 }; 255 256 static const struct snd_kcontrol_new mtk_i2s3_ch2_mix[] = { 257 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN1, 258 I_DL1_CH2, 1, 0), 259 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN1, 260 I_DL2_CH2, 1, 0), 261 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN1, 262 I_DL3_CH2, 1, 0), 263 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN1, 264 I_DL12_CH2, 1, 0), 265 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN1, 266 I_DL12_CH4, 1, 0), 267 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN1_1, 268 I_DL6_CH2, 1, 0), 269 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN1_1, 270 I_DL4_CH2, 1, 0), 271 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN1_1, 272 I_DL5_CH2, 1, 0), 273 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2 Switch", AFE_CONN1_1, 274 I_DL8_CH2, 1, 0), 275 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN1, 276 I_GAIN1_OUT_CH2, 1, 0), 277 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN1, 278 I_ADDA_UL_CH1, 1, 0), 279 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN1, 280 I_ADDA_UL_CH2, 1, 0), 281 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN1, 282 I_ADDA_UL_CH3, 1, 0), 283 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN1, 284 I_PCM_1_CAP_CH2, 1, 0), 285 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2 Switch", AFE_CONN1, 286 I_PCM_2_CAP_CH2, 1, 0), 287 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN1_1, 288 I_SRC_1_OUT_CH2, 1, 0), 289 }; 290 291 static const struct snd_kcontrol_new mtk_i2s1_ch1_mix[] = { 292 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN28, 293 I_DL1_CH1, 1, 0), 294 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN28, 295 I_DL2_CH1, 1, 0), 296 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN28, 297 I_DL3_CH1, 1, 0), 298 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN28, 299 I_DL12_CH1, 1, 0), 300 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN28, 301 I_DL12_CH3, 1, 0), 302 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN28_1, 303 I_DL6_CH1, 1, 0), 304 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN28_1, 305 I_DL4_CH1, 1, 0), 306 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN28_1, 307 I_DL5_CH1, 1, 0), 308 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1 Switch", AFE_CONN28_1, 309 I_DL8_CH1, 1, 0), 310 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN28, 311 I_GAIN1_OUT_CH1, 1, 0), 312 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN28, 313 I_ADDA_UL_CH1, 1, 0), 314 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN28, 315 I_PCM_1_CAP_CH1, 1, 0), 316 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN28_1, 317 I_SRC_1_OUT_CH1, 1, 0), 318 }; 319 320 static const struct snd_kcontrol_new mtk_i2s1_ch2_mix[] = { 321 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN29, 322 I_DL1_CH2, 1, 0), 323 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN29, 324 I_DL2_CH2, 1, 0), 325 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN29, 326 I_DL3_CH2, 1, 0), 327 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN29, 328 I_DL12_CH2, 1, 0), 329 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN29, 330 I_DL12_CH4, 1, 0), 331 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN29_1, 332 I_DL6_CH2, 1, 0), 333 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN29_1, 334 I_DL4_CH2, 1, 0), 335 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN29_1, 336 I_DL5_CH2, 1, 0), 337 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2 Switch", AFE_CONN29_1, 338 I_DL8_CH2, 1, 0), 339 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN29, 340 I_GAIN1_OUT_CH2, 1, 0), 341 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN29, 342 I_ADDA_UL_CH2, 1, 0), 343 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN29, 344 I_PCM_1_CAP_CH2, 1, 0), 345 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2 Switch", AFE_CONN29, 346 I_PCM_2_CAP_CH2, 1, 0), 347 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN29_1, 348 I_SRC_1_OUT_CH2, 1, 0), 349 }; 350 351 enum { 352 SUPPLY_SEQ_APLL, 353 SUPPLY_SEQ_I2S_MCLK_EN, 354 SUPPLY_SEQ_I2S_HD_EN, 355 SUPPLY_SEQ_I2S_EN, 356 }; 357 358 static int mtk_i2s_en_event(struct snd_soc_dapm_widget *w, 359 struct snd_kcontrol *kcontrol, 360 int event) 361 { 362 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 363 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 364 struct mtk_afe_i2s_priv *i2s_priv; 365 366 i2s_priv = get_i2s_priv_by_name(afe, w->name); 367 368 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 369 __func__, w->name, event); 370 371 switch (event) { 372 case SND_SOC_DAPM_PRE_PMU: 373 mt8186_afe_gpio_request(afe->dev, true, i2s_priv->id, 0); 374 break; 375 case SND_SOC_DAPM_POST_PMD: 376 mt8186_afe_gpio_request(afe->dev, false, i2s_priv->id, 0); 377 break; 378 default: 379 break; 380 } 381 382 return 0; 383 } 384 385 static int mtk_apll_event(struct snd_soc_dapm_widget *w, 386 struct snd_kcontrol *kcontrol, 387 int event) 388 { 389 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 390 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 391 392 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 393 __func__, w->name, event); 394 395 switch (event) { 396 case SND_SOC_DAPM_PRE_PMU: 397 if (strcmp(w->name, APLL1_W_NAME) == 0) 398 mt8186_apll1_enable(afe); 399 else 400 mt8186_apll2_enable(afe); 401 break; 402 case SND_SOC_DAPM_POST_PMD: 403 if (strcmp(w->name, APLL1_W_NAME) == 0) 404 mt8186_apll1_disable(afe); 405 else 406 mt8186_apll2_disable(afe); 407 break; 408 default: 409 break; 410 } 411 412 return 0; 413 } 414 415 static int mtk_mclk_en_event(struct snd_soc_dapm_widget *w, 416 struct snd_kcontrol *kcontrol, 417 int event) 418 { 419 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 420 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 421 struct mtk_afe_i2s_priv *i2s_priv; 422 423 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 424 __func__, w->name, event); 425 426 i2s_priv = get_i2s_priv_by_name(afe, w->name); 427 428 switch (event) { 429 case SND_SOC_DAPM_PRE_PMU: 430 mt8186_mck_enable(afe, i2s_priv->mclk_id, i2s_priv->mclk_rate); 431 break; 432 case SND_SOC_DAPM_POST_PMD: 433 i2s_priv->mclk_rate = 0; 434 mt8186_mck_disable(afe, i2s_priv->mclk_id); 435 break; 436 default: 437 break; 438 } 439 440 return 0; 441 } 442 443 static const struct snd_soc_dapm_widget mtk_dai_i2s_widgets[] = { 444 SND_SOC_DAPM_INPUT("CONNSYS"), 445 446 SND_SOC_DAPM_MIXER("I2S1_CH1", SND_SOC_NOPM, 0, 0, 447 mtk_i2s1_ch1_mix, 448 ARRAY_SIZE(mtk_i2s1_ch1_mix)), 449 SND_SOC_DAPM_MIXER("I2S1_CH2", SND_SOC_NOPM, 0, 0, 450 mtk_i2s1_ch2_mix, 451 ARRAY_SIZE(mtk_i2s1_ch2_mix)), 452 453 SND_SOC_DAPM_MIXER("I2S3_CH1", SND_SOC_NOPM, 0, 0, 454 mtk_i2s3_ch1_mix, 455 ARRAY_SIZE(mtk_i2s3_ch1_mix)), 456 SND_SOC_DAPM_MIXER("I2S3_CH2", SND_SOC_NOPM, 0, 0, 457 mtk_i2s3_ch2_mix, 458 ARRAY_SIZE(mtk_i2s3_ch2_mix)), 459 460 /* i2s en*/ 461 SND_SOC_DAPM_SUPPLY_S("I2S0_EN", SUPPLY_SEQ_I2S_EN, 462 AFE_I2S_CON, I2S_EN_SFT, 0, 463 mtk_i2s_en_event, 464 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 465 SND_SOC_DAPM_SUPPLY_S("I2S1_EN", SUPPLY_SEQ_I2S_EN, 466 AFE_I2S_CON1, I2S_EN_SFT, 0, 467 mtk_i2s_en_event, 468 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 469 SND_SOC_DAPM_SUPPLY_S("I2S2_EN", SUPPLY_SEQ_I2S_EN, 470 AFE_I2S_CON2, I2S_EN_SFT, 0, 471 mtk_i2s_en_event, 472 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 473 SND_SOC_DAPM_SUPPLY_S("I2S3_EN", SUPPLY_SEQ_I2S_EN, 474 AFE_I2S_CON3, I2S_EN_SFT, 0, 475 mtk_i2s_en_event, 476 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 477 /* i2s hd en */ 478 SND_SOC_DAPM_SUPPLY_S(I2S0_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, 479 AFE_I2S_CON, I2S1_HD_EN_SFT, 0, NULL, 480 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 481 SND_SOC_DAPM_SUPPLY_S(I2S1_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, 482 AFE_I2S_CON1, I2S2_HD_EN_SFT, 0, NULL, 483 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 484 SND_SOC_DAPM_SUPPLY_S(I2S2_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, 485 AFE_I2S_CON2, I2S3_HD_EN_SFT, 0, NULL, 486 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 487 SND_SOC_DAPM_SUPPLY_S(I2S3_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, 488 AFE_I2S_CON3, I2S4_HD_EN_SFT, 0, NULL, 489 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 490 491 /* i2s mclk en */ 492 SND_SOC_DAPM_SUPPLY_S(I2S0_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 493 SND_SOC_NOPM, 0, 0, 494 mtk_mclk_en_event, 495 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 496 SND_SOC_DAPM_SUPPLY_S(I2S1_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 497 SND_SOC_NOPM, 0, 0, 498 mtk_mclk_en_event, 499 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 500 SND_SOC_DAPM_SUPPLY_S(I2S2_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 501 SND_SOC_NOPM, 0, 0, 502 mtk_mclk_en_event, 503 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 504 SND_SOC_DAPM_SUPPLY_S(I2S3_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 505 SND_SOC_NOPM, 0, 0, 506 mtk_mclk_en_event, 507 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 508 509 /* apll */ 510 SND_SOC_DAPM_SUPPLY_S(APLL1_W_NAME, SUPPLY_SEQ_APLL, 511 SND_SOC_NOPM, 0, 0, 512 mtk_apll_event, 513 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 514 SND_SOC_DAPM_SUPPLY_S(APLL2_W_NAME, SUPPLY_SEQ_APLL, 515 SND_SOC_NOPM, 0, 0, 516 mtk_apll_event, 517 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 518 519 /* allow i2s on without codec on */ 520 SND_SOC_DAPM_OUTPUT("I2S_DUMMY_OUT"), 521 SND_SOC_DAPM_MUX("I2S1_Out_Mux", 522 SND_SOC_NOPM, 0, 0, &i2s1_out_mux_control), 523 SND_SOC_DAPM_MUX("I2S3_Out_Mux", 524 SND_SOC_NOPM, 0, 0, &i2s3_out_mux_control), 525 SND_SOC_DAPM_INPUT("I2S_DUMMY_IN"), 526 SND_SOC_DAPM_MUX("I2S0_In_Mux", 527 SND_SOC_NOPM, 0, 0, &i2s0_in_mux_control), 528 SND_SOC_DAPM_MUX("I2S2_In_Mux", 529 SND_SOC_NOPM, 0, 0, &i2s2_in_mux_control), 530 531 /* i2s in lpbk */ 532 SND_SOC_DAPM_MUX("I2S0_Lpbk_Mux", 533 SND_SOC_NOPM, 0, 0, &i2s0_lpbk_mux_control), 534 SND_SOC_DAPM_MUX("I2S2_Lpbk_Mux", 535 SND_SOC_NOPM, 0, 0, &i2s2_lpbk_mux_control), 536 }; 537 538 static int mtk_afe_i2s_share_connect(struct snd_soc_dapm_widget *source, 539 struct snd_soc_dapm_widget *sink) 540 { 541 struct snd_soc_dapm_widget *w = sink; 542 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 543 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 544 struct mtk_afe_i2s_priv *i2s_priv; 545 546 i2s_priv = get_i2s_priv_by_name(afe, sink->name); 547 if (i2s_priv->share_i2s_id < 0) 548 return 0; 549 550 return i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name); 551 } 552 553 static int mtk_afe_i2s_hd_connect(struct snd_soc_dapm_widget *source, 554 struct snd_soc_dapm_widget *sink) 555 { 556 struct snd_soc_dapm_widget *w = sink; 557 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 558 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 559 struct mtk_afe_i2s_priv *i2s_priv; 560 561 i2s_priv = get_i2s_priv_by_name(afe, sink->name); 562 if (get_i2s_id_by_name(afe, sink->name) == 563 get_i2s_id_by_name(afe, source->name)) 564 return i2s_priv->low_jitter_en; 565 566 /* check if share i2s need hd en */ 567 if (i2s_priv->share_i2s_id < 0) 568 return 0; 569 570 if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name)) 571 return i2s_priv->low_jitter_en; 572 573 return 0; 574 } 575 576 static int mtk_afe_i2s_apll_connect(struct snd_soc_dapm_widget *source, 577 struct snd_soc_dapm_widget *sink) 578 { 579 struct snd_soc_dapm_widget *w = sink; 580 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 581 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 582 struct mtk_afe_i2s_priv *i2s_priv; 583 int cur_apll; 584 int i2s_need_apll; 585 586 i2s_priv = get_i2s_priv_by_name(afe, w->name); 587 /* which apll */ 588 cur_apll = mt8186_get_apll_by_name(afe, source->name); 589 /* choose APLL from i2s rate */ 590 i2s_need_apll = mt8186_get_apll_by_rate(afe, i2s_priv->rate); 591 592 return (i2s_need_apll == cur_apll) ? 1 : 0; 593 } 594 595 static int mtk_afe_i2s_mclk_connect(struct snd_soc_dapm_widget *source, 596 struct snd_soc_dapm_widget *sink) 597 { 598 struct snd_soc_dapm_widget *w = sink; 599 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 600 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 601 struct mtk_afe_i2s_priv *i2s_priv; 602 603 i2s_priv = get_i2s_priv_by_name(afe, sink->name); 604 if (get_i2s_id_by_name(afe, sink->name) == 605 get_i2s_id_by_name(afe, source->name)) 606 return (i2s_priv->mclk_rate > 0) ? 1 : 0; 607 608 /* check if share i2s need mclk */ 609 if (i2s_priv->share_i2s_id < 0) 610 return 0; 611 612 if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name)) 613 return (i2s_priv->mclk_rate > 0) ? 1 : 0; 614 615 return 0; 616 } 617 618 static int mtk_afe_mclk_apll_connect(struct snd_soc_dapm_widget *source, 619 struct snd_soc_dapm_widget *sink) 620 { 621 struct snd_soc_dapm_widget *w = sink; 622 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 623 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 624 struct mtk_afe_i2s_priv *i2s_priv; 625 int cur_apll; 626 627 i2s_priv = get_i2s_priv_by_name(afe, w->name); 628 /* which apll */ 629 cur_apll = mt8186_get_apll_by_name(afe, source->name); 630 631 return (i2s_priv->mclk_apll == cur_apll) ? 1 : 0; 632 } 633 634 static const struct snd_soc_dapm_route mtk_dai_i2s_routes[] = { 635 {"Connsys I2S", NULL, "CONNSYS"}, 636 637 /* i2s0 */ 638 {"I2S0", NULL, "I2S0_EN"}, 639 {"I2S0", NULL, "I2S1_EN", mtk_afe_i2s_share_connect}, 640 {"I2S0", NULL, "I2S2_EN", mtk_afe_i2s_share_connect}, 641 {"I2S0", NULL, "I2S3_EN", mtk_afe_i2s_share_connect}, 642 643 {"I2S0", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 644 {"I2S0", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 645 {"I2S0", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 646 {"I2S0", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 647 {I2S0_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 648 {I2S0_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 649 650 {"I2S0", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 651 {"I2S0", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 652 {"I2S0", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 653 {"I2S0", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 654 {I2S0_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 655 {I2S0_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 656 657 /* i2s1 */ 658 {"I2S1_CH1", "DL1_CH1 Switch", "DL1"}, 659 {"I2S1_CH2", "DL1_CH2 Switch", "DL1"}, 660 661 {"I2S1_CH1", "DL2_CH1 Switch", "DL2"}, 662 {"I2S1_CH2", "DL2_CH2 Switch", "DL2"}, 663 664 {"I2S1_CH1", "DL3_CH1 Switch", "DL3"}, 665 {"I2S1_CH2", "DL3_CH2 Switch", "DL3"}, 666 667 {"I2S1_CH1", "DL12_CH1 Switch", "DL12"}, 668 {"I2S1_CH2", "DL12_CH2 Switch", "DL12"}, 669 670 {"I2S1_CH1", "DL12_CH3 Switch", "DL12"}, 671 {"I2S1_CH2", "DL12_CH4 Switch", "DL12"}, 672 673 {"I2S1_CH1", "DL6_CH1 Switch", "DL6"}, 674 {"I2S1_CH2", "DL6_CH2 Switch", "DL6"}, 675 676 {"I2S1_CH1", "DL4_CH1 Switch", "DL4"}, 677 {"I2S1_CH2", "DL4_CH2 Switch", "DL4"}, 678 679 {"I2S1_CH1", "DL5_CH1 Switch", "DL5"}, 680 {"I2S1_CH2", "DL5_CH2 Switch", "DL5"}, 681 682 {"I2S1_CH1", "DL8_CH1 Switch", "DL8"}, 683 {"I2S1_CH2", "DL8_CH2 Switch", "DL8"}, 684 685 {"I2S1", NULL, "I2S1_CH1"}, 686 {"I2S1", NULL, "I2S1_CH2"}, 687 688 {"I2S1", NULL, "I2S0_EN", mtk_afe_i2s_share_connect}, 689 {"I2S1", NULL, "I2S1_EN"}, 690 {"I2S1", NULL, "I2S2_EN", mtk_afe_i2s_share_connect}, 691 {"I2S1", NULL, "I2S3_EN", mtk_afe_i2s_share_connect}, 692 693 {"I2S1", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 694 {"I2S1", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 695 {"I2S1", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 696 {"I2S1", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 697 {I2S1_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 698 {I2S1_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 699 700 {"I2S1", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 701 {"I2S1", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 702 {"I2S1", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 703 {"I2S1", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 704 {I2S1_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 705 {I2S1_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 706 707 /* i2s2 */ 708 {"I2S2", NULL, "I2S0_EN", mtk_afe_i2s_share_connect}, 709 {"I2S2", NULL, "I2S1_EN", mtk_afe_i2s_share_connect}, 710 {"I2S2", NULL, "I2S2_EN"}, 711 {"I2S2", NULL, "I2S3_EN", mtk_afe_i2s_share_connect}, 712 713 {"I2S2", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 714 {"I2S2", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 715 {"I2S2", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 716 {"I2S2", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 717 {I2S2_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 718 {I2S2_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 719 720 {"I2S2", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 721 {"I2S2", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 722 {"I2S2", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 723 {"I2S2", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 724 {I2S2_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 725 {I2S2_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 726 727 /* i2s3 */ 728 {"I2S3_CH1", "DL1_CH1 Switch", "DL1"}, 729 {"I2S3_CH2", "DL1_CH2 Switch", "DL1"}, 730 731 {"I2S3_CH1", "DL2_CH1 Switch", "DL2"}, 732 {"I2S3_CH2", "DL2_CH2 Switch", "DL2"}, 733 734 {"I2S3_CH1", "DL3_CH1 Switch", "DL3"}, 735 {"I2S3_CH2", "DL3_CH2 Switch", "DL3"}, 736 737 {"I2S3_CH1", "DL12_CH1 Switch", "DL12"}, 738 {"I2S3_CH2", "DL12_CH2 Switch", "DL12"}, 739 740 {"I2S3_CH1", "DL12_CH3 Switch", "DL12"}, 741 {"I2S3_CH2", "DL12_CH4 Switch", "DL12"}, 742 743 {"I2S3_CH1", "DL6_CH1 Switch", "DL6"}, 744 {"I2S3_CH2", "DL6_CH2 Switch", "DL6"}, 745 746 {"I2S3_CH1", "DL4_CH1 Switch", "DL4"}, 747 {"I2S3_CH2", "DL4_CH2 Switch", "DL4"}, 748 749 {"I2S3_CH1", "DL5_CH1 Switch", "DL5"}, 750 {"I2S3_CH2", "DL5_CH2 Switch", "DL5"}, 751 752 {"I2S3_CH1", "DL8_CH1 Switch", "DL8"}, 753 {"I2S3_CH2", "DL8_CH2 Switch", "DL8"}, 754 755 {"I2S3", NULL, "I2S3_CH1"}, 756 {"I2S3", NULL, "I2S3_CH2"}, 757 758 {"I2S3", NULL, "I2S0_EN", mtk_afe_i2s_share_connect}, 759 {"I2S3", NULL, "I2S1_EN", mtk_afe_i2s_share_connect}, 760 {"I2S3", NULL, "I2S2_EN", mtk_afe_i2s_share_connect}, 761 {"I2S3", NULL, "I2S3_EN"}, 762 763 {"I2S3", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 764 {"I2S3", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 765 {"I2S3", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 766 {"I2S3", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 767 {I2S3_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 768 {I2S3_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 769 770 {"I2S3", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 771 {"I2S3", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 772 {"I2S3", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 773 {"I2S3", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 774 {I2S3_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 775 {I2S3_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 776 777 /* allow i2s on without codec on */ 778 {"I2S0", NULL, "I2S0_In_Mux"}, 779 {"I2S0_In_Mux", "Dummy_Widget", "I2S_DUMMY_IN"}, 780 781 {"I2S1_Out_Mux", "Dummy_Widget", "I2S1"}, 782 {"I2S_DUMMY_OUT", NULL, "I2S1_Out_Mux"}, 783 784 {"I2S2", NULL, "I2S2_In_Mux"}, 785 {"I2S2_In_Mux", "Dummy_Widget", "I2S_DUMMY_IN"}, 786 787 {"I2S3_Out_Mux", "Dummy_Widget", "I2S3"}, 788 {"I2S_DUMMY_OUT", NULL, "I2S3_Out_Mux"}, 789 790 /* i2s in lpbk */ 791 {"I2S0_Lpbk_Mux", "Lpbk", "I2S3"}, 792 {"I2S2_Lpbk_Mux", "Lpbk", "I2S1"}, 793 {"I2S0", NULL, "I2S0_Lpbk_Mux"}, 794 {"I2S2", NULL, "I2S2_Lpbk_Mux"}, 795 }; 796 797 /* dai ops */ 798 static int mtk_dai_connsys_i2s_hw_params(struct snd_pcm_substream *substream, 799 struct snd_pcm_hw_params *params, 800 struct snd_soc_dai *dai) 801 { 802 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 803 unsigned int rate = params_rate(params); 804 unsigned int rate_reg = mt8186_rate_transform(afe->dev, 805 rate, dai->id); 806 unsigned int i2s_con = 0; 807 808 dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n", 809 __func__, dai->id, substream->stream, rate); 810 811 /* non-inverse, i2s mode, slave, 16bits, from connsys */ 812 i2s_con |= 0 << INV_PAD_CTRL_SFT; 813 i2s_con |= I2S_FMT_I2S << I2S_FMT_SFT; 814 i2s_con |= 1 << I2S_SRC_SFT; 815 i2s_con |= get_i2s_wlen(SNDRV_PCM_FORMAT_S16_LE) << I2S_WLEN_SFT; 816 i2s_con |= 0 << I2SIN_PAD_SEL_SFT; 817 regmap_write(afe->regmap, AFE_CONNSYS_I2S_CON, i2s_con); 818 819 /* use asrc */ 820 regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON, 821 I2S_BYPSRC_MASK_SFT, 0); 822 823 /* slave mode, set i2s for asrc */ 824 regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON, 825 I2S_MODE_MASK_SFT, rate_reg << I2S_MODE_SFT); 826 827 if (rate == 44100) 828 regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x1b9000); 829 else if (rate == 32000) 830 regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x140000); 831 else 832 regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x1e0000); 833 834 /* Calibration setting */ 835 regmap_write(afe->regmap, AFE_ASRC_2CH_CON4, 0x140000); 836 regmap_write(afe->regmap, AFE_ASRC_2CH_CON9, 0x36000); 837 regmap_write(afe->regmap, AFE_ASRC_2CH_CON10, 0x2fc00); 838 regmap_write(afe->regmap, AFE_ASRC_2CH_CON6, 0x7ef4); 839 regmap_write(afe->regmap, AFE_ASRC_2CH_CON5, 0xff5986); 840 841 /* 0:Stereo 1:Mono */ 842 regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON2, 843 CHSET_IS_MONO_MASK_SFT, 0); 844 845 return 0; 846 } 847 848 static int mtk_dai_connsys_i2s_trigger(struct snd_pcm_substream *substream, 849 int cmd, struct snd_soc_dai *dai) 850 { 851 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 852 struct mt8186_afe_private *afe_priv = afe->platform_priv; 853 854 dev_dbg(afe->dev, "%s(), cmd %d, stream %d\n", 855 __func__, cmd, substream->stream); 856 857 switch (cmd) { 858 case SNDRV_PCM_TRIGGER_START: 859 case SNDRV_PCM_TRIGGER_RESUME: 860 /* i2s enable */ 861 regmap_update_bits(afe->regmap, 862 AFE_CONNSYS_I2S_CON, 863 I2S_EN_MASK_SFT, 864 BIT(I2S_EN_SFT)); 865 866 /* calibrator enable */ 867 regmap_update_bits(afe->regmap, 868 AFE_ASRC_2CH_CON5, 869 CALI_EN_MASK_SFT, 870 BIT(CALI_EN_SFT)); 871 872 /* asrc enable */ 873 regmap_update_bits(afe->regmap, 874 AFE_ASRC_2CH_CON0, 875 CON0_CHSET_STR_CLR_MASK_SFT, 876 BIT(CON0_CHSET_STR_CLR_SFT)); 877 regmap_update_bits(afe->regmap, 878 AFE_ASRC_2CH_CON0, 879 CON0_ASM_ON_MASK_SFT, 880 BIT(CON0_ASM_ON_SFT)); 881 882 afe_priv->dai_on[dai->id] = true; 883 return 0; 884 case SNDRV_PCM_TRIGGER_STOP: 885 case SNDRV_PCM_TRIGGER_SUSPEND: 886 regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON0, 887 CON0_ASM_ON_MASK_SFT, 0); 888 regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON5, 889 CALI_EN_MASK_SFT, 0); 890 891 /* i2s disable */ 892 regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON, 893 I2S_EN_MASK_SFT, 0); 894 895 /* bypass asrc */ 896 regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON, 897 I2S_BYPSRC_MASK_SFT, BIT(I2S_BYPSRC_SFT)); 898 899 afe_priv->dai_on[dai->id] = false; 900 return 0; 901 default: 902 return -EINVAL; 903 } 904 return 0; 905 } 906 907 static const struct snd_soc_dai_ops mtk_dai_connsys_i2s_ops = { 908 .hw_params = mtk_dai_connsys_i2s_hw_params, 909 .trigger = mtk_dai_connsys_i2s_trigger, 910 }; 911 912 /* i2s */ 913 static int mtk_dai_i2s_config(struct mtk_base_afe *afe, 914 struct snd_pcm_hw_params *params, 915 int i2s_id) 916 { 917 struct mt8186_afe_private *afe_priv = afe->platform_priv; 918 struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[i2s_id]; 919 920 unsigned int rate = params_rate(params); 921 unsigned int rate_reg = mt8186_rate_transform(afe->dev, 922 rate, i2s_id); 923 snd_pcm_format_t format = params_format(params); 924 unsigned int i2s_con = 0; 925 int ret; 926 927 dev_dbg(afe->dev, "%s(), id %d, rate %d, format %d\n", 928 __func__, i2s_id, rate, format); 929 930 i2s_priv->rate = rate; 931 932 switch (i2s_id) { 933 case MT8186_DAI_I2S_0: 934 i2s_con = I2S_IN_PAD_IO_MUX << I2SIN_PAD_SEL_SFT; 935 i2s_con |= rate_reg << I2S_OUT_MODE_SFT; 936 i2s_con |= I2S_FMT_I2S << I2S_FMT_SFT; 937 i2s_con |= get_i2s_wlen(format) << I2S_WLEN_SFT; 938 regmap_update_bits(afe->regmap, AFE_I2S_CON, 939 0xffffeffa, i2s_con); 940 break; 941 case MT8186_DAI_I2S_1: 942 i2s_con = I2S1_SEL_O28_O29 << I2S2_SEL_O03_O04_SFT; 943 i2s_con |= rate_reg << I2S2_OUT_MODE_SFT; 944 i2s_con |= I2S_FMT_I2S << I2S2_FMT_SFT; 945 i2s_con |= get_i2s_wlen(format) << I2S2_WLEN_SFT; 946 regmap_update_bits(afe->regmap, AFE_I2S_CON1, 947 0xffffeffa, i2s_con); 948 break; 949 case MT8186_DAI_I2S_2: 950 i2s_con = 8 << I2S3_UPDATE_WORD_SFT; 951 i2s_con |= rate_reg << I2S3_OUT_MODE_SFT; 952 i2s_con |= I2S_FMT_I2S << I2S3_FMT_SFT; 953 i2s_con |= get_i2s_wlen(format) << I2S3_WLEN_SFT; 954 regmap_update_bits(afe->regmap, AFE_I2S_CON2, 955 0xffffeffa, i2s_con); 956 break; 957 case MT8186_DAI_I2S_3: 958 i2s_con = rate_reg << I2S4_OUT_MODE_SFT; 959 i2s_con |= I2S_FMT_I2S << I2S4_FMT_SFT; 960 i2s_con |= get_i2s_wlen(format) << I2S4_WLEN_SFT; 961 regmap_update_bits(afe->regmap, AFE_I2S_CON3, 962 0xffffeffa, i2s_con); 963 break; 964 default: 965 dev_err(afe->dev, "%s(), id %d not support\n", 966 __func__, i2s_id); 967 return -EINVAL; 968 } 969 970 /* set share i2s */ 971 if (i2s_priv && i2s_priv->share_i2s_id >= 0) { 972 ret = mtk_dai_i2s_config(afe, params, i2s_priv->share_i2s_id); 973 if (ret) 974 return ret; 975 } 976 977 return 0; 978 } 979 980 static int mtk_dai_i2s_hw_params(struct snd_pcm_substream *substream, 981 struct snd_pcm_hw_params *params, 982 struct snd_soc_dai *dai) 983 { 984 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 985 986 return mtk_dai_i2s_config(afe, params, dai->id); 987 } 988 989 static int mtk_dai_i2s_set_sysclk(struct snd_soc_dai *dai, 990 int clk_id, unsigned int freq, int dir) 991 { 992 struct mtk_base_afe *afe = dev_get_drvdata(dai->dev); 993 struct mt8186_afe_private *afe_priv = afe->platform_priv; 994 struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[dai->id]; 995 int apll; 996 int apll_rate; 997 998 if (dir != SND_SOC_CLOCK_OUT) { 999 dev_err(afe->dev, "%s(), dir != SND_SOC_CLOCK_OUT", __func__); 1000 return -EINVAL; 1001 } 1002 1003 dev_dbg(afe->dev, "%s(), freq %d\n", __func__, freq); 1004 1005 apll = mt8186_get_apll_by_rate(afe, freq); 1006 apll_rate = mt8186_get_apll_rate(afe, apll); 1007 1008 if (freq > apll_rate) { 1009 dev_err(afe->dev, "%s(), freq > apll rate", __func__); 1010 return -EINVAL; 1011 } 1012 1013 if (apll_rate % freq != 0) { 1014 dev_err(afe->dev, "%s(), APLL cannot generate freq Hz", __func__); 1015 return -EINVAL; 1016 } 1017 1018 i2s_priv->mclk_rate = freq; 1019 i2s_priv->mclk_apll = apll; 1020 1021 if (i2s_priv->share_i2s_id > 0) { 1022 struct mtk_afe_i2s_priv *share_i2s_priv; 1023 1024 share_i2s_priv = afe_priv->dai_priv[i2s_priv->share_i2s_id]; 1025 if (!share_i2s_priv) { 1026 dev_err(afe->dev, "%s(), share_i2s_priv == NULL", __func__); 1027 return -EINVAL; 1028 } 1029 1030 share_i2s_priv->mclk_rate = i2s_priv->mclk_rate; 1031 share_i2s_priv->mclk_apll = i2s_priv->mclk_apll; 1032 } 1033 1034 return 0; 1035 } 1036 1037 static const struct snd_soc_dai_ops mtk_dai_i2s_ops = { 1038 .hw_params = mtk_dai_i2s_hw_params, 1039 .set_sysclk = mtk_dai_i2s_set_sysclk, 1040 }; 1041 1042 /* dai driver */ 1043 #define MTK_CONNSYS_I2S_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 1044 1045 #define MTK_I2S_RATES (SNDRV_PCM_RATE_8000_48000 |\ 1046 SNDRV_PCM_RATE_88200 |\ 1047 SNDRV_PCM_RATE_96000 |\ 1048 SNDRV_PCM_RATE_176400 |\ 1049 SNDRV_PCM_RATE_192000) 1050 1051 #define MTK_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1052 SNDRV_PCM_FMTBIT_S24_LE |\ 1053 SNDRV_PCM_FMTBIT_S32_LE) 1054 1055 static struct snd_soc_dai_driver mtk_dai_i2s_driver[] = { 1056 { 1057 .name = "CONNSYS_I2S", 1058 .id = MT8186_DAI_CONNSYS_I2S, 1059 .capture = { 1060 .stream_name = "Connsys I2S", 1061 .channels_min = 1, 1062 .channels_max = 2, 1063 .rates = MTK_CONNSYS_I2S_RATES, 1064 .formats = MTK_I2S_FORMATS, 1065 }, 1066 .ops = &mtk_dai_connsys_i2s_ops, 1067 }, 1068 { 1069 .name = "I2S0", 1070 .id = MT8186_DAI_I2S_0, 1071 .capture = { 1072 .stream_name = "I2S0", 1073 .channels_min = 1, 1074 .channels_max = 2, 1075 .rates = MTK_I2S_RATES, 1076 .formats = MTK_I2S_FORMATS, 1077 }, 1078 .ops = &mtk_dai_i2s_ops, 1079 }, 1080 { 1081 .name = "I2S1", 1082 .id = MT8186_DAI_I2S_1, 1083 .playback = { 1084 .stream_name = "I2S1", 1085 .channels_min = 1, 1086 .channels_max = 2, 1087 .rates = MTK_I2S_RATES, 1088 .formats = MTK_I2S_FORMATS, 1089 }, 1090 .ops = &mtk_dai_i2s_ops, 1091 }, 1092 { 1093 .name = "I2S2", 1094 .id = MT8186_DAI_I2S_2, 1095 .capture = { 1096 .stream_name = "I2S2", 1097 .channels_min = 1, 1098 .channels_max = 2, 1099 .rates = MTK_I2S_RATES, 1100 .formats = MTK_I2S_FORMATS, 1101 }, 1102 .ops = &mtk_dai_i2s_ops, 1103 }, 1104 { 1105 .name = "I2S3", 1106 .id = MT8186_DAI_I2S_3, 1107 .playback = { 1108 .stream_name = "I2S3", 1109 .channels_min = 1, 1110 .channels_max = 2, 1111 .rates = MTK_I2S_RATES, 1112 .formats = MTK_I2S_FORMATS, 1113 }, 1114 .ops = &mtk_dai_i2s_ops, 1115 } 1116 }; 1117 1118 /* this enum is merely for mtk_afe_i2s_priv declare */ 1119 enum { 1120 DAI_I2S0 = 0, 1121 DAI_I2S1, 1122 DAI_I2S2, 1123 DAI_I2S3, 1124 DAI_I2S_NUM, 1125 }; 1126 1127 static const struct mtk_afe_i2s_priv mt8186_i2s_priv[DAI_I2S_NUM] = { 1128 [DAI_I2S0] = { 1129 .id = MT8186_DAI_I2S_0, 1130 .mclk_id = MT8186_I2S0_MCK, 1131 .share_property_name = "i2s0-share", 1132 .share_i2s_id = -1, 1133 }, 1134 [DAI_I2S1] = { 1135 .id = MT8186_DAI_I2S_1, 1136 .mclk_id = MT8186_I2S1_MCK, 1137 .share_property_name = "i2s1-share", 1138 .share_i2s_id = -1, 1139 }, 1140 [DAI_I2S2] = { 1141 .id = MT8186_DAI_I2S_2, 1142 .mclk_id = MT8186_I2S2_MCK, 1143 .share_property_name = "i2s2-share", 1144 .share_i2s_id = -1, 1145 }, 1146 [DAI_I2S3] = { 1147 .id = MT8186_DAI_I2S_3, 1148 /* clock gate naming is hf_faud_i2s4_m_ck*/ 1149 .mclk_id = MT8186_I2S4_MCK, 1150 .share_property_name = "i2s3-share", 1151 .share_i2s_id = -1, 1152 } 1153 }; 1154 1155 static int mt8186_dai_i2s_get_share(struct mtk_base_afe *afe) 1156 { 1157 struct mt8186_afe_private *afe_priv = afe->platform_priv; 1158 const struct device_node *of_node = afe->dev->of_node; 1159 const char *of_str; 1160 const char *property_name; 1161 struct mtk_afe_i2s_priv *i2s_priv; 1162 int i; 1163 1164 for (i = 0; i < DAI_I2S_NUM; i++) { 1165 i2s_priv = afe_priv->dai_priv[mt8186_i2s_priv[i].id]; 1166 property_name = mt8186_i2s_priv[i].share_property_name; 1167 if (of_property_read_string(of_node, property_name, &of_str)) 1168 continue; 1169 i2s_priv->share_i2s_id = get_i2s_id_by_name(afe, of_str); 1170 } 1171 1172 return 0; 1173 } 1174 1175 static int mt8186_dai_i2s_set_priv(struct mtk_base_afe *afe) 1176 { 1177 int i; 1178 int ret; 1179 1180 for (i = 0; i < DAI_I2S_NUM; i++) { 1181 ret = mt8186_dai_set_priv(afe, mt8186_i2s_priv[i].id, 1182 sizeof(struct mtk_afe_i2s_priv), 1183 &mt8186_i2s_priv[i]); 1184 if (ret) 1185 return ret; 1186 } 1187 1188 return 0; 1189 } 1190 1191 int mt8186_dai_i2s_register(struct mtk_base_afe *afe) 1192 { 1193 struct mtk_base_afe_dai *dai; 1194 int ret; 1195 1196 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 1197 if (!dai) 1198 return -ENOMEM; 1199 1200 list_add(&dai->list, &afe->sub_dais); 1201 1202 dai->dai_drivers = mtk_dai_i2s_driver; 1203 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_i2s_driver); 1204 1205 dai->controls = mtk_dai_i2s_controls; 1206 dai->num_controls = ARRAY_SIZE(mtk_dai_i2s_controls); 1207 dai->dapm_widgets = mtk_dai_i2s_widgets; 1208 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_i2s_widgets); 1209 dai->dapm_routes = mtk_dai_i2s_routes; 1210 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_i2s_routes); 1211 1212 /* set all dai i2s private data */ 1213 ret = mt8186_dai_i2s_set_priv(afe); 1214 if (ret) 1215 return ret; 1216 1217 /* parse share i2s */ 1218 ret = mt8186_dai_i2s_get_share(afe); 1219 if (ret) 1220 return ret; 1221 1222 return 0; 1223 } 1224