1*58949aa3SJiaxin Yu /* SPDX-License-Identifier: GPL-2.0 2*58949aa3SJiaxin Yu * 3*58949aa3SJiaxin Yu * mt8186-audsys-clkid.h -- Mediatek 8186 audsys clock id definition 4*58949aa3SJiaxin Yu * 5*58949aa3SJiaxin Yu * Copyright (c) 2022 MediaTek Inc. 6*58949aa3SJiaxin Yu * Author: Jiaxin Yu <jiaxin.yu@mediatek.com> 7*58949aa3SJiaxin Yu */ 8*58949aa3SJiaxin Yu 9*58949aa3SJiaxin Yu #ifndef _MT8186_AUDSYS_CLKID_H_ 10*58949aa3SJiaxin Yu #define _MT8186_AUDSYS_CLKID_H_ 11*58949aa3SJiaxin Yu 12*58949aa3SJiaxin Yu enum{ 13*58949aa3SJiaxin Yu CLK_AUD_AFE, 14*58949aa3SJiaxin Yu CLK_AUD_22M, 15*58949aa3SJiaxin Yu CLK_AUD_24M, 16*58949aa3SJiaxin Yu CLK_AUD_APLL2_TUNER, 17*58949aa3SJiaxin Yu CLK_AUD_APLL_TUNER, 18*58949aa3SJiaxin Yu CLK_AUD_TDM, 19*58949aa3SJiaxin Yu CLK_AUD_ADC, 20*58949aa3SJiaxin Yu CLK_AUD_DAC, 21*58949aa3SJiaxin Yu CLK_AUD_DAC_PREDIS, 22*58949aa3SJiaxin Yu CLK_AUD_TML, 23*58949aa3SJiaxin Yu CLK_AUD_NLE, 24*58949aa3SJiaxin Yu CLK_AUD_I2S1_BCLK, 25*58949aa3SJiaxin Yu CLK_AUD_I2S2_BCLK, 26*58949aa3SJiaxin Yu CLK_AUD_I2S3_BCLK, 27*58949aa3SJiaxin Yu CLK_AUD_I2S4_BCLK, 28*58949aa3SJiaxin Yu CLK_AUD_CONNSYS_I2S_ASRC, 29*58949aa3SJiaxin Yu CLK_AUD_GENERAL1_ASRC, 30*58949aa3SJiaxin Yu CLK_AUD_GENERAL2_ASRC, 31*58949aa3SJiaxin Yu CLK_AUD_DAC_HIRES, 32*58949aa3SJiaxin Yu CLK_AUD_ADC_HIRES, 33*58949aa3SJiaxin Yu CLK_AUD_ADC_HIRES_TML, 34*58949aa3SJiaxin Yu CLK_AUD_ADDA6_ADC, 35*58949aa3SJiaxin Yu CLK_AUD_ADDA6_ADC_HIRES, 36*58949aa3SJiaxin Yu CLK_AUD_3RD_DAC, 37*58949aa3SJiaxin Yu CLK_AUD_3RD_DAC_PREDIS, 38*58949aa3SJiaxin Yu CLK_AUD_3RD_DAC_TML, 39*58949aa3SJiaxin Yu CLK_AUD_3RD_DAC_HIRES, 40*58949aa3SJiaxin Yu CLK_AUD_ETDM_IN1_BCLK, 41*58949aa3SJiaxin Yu CLK_AUD_ETDM_OUT1_BCLK, 42*58949aa3SJiaxin Yu CLK_AUD_NR_CLK, 43*58949aa3SJiaxin Yu }; 44*58949aa3SJiaxin Yu 45*58949aa3SJiaxin Yu #endif 46