1*58949aa3SJiaxin Yu /* SPDX-License-Identifier: GPL-2.0 2*58949aa3SJiaxin Yu * 3*58949aa3SJiaxin Yu * mt8186-audsys-clk.h -- Mediatek 8186 audsys clock definition 4*58949aa3SJiaxin Yu * 5*58949aa3SJiaxin Yu * Copyright (c) 2022 MediaTek Inc. 6*58949aa3SJiaxin Yu * Author: Trevor Wu <trevor.wu@mediatek.com> 7*58949aa3SJiaxin Yu */ 8*58949aa3SJiaxin Yu 9*58949aa3SJiaxin Yu #ifndef _MT8186_AUDSYS_CLK_H_ 10*58949aa3SJiaxin Yu #define _MT8186_AUDSYS_CLK_H_ 11*58949aa3SJiaxin Yu 12*58949aa3SJiaxin Yu int mt8186_audsys_clk_register(struct mtk_base_afe *afe); 13*58949aa3SJiaxin Yu 14*58949aa3SJiaxin Yu #endif 15