1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * mt8186-afe-clk.h  --  Mediatek 8186 afe clock ctrl definition
4  *
5  * Copyright (c) 2022 MediaTek Inc.
6  * Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
7  */
8 
9 #ifndef _MT8186_AFE_CLOCK_CTRL_H_
10 #define _MT8186_AFE_CLOCK_CTRL_H_
11 
12 #define PERI_BUS_DCM_CTRL	0x74
13 
14 /* APLL */
15 #define APLL1_W_NAME "APLL1"
16 #define APLL2_W_NAME "APLL2"
17 enum {
18 	MT8186_APLL1 = 0,
19 	MT8186_APLL2,
20 };
21 
22 enum {
23 	CLK_AFE = 0,
24 	CLK_DAC,
25 	CLK_DAC_PREDIS,
26 	CLK_ADC,
27 	CLK_TML,
28 	CLK_APLL22M,
29 	CLK_APLL24M,
30 	CLK_APLL1_TUNER,
31 	CLK_APLL2_TUNER,
32 	CLK_TDM,
33 	CLK_NLE,
34 	CLK_DAC_HIRES,
35 	CLK_ADC_HIRES,
36 	CLK_I2S1_BCLK,
37 	CLK_I2S2_BCLK,
38 	CLK_I2S3_BCLK,
39 	CLK_I2S4_BCLK,
40 	CLK_CONNSYS_I2S_ASRC,
41 	CLK_GENERAL1_ASRC,
42 	CLK_GENERAL2_ASRC,
43 	CLK_ADC_HIRES_TML,
44 	CLK_ADDA6_ADC,
45 	CLK_ADDA6_ADC_HIRES,
46 	CLK_3RD_DAC,
47 	CLK_3RD_DAC_PREDIS,
48 	CLK_3RD_DAC_TML,
49 	CLK_3RD_DAC_HIRES,
50 	CLK_ETDM_IN1_BCLK,
51 	CLK_ETDM_OUT1_BCLK,
52 	CLK_INFRA_SYS_AUDIO,
53 	CLK_INFRA_AUDIO_26M,
54 	CLK_MUX_AUDIO,
55 	CLK_MUX_AUDIOINTBUS,
56 	CLK_TOP_MAINPLL_D2_D4,
57 	/* apll related mux */
58 	CLK_TOP_MUX_AUD_1,
59 	CLK_TOP_APLL1_CK,
60 	CLK_TOP_MUX_AUD_2,
61 	CLK_TOP_APLL2_CK,
62 	CLK_TOP_MUX_AUD_ENG1,
63 	CLK_TOP_APLL1_D8,
64 	CLK_TOP_MUX_AUD_ENG2,
65 	CLK_TOP_APLL2_D8,
66 	CLK_TOP_MUX_AUDIO_H,
67 	CLK_TOP_I2S0_M_SEL,
68 	CLK_TOP_I2S1_M_SEL,
69 	CLK_TOP_I2S2_M_SEL,
70 	CLK_TOP_I2S4_M_SEL,
71 	CLK_TOP_TDM_M_SEL,
72 	CLK_TOP_APLL12_DIV0,
73 	CLK_TOP_APLL12_DIV1,
74 	CLK_TOP_APLL12_DIV2,
75 	CLK_TOP_APLL12_DIV4,
76 	CLK_TOP_APLL12_DIV_TDM,
77 	CLK_CLK26M,
78 	CLK_NUM
79 };
80 
81 struct mtk_base_afe;
82 int mt8186_set_audio_int_bus_parent(struct mtk_base_afe *afe, int clk_id);
83 int mt8186_init_clock(struct mtk_base_afe *afe);
84 void mt8186_deinit_clock(void *priv);
85 int mt8186_afe_enable_cgs(struct mtk_base_afe *afe);
86 void mt8186_afe_disable_cgs(struct mtk_base_afe *afe);
87 int mt8186_afe_enable_clock(struct mtk_base_afe *afe);
88 void mt8186_afe_disable_clock(struct mtk_base_afe *afe);
89 int mt8186_afe_suspend_clock(struct mtk_base_afe *afe);
90 int mt8186_afe_resume_clock(struct mtk_base_afe *afe);
91 
92 int mt8186_apll1_enable(struct mtk_base_afe *afe);
93 void mt8186_apll1_disable(struct mtk_base_afe *afe);
94 
95 int mt8186_apll2_enable(struct mtk_base_afe *afe);
96 void mt8186_apll2_disable(struct mtk_base_afe *afe);
97 
98 int mt8186_get_apll_rate(struct mtk_base_afe *afe, int apll);
99 int mt8186_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
100 int mt8186_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
101 
102 /* these will be replaced by using CCF */
103 int mt8186_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate);
104 void mt8186_mck_disable(struct mtk_base_afe *afe, int mck_id);
105 
106 #endif
107