1*55b423d5SJiaxin Yu /* SPDX-License-Identifier: GPL-2.0 2*55b423d5SJiaxin Yu * 3*55b423d5SJiaxin Yu * mt8186-afe-clk.h -- Mediatek 8186 afe clock ctrl definition 4*55b423d5SJiaxin Yu * 5*55b423d5SJiaxin Yu * Copyright (c) 2022 MediaTek Inc. 6*55b423d5SJiaxin Yu * Author: Jiaxin Yu <jiaxin.yu@mediatek.com> 7*55b423d5SJiaxin Yu */ 8*55b423d5SJiaxin Yu 9*55b423d5SJiaxin Yu #ifndef _MT8186_AFE_CLOCK_CTRL_H_ 10*55b423d5SJiaxin Yu #define _MT8186_AFE_CLOCK_CTRL_H_ 11*55b423d5SJiaxin Yu 12*55b423d5SJiaxin Yu #define PERI_BUS_DCM_CTRL 0x74 13*55b423d5SJiaxin Yu 14*55b423d5SJiaxin Yu /* APLL */ 15*55b423d5SJiaxin Yu #define APLL1_W_NAME "APLL1" 16*55b423d5SJiaxin Yu #define APLL2_W_NAME "APLL2" 17*55b423d5SJiaxin Yu enum { 18*55b423d5SJiaxin Yu MT8186_APLL1 = 0, 19*55b423d5SJiaxin Yu MT8186_APLL2, 20*55b423d5SJiaxin Yu }; 21*55b423d5SJiaxin Yu 22*55b423d5SJiaxin Yu enum { 23*55b423d5SJiaxin Yu CLK_AFE = 0, 24*55b423d5SJiaxin Yu CLK_DAC, 25*55b423d5SJiaxin Yu CLK_DAC_PREDIS, 26*55b423d5SJiaxin Yu CLK_ADC, 27*55b423d5SJiaxin Yu CLK_TML, 28*55b423d5SJiaxin Yu CLK_APLL22M, 29*55b423d5SJiaxin Yu CLK_APLL24M, 30*55b423d5SJiaxin Yu CLK_APLL1_TUNER, 31*55b423d5SJiaxin Yu CLK_APLL2_TUNER, 32*55b423d5SJiaxin Yu CLK_TDM, 33*55b423d5SJiaxin Yu CLK_NLE, 34*55b423d5SJiaxin Yu CLK_DAC_HIRES, 35*55b423d5SJiaxin Yu CLK_ADC_HIRES, 36*55b423d5SJiaxin Yu CLK_I2S1_BCLK, 37*55b423d5SJiaxin Yu CLK_I2S2_BCLK, 38*55b423d5SJiaxin Yu CLK_I2S3_BCLK, 39*55b423d5SJiaxin Yu CLK_I2S4_BCLK, 40*55b423d5SJiaxin Yu CLK_CONNSYS_I2S_ASRC, 41*55b423d5SJiaxin Yu CLK_GENERAL1_ASRC, 42*55b423d5SJiaxin Yu CLK_GENERAL2_ASRC, 43*55b423d5SJiaxin Yu CLK_ADC_HIRES_TML, 44*55b423d5SJiaxin Yu CLK_ADDA6_ADC, 45*55b423d5SJiaxin Yu CLK_ADDA6_ADC_HIRES, 46*55b423d5SJiaxin Yu CLK_3RD_DAC, 47*55b423d5SJiaxin Yu CLK_3RD_DAC_PREDIS, 48*55b423d5SJiaxin Yu CLK_3RD_DAC_TML, 49*55b423d5SJiaxin Yu CLK_3RD_DAC_HIRES, 50*55b423d5SJiaxin Yu CLK_ETDM_IN1_BCLK, 51*55b423d5SJiaxin Yu CLK_ETDM_OUT1_BCLK, 52*55b423d5SJiaxin Yu CLK_INFRA_SYS_AUDIO, 53*55b423d5SJiaxin Yu CLK_INFRA_AUDIO_26M, 54*55b423d5SJiaxin Yu CLK_MUX_AUDIO, 55*55b423d5SJiaxin Yu CLK_MUX_AUDIOINTBUS, 56*55b423d5SJiaxin Yu CLK_TOP_MAINPLL_D2_D4, 57*55b423d5SJiaxin Yu /* apll related mux */ 58*55b423d5SJiaxin Yu CLK_TOP_MUX_AUD_1, 59*55b423d5SJiaxin Yu CLK_TOP_APLL1_CK, 60*55b423d5SJiaxin Yu CLK_TOP_MUX_AUD_2, 61*55b423d5SJiaxin Yu CLK_TOP_APLL2_CK, 62*55b423d5SJiaxin Yu CLK_TOP_MUX_AUD_ENG1, 63*55b423d5SJiaxin Yu CLK_TOP_APLL1_D8, 64*55b423d5SJiaxin Yu CLK_TOP_MUX_AUD_ENG2, 65*55b423d5SJiaxin Yu CLK_TOP_APLL2_D8, 66*55b423d5SJiaxin Yu CLK_TOP_MUX_AUDIO_H, 67*55b423d5SJiaxin Yu CLK_TOP_I2S0_M_SEL, 68*55b423d5SJiaxin Yu CLK_TOP_I2S1_M_SEL, 69*55b423d5SJiaxin Yu CLK_TOP_I2S2_M_SEL, 70*55b423d5SJiaxin Yu CLK_TOP_I2S4_M_SEL, 71*55b423d5SJiaxin Yu CLK_TOP_TDM_M_SEL, 72*55b423d5SJiaxin Yu CLK_TOP_APLL12_DIV0, 73*55b423d5SJiaxin Yu CLK_TOP_APLL12_DIV1, 74*55b423d5SJiaxin Yu CLK_TOP_APLL12_DIV2, 75*55b423d5SJiaxin Yu CLK_TOP_APLL12_DIV4, 76*55b423d5SJiaxin Yu CLK_TOP_APLL12_DIV_TDM, 77*55b423d5SJiaxin Yu CLK_CLK26M, 78*55b423d5SJiaxin Yu CLK_NUM 79*55b423d5SJiaxin Yu }; 80*55b423d5SJiaxin Yu 81*55b423d5SJiaxin Yu struct mtk_base_afe; 82*55b423d5SJiaxin Yu int mt8186_set_audio_int_bus_parent(struct mtk_base_afe *afe, int clk_id); 83*55b423d5SJiaxin Yu int mt8186_init_clock(struct mtk_base_afe *afe); 84*55b423d5SJiaxin Yu void mt8186_deinit_clock(struct mtk_base_afe *afe); 85*55b423d5SJiaxin Yu int mt8186_afe_enable_cgs(struct mtk_base_afe *afe); 86*55b423d5SJiaxin Yu void mt8186_afe_disable_cgs(struct mtk_base_afe *afe); 87*55b423d5SJiaxin Yu int mt8186_afe_enable_clock(struct mtk_base_afe *afe); 88*55b423d5SJiaxin Yu void mt8186_afe_disable_clock(struct mtk_base_afe *afe); 89*55b423d5SJiaxin Yu int mt8186_afe_suspend_clock(struct mtk_base_afe *afe); 90*55b423d5SJiaxin Yu int mt8186_afe_resume_clock(struct mtk_base_afe *afe); 91*55b423d5SJiaxin Yu 92*55b423d5SJiaxin Yu int mt8186_apll1_enable(struct mtk_base_afe *afe); 93*55b423d5SJiaxin Yu void mt8186_apll1_disable(struct mtk_base_afe *afe); 94*55b423d5SJiaxin Yu 95*55b423d5SJiaxin Yu int mt8186_apll2_enable(struct mtk_base_afe *afe); 96*55b423d5SJiaxin Yu void mt8186_apll2_disable(struct mtk_base_afe *afe); 97*55b423d5SJiaxin Yu 98*55b423d5SJiaxin Yu int mt8186_get_apll_rate(struct mtk_base_afe *afe, int apll); 99*55b423d5SJiaxin Yu int mt8186_get_apll_by_rate(struct mtk_base_afe *afe, int rate); 100*55b423d5SJiaxin Yu int mt8186_get_apll_by_name(struct mtk_base_afe *afe, const char *name); 101*55b423d5SJiaxin Yu 102*55b423d5SJiaxin Yu /* these will be replaced by using CCF */ 103*55b423d5SJiaxin Yu int mt8186_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate); 104*55b423d5SJiaxin Yu void mt8186_mck_disable(struct mtk_base_afe *afe, int mck_id); 105*55b423d5SJiaxin Yu 106*55b423d5SJiaxin Yu #endif 107