1*55b423d5SJiaxin Yu // SPDX-License-Identifier: GPL-2.0 2*55b423d5SJiaxin Yu // 3*55b423d5SJiaxin Yu // mt8186-afe-clk.c -- Mediatek 8186 afe clock ctrl 4*55b423d5SJiaxin Yu // 5*55b423d5SJiaxin Yu // Copyright (c) 2022 MediaTek Inc. 6*55b423d5SJiaxin Yu // Author: Jiaxin Yu <jiaxin.yu@mediatek.com> 7*55b423d5SJiaxin Yu 8*55b423d5SJiaxin Yu #include <linux/clk.h> 9*55b423d5SJiaxin Yu #include <linux/regmap.h> 10*55b423d5SJiaxin Yu #include <linux/mfd/syscon.h> 11*55b423d5SJiaxin Yu 12*55b423d5SJiaxin Yu #include "mt8186-afe-common.h" 13*55b423d5SJiaxin Yu #include "mt8186-afe-clk.h" 14*55b423d5SJiaxin Yu #include "mt8186-audsys-clk.h" 15*55b423d5SJiaxin Yu 16*55b423d5SJiaxin Yu static DEFINE_MUTEX(mutex_request_dram); 17*55b423d5SJiaxin Yu 18*55b423d5SJiaxin Yu static const char *aud_clks[CLK_NUM] = { 19*55b423d5SJiaxin Yu [CLK_AFE] = "aud_afe_clk", 20*55b423d5SJiaxin Yu [CLK_DAC] = "aud_dac_clk", 21*55b423d5SJiaxin Yu [CLK_DAC_PREDIS] = "aud_dac_predis_clk", 22*55b423d5SJiaxin Yu [CLK_ADC] = "aud_adc_clk", 23*55b423d5SJiaxin Yu [CLK_TML] = "aud_tml_clk", 24*55b423d5SJiaxin Yu [CLK_APLL22M] = "aud_apll22m_clk", 25*55b423d5SJiaxin Yu [CLK_APLL24M] = "aud_apll24m_clk", 26*55b423d5SJiaxin Yu [CLK_APLL1_TUNER] = "aud_apll_tuner_clk", 27*55b423d5SJiaxin Yu [CLK_APLL2_TUNER] = "aud_apll2_tuner_clk", 28*55b423d5SJiaxin Yu [CLK_TDM] = "aud_tdm_clk", 29*55b423d5SJiaxin Yu [CLK_NLE] = "aud_nle_clk", 30*55b423d5SJiaxin Yu [CLK_DAC_HIRES] = "aud_dac_hires_clk", 31*55b423d5SJiaxin Yu [CLK_ADC_HIRES] = "aud_adc_hires_clk", 32*55b423d5SJiaxin Yu [CLK_I2S1_BCLK] = "aud_i2s1_bclk", 33*55b423d5SJiaxin Yu [CLK_I2S2_BCLK] = "aud_i2s2_bclk", 34*55b423d5SJiaxin Yu [CLK_I2S3_BCLK] = "aud_i2s3_bclk", 35*55b423d5SJiaxin Yu [CLK_I2S4_BCLK] = "aud_i2s4_bclk", 36*55b423d5SJiaxin Yu [CLK_CONNSYS_I2S_ASRC] = "aud_connsys_i2s_asrc", 37*55b423d5SJiaxin Yu [CLK_GENERAL1_ASRC] = "aud_general1_asrc", 38*55b423d5SJiaxin Yu [CLK_GENERAL2_ASRC] = "aud_general2_asrc", 39*55b423d5SJiaxin Yu [CLK_ADC_HIRES_TML] = "aud_adc_hires_tml", 40*55b423d5SJiaxin Yu [CLK_ADDA6_ADC] = "aud_adda6_adc", 41*55b423d5SJiaxin Yu [CLK_ADDA6_ADC_HIRES] = "aud_adda6_adc_hires", 42*55b423d5SJiaxin Yu [CLK_3RD_DAC] = "aud_3rd_dac", 43*55b423d5SJiaxin Yu [CLK_3RD_DAC_PREDIS] = "aud_3rd_dac_predis", 44*55b423d5SJiaxin Yu [CLK_3RD_DAC_TML] = "aud_3rd_dac_tml", 45*55b423d5SJiaxin Yu [CLK_3RD_DAC_HIRES] = "aud_3rd_dac_hires", 46*55b423d5SJiaxin Yu [CLK_ETDM_IN1_BCLK] = "aud_etdm_in1_bclk", 47*55b423d5SJiaxin Yu [CLK_ETDM_OUT1_BCLK] = "aud_etdm_out1_bclk", 48*55b423d5SJiaxin Yu [CLK_INFRA_SYS_AUDIO] = "aud_infra_clk", 49*55b423d5SJiaxin Yu [CLK_INFRA_AUDIO_26M] = "mtkaif_26m_clk", 50*55b423d5SJiaxin Yu [CLK_MUX_AUDIO] = "top_mux_audio", 51*55b423d5SJiaxin Yu [CLK_MUX_AUDIOINTBUS] = "top_mux_audio_int", 52*55b423d5SJiaxin Yu [CLK_TOP_MAINPLL_D2_D4] = "top_mainpll_d2_d4", 53*55b423d5SJiaxin Yu [CLK_TOP_MUX_AUD_1] = "top_mux_aud_1", 54*55b423d5SJiaxin Yu [CLK_TOP_APLL1_CK] = "top_apll1_ck", 55*55b423d5SJiaxin Yu [CLK_TOP_MUX_AUD_2] = "top_mux_aud_2", 56*55b423d5SJiaxin Yu [CLK_TOP_APLL2_CK] = "top_apll2_ck", 57*55b423d5SJiaxin Yu [CLK_TOP_MUX_AUD_ENG1] = "top_mux_aud_eng1", 58*55b423d5SJiaxin Yu [CLK_TOP_APLL1_D8] = "top_apll1_d8", 59*55b423d5SJiaxin Yu [CLK_TOP_MUX_AUD_ENG2] = "top_mux_aud_eng2", 60*55b423d5SJiaxin Yu [CLK_TOP_APLL2_D8] = "top_apll2_d8", 61*55b423d5SJiaxin Yu [CLK_TOP_MUX_AUDIO_H] = "top_mux_audio_h", 62*55b423d5SJiaxin Yu [CLK_TOP_I2S0_M_SEL] = "top_i2s0_m_sel", 63*55b423d5SJiaxin Yu [CLK_TOP_I2S1_M_SEL] = "top_i2s1_m_sel", 64*55b423d5SJiaxin Yu [CLK_TOP_I2S2_M_SEL] = "top_i2s2_m_sel", 65*55b423d5SJiaxin Yu [CLK_TOP_I2S4_M_SEL] = "top_i2s4_m_sel", 66*55b423d5SJiaxin Yu [CLK_TOP_TDM_M_SEL] = "top_tdm_m_sel", 67*55b423d5SJiaxin Yu [CLK_TOP_APLL12_DIV0] = "top_apll12_div0", 68*55b423d5SJiaxin Yu [CLK_TOP_APLL12_DIV1] = "top_apll12_div1", 69*55b423d5SJiaxin Yu [CLK_TOP_APLL12_DIV2] = "top_apll12_div2", 70*55b423d5SJiaxin Yu [CLK_TOP_APLL12_DIV4] = "top_apll12_div4", 71*55b423d5SJiaxin Yu [CLK_TOP_APLL12_DIV_TDM] = "top_apll12_div_tdm", 72*55b423d5SJiaxin Yu [CLK_CLK26M] = "top_clk26m_clk", 73*55b423d5SJiaxin Yu }; 74*55b423d5SJiaxin Yu 75*55b423d5SJiaxin Yu int mt8186_set_audio_int_bus_parent(struct mtk_base_afe *afe, 76*55b423d5SJiaxin Yu int clk_id) 77*55b423d5SJiaxin Yu { 78*55b423d5SJiaxin Yu struct mt8186_afe_private *afe_priv = afe->platform_priv; 79*55b423d5SJiaxin Yu int ret; 80*55b423d5SJiaxin Yu 81*55b423d5SJiaxin Yu ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], 82*55b423d5SJiaxin Yu afe_priv->clk[clk_id]); 83*55b423d5SJiaxin Yu if (ret) { 84*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 85*55b423d5SJiaxin Yu __func__, aud_clks[CLK_MUX_AUDIOINTBUS], 86*55b423d5SJiaxin Yu aud_clks[clk_id], ret); 87*55b423d5SJiaxin Yu return ret; 88*55b423d5SJiaxin Yu } 89*55b423d5SJiaxin Yu 90*55b423d5SJiaxin Yu return 0; 91*55b423d5SJiaxin Yu } 92*55b423d5SJiaxin Yu 93*55b423d5SJiaxin Yu static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable) 94*55b423d5SJiaxin Yu { 95*55b423d5SJiaxin Yu struct mt8186_afe_private *afe_priv = afe->platform_priv; 96*55b423d5SJiaxin Yu int ret; 97*55b423d5SJiaxin Yu 98*55b423d5SJiaxin Yu if (enable) { 99*55b423d5SJiaxin Yu ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]); 100*55b423d5SJiaxin Yu if (ret) { 101*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 102*55b423d5SJiaxin Yu __func__, aud_clks[CLK_TOP_MUX_AUD_1], ret); 103*55b423d5SJiaxin Yu return ret; 104*55b423d5SJiaxin Yu } 105*55b423d5SJiaxin Yu ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], 106*55b423d5SJiaxin Yu afe_priv->clk[CLK_TOP_APLL1_CK]); 107*55b423d5SJiaxin Yu if (ret) { 108*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 109*55b423d5SJiaxin Yu __func__, aud_clks[CLK_TOP_MUX_AUD_1], 110*55b423d5SJiaxin Yu aud_clks[CLK_TOP_APLL1_CK], ret); 111*55b423d5SJiaxin Yu return ret; 112*55b423d5SJiaxin Yu } 113*55b423d5SJiaxin Yu 114*55b423d5SJiaxin Yu /* 180.6336 / 8 = 22.5792MHz */ 115*55b423d5SJiaxin Yu ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]); 116*55b423d5SJiaxin Yu if (ret) { 117*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 118*55b423d5SJiaxin Yu __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret); 119*55b423d5SJiaxin Yu return ret; 120*55b423d5SJiaxin Yu } 121*55b423d5SJiaxin Yu ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], 122*55b423d5SJiaxin Yu afe_priv->clk[CLK_TOP_APLL1_D8]); 123*55b423d5SJiaxin Yu if (ret) { 124*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 125*55b423d5SJiaxin Yu __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], 126*55b423d5SJiaxin Yu aud_clks[CLK_TOP_APLL1_D8], ret); 127*55b423d5SJiaxin Yu return ret; 128*55b423d5SJiaxin Yu } 129*55b423d5SJiaxin Yu } else { 130*55b423d5SJiaxin Yu ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], 131*55b423d5SJiaxin Yu afe_priv->clk[CLK_CLK26M]); 132*55b423d5SJiaxin Yu if (ret) { 133*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 134*55b423d5SJiaxin Yu __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], 135*55b423d5SJiaxin Yu aud_clks[CLK_CLK26M], ret); 136*55b423d5SJiaxin Yu return ret; 137*55b423d5SJiaxin Yu } 138*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]); 139*55b423d5SJiaxin Yu 140*55b423d5SJiaxin Yu ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], 141*55b423d5SJiaxin Yu afe_priv->clk[CLK_CLK26M]); 142*55b423d5SJiaxin Yu if (ret) { 143*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 144*55b423d5SJiaxin Yu __func__, aud_clks[CLK_TOP_MUX_AUD_1], 145*55b423d5SJiaxin Yu aud_clks[CLK_CLK26M], ret); 146*55b423d5SJiaxin Yu return ret; 147*55b423d5SJiaxin Yu } 148*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]); 149*55b423d5SJiaxin Yu } 150*55b423d5SJiaxin Yu 151*55b423d5SJiaxin Yu return 0; 152*55b423d5SJiaxin Yu } 153*55b423d5SJiaxin Yu 154*55b423d5SJiaxin Yu static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable) 155*55b423d5SJiaxin Yu { 156*55b423d5SJiaxin Yu struct mt8186_afe_private *afe_priv = afe->platform_priv; 157*55b423d5SJiaxin Yu int ret; 158*55b423d5SJiaxin Yu 159*55b423d5SJiaxin Yu if (enable) { 160*55b423d5SJiaxin Yu ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]); 161*55b423d5SJiaxin Yu if (ret) { 162*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 163*55b423d5SJiaxin Yu __func__, aud_clks[CLK_TOP_MUX_AUD_2], ret); 164*55b423d5SJiaxin Yu return ret; 165*55b423d5SJiaxin Yu } 166*55b423d5SJiaxin Yu ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], 167*55b423d5SJiaxin Yu afe_priv->clk[CLK_TOP_APLL2_CK]); 168*55b423d5SJiaxin Yu if (ret) { 169*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 170*55b423d5SJiaxin Yu __func__, aud_clks[CLK_TOP_MUX_AUD_2], 171*55b423d5SJiaxin Yu aud_clks[CLK_TOP_APLL2_CK], ret); 172*55b423d5SJiaxin Yu return ret; 173*55b423d5SJiaxin Yu } 174*55b423d5SJiaxin Yu 175*55b423d5SJiaxin Yu /* 196.608 / 8 = 24.576MHz */ 176*55b423d5SJiaxin Yu ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]); 177*55b423d5SJiaxin Yu if (ret) { 178*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 179*55b423d5SJiaxin Yu __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret); 180*55b423d5SJiaxin Yu return ret; 181*55b423d5SJiaxin Yu } 182*55b423d5SJiaxin Yu ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], 183*55b423d5SJiaxin Yu afe_priv->clk[CLK_TOP_APLL2_D8]); 184*55b423d5SJiaxin Yu if (ret) { 185*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 186*55b423d5SJiaxin Yu __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], 187*55b423d5SJiaxin Yu aud_clks[CLK_TOP_APLL2_D8], ret); 188*55b423d5SJiaxin Yu return ret; 189*55b423d5SJiaxin Yu } 190*55b423d5SJiaxin Yu } else { 191*55b423d5SJiaxin Yu ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], 192*55b423d5SJiaxin Yu afe_priv->clk[CLK_CLK26M]); 193*55b423d5SJiaxin Yu if (ret) { 194*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 195*55b423d5SJiaxin Yu __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], 196*55b423d5SJiaxin Yu aud_clks[CLK_CLK26M], ret); 197*55b423d5SJiaxin Yu return ret; 198*55b423d5SJiaxin Yu } 199*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]); 200*55b423d5SJiaxin Yu 201*55b423d5SJiaxin Yu ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], 202*55b423d5SJiaxin Yu afe_priv->clk[CLK_CLK26M]); 203*55b423d5SJiaxin Yu if (ret) { 204*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 205*55b423d5SJiaxin Yu __func__, aud_clks[CLK_TOP_MUX_AUD_2], 206*55b423d5SJiaxin Yu aud_clks[CLK_CLK26M], ret); 207*55b423d5SJiaxin Yu return ret; 208*55b423d5SJiaxin Yu } 209*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]); 210*55b423d5SJiaxin Yu } 211*55b423d5SJiaxin Yu 212*55b423d5SJiaxin Yu return 0; 213*55b423d5SJiaxin Yu } 214*55b423d5SJiaxin Yu 215*55b423d5SJiaxin Yu int mt8186_afe_enable_cgs(struct mtk_base_afe *afe) 216*55b423d5SJiaxin Yu { 217*55b423d5SJiaxin Yu struct mt8186_afe_private *afe_priv = afe->platform_priv; 218*55b423d5SJiaxin Yu int ret = 0; 219*55b423d5SJiaxin Yu int i; 220*55b423d5SJiaxin Yu 221*55b423d5SJiaxin Yu for (i = CLK_I2S1_BCLK; i <= CLK_ETDM_OUT1_BCLK; i++) { 222*55b423d5SJiaxin Yu ret = clk_prepare_enable(afe_priv->clk[i]); 223*55b423d5SJiaxin Yu if (ret) { 224*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 225*55b423d5SJiaxin Yu __func__, aud_clks[i], ret); 226*55b423d5SJiaxin Yu return ret; 227*55b423d5SJiaxin Yu } 228*55b423d5SJiaxin Yu } 229*55b423d5SJiaxin Yu 230*55b423d5SJiaxin Yu return 0; 231*55b423d5SJiaxin Yu } 232*55b423d5SJiaxin Yu 233*55b423d5SJiaxin Yu void mt8186_afe_disable_cgs(struct mtk_base_afe *afe) 234*55b423d5SJiaxin Yu { 235*55b423d5SJiaxin Yu struct mt8186_afe_private *afe_priv = afe->platform_priv; 236*55b423d5SJiaxin Yu int i; 237*55b423d5SJiaxin Yu 238*55b423d5SJiaxin Yu for (i = CLK_I2S1_BCLK; i <= CLK_ETDM_OUT1_BCLK; i++) 239*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[i]); 240*55b423d5SJiaxin Yu } 241*55b423d5SJiaxin Yu 242*55b423d5SJiaxin Yu int mt8186_afe_enable_clock(struct mtk_base_afe *afe) 243*55b423d5SJiaxin Yu { 244*55b423d5SJiaxin Yu struct mt8186_afe_private *afe_priv = afe->platform_priv; 245*55b423d5SJiaxin Yu int ret = 0; 246*55b423d5SJiaxin Yu 247*55b423d5SJiaxin Yu ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]); 248*55b423d5SJiaxin Yu if (ret) { 249*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 250*55b423d5SJiaxin Yu __func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret); 251*55b423d5SJiaxin Yu goto clk_infra_sys_audio_err; 252*55b423d5SJiaxin Yu } 253*55b423d5SJiaxin Yu 254*55b423d5SJiaxin Yu ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_AUDIO_26M]); 255*55b423d5SJiaxin Yu if (ret) { 256*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 257*55b423d5SJiaxin Yu __func__, aud_clks[CLK_INFRA_AUDIO_26M], ret); 258*55b423d5SJiaxin Yu goto clk_infra_audio_26m_err; 259*55b423d5SJiaxin Yu } 260*55b423d5SJiaxin Yu 261*55b423d5SJiaxin Yu ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]); 262*55b423d5SJiaxin Yu if (ret) { 263*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 264*55b423d5SJiaxin Yu __func__, aud_clks[CLK_MUX_AUDIO], ret); 265*55b423d5SJiaxin Yu goto clk_mux_audio_err; 266*55b423d5SJiaxin Yu } 267*55b423d5SJiaxin Yu ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO], 268*55b423d5SJiaxin Yu afe_priv->clk[CLK_CLK26M]); 269*55b423d5SJiaxin Yu if (ret) { 270*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 271*55b423d5SJiaxin Yu __func__, aud_clks[CLK_MUX_AUDIO], 272*55b423d5SJiaxin Yu aud_clks[CLK_CLK26M], ret); 273*55b423d5SJiaxin Yu goto clk_mux_audio_err; 274*55b423d5SJiaxin Yu } 275*55b423d5SJiaxin Yu 276*55b423d5SJiaxin Yu ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); 277*55b423d5SJiaxin Yu if (ret) { 278*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 279*55b423d5SJiaxin Yu __func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret); 280*55b423d5SJiaxin Yu goto clk_mux_audio_intbus_err; 281*55b423d5SJiaxin Yu } 282*55b423d5SJiaxin Yu ret = mt8186_set_audio_int_bus_parent(afe, 283*55b423d5SJiaxin Yu CLK_TOP_MAINPLL_D2_D4); 284*55b423d5SJiaxin Yu if (ret) 285*55b423d5SJiaxin Yu goto clk_mux_audio_intbus_parent_err; 286*55b423d5SJiaxin Yu 287*55b423d5SJiaxin Yu ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUDIO_H], 288*55b423d5SJiaxin Yu afe_priv->clk[CLK_TOP_APLL2_CK]); 289*55b423d5SJiaxin Yu if (ret) { 290*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", 291*55b423d5SJiaxin Yu __func__, aud_clks[CLK_TOP_MUX_AUDIO_H], 292*55b423d5SJiaxin Yu aud_clks[CLK_TOP_APLL2_CK], ret); 293*55b423d5SJiaxin Yu goto clk_mux_audio_h_parent_err; 294*55b423d5SJiaxin Yu } 295*55b423d5SJiaxin Yu 296*55b423d5SJiaxin Yu ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]); 297*55b423d5SJiaxin Yu if (ret) { 298*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 299*55b423d5SJiaxin Yu __func__, aud_clks[CLK_AFE], ret); 300*55b423d5SJiaxin Yu goto clk_afe_err; 301*55b423d5SJiaxin Yu } 302*55b423d5SJiaxin Yu 303*55b423d5SJiaxin Yu return 0; 304*55b423d5SJiaxin Yu 305*55b423d5SJiaxin Yu clk_afe_err: 306*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_AFE]); 307*55b423d5SJiaxin Yu clk_mux_audio_h_parent_err: 308*55b423d5SJiaxin Yu clk_mux_audio_intbus_parent_err: 309*55b423d5SJiaxin Yu mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M); 310*55b423d5SJiaxin Yu clk_mux_audio_intbus_err: 311*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); 312*55b423d5SJiaxin Yu clk_mux_audio_err: 313*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]); 314*55b423d5SJiaxin Yu clk_infra_sys_audio_err: 315*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]); 316*55b423d5SJiaxin Yu clk_infra_audio_26m_err: 317*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]); 318*55b423d5SJiaxin Yu 319*55b423d5SJiaxin Yu return ret; 320*55b423d5SJiaxin Yu } 321*55b423d5SJiaxin Yu 322*55b423d5SJiaxin Yu void mt8186_afe_disable_clock(struct mtk_base_afe *afe) 323*55b423d5SJiaxin Yu { 324*55b423d5SJiaxin Yu struct mt8186_afe_private *afe_priv = afe->platform_priv; 325*55b423d5SJiaxin Yu 326*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_AFE]); 327*55b423d5SJiaxin Yu mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M); 328*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); 329*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]); 330*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]); 331*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]); 332*55b423d5SJiaxin Yu } 333*55b423d5SJiaxin Yu 334*55b423d5SJiaxin Yu int mt8186_afe_suspend_clock(struct mtk_base_afe *afe) 335*55b423d5SJiaxin Yu { 336*55b423d5SJiaxin Yu struct mt8186_afe_private *afe_priv = afe->platform_priv; 337*55b423d5SJiaxin Yu int ret; 338*55b423d5SJiaxin Yu 339*55b423d5SJiaxin Yu /* set audio int bus to 26M */ 340*55b423d5SJiaxin Yu ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); 341*55b423d5SJiaxin Yu if (ret) { 342*55b423d5SJiaxin Yu dev_info(afe->dev, "%s clk_prepare_enable %s fail %d\n", 343*55b423d5SJiaxin Yu __func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret); 344*55b423d5SJiaxin Yu goto clk_mux_audio_intbus_err; 345*55b423d5SJiaxin Yu } 346*55b423d5SJiaxin Yu ret = mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M); 347*55b423d5SJiaxin Yu if (ret) 348*55b423d5SJiaxin Yu goto clk_mux_audio_intbus_parent_err; 349*55b423d5SJiaxin Yu 350*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); 351*55b423d5SJiaxin Yu 352*55b423d5SJiaxin Yu return 0; 353*55b423d5SJiaxin Yu 354*55b423d5SJiaxin Yu clk_mux_audio_intbus_parent_err: 355*55b423d5SJiaxin Yu mt8186_set_audio_int_bus_parent(afe, CLK_TOP_MAINPLL_D2_D4); 356*55b423d5SJiaxin Yu clk_mux_audio_intbus_err: 357*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); 358*55b423d5SJiaxin Yu return ret; 359*55b423d5SJiaxin Yu } 360*55b423d5SJiaxin Yu 361*55b423d5SJiaxin Yu int mt8186_afe_resume_clock(struct mtk_base_afe *afe) 362*55b423d5SJiaxin Yu { 363*55b423d5SJiaxin Yu struct mt8186_afe_private *afe_priv = afe->platform_priv; 364*55b423d5SJiaxin Yu int ret; 365*55b423d5SJiaxin Yu 366*55b423d5SJiaxin Yu /* set audio int bus to normal working clock */ 367*55b423d5SJiaxin Yu ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); 368*55b423d5SJiaxin Yu if (ret) { 369*55b423d5SJiaxin Yu dev_info(afe->dev, "%s clk_prepare_enable %s fail %d\n", 370*55b423d5SJiaxin Yu __func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret); 371*55b423d5SJiaxin Yu goto clk_mux_audio_intbus_err; 372*55b423d5SJiaxin Yu } 373*55b423d5SJiaxin Yu ret = mt8186_set_audio_int_bus_parent(afe, 374*55b423d5SJiaxin Yu CLK_TOP_MAINPLL_D2_D4); 375*55b423d5SJiaxin Yu if (ret) 376*55b423d5SJiaxin Yu goto clk_mux_audio_intbus_parent_err; 377*55b423d5SJiaxin Yu 378*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); 379*55b423d5SJiaxin Yu 380*55b423d5SJiaxin Yu return 0; 381*55b423d5SJiaxin Yu 382*55b423d5SJiaxin Yu clk_mux_audio_intbus_parent_err: 383*55b423d5SJiaxin Yu mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M); 384*55b423d5SJiaxin Yu clk_mux_audio_intbus_err: 385*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); 386*55b423d5SJiaxin Yu return ret; 387*55b423d5SJiaxin Yu } 388*55b423d5SJiaxin Yu 389*55b423d5SJiaxin Yu int mt8186_apll1_enable(struct mtk_base_afe *afe) 390*55b423d5SJiaxin Yu { 391*55b423d5SJiaxin Yu struct mt8186_afe_private *afe_priv = afe->platform_priv; 392*55b423d5SJiaxin Yu int ret; 393*55b423d5SJiaxin Yu 394*55b423d5SJiaxin Yu /* setting for APLL */ 395*55b423d5SJiaxin Yu apll1_mux_setting(afe, true); 396*55b423d5SJiaxin Yu 397*55b423d5SJiaxin Yu ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]); 398*55b423d5SJiaxin Yu if (ret) { 399*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 400*55b423d5SJiaxin Yu __func__, aud_clks[CLK_APLL22M], ret); 401*55b423d5SJiaxin Yu goto err_clk_apll22m; 402*55b423d5SJiaxin Yu } 403*55b423d5SJiaxin Yu 404*55b423d5SJiaxin Yu ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]); 405*55b423d5SJiaxin Yu if (ret) { 406*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 407*55b423d5SJiaxin Yu __func__, aud_clks[CLK_APLL1_TUNER], ret); 408*55b423d5SJiaxin Yu goto err_clk_apll1_tuner; 409*55b423d5SJiaxin Yu } 410*55b423d5SJiaxin Yu 411*55b423d5SJiaxin Yu regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0xfff7, 0x832); 412*55b423d5SJiaxin Yu regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1); 413*55b423d5SJiaxin Yu 414*55b423d5SJiaxin Yu regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, 415*55b423d5SJiaxin Yu AFE_22M_ON_MASK_SFT, BIT(AFE_22M_ON_SFT)); 416*55b423d5SJiaxin Yu 417*55b423d5SJiaxin Yu return 0; 418*55b423d5SJiaxin Yu 419*55b423d5SJiaxin Yu err_clk_apll1_tuner: 420*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]); 421*55b423d5SJiaxin Yu err_clk_apll22m: 422*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]); 423*55b423d5SJiaxin Yu 424*55b423d5SJiaxin Yu return ret; 425*55b423d5SJiaxin Yu } 426*55b423d5SJiaxin Yu 427*55b423d5SJiaxin Yu void mt8186_apll1_disable(struct mtk_base_afe *afe) 428*55b423d5SJiaxin Yu { 429*55b423d5SJiaxin Yu struct mt8186_afe_private *afe_priv = afe->platform_priv; 430*55b423d5SJiaxin Yu 431*55b423d5SJiaxin Yu regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, 432*55b423d5SJiaxin Yu AFE_22M_ON_MASK_SFT, 0); 433*55b423d5SJiaxin Yu 434*55b423d5SJiaxin Yu regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0); 435*55b423d5SJiaxin Yu 436*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]); 437*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]); 438*55b423d5SJiaxin Yu 439*55b423d5SJiaxin Yu apll1_mux_setting(afe, false); 440*55b423d5SJiaxin Yu } 441*55b423d5SJiaxin Yu 442*55b423d5SJiaxin Yu int mt8186_apll2_enable(struct mtk_base_afe *afe) 443*55b423d5SJiaxin Yu { 444*55b423d5SJiaxin Yu struct mt8186_afe_private *afe_priv = afe->platform_priv; 445*55b423d5SJiaxin Yu int ret; 446*55b423d5SJiaxin Yu 447*55b423d5SJiaxin Yu /* setting for APLL */ 448*55b423d5SJiaxin Yu apll2_mux_setting(afe, true); 449*55b423d5SJiaxin Yu 450*55b423d5SJiaxin Yu ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]); 451*55b423d5SJiaxin Yu if (ret) { 452*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 453*55b423d5SJiaxin Yu __func__, aud_clks[CLK_APLL24M], ret); 454*55b423d5SJiaxin Yu goto err_clk_apll24m; 455*55b423d5SJiaxin Yu } 456*55b423d5SJiaxin Yu 457*55b423d5SJiaxin Yu ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]); 458*55b423d5SJiaxin Yu if (ret) { 459*55b423d5SJiaxin Yu dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 460*55b423d5SJiaxin Yu __func__, aud_clks[CLK_APLL2_TUNER], ret); 461*55b423d5SJiaxin Yu goto err_clk_apll2_tuner; 462*55b423d5SJiaxin Yu } 463*55b423d5SJiaxin Yu 464*55b423d5SJiaxin Yu regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0xfff7, 0x634); 465*55b423d5SJiaxin Yu regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1); 466*55b423d5SJiaxin Yu 467*55b423d5SJiaxin Yu regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, 468*55b423d5SJiaxin Yu AFE_24M_ON_MASK_SFT, BIT(AFE_24M_ON_SFT)); 469*55b423d5SJiaxin Yu 470*55b423d5SJiaxin Yu return 0; 471*55b423d5SJiaxin Yu 472*55b423d5SJiaxin Yu err_clk_apll2_tuner: 473*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]); 474*55b423d5SJiaxin Yu err_clk_apll24m: 475*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]); 476*55b423d5SJiaxin Yu 477*55b423d5SJiaxin Yu return ret; 478*55b423d5SJiaxin Yu } 479*55b423d5SJiaxin Yu 480*55b423d5SJiaxin Yu void mt8186_apll2_disable(struct mtk_base_afe *afe) 481*55b423d5SJiaxin Yu { 482*55b423d5SJiaxin Yu struct mt8186_afe_private *afe_priv = afe->platform_priv; 483*55b423d5SJiaxin Yu 484*55b423d5SJiaxin Yu regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, 485*55b423d5SJiaxin Yu AFE_24M_ON_MASK_SFT, 0); 486*55b423d5SJiaxin Yu 487*55b423d5SJiaxin Yu regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0); 488*55b423d5SJiaxin Yu 489*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]); 490*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]); 491*55b423d5SJiaxin Yu 492*55b423d5SJiaxin Yu apll2_mux_setting(afe, false); 493*55b423d5SJiaxin Yu } 494*55b423d5SJiaxin Yu 495*55b423d5SJiaxin Yu int mt8186_get_apll_rate(struct mtk_base_afe *afe, int apll) 496*55b423d5SJiaxin Yu { 497*55b423d5SJiaxin Yu return (apll == MT8186_APLL1) ? 180633600 : 196608000; 498*55b423d5SJiaxin Yu } 499*55b423d5SJiaxin Yu 500*55b423d5SJiaxin Yu int mt8186_get_apll_by_rate(struct mtk_base_afe *afe, int rate) 501*55b423d5SJiaxin Yu { 502*55b423d5SJiaxin Yu return ((rate % 8000) == 0) ? MT8186_APLL2 : MT8186_APLL1; 503*55b423d5SJiaxin Yu } 504*55b423d5SJiaxin Yu 505*55b423d5SJiaxin Yu int mt8186_get_apll_by_name(struct mtk_base_afe *afe, const char *name) 506*55b423d5SJiaxin Yu { 507*55b423d5SJiaxin Yu if (strcmp(name, APLL1_W_NAME) == 0) 508*55b423d5SJiaxin Yu return MT8186_APLL1; 509*55b423d5SJiaxin Yu 510*55b423d5SJiaxin Yu return MT8186_APLL2; 511*55b423d5SJiaxin Yu } 512*55b423d5SJiaxin Yu 513*55b423d5SJiaxin Yu /* mck */ 514*55b423d5SJiaxin Yu struct mt8186_mck_div { 515*55b423d5SJiaxin Yu u32 m_sel_id; 516*55b423d5SJiaxin Yu u32 div_clk_id; 517*55b423d5SJiaxin Yu }; 518*55b423d5SJiaxin Yu 519*55b423d5SJiaxin Yu static const struct mt8186_mck_div mck_div[MT8186_MCK_NUM] = { 520*55b423d5SJiaxin Yu [MT8186_I2S0_MCK] = { 521*55b423d5SJiaxin Yu .m_sel_id = CLK_TOP_I2S0_M_SEL, 522*55b423d5SJiaxin Yu .div_clk_id = CLK_TOP_APLL12_DIV0, 523*55b423d5SJiaxin Yu }, 524*55b423d5SJiaxin Yu [MT8186_I2S1_MCK] = { 525*55b423d5SJiaxin Yu .m_sel_id = CLK_TOP_I2S1_M_SEL, 526*55b423d5SJiaxin Yu .div_clk_id = CLK_TOP_APLL12_DIV1, 527*55b423d5SJiaxin Yu }, 528*55b423d5SJiaxin Yu [MT8186_I2S2_MCK] = { 529*55b423d5SJiaxin Yu .m_sel_id = CLK_TOP_I2S2_M_SEL, 530*55b423d5SJiaxin Yu .div_clk_id = CLK_TOP_APLL12_DIV2, 531*55b423d5SJiaxin Yu }, 532*55b423d5SJiaxin Yu [MT8186_I2S4_MCK] = { 533*55b423d5SJiaxin Yu .m_sel_id = CLK_TOP_I2S4_M_SEL, 534*55b423d5SJiaxin Yu .div_clk_id = CLK_TOP_APLL12_DIV4, 535*55b423d5SJiaxin Yu }, 536*55b423d5SJiaxin Yu [MT8186_TDM_MCK] = { 537*55b423d5SJiaxin Yu .m_sel_id = CLK_TOP_TDM_M_SEL, 538*55b423d5SJiaxin Yu .div_clk_id = CLK_TOP_APLL12_DIV_TDM, 539*55b423d5SJiaxin Yu }, 540*55b423d5SJiaxin Yu }; 541*55b423d5SJiaxin Yu 542*55b423d5SJiaxin Yu int mt8186_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate) 543*55b423d5SJiaxin Yu { 544*55b423d5SJiaxin Yu struct mt8186_afe_private *afe_priv = afe->platform_priv; 545*55b423d5SJiaxin Yu int apll = mt8186_get_apll_by_rate(afe, rate); 546*55b423d5SJiaxin Yu int apll_clk_id = apll == MT8186_APLL1 ? 547*55b423d5SJiaxin Yu CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2; 548*55b423d5SJiaxin Yu int m_sel_id = mck_div[mck_id].m_sel_id; 549*55b423d5SJiaxin Yu int div_clk_id = mck_div[mck_id].div_clk_id; 550*55b423d5SJiaxin Yu int ret; 551*55b423d5SJiaxin Yu 552*55b423d5SJiaxin Yu /* select apll */ 553*55b423d5SJiaxin Yu if (m_sel_id >= 0) { 554*55b423d5SJiaxin Yu ret = clk_prepare_enable(afe_priv->clk[m_sel_id]); 555*55b423d5SJiaxin Yu if (ret) { 556*55b423d5SJiaxin Yu dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n", 557*55b423d5SJiaxin Yu __func__, aud_clks[m_sel_id], ret); 558*55b423d5SJiaxin Yu return ret; 559*55b423d5SJiaxin Yu } 560*55b423d5SJiaxin Yu ret = clk_set_parent(afe_priv->clk[m_sel_id], 561*55b423d5SJiaxin Yu afe_priv->clk[apll_clk_id]); 562*55b423d5SJiaxin Yu if (ret) { 563*55b423d5SJiaxin Yu dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n", 564*55b423d5SJiaxin Yu __func__, aud_clks[m_sel_id], 565*55b423d5SJiaxin Yu aud_clks[apll_clk_id], ret); 566*55b423d5SJiaxin Yu return ret; 567*55b423d5SJiaxin Yu } 568*55b423d5SJiaxin Yu } 569*55b423d5SJiaxin Yu 570*55b423d5SJiaxin Yu /* enable div, set rate */ 571*55b423d5SJiaxin Yu ret = clk_prepare_enable(afe_priv->clk[div_clk_id]); 572*55b423d5SJiaxin Yu if (ret) { 573*55b423d5SJiaxin Yu dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n", 574*55b423d5SJiaxin Yu __func__, aud_clks[div_clk_id], ret); 575*55b423d5SJiaxin Yu return ret; 576*55b423d5SJiaxin Yu } 577*55b423d5SJiaxin Yu ret = clk_set_rate(afe_priv->clk[div_clk_id], rate); 578*55b423d5SJiaxin Yu if (ret) { 579*55b423d5SJiaxin Yu dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n", 580*55b423d5SJiaxin Yu __func__, aud_clks[div_clk_id], rate, ret); 581*55b423d5SJiaxin Yu return ret; 582*55b423d5SJiaxin Yu } 583*55b423d5SJiaxin Yu 584*55b423d5SJiaxin Yu return 0; 585*55b423d5SJiaxin Yu } 586*55b423d5SJiaxin Yu 587*55b423d5SJiaxin Yu void mt8186_mck_disable(struct mtk_base_afe *afe, int mck_id) 588*55b423d5SJiaxin Yu { 589*55b423d5SJiaxin Yu struct mt8186_afe_private *afe_priv = afe->platform_priv; 590*55b423d5SJiaxin Yu int m_sel_id = mck_div[mck_id].m_sel_id; 591*55b423d5SJiaxin Yu int div_clk_id = mck_div[mck_id].div_clk_id; 592*55b423d5SJiaxin Yu 593*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[div_clk_id]); 594*55b423d5SJiaxin Yu if (m_sel_id >= 0) 595*55b423d5SJiaxin Yu clk_disable_unprepare(afe_priv->clk[m_sel_id]); 596*55b423d5SJiaxin Yu } 597*55b423d5SJiaxin Yu 598*55b423d5SJiaxin Yu int mt8186_init_clock(struct mtk_base_afe *afe) 599*55b423d5SJiaxin Yu { 600*55b423d5SJiaxin Yu struct mt8186_afe_private *afe_priv = afe->platform_priv; 601*55b423d5SJiaxin Yu struct device_node *of_node = afe->dev->of_node; 602*55b423d5SJiaxin Yu int i = 0; 603*55b423d5SJiaxin Yu 604*55b423d5SJiaxin Yu mt8186_audsys_clk_register(afe); 605*55b423d5SJiaxin Yu 606*55b423d5SJiaxin Yu afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk), 607*55b423d5SJiaxin Yu GFP_KERNEL); 608*55b423d5SJiaxin Yu if (!afe_priv->clk) 609*55b423d5SJiaxin Yu return -ENOMEM; 610*55b423d5SJiaxin Yu 611*55b423d5SJiaxin Yu for (i = 0; i < CLK_NUM; i++) { 612*55b423d5SJiaxin Yu afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); 613*55b423d5SJiaxin Yu if (IS_ERR(afe_priv->clk[i])) { 614*55b423d5SJiaxin Yu dev_err(afe->dev, "%s devm_clk_get %s fail, ret %ld\n", 615*55b423d5SJiaxin Yu __func__, 616*55b423d5SJiaxin Yu aud_clks[i], PTR_ERR(afe_priv->clk[i])); 617*55b423d5SJiaxin Yu afe_priv->clk[i] = NULL; 618*55b423d5SJiaxin Yu } 619*55b423d5SJiaxin Yu } 620*55b423d5SJiaxin Yu 621*55b423d5SJiaxin Yu afe_priv->apmixedsys = syscon_regmap_lookup_by_phandle(of_node, 622*55b423d5SJiaxin Yu "mediatek,apmixedsys"); 623*55b423d5SJiaxin Yu if (IS_ERR(afe_priv->apmixedsys)) { 624*55b423d5SJiaxin Yu dev_err(afe->dev, "%s() Cannot find apmixedsys controller: %ld\n", 625*55b423d5SJiaxin Yu __func__, PTR_ERR(afe_priv->apmixedsys)); 626*55b423d5SJiaxin Yu return PTR_ERR(afe_priv->apmixedsys); 627*55b423d5SJiaxin Yu } 628*55b423d5SJiaxin Yu 629*55b423d5SJiaxin Yu afe_priv->topckgen = syscon_regmap_lookup_by_phandle(of_node, 630*55b423d5SJiaxin Yu "mediatek,topckgen"); 631*55b423d5SJiaxin Yu if (IS_ERR(afe_priv->topckgen)) { 632*55b423d5SJiaxin Yu dev_err(afe->dev, "%s() Cannot find topckgen controller: %ld\n", 633*55b423d5SJiaxin Yu __func__, PTR_ERR(afe_priv->topckgen)); 634*55b423d5SJiaxin Yu return PTR_ERR(afe_priv->topckgen); 635*55b423d5SJiaxin Yu } 636*55b423d5SJiaxin Yu 637*55b423d5SJiaxin Yu afe_priv->infracfg = syscon_regmap_lookup_by_phandle(of_node, 638*55b423d5SJiaxin Yu "mediatek,infracfg"); 639*55b423d5SJiaxin Yu if (IS_ERR(afe_priv->infracfg)) { 640*55b423d5SJiaxin Yu dev_err(afe->dev, "%s() Cannot find infracfg: %ld\n", 641*55b423d5SJiaxin Yu __func__, PTR_ERR(afe_priv->infracfg)); 642*55b423d5SJiaxin Yu return PTR_ERR(afe_priv->infracfg); 643*55b423d5SJiaxin Yu } 644*55b423d5SJiaxin Yu 645*55b423d5SJiaxin Yu return 0; 646*55b423d5SJiaxin Yu } 647*55b423d5SJiaxin Yu 648*55b423d5SJiaxin Yu void mt8186_deinit_clock(struct mtk_base_afe *afe) 649*55b423d5SJiaxin Yu { 650*55b423d5SJiaxin Yu mt8186_audsys_clk_unregister(afe); 651*55b423d5SJiaxin Yu } 652