1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * mt8183-reg.h  --  Mediatek 8183 audio driver reg definition
4  *
5  * Copyright (c) 2018 MediaTek Inc.
6  * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7  */
8 
9 #ifndef _MT8183_REG_H_
10 #define _MT8183_REG_H_
11 
12 #define AUDIO_TOP_CON0              0x0000
13 #define AUDIO_TOP_CON1              0x0004
14 #define AUDIO_TOP_CON3              0x000c
15 #define AFE_DAC_CON0                0x0010
16 #define AFE_DAC_CON1                0x0014
17 #define AFE_I2S_CON                 0x0018
18 #define AFE_DAIBT_CON0              0x001c
19 #define AFE_CONN0                   0x0020
20 #define AFE_CONN1                   0x0024
21 #define AFE_CONN2                   0x0028
22 #define AFE_CONN3                   0x002c
23 #define AFE_CONN4                   0x0030
24 #define AFE_I2S_CON1                0x0034
25 #define AFE_I2S_CON2                0x0038
26 #define AFE_MRGIF_CON               0x003c
27 #define AFE_DL1_BASE                0x0040
28 #define AFE_DL1_CUR                 0x0044
29 #define AFE_DL1_END                 0x0048
30 #define AFE_I2S_CON3                0x004c
31 #define AFE_DL2_BASE                0x0050
32 #define AFE_DL2_CUR                 0x0054
33 #define AFE_DL2_END                 0x0058
34 #define AFE_CONN5                   0x005c
35 #define AFE_CONN_24BIT              0x006c
36 #define AFE_AWB_BASE                0x0070
37 #define AFE_AWB_END                 0x0078
38 #define AFE_AWB_CUR                 0x007c
39 #define AFE_VUL_BASE                0x0080
40 #define AFE_VUL_END                 0x0088
41 #define AFE_VUL_CUR                 0x008c
42 #define AFE_CONN6                   0x00bc
43 #define AFE_MEMIF_MSB               0x00cc
44 #define AFE_MEMIF_MON0              0x00d0
45 #define AFE_MEMIF_MON1              0x00d4
46 #define AFE_MEMIF_MON2              0x00d8
47 #define AFE_MEMIF_MON3              0x00dc
48 #define AFE_MEMIF_MON4              0x00e0
49 #define AFE_MEMIF_MON5              0x00e4
50 #define AFE_MEMIF_MON6              0x00e8
51 #define AFE_MEMIF_MON7              0x00ec
52 #define AFE_MEMIF_MON8              0x00f0
53 #define AFE_MEMIF_MON9              0x00f4
54 #define AFE_ADDA_DL_SRC2_CON0       0x0108
55 #define AFE_ADDA_DL_SRC2_CON1       0x010c
56 #define AFE_ADDA_UL_SRC_CON0        0x0114
57 #define AFE_ADDA_UL_SRC_CON1        0x0118
58 #define AFE_ADDA_TOP_CON0           0x0120
59 #define AFE_ADDA_UL_DL_CON0         0x0124
60 #define AFE_ADDA_SRC_DEBUG          0x012c
61 #define AFE_ADDA_SRC_DEBUG_MON0     0x0130
62 #define AFE_ADDA_SRC_DEBUG_MON1     0x0134
63 #define AFE_ADDA_UL_SRC_MON0        0x0148
64 #define AFE_ADDA_UL_SRC_MON1        0x014c
65 #define AFE_SIDETONE_DEBUG          0x01d0
66 #define AFE_SIDETONE_MON            0x01d4
67 #define AFE_SINEGEN_CON2            0x01dc
68 #define AFE_SIDETONE_CON0           0x01e0
69 #define AFE_SIDETONE_COEFF          0x01e4
70 #define AFE_SIDETONE_CON1           0x01e8
71 #define AFE_SIDETONE_GAIN           0x01ec
72 #define AFE_SINEGEN_CON0            0x01f0
73 #define AFE_TOP_CON0                0x0200
74 #define AFE_BUS_CFG                 0x0240
75 #define AFE_BUS_MON0                0x0244
76 #define AFE_ADDA_PREDIS_CON0        0x0260
77 #define AFE_ADDA_PREDIS_CON1        0x0264
78 #define AFE_MRGIF_MON0              0x0270
79 #define AFE_MRGIF_MON1              0x0274
80 #define AFE_MRGIF_MON2              0x0278
81 #define AFE_I2S_MON                 0x027c
82 #define AFE_ADDA_IIR_COEF_02_01     0x0290
83 #define AFE_ADDA_IIR_COEF_04_03     0x0294
84 #define AFE_ADDA_IIR_COEF_06_05     0x0298
85 #define AFE_ADDA_IIR_COEF_08_07     0x029c
86 #define AFE_ADDA_IIR_COEF_10_09     0x02a0
87 #define AFE_DAC_CON2                0x02e0
88 #define AFE_IRQ_MCU_CON1            0x02e4
89 #define AFE_IRQ_MCU_CON2            0x02e8
90 #define AFE_DAC_MON                 0x02ec
91 #define AFE_VUL2_BASE               0x02f0
92 #define AFE_VUL2_END                0x02f8
93 #define AFE_VUL2_CUR                0x02fc
94 #define AFE_IRQ_MCU_CNT0            0x0300
95 #define AFE_IRQ_MCU_CNT6            0x0304
96 #define AFE_IRQ_MCU_CNT8            0x0308
97 #define AFE_IRQ_MCU_EN1             0x030c
98 #define AFE_IRQ0_MCU_CNT_MON        0x0310
99 #define AFE_IRQ6_MCU_CNT_MON        0x0314
100 #define AFE_MOD_DAI_BASE            0x0330
101 #define AFE_MOD_DAI_END             0x0338
102 #define AFE_MOD_DAI_CUR             0x033c
103 #define AFE_VUL_D2_BASE             0x0350
104 #define AFE_VUL_D2_END              0x0358
105 #define AFE_VUL_D2_CUR              0x035c
106 #define AFE_DL3_BASE                0x0360
107 #define AFE_DL3_CUR                 0x0364
108 #define AFE_DL3_END                 0x0368
109 #define AFE_HDMI_OUT_CON0           0x0370
110 #define AFE_HDMI_OUT_BASE           0x0374
111 #define AFE_HDMI_OUT_CUR            0x0378
112 #define AFE_HDMI_OUT_END            0x037c
113 #define AFE_HDMI_CONN0              0x0390
114 #define AFE_IRQ3_MCU_CNT_MON        0x0398
115 #define AFE_IRQ4_MCU_CNT_MON        0x039c
116 #define AFE_IRQ_MCU_CON0            0x03a0
117 #define AFE_IRQ_MCU_STATUS          0x03a4
118 #define AFE_IRQ_MCU_CLR             0x03a8
119 #define AFE_IRQ_MCU_CNT1            0x03ac
120 #define AFE_IRQ_MCU_CNT2            0x03b0
121 #define AFE_IRQ_MCU_EN              0x03b4
122 #define AFE_IRQ_MCU_MON2            0x03b8
123 #define AFE_IRQ_MCU_CNT5            0x03bc
124 #define AFE_IRQ1_MCU_CNT_MON        0x03c0
125 #define AFE_IRQ2_MCU_CNT_MON        0x03c4
126 #define AFE_IRQ1_MCU_EN_CNT_MON     0x03c8
127 #define AFE_IRQ5_MCU_CNT_MON        0x03cc
128 #define AFE_MEMIF_MINLEN            0x03d0
129 #define AFE_MEMIF_MAXLEN            0x03d4
130 #define AFE_MEMIF_PBUF_SIZE         0x03d8
131 #define AFE_IRQ_MCU_CNT7            0x03dc
132 #define AFE_IRQ7_MCU_CNT_MON        0x03e0
133 #define AFE_IRQ_MCU_CNT3            0x03e4
134 #define AFE_IRQ_MCU_CNT4            0x03e8
135 #define AFE_IRQ_MCU_CNT11           0x03ec
136 #define AFE_APLL1_TUNER_CFG         0x03f0
137 #define AFE_APLL2_TUNER_CFG         0x03f4
138 #define AFE_MEMIF_HD_MODE           0x03f8
139 #define AFE_MEMIF_HDALIGN           0x03fc
140 #define AFE_CONN33                  0x0408
141 #define AFE_IRQ_MCU_CNT12           0x040c
142 #define AFE_GAIN1_CON0              0x0410
143 #define AFE_GAIN1_CON1              0x0414
144 #define AFE_GAIN1_CON2              0x0418
145 #define AFE_GAIN1_CON3              0x041c
146 #define AFE_CONN7                   0x0420
147 #define AFE_GAIN1_CUR               0x0424
148 #define AFE_GAIN2_CON0              0x0428
149 #define AFE_GAIN2_CON1              0x042c
150 #define AFE_GAIN2_CON2              0x0430
151 #define AFE_GAIN2_CON3              0x0434
152 #define AFE_CONN8                   0x0438
153 #define AFE_GAIN2_CUR               0x043c
154 #define AFE_CONN9                   0x0440
155 #define AFE_CONN10                  0x0444
156 #define AFE_CONN11                  0x0448
157 #define AFE_CONN12                  0x044c
158 #define AFE_CONN13                  0x0450
159 #define AFE_CONN14                  0x0454
160 #define AFE_CONN15                  0x0458
161 #define AFE_CONN16                  0x045c
162 #define AFE_CONN17                  0x0460
163 #define AFE_CONN18                  0x0464
164 #define AFE_CONN19                  0x0468
165 #define AFE_CONN20                  0x046c
166 #define AFE_CONN21                  0x0470
167 #define AFE_CONN22                  0x0474
168 #define AFE_CONN23                  0x0478
169 #define AFE_CONN24                  0x047c
170 #define AFE_CONN_RS                 0x0494
171 #define AFE_CONN_DI                 0x0498
172 #define AFE_CONN25                  0x04b0
173 #define AFE_CONN26                  0x04b4
174 #define AFE_CONN27                  0x04b8
175 #define AFE_CONN28                  0x04bc
176 #define AFE_CONN29                  0x04c0
177 #define AFE_CONN30                  0x04c4
178 #define AFE_CONN31                  0x04c8
179 #define AFE_CONN32                  0x04cc
180 #define AFE_SRAM_DELSEL_CON0        0x04f0
181 #define AFE_SRAM_DELSEL_CON2        0x04f8
182 #define AFE_SRAM_DELSEL_CON3        0x04fc
183 #define AFE_ASRC_2CH_CON12          0x0528
184 #define AFE_ASRC_2CH_CON13          0x052c
185 #define PCM_INTF_CON1               0x0530
186 #define PCM_INTF_CON2               0x0538
187 #define PCM2_INTF_CON               0x053c
188 #define AFE_TDM_CON1                0x0548
189 #define AFE_TDM_CON2                0x054c
190 #define AFE_CONN34                  0x0580
191 #define FPGA_CFG0                   0x05b0
192 #define FPGA_CFG1                   0x05b4
193 #define FPGA_CFG2                   0x05c0
194 #define FPGA_CFG3                   0x05c4
195 #define AUDIO_TOP_DBG_CON           0x05c8
196 #define AUDIO_TOP_DBG_MON0          0x05cc
197 #define AUDIO_TOP_DBG_MON1          0x05d0
198 #define AFE_IRQ8_MCU_CNT_MON        0x05e4
199 #define AFE_IRQ11_MCU_CNT_MON       0x05e8
200 #define AFE_IRQ12_MCU_CNT_MON       0x05ec
201 #define AFE_GENERAL_REG0            0x0800
202 #define AFE_GENERAL_REG1            0x0804
203 #define AFE_GENERAL_REG2            0x0808
204 #define AFE_GENERAL_REG3            0x080c
205 #define AFE_GENERAL_REG4            0x0810
206 #define AFE_GENERAL_REG5            0x0814
207 #define AFE_GENERAL_REG6            0x0818
208 #define AFE_GENERAL_REG7            0x081c
209 #define AFE_GENERAL_REG8            0x0820
210 #define AFE_GENERAL_REG9            0x0824
211 #define AFE_GENERAL_REG10           0x0828
212 #define AFE_GENERAL_REG11           0x082c
213 #define AFE_GENERAL_REG12           0x0830
214 #define AFE_GENERAL_REG13           0x0834
215 #define AFE_GENERAL_REG14           0x0838
216 #define AFE_GENERAL_REG15           0x083c
217 #define AFE_CBIP_CFG0               0x0840
218 #define AFE_CBIP_MON0               0x0844
219 #define AFE_CBIP_SLV_MUX_MON0       0x0848
220 #define AFE_CBIP_SLV_DECODER_MON0   0x084c
221 #define AFE_CONN0_1                 0x0900
222 #define AFE_CONN1_1                 0x0904
223 #define AFE_CONN2_1                 0x0908
224 #define AFE_CONN3_1                 0x090c
225 #define AFE_CONN4_1                 0x0910
226 #define AFE_CONN5_1                 0x0914
227 #define AFE_CONN6_1                 0x0918
228 #define AFE_CONN7_1                 0x091c
229 #define AFE_CONN8_1                 0x0920
230 #define AFE_CONN9_1                 0x0924
231 #define AFE_CONN10_1                0x0928
232 #define AFE_CONN11_1                0x092c
233 #define AFE_CONN12_1                0x0930
234 #define AFE_CONN13_1                0x0934
235 #define AFE_CONN14_1                0x0938
236 #define AFE_CONN15_1                0x093c
237 #define AFE_CONN16_1                0x0940
238 #define AFE_CONN17_1                0x0944
239 #define AFE_CONN18_1                0x0948
240 #define AFE_CONN19_1                0x094c
241 #define AFE_CONN20_1                0x0950
242 #define AFE_CONN21_1                0x0954
243 #define AFE_CONN22_1                0x0958
244 #define AFE_CONN23_1                0x095c
245 #define AFE_CONN24_1                0x0960
246 #define AFE_CONN25_1                0x0964
247 #define AFE_CONN26_1                0x0968
248 #define AFE_CONN27_1                0x096c
249 #define AFE_CONN28_1                0x0970
250 #define AFE_CONN29_1                0x0974
251 #define AFE_CONN30_1                0x0978
252 #define AFE_CONN31_1                0x097c
253 #define AFE_CONN32_1                0x0980
254 #define AFE_CONN33_1                0x0984
255 #define AFE_CONN34_1                0x0988
256 #define AFE_CONN_RS_1               0x098c
257 #define AFE_CONN_DI_1               0x0990
258 #define AFE_CONN_24BIT_1            0x0994
259 #define AFE_CONN_REG                0x0998
260 #define AFE_CONN35                  0x09a0
261 #define AFE_CONN36                  0x09a4
262 #define AFE_CONN37                  0x09a8
263 #define AFE_CONN38                  0x09ac
264 #define AFE_CONN35_1                0x09b0
265 #define AFE_CONN36_1                0x09b4
266 #define AFE_CONN37_1                0x09b8
267 #define AFE_CONN38_1                0x09bc
268 #define AFE_CONN39                  0x09c0
269 #define AFE_CONN40                  0x09c4
270 #define AFE_CONN41                  0x09c8
271 #define AFE_CONN42                  0x09cc
272 #define AFE_CONN39_1                0x09e0
273 #define AFE_CONN40_1                0x09e4
274 #define AFE_CONN41_1                0x09e8
275 #define AFE_CONN42_1                0x09ec
276 #define AFE_I2S_CON4                0x09f8
277 #define AFE_ADDA6_TOP_CON0          0x0a80
278 #define AFE_ADDA6_UL_SRC_CON0       0x0a84
279 #define AFE_ADD6_UL_SRC_CON1        0x0a88
280 #define AFE_ADDA6_SRC_DEBUG         0x0a8c
281 #define AFE_ADDA6_SRC_DEBUG_MON0    0x0a90
282 #define AFE_ADDA6_ULCF_CFG_02_01    0x0aa0
283 #define AFE_ADDA6_ULCF_CFG_04_03    0x0aa4
284 #define AFE_ADDA6_ULCF_CFG_06_05    0x0aa8
285 #define AFE_ADDA6_ULCF_CFG_08_07    0x0aac
286 #define AFE_ADDA6_ULCF_CFG_10_09    0x0ab0
287 #define AFE_ADDA6_ULCF_CFG_12_11    0x0ab4
288 #define AFE_ADDA6_ULCF_CFG_14_13    0x0ab8
289 #define AFE_ADDA6_ULCF_CFG_16_15    0x0abc
290 #define AFE_ADDA6_ULCF_CFG_18_17    0x0ac0
291 #define AFE_ADDA6_ULCF_CFG_20_19    0x0ac4
292 #define AFE_ADDA6_ULCF_CFG_22_21    0x0ac8
293 #define AFE_ADDA6_ULCF_CFG_24_23    0x0acc
294 #define AFE_ADDA6_ULCF_CFG_26_25    0x0ad0
295 #define AFE_ADDA6_ULCF_CFG_28_27    0x0ad4
296 #define AFE_ADDA6_ULCF_CFG_30_29    0x0ad8
297 #define AFE_ADD6A_UL_SRC_MON0       0x0ae4
298 #define AFE_ADDA6_UL_SRC_MON1       0x0ae8
299 #define AFE_CONN43                  0x0af8
300 #define AFE_CONN43_1                0x0afc
301 #define AFE_DL1_BASE_MSB            0x0b00
302 #define AFE_DL1_CUR_MSB             0x0b04
303 #define AFE_DL1_END_MSB             0x0b08
304 #define AFE_DL2_BASE_MSB            0x0b10
305 #define AFE_DL2_CUR_MSB             0x0b14
306 #define AFE_DL2_END_MSB             0x0b18
307 #define AFE_AWB_BASE_MSB            0x0b20
308 #define AFE_AWB_END_MSB             0x0b28
309 #define AFE_AWB_CUR_MSB             0x0b2c
310 #define AFE_VUL_BASE_MSB            0x0b30
311 #define AFE_VUL_END_MSB             0x0b38
312 #define AFE_VUL_CUR_MSB             0x0b3c
313 #define AFE_VUL2_BASE_MSB           0x0b50
314 #define AFE_VUL2_END_MSB            0x0b58
315 #define AFE_VUL2_CUR_MSB            0x0b5c
316 #define AFE_MOD_DAI_BASE_MSB        0x0b60
317 #define AFE_MOD_DAI_END_MSB         0x0b68
318 #define AFE_MOD_DAI_CUR_MSB         0x0b6c
319 #define AFE_VUL_D2_BASE_MSB         0x0b80
320 #define AFE_VUL_D2_END_MSB          0x0b88
321 #define AFE_VUL_D2_CUR_MSB          0x0b8c
322 #define AFE_DL3_BASE_MSB            0x0b90
323 #define AFE_DL3_CUR_MSB             0x0b94
324 #define AFE_DL3_END_MSB             0x0b98
325 #define AFE_HDMI_OUT_BASE_MSB       0x0ba4
326 #define AFE_HDMI_OUT_CUR_MSB        0x0ba8
327 #define AFE_HDMI_OUT_END_MSB        0x0bac
328 #define AFE_AWB2_BASE               0x0bd0
329 #define AFE_AWB2_END                0x0bd8
330 #define AFE_AWB2_CUR                0x0bdc
331 #define AFE_AWB2_BASE_MSB           0x0be0
332 #define AFE_AWB2_END_MSB            0x0be8
333 #define AFE_AWB2_CUR_MSB            0x0bec
334 #define AFE_ADDA_DL_SDM_DCCOMP_CON  0x0c50
335 #define AFE_ADDA_DL_SDM_TEST        0x0c54
336 #define AFE_ADDA_DL_DC_COMP_CFG0    0x0c58
337 #define AFE_ADDA_DL_DC_COMP_CFG1    0x0c5c
338 #define AFE_ADDA_DL_SDM_FIFO_MON    0x0c60
339 #define AFE_ADDA_DL_SRC_LCH_MON     0x0c64
340 #define AFE_ADDA_DL_SRC_RCH_MON     0x0c68
341 #define AFE_ADDA_DL_SDM_OUT_MON     0x0c6c
342 #define AFE_CONNSYS_I2S_CON         0x0c78
343 #define AFE_CONNSYS_I2S_MON         0x0c7c
344 #define AFE_ASRC_2CH_CON0           0x0c80
345 #define AFE_ASRC_2CH_CON1           0x0c84
346 #define AFE_ASRC_2CH_CON2           0x0c88
347 #define AFE_ASRC_2CH_CON3           0x0c8c
348 #define AFE_ASRC_2CH_CON4           0x0c90
349 #define AFE_ASRC_2CH_CON5           0x0c94
350 #define AFE_ASRC_2CH_CON6           0x0c98
351 #define AFE_ASRC_2CH_CON7           0x0c9c
352 #define AFE_ASRC_2CH_CON8           0x0ca0
353 #define AFE_ASRC_2CH_CON9           0x0ca4
354 #define AFE_ASRC_2CH_CON10          0x0ca8
355 #define AFE_ADDA6_IIR_COEF_02_01    0x0ce0
356 #define AFE_ADDA6_IIR_COEF_04_03    0x0ce4
357 #define AFE_ADDA6_IIR_COEF_06_05    0x0ce8
358 #define AFE_ADDA6_IIR_COEF_08_07    0x0cec
359 #define AFE_ADDA6_IIR_COEF_10_09    0x0cf0
360 #define AFE_ADDA_PREDIS_CON2        0x0d40
361 #define AFE_ADDA_PREDIS_CON3        0x0d44
362 #define AFE_MEMIF_MON12             0x0d70
363 #define AFE_MEMIF_MON13             0x0d74
364 #define AFE_MEMIF_MON14             0x0d78
365 #define AFE_MEMIF_MON15             0x0d7c
366 #define AFE_MEMIF_MON16             0x0d80
367 #define AFE_MEMIF_MON17             0x0d84
368 #define AFE_MEMIF_MON18             0x0d88
369 #define AFE_MEMIF_MON19             0x0d8c
370 #define AFE_MEMIF_MON20             0x0d90
371 #define AFE_MEMIF_MON21             0x0d94
372 #define AFE_MEMIF_MON22             0x0d98
373 #define AFE_MEMIF_MON23             0x0d9c
374 #define AFE_MEMIF_MON24             0x0da0
375 #define AFE_HD_ENGEN_ENABLE         0x0dd0
376 #define AFE_ADDA_MTKAIF_CFG0        0x0e00
377 #define AFE_ADDA_MTKAIF_TX_CFG1     0x0e14
378 #define AFE_ADDA_MTKAIF_RX_CFG0     0x0e20
379 #define AFE_ADDA_MTKAIF_RX_CFG1     0x0e24
380 #define AFE_ADDA_MTKAIF_RX_CFG2     0x0e28
381 #define AFE_ADDA_MTKAIF_MON0        0x0e34
382 #define AFE_ADDA_MTKAIF_MON1        0x0e38
383 #define AFE_AUD_PAD_TOP             0x0e40
384 #define AFE_GENERAL1_ASRC_2CH_CON0  0x0e80
385 #define AFE_GENERAL1_ASRC_2CH_CON1  0x0e84
386 #define AFE_GENERAL1_ASRC_2CH_CON2  0x0e88
387 #define AFE_GENERAL1_ASRC_2CH_CON3  0x0e8c
388 #define AFE_GENERAL1_ASRC_2CH_CON4  0x0e90
389 #define AFE_GENERAL1_ASRC_2CH_CON5  0x0e94
390 #define AFE_GENERAL1_ASRC_2CH_CON6  0x0e98
391 #define AFE_GENERAL1_ASRC_2CH_CON7  0x0e9c
392 #define AFE_GENERAL1_ASRC_2CH_CON8  0x0ea0
393 #define AFE_GENERAL1_ASRC_2CH_CON9  0x0ea4
394 #define AFE_GENERAL1_ASRC_2CH_CON10 0x0ea8
395 #define AFE_GENERAL1_ASRC_2CH_CON12 0x0eb0
396 #define AFE_GENERAL1_ASRC_2CH_CON13 0x0eb4
397 #define GENERAL_ASRC_MODE           0x0eb8
398 #define GENERAL_ASRC_EN_ON          0x0ebc
399 #define AFE_GENERAL2_ASRC_2CH_CON0  0x0f00
400 #define AFE_GENERAL2_ASRC_2CH_CON1  0x0f04
401 #define AFE_GENERAL2_ASRC_2CH_CON2  0x0f08
402 #define AFE_GENERAL2_ASRC_2CH_CON3  0x0f0c
403 #define AFE_GENERAL2_ASRC_2CH_CON4  0x0f10
404 #define AFE_GENERAL2_ASRC_2CH_CON5  0x0f14
405 #define AFE_GENERAL2_ASRC_2CH_CON6  0x0f18
406 #define AFE_GENERAL2_ASRC_2CH_CON7  0x0f1c
407 #define AFE_GENERAL2_ASRC_2CH_CON8  0x0f20
408 #define AFE_GENERAL2_ASRC_2CH_CON9  0x0f24
409 #define AFE_GENERAL2_ASRC_2CH_CON10 0x0f28
410 #define AFE_GENERAL2_ASRC_2CH_CON12 0x0f30
411 #define AFE_GENERAL2_ASRC_2CH_CON13 0x0f34
412 
413 #define AFE_MAX_REGISTER AFE_GENERAL2_ASRC_2CH_CON13
414 #define AFE_IRQ_STATUS_BITS 0x1fff
415 
416 /* AFE_DAC_CON0 */
417 #define AWB2_ON_SFT                                   29
418 #define AWB2_ON_MASK                                  0x1
419 #define AWB2_ON_MASK_SFT                              (0x1 << 29)
420 #define VUL2_ON_SFT                                   27
421 #define VUL2_ON_MASK                                  0x1
422 #define VUL2_ON_MASK_SFT                              (0x1 << 27)
423 #define MOD_DAI_DUP_WR_SFT                            26
424 #define MOD_DAI_DUP_WR_MASK                           0x1
425 #define MOD_DAI_DUP_WR_MASK_SFT                       (0x1 << 26)
426 #define VUL12_MODE_SFT                                20
427 #define VUL12_MODE_MASK                               0xf
428 #define VUL12_MODE_MASK_SFT                           (0xf << 20)
429 #define VUL12_R_MONO_SFT                              11
430 #define VUL12_R_MONO_MASK                             0x1
431 #define VUL12_R_MONO_MASK_SFT                         (0x1 << 11)
432 #define VUL12_MONO_SFT                                10
433 #define VUL12_MONO_MASK                               0x1
434 #define VUL12_MONO_MASK_SFT                           (0x1 << 10)
435 #define VUL12_ON_SFT                                  9
436 #define VUL12_ON_MASK                                 0x1
437 #define VUL12_ON_MASK_SFT                             (0x1 << 9)
438 #define MOD_DAI_ON_SFT                                7
439 #define MOD_DAI_ON_MASK                               0x1
440 #define MOD_DAI_ON_MASK_SFT                           (0x1 << 7)
441 #define AWB_ON_SFT                                    6
442 #define AWB_ON_MASK                                   0x1
443 #define AWB_ON_MASK_SFT                               (0x1 << 6)
444 #define DL3_ON_SFT                                    5
445 #define DL3_ON_MASK                                   0x1
446 #define DL3_ON_MASK_SFT                               (0x1 << 5)
447 #define VUL_ON_SFT                                    3
448 #define VUL_ON_MASK                                   0x1
449 #define VUL_ON_MASK_SFT                               (0x1 << 3)
450 #define DL2_ON_SFT                                    2
451 #define DL2_ON_MASK                                   0x1
452 #define DL2_ON_MASK_SFT                               (0x1 << 2)
453 #define DL1_ON_SFT                                    1
454 #define DL1_ON_MASK                                   0x1
455 #define DL1_ON_MASK_SFT                               (0x1 << 1)
456 #define AFE_ON_SFT                                    0
457 #define AFE_ON_MASK                                   0x1
458 #define AFE_ON_MASK_SFT                               (0x1 << 0)
459 
460 /* AFE_DAC_CON1 */
461 #define MOD_DAI_MODE_SFT                              30
462 #define MOD_DAI_MODE_MASK                             0x3
463 #define MOD_DAI_MODE_MASK_SFT                         (0x3 << 30)
464 #define VUL_R_MONO_SFT                                28
465 #define VUL_R_MONO_MASK                               0x1
466 #define VUL_R_MONO_MASK_SFT                           (0x1 << 28)
467 #define VUL_DATA_SFT                                  27
468 #define VUL_DATA_MASK                                 0x1
469 #define VUL_DATA_MASK_SFT                             (0x1 << 27)
470 #define AWB_R_MONO_SFT                                25
471 #define AWB_R_MONO_MASK                               0x1
472 #define AWB_R_MONO_MASK_SFT                           (0x1 << 25)
473 #define AWB_DATA_SFT                                  24
474 #define AWB_DATA_MASK                                 0x1
475 #define AWB_DATA_MASK_SFT                             (0x1 << 24)
476 #define DL3_DATA_SFT                                  23
477 #define DL3_DATA_MASK                                 0x1
478 #define DL3_DATA_MASK_SFT                             (0x1 << 23)
479 #define DL2_DATA_SFT                                  22
480 #define DL2_DATA_MASK                                 0x1
481 #define DL2_DATA_MASK_SFT                             (0x1 << 22)
482 #define DL1_DATA_SFT                                  21
483 #define DL1_DATA_MASK                                 0x1
484 #define DL1_DATA_MASK_SFT                             (0x1 << 21)
485 #define VUL_MODE_SFT                                  16
486 #define VUL_MODE_MASK                                 0xf
487 #define VUL_MODE_MASK_SFT                             (0xf << 16)
488 #define AWB_MODE_SFT                                  12
489 #define AWB_MODE_MASK                                 0xf
490 #define AWB_MODE_MASK_SFT                             (0xf << 12)
491 #define I2S_MODE_SFT                                  8
492 #define I2S_MODE_MASK                                 0xf
493 #define I2S_MODE_MASK_SFT                             (0xf << 8)
494 #define DL2_MODE_SFT                                  4
495 #define DL2_MODE_MASK                                 0xf
496 #define DL2_MODE_MASK_SFT                             (0xf << 4)
497 #define DL1_MODE_SFT                                  0
498 #define DL1_MODE_MASK                                 0xf
499 #define DL1_MODE_MASK_SFT                             (0xf << 0)
500 
501 /* AFE_DAC_CON2 */
502 #define AWB2_R_MONO_SFT                               21
503 #define AWB2_R_MONO_MASK                              0x1
504 #define AWB2_R_MONO_MASK_SFT                          (0x1 << 21)
505 #define AWB2_DATA_SFT                                 20
506 #define AWB2_DATA_MASK                                0x1
507 #define AWB2_DATA_MASK_SFT                            (0x1 << 20)
508 #define AWB2_MODE_SFT                                 16
509 #define AWB2_MODE_MASK                                0xf
510 #define AWB2_MODE_MASK_SFT                            (0xf << 16)
511 #define DL3_MODE_SFT                                  8
512 #define DL3_MODE_MASK                                 0xf
513 #define DL3_MODE_MASK_SFT                             (0xf << 8)
514 #define VUL2_MODE_SFT                                 4
515 #define VUL2_MODE_MASK                                0xf
516 #define VUL2_MODE_MASK_SFT                            (0xf << 4)
517 #define VUL2_R_MONO_SFT                               1
518 #define VUL2_R_MONO_MASK                              0x1
519 #define VUL2_R_MONO_MASK_SFT                          (0x1 << 1)
520 #define VUL2_DATA_SFT                                 0
521 #define VUL2_DATA_MASK                                0x1
522 #define VUL2_DATA_MASK_SFT                            (0x1 << 0)
523 
524 /* AFE_DAC_MON */
525 #define AFE_ON_RETM_SFT                               0
526 #define AFE_ON_RETM_MASK                              0x1
527 #define AFE_ON_RETM_MASK_SFT                          (0x1 << 0)
528 
529 /* AFE_I2S_CON */
530 #define BCK_NEG_EG_LATCH_SFT                          30
531 #define BCK_NEG_EG_LATCH_MASK                         0x1
532 #define BCK_NEG_EG_LATCH_MASK_SFT                     (0x1 << 30)
533 #define BCK_INV_SFT                                   29
534 #define BCK_INV_MASK                                  0x1
535 #define BCK_INV_MASK_SFT                              (0x1 << 29)
536 #define I2SIN_PAD_SEL_SFT                             28
537 #define I2SIN_PAD_SEL_MASK                            0x1
538 #define I2SIN_PAD_SEL_MASK_SFT                        (0x1 << 28)
539 #define I2S_LOOPBACK_SFT                              20
540 #define I2S_LOOPBACK_MASK                             0x1
541 #define I2S_LOOPBACK_MASK_SFT                         (0x1 << 20)
542 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT             17
543 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK            0x1
544 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT        (0x1 << 17)
545 #define I2S1_HD_EN_SFT                                12
546 #define I2S1_HD_EN_MASK                               0x1
547 #define I2S1_HD_EN_MASK_SFT                           (0x1 << 12)
548 #define INV_PAD_CTRL_SFT                              7
549 #define INV_PAD_CTRL_MASK                             0x1
550 #define INV_PAD_CTRL_MASK_SFT                         (0x1 << 7)
551 #define I2S_BYPSRC_SFT                                6
552 #define I2S_BYPSRC_MASK                               0x1
553 #define I2S_BYPSRC_MASK_SFT                           (0x1 << 6)
554 #define INV_LRCK_SFT                                  5
555 #define INV_LRCK_MASK                                 0x1
556 #define INV_LRCK_MASK_SFT                             (0x1 << 5)
557 #define I2S_FMT_SFT                                   3
558 #define I2S_FMT_MASK                                  0x1
559 #define I2S_FMT_MASK_SFT                              (0x1 << 3)
560 #define I2S_SRC_SFT                                   2
561 #define I2S_SRC_MASK                                  0x1
562 #define I2S_SRC_MASK_SFT                              (0x1 << 2)
563 #define I2S_WLEN_SFT                                  1
564 #define I2S_WLEN_MASK                                 0x1
565 #define I2S_WLEN_MASK_SFT                             (0x1 << 1)
566 #define I2S_EN_SFT                                    0
567 #define I2S_EN_MASK                                   0x1
568 #define I2S_EN_MASK_SFT                               (0x1 << 0)
569 
570 /* AFE_I2S_CON1 */
571 #define I2S2_LR_SWAP_SFT                              31
572 #define I2S2_LR_SWAP_MASK                             0x1
573 #define I2S2_LR_SWAP_MASK_SFT                         (0x1 << 31)
574 #define I2S2_SEL_O19_O20_SFT                          18
575 #define I2S2_SEL_O19_O20_MASK                         0x1
576 #define I2S2_SEL_O19_O20_MASK_SFT                     (0x1 << 18)
577 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT             17
578 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK            0x1
579 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT        (0x1 << 17)
580 #define I2S2_SEL_O03_O04_SFT                          16
581 #define I2S2_SEL_O03_O04_MASK                         0x1
582 #define I2S2_SEL_O03_O04_MASK_SFT                     (0x1 << 16)
583 #define I2S2_32BIT_EN_SFT                             13
584 #define I2S2_32BIT_EN_MASK                            0x1
585 #define I2S2_32BIT_EN_MASK_SFT                        (0x1 << 13)
586 #define I2S2_HD_EN_SFT                                12
587 #define I2S2_HD_EN_MASK                               0x1
588 #define I2S2_HD_EN_MASK_SFT                           (0x1 << 12)
589 #define I2S2_OUT_MODE_SFT                             8
590 #define I2S2_OUT_MODE_MASK                            0xf
591 #define I2S2_OUT_MODE_MASK_SFT                        (0xf << 8)
592 #define INV_LRCK_SFT                                  5
593 #define INV_LRCK_MASK                                 0x1
594 #define INV_LRCK_MASK_SFT                             (0x1 << 5)
595 #define I2S2_FMT_SFT                                  3
596 #define I2S2_FMT_MASK                                 0x1
597 #define I2S2_FMT_MASK_SFT                             (0x1 << 3)
598 #define I2S2_WLEN_SFT                                 1
599 #define I2S2_WLEN_MASK                                0x1
600 #define I2S2_WLEN_MASK_SFT                            (0x1 << 1)
601 #define I2S2_EN_SFT                                   0
602 #define I2S2_EN_MASK                                  0x1
603 #define I2S2_EN_MASK_SFT                              (0x1 << 0)
604 
605 /* AFE_I2S_CON2 */
606 #define I2S3_LR_SWAP_SFT                              31
607 #define I2S3_LR_SWAP_MASK                             0x1
608 #define I2S3_LR_SWAP_MASK_SFT                         (0x1 << 31)
609 #define I2S3_UPDATE_WORD_SFT                          24
610 #define I2S3_UPDATE_WORD_MASK                         0x1f
611 #define I2S3_UPDATE_WORD_MASK_SFT                     (0x1f << 24)
612 #define I2S3_BCK_INV_SFT                              23
613 #define I2S3_BCK_INV_MASK                             0x1
614 #define I2S3_BCK_INV_MASK_SFT                         (0x1 << 23)
615 #define I2S3_FPGA_BIT_TEST_SFT                        22
616 #define I2S3_FPGA_BIT_TEST_MASK                       0x1
617 #define I2S3_FPGA_BIT_TEST_MASK_SFT                   (0x1 << 22)
618 #define I2S3_FPGA_BIT_SFT                             21
619 #define I2S3_FPGA_BIT_MASK                            0x1
620 #define I2S3_FPGA_BIT_MASK_SFT                        (0x1 << 21)
621 #define I2S3_LOOPBACK_SFT                             20
622 #define I2S3_LOOPBACK_MASK                            0x1
623 #define I2S3_LOOPBACK_MASK_SFT                        (0x1 << 20)
624 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT             17
625 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK            0x1
626 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT        (0x1 << 17)
627 #define I2S3_HD_EN_SFT                                12
628 #define I2S3_HD_EN_MASK                               0x1
629 #define I2S3_HD_EN_MASK_SFT                           (0x1 << 12)
630 #define I2S3_OUT_MODE_SFT                             8
631 #define I2S3_OUT_MODE_MASK                            0xf
632 #define I2S3_OUT_MODE_MASK_SFT                        (0xf << 8)
633 #define I2S3_FMT_SFT                                  3
634 #define I2S3_FMT_MASK                                 0x1
635 #define I2S3_FMT_MASK_SFT                             (0x1 << 3)
636 #define I2S3_WLEN_SFT                                 1
637 #define I2S3_WLEN_MASK                                0x1
638 #define I2S3_WLEN_MASK_SFT                            (0x1 << 1)
639 #define I2S3_EN_SFT                                   0
640 #define I2S3_EN_MASK                                  0x1
641 #define I2S3_EN_MASK_SFT                              (0x1 << 0)
642 
643 /* AFE_I2S_CON3 */
644 #define I2S4_LR_SWAP_SFT                              31
645 #define I2S4_LR_SWAP_MASK                             0x1
646 #define I2S4_LR_SWAP_MASK_SFT                         (0x1 << 31)
647 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT             17
648 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK            0x1
649 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT        (0x1 << 17)
650 #define I2S4_32BIT_EN_SFT                             13
651 #define I2S4_32BIT_EN_MASK                            0x1
652 #define I2S4_32BIT_EN_MASK_SFT                        (0x1 << 13)
653 #define I2S4_HD_EN_SFT                                12
654 #define I2S4_HD_EN_MASK                               0x1
655 #define I2S4_HD_EN_MASK_SFT                           (0x1 << 12)
656 #define I2S4_OUT_MODE_SFT                             8
657 #define I2S4_OUT_MODE_MASK                            0xf
658 #define I2S4_OUT_MODE_MASK_SFT                        (0xf << 8)
659 #define INV_LRCK_SFT                                  5
660 #define INV_LRCK_MASK                                 0x1
661 #define INV_LRCK_MASK_SFT                             (0x1 << 5)
662 #define I2S4_FMT_SFT                                  3
663 #define I2S4_FMT_MASK                                 0x1
664 #define I2S4_FMT_MASK_SFT                             (0x1 << 3)
665 #define I2S4_WLEN_SFT                                 1
666 #define I2S4_WLEN_MASK                                0x1
667 #define I2S4_WLEN_MASK_SFT                            (0x1 << 1)
668 #define I2S4_EN_SFT                                   0
669 #define I2S4_EN_MASK                                  0x1
670 #define I2S4_EN_MASK_SFT                              (0x1 << 0)
671 
672 /* AFE_I2S_CON4 */
673 #define I2S5_LR_SWAP_SFT                              31
674 #define I2S5_LR_SWAP_MASK                             0x1
675 #define I2S5_LR_SWAP_MASK_SFT                         (0x1 << 31)
676 #define I2S_LOOPBACK_SFT                              20
677 #define I2S_LOOPBACK_MASK                             0x1
678 #define I2S_LOOPBACK_MASK_SFT                         (0x1 << 20)
679 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT             17
680 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK            0x1
681 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT        (0x1 << 17)
682 #define I2S5_32BIT_EN_SFT                             13
683 #define I2S5_32BIT_EN_MASK                            0x1
684 #define I2S5_32BIT_EN_MASK_SFT                        (0x1 << 13)
685 #define I2S5_HD_EN_SFT                                12
686 #define I2S5_HD_EN_MASK                               0x1
687 #define I2S5_HD_EN_MASK_SFT                           (0x1 << 12)
688 #define I2S5_OUT_MODE_SFT                             8
689 #define I2S5_OUT_MODE_MASK                            0xf
690 #define I2S5_OUT_MODE_MASK_SFT                        (0xf << 8)
691 #define INV_LRCK_SFT                                  5
692 #define INV_LRCK_MASK                                 0x1
693 #define INV_LRCK_MASK_SFT                             (0x1 << 5)
694 #define I2S5_FMT_SFT                                  3
695 #define I2S5_FMT_MASK                                 0x1
696 #define I2S5_FMT_MASK_SFT                             (0x1 << 3)
697 #define I2S5_WLEN_SFT                                 1
698 #define I2S5_WLEN_MASK                                0x1
699 #define I2S5_WLEN_MASK_SFT                            (0x1 << 1)
700 #define I2S5_EN_SFT                                   0
701 #define I2S5_EN_MASK                                  0x1
702 #define I2S5_EN_MASK_SFT                              (0x1 << 0)
703 
704 /* AFE_GAIN1_CON0 */
705 #define GAIN1_SAMPLE_PER_STEP_SFT                     8
706 #define GAIN1_SAMPLE_PER_STEP_MASK                    0xff
707 #define GAIN1_SAMPLE_PER_STEP_MASK_SFT                (0xff << 8)
708 #define GAIN1_MODE_SFT                                4
709 #define GAIN1_MODE_MASK                               0xf
710 #define GAIN1_MODE_MASK_SFT                           (0xf << 4)
711 #define GAIN1_ON_SFT                                  0
712 #define GAIN1_ON_MASK                                 0x1
713 #define GAIN1_ON_MASK_SFT                             (0x1 << 0)
714 
715 /* AFE_GAIN1_CON1 */
716 #define GAIN1_TARGET_SFT                              0
717 #define GAIN1_TARGET_MASK                             0xfffff
718 #define GAIN1_TARGET_MASK_SFT                         (0xfffff << 0)
719 
720 /* AFE_GAIN2_CON0 */
721 #define GAIN2_SAMPLE_PER_STEP_SFT                     8
722 #define GAIN2_SAMPLE_PER_STEP_MASK                    0xff
723 #define GAIN2_SAMPLE_PER_STEP_MASK_SFT                (0xff << 8)
724 #define GAIN2_MODE_SFT                                4
725 #define GAIN2_MODE_MASK                               0xf
726 #define GAIN2_MODE_MASK_SFT                           (0xf << 4)
727 #define GAIN2_ON_SFT                                  0
728 #define GAIN2_ON_MASK                                 0x1
729 #define GAIN2_ON_MASK_SFT                             (0x1 << 0)
730 
731 /* AFE_GAIN2_CON1 */
732 #define GAIN2_TARGET_SFT                              0
733 #define GAIN2_TARGET_MASK                             0xfffff
734 #define GAIN2_TARGET_MASK_SFT                         (0xfffff << 0)
735 
736 /* AFE_GAIN1_CUR */
737 #define AFE_GAIN1_CUR_SFT                             0
738 #define AFE_GAIN1_CUR_MASK                            0xfffff
739 #define AFE_GAIN1_CUR_MASK_SFT                        (0xfffff << 0)
740 
741 /* AFE_GAIN2_CUR */
742 #define AFE_GAIN2_CUR_SFT                             0
743 #define AFE_GAIN2_CUR_MASK                            0xfffff
744 #define AFE_GAIN2_CUR_MASK_SFT                        (0xfffff << 0)
745 
746 /* AFE_MEMIF_HD_MODE */
747 #define AWB2_HD_SFT                                   28
748 #define AWB2_HD_MASK                                  0x3
749 #define AWB2_HD_MASK_SFT                              (0x3 << 28)
750 #define HDMI_HD_SFT                                   20
751 #define HDMI_HD_MASK                                  0x3
752 #define HDMI_HD_MASK_SFT                              (0x3 << 20)
753 #define MOD_DAI_HD_SFT                                18
754 #define MOD_DAI_HD_MASK                               0x3
755 #define MOD_DAI_HD_MASK_SFT                           (0x3 << 18)
756 #define DAI_HD_SFT                                    16
757 #define DAI_HD_MASK                                   0x3
758 #define DAI_HD_MASK_SFT                               (0x3 << 16)
759 #define VUL2_HD_SFT                                   14
760 #define VUL2_HD_MASK                                  0x3
761 #define VUL2_HD_MASK_SFT                              (0x3 << 14)
762 #define VUL12_HD_SFT                                  12
763 #define VUL12_HD_MASK                                 0x3
764 #define VUL12_HD_MASK_SFT                             (0x3 << 12)
765 #define VUL_HD_SFT                                    10
766 #define VUL_HD_MASK                                   0x3
767 #define VUL_HD_MASK_SFT                               (0x3 << 10)
768 #define AWB_HD_SFT                                    8
769 #define AWB_HD_MASK                                   0x3
770 #define AWB_HD_MASK_SFT                               (0x3 << 8)
771 #define DL3_HD_SFT                                    6
772 #define DL3_HD_MASK                                   0x3
773 #define DL3_HD_MASK_SFT                               (0x3 << 6)
774 #define DL2_HD_SFT                                    4
775 #define DL2_HD_MASK                                   0x3
776 #define DL2_HD_MASK_SFT                               (0x3 << 4)
777 #define DL1_HD_SFT                                    0
778 #define DL1_HD_MASK                                   0x3
779 #define DL1_HD_MASK_SFT                               (0x3 << 0)
780 
781 /* AFE_MEMIF_HDALIGN */
782 #define AWB2_NORMAL_MODE_SFT                          30
783 #define AWB2_NORMAL_MODE_MASK                         0x1
784 #define AWB2_NORMAL_MODE_MASK_SFT                     (0x1 << 30)
785 #define HDMI_NORMAL_MODE_SFT                          26
786 #define HDMI_NORMAL_MODE_MASK                         0x1
787 #define HDMI_NORMAL_MODE_MASK_SFT                     (0x1 << 26)
788 #define MOD_DAI_NORMAL_MODE_SFT                       25
789 #define MOD_DAI_NORMAL_MODE_MASK                      0x1
790 #define MOD_DAI_NORMAL_MODE_MASK_SFT                  (0x1 << 25)
791 #define DAI_NORMAL_MODE_SFT                           24
792 #define DAI_NORMAL_MODE_MASK                          0x1
793 #define DAI_NORMAL_MODE_MASK_SFT                      (0x1 << 24)
794 #define VUL2_NORMAL_MODE_SFT                          23
795 #define VUL2_NORMAL_MODE_MASK                         0x1
796 #define VUL2_NORMAL_MODE_MASK_SFT                     (0x1 << 23)
797 #define VUL12_NORMAL_MODE_SFT                         22
798 #define VUL12_NORMAL_MODE_MASK                        0x1
799 #define VUL12_NORMAL_MODE_MASK_SFT                    (0x1 << 22)
800 #define VUL_NORMAL_MODE_SFT                           21
801 #define VUL_NORMAL_MODE_MASK                          0x1
802 #define VUL_NORMAL_MODE_MASK_SFT                      (0x1 << 21)
803 #define AWB_NORMAL_MODE_SFT                           20
804 #define AWB_NORMAL_MODE_MASK                          0x1
805 #define AWB_NORMAL_MODE_MASK_SFT                      (0x1 << 20)
806 #define DL3_NORMAL_MODE_SFT                           19
807 #define DL3_NORMAL_MODE_MASK                          0x1
808 #define DL3_NORMAL_MODE_MASK_SFT                      (0x1 << 19)
809 #define DL2_NORMAL_MODE_SFT                           18
810 #define DL2_NORMAL_MODE_MASK                          0x1
811 #define DL2_NORMAL_MODE_MASK_SFT                      (0x1 << 18)
812 #define DL1_NORMAL_MODE_SFT                           16
813 #define DL1_NORMAL_MODE_MASK                          0x1
814 #define DL1_NORMAL_MODE_MASK_SFT                      (0x1 << 16)
815 #define RESERVED1_SFT                                 15
816 #define RESERVED1_MASK                                0x1
817 #define RESERVED1_MASK_SFT                            (0x1 << 15)
818 #define AWB2_ALIGN_SFT                                14
819 #define AWB2_ALIGN_MASK                               0x1
820 #define AWB2_ALIGN_MASK_SFT                           (0x1 << 14)
821 #define HDMI_HD_ALIGN_SFT                             10
822 #define HDMI_HD_ALIGN_MASK                            0x1
823 #define HDMI_HD_ALIGN_MASK_SFT                        (0x1 << 10)
824 #define MOD_DAI_HD_ALIGN_SFT                          9
825 #define MOD_DAI_HD_ALIGN_MASK                         0x1
826 #define MOD_DAI_HD_ALIGN_MASK_SFT                     (0x1 << 9)
827 #define VUL2_HD_ALIGN_SFT                             7
828 #define VUL2_HD_ALIGN_MASK                            0x1
829 #define VUL2_HD_ALIGN_MASK_SFT                        (0x1 << 7)
830 #define VUL12_HD_ALIGN_SFT                            6
831 #define VUL12_HD_ALIGN_MASK                           0x1
832 #define VUL12_HD_ALIGN_MASK_SFT                       (0x1 << 6)
833 #define VUL_HD_ALIGN_SFT                              5
834 #define VUL_HD_ALIGN_MASK                             0x1
835 #define VUL_HD_ALIGN_MASK_SFT                         (0x1 << 5)
836 #define AWB_HD_ALIGN_SFT                              4
837 #define AWB_HD_ALIGN_MASK                             0x1
838 #define AWB_HD_ALIGN_MASK_SFT                         (0x1 << 4)
839 #define DL3_HD_ALIGN_SFT                              3
840 #define DL3_HD_ALIGN_MASK                             0x1
841 #define DL3_HD_ALIGN_MASK_SFT                         (0x1 << 3)
842 #define DL2_HD_ALIGN_SFT                              2
843 #define DL2_HD_ALIGN_MASK                             0x1
844 #define DL2_HD_ALIGN_MASK_SFT                         (0x1 << 2)
845 #define DL1_HD_ALIGN_SFT                              0
846 #define DL1_HD_ALIGN_MASK                             0x1
847 #define DL1_HD_ALIGN_MASK_SFT                         (0x1 << 0)
848 
849 /* PCM_INTF_CON1 */
850 #define PCM_FIX_VALUE_SEL_SFT                         31
851 #define PCM_FIX_VALUE_SEL_MASK                        0x1
852 #define PCM_FIX_VALUE_SEL_MASK_SFT                    (0x1 << 31)
853 #define PCM_BUFFER_LOOPBACK_SFT                       30
854 #define PCM_BUFFER_LOOPBACK_MASK                      0x1
855 #define PCM_BUFFER_LOOPBACK_MASK_SFT                  (0x1 << 30)
856 #define PCM_PARALLEL_LOOPBACK_SFT                     29
857 #define PCM_PARALLEL_LOOPBACK_MASK                    0x1
858 #define PCM_PARALLEL_LOOPBACK_MASK_SFT                (0x1 << 29)
859 #define PCM_SERIAL_LOOPBACK_SFT                       28
860 #define PCM_SERIAL_LOOPBACK_MASK                      0x1
861 #define PCM_SERIAL_LOOPBACK_MASK_SFT                  (0x1 << 28)
862 #define PCM_DAI_PCM_LOOPBACK_SFT                      27
863 #define PCM_DAI_PCM_LOOPBACK_MASK                     0x1
864 #define PCM_DAI_PCM_LOOPBACK_MASK_SFT                 (0x1 << 27)
865 #define PCM_I2S_PCM_LOOPBACK_SFT                      26
866 #define PCM_I2S_PCM_LOOPBACK_MASK                     0x1
867 #define PCM_I2S_PCM_LOOPBACK_MASK_SFT                 (0x1 << 26)
868 #define PCM_SYNC_DELSEL_SFT                           25
869 #define PCM_SYNC_DELSEL_MASK                          0x1
870 #define PCM_SYNC_DELSEL_MASK_SFT                      (0x1 << 25)
871 #define PCM_TX_LR_SWAP_SFT                            24
872 #define PCM_TX_LR_SWAP_MASK                           0x1
873 #define PCM_TX_LR_SWAP_MASK_SFT                       (0x1 << 24)
874 #define PCM_SYNC_OUT_INV_SFT                          23
875 #define PCM_SYNC_OUT_INV_MASK                         0x1
876 #define PCM_SYNC_OUT_INV_MASK_SFT                     (0x1 << 23)
877 #define PCM_BCLK_OUT_INV_SFT                          22
878 #define PCM_BCLK_OUT_INV_MASK                         0x1
879 #define PCM_BCLK_OUT_INV_MASK_SFT                     (0x1 << 22)
880 #define PCM_SYNC_IN_INV_SFT                           21
881 #define PCM_SYNC_IN_INV_MASK                          0x1
882 #define PCM_SYNC_IN_INV_MASK_SFT                      (0x1 << 21)
883 #define PCM_BCLK_IN_INV_SFT                           20
884 #define PCM_BCLK_IN_INV_MASK                          0x1
885 #define PCM_BCLK_IN_INV_MASK_SFT                      (0x1 << 20)
886 #define PCM_TX_LCH_RPT_SFT                            19
887 #define PCM_TX_LCH_RPT_MASK                           0x1
888 #define PCM_TX_LCH_RPT_MASK_SFT                       (0x1 << 19)
889 #define PCM_VBT_16K_MODE_SFT                          18
890 #define PCM_VBT_16K_MODE_MASK                         0x1
891 #define PCM_VBT_16K_MODE_MASK_SFT                     (0x1 << 18)
892 #define PCM_EXT_MODEM_SFT                             17
893 #define PCM_EXT_MODEM_MASK                            0x1
894 #define PCM_EXT_MODEM_MASK_SFT                        (0x1 << 17)
895 #define PCM_24BIT_SFT                                 16
896 #define PCM_24BIT_MASK                                0x1
897 #define PCM_24BIT_MASK_SFT                            (0x1 << 16)
898 #define PCM_WLEN_SFT                                  14
899 #define PCM_WLEN_MASK                                 0x3
900 #define PCM_WLEN_MASK_SFT                             (0x3 << 14)
901 #define PCM_SYNC_LENGTH_SFT                           9
902 #define PCM_SYNC_LENGTH_MASK                          0x1f
903 #define PCM_SYNC_LENGTH_MASK_SFT                      (0x1f << 9)
904 #define PCM_SYNC_TYPE_SFT                             8
905 #define PCM_SYNC_TYPE_MASK                            0x1
906 #define PCM_SYNC_TYPE_MASK_SFT                        (0x1 << 8)
907 #define PCM_BT_MODE_SFT                               7
908 #define PCM_BT_MODE_MASK                              0x1
909 #define PCM_BT_MODE_MASK_SFT                          (0x1 << 7)
910 #define PCM_BYP_ASRC_SFT                              6
911 #define PCM_BYP_ASRC_MASK                             0x1
912 #define PCM_BYP_ASRC_MASK_SFT                         (0x1 << 6)
913 #define PCM_SLAVE_SFT                                 5
914 #define PCM_SLAVE_MASK                                0x1
915 #define PCM_SLAVE_MASK_SFT                            (0x1 << 5)
916 #define PCM_MODE_SFT                                  3
917 #define PCM_MODE_MASK                                 0x3
918 #define PCM_MODE_MASK_SFT                             (0x3 << 3)
919 #define PCM_FMT_SFT                                   1
920 #define PCM_FMT_MASK                                  0x3
921 #define PCM_FMT_MASK_SFT                              (0x3 << 1)
922 #define PCM_EN_SFT                                    0
923 #define PCM_EN_MASK                                   0x1
924 #define PCM_EN_MASK_SFT                               (0x1 << 0)
925 
926 /* PCM_INTF_CON2 */
927 #define PCM1_TX_FIFO_OV_SFT                           31
928 #define PCM1_TX_FIFO_OV_MASK                          0x1
929 #define PCM1_TX_FIFO_OV_MASK_SFT                      (0x1 << 31)
930 #define PCM1_RX_FIFO_OV_SFT                           30
931 #define PCM1_RX_FIFO_OV_MASK                          0x1
932 #define PCM1_RX_FIFO_OV_MASK_SFT                      (0x1 << 30)
933 #define PCM2_TX_FIFO_OV_SFT                           29
934 #define PCM2_TX_FIFO_OV_MASK                          0x1
935 #define PCM2_TX_FIFO_OV_MASK_SFT                      (0x1 << 29)
936 #define PCM2_RX_FIFO_OV_SFT                           28
937 #define PCM2_RX_FIFO_OV_MASK                          0x1
938 #define PCM2_RX_FIFO_OV_MASK_SFT                      (0x1 << 28)
939 #define PCM1_SYNC_GLITCH_SFT                          27
940 #define PCM1_SYNC_GLITCH_MASK                         0x1
941 #define PCM1_SYNC_GLITCH_MASK_SFT                     (0x1 << 27)
942 #define PCM2_SYNC_GLITCH_SFT                          26
943 #define PCM2_SYNC_GLITCH_MASK                         0x1
944 #define PCM2_SYNC_GLITCH_MASK_SFT                     (0x1 << 26)
945 #define TX3_RCH_DBG_MODE_SFT                          17
946 #define TX3_RCH_DBG_MODE_MASK                         0x1
947 #define TX3_RCH_DBG_MODE_MASK_SFT                     (0x1 << 17)
948 #define PCM1_PCM2_LOOPBACK_SFT                        16
949 #define PCM1_PCM2_LOOPBACK_MASK                       0x1
950 #define PCM1_PCM2_LOOPBACK_MASK_SFT                   (0x1 << 16)
951 #define DAI_PCM_LOOPBACK_CH_SFT                       14
952 #define DAI_PCM_LOOPBACK_CH_MASK                      0x3
953 #define DAI_PCM_LOOPBACK_CH_MASK_SFT                  (0x3 << 14)
954 #define I2S_PCM_LOOPBACK_CH_SFT                       12
955 #define I2S_PCM_LOOPBACK_CH_MASK                      0x3
956 #define I2S_PCM_LOOPBACK_CH_MASK_SFT                  (0x3 << 12)
957 #define TX_FIX_VALUE_SFT                              0
958 #define TX_FIX_VALUE_MASK                             0xff
959 #define TX_FIX_VALUE_MASK_SFT                         (0xff << 0)
960 
961 /* PCM2_INTF_CON */
962 #define PCM2_TX_FIX_VALUE_SFT                         24
963 #define PCM2_TX_FIX_VALUE_MASK                        0xff
964 #define PCM2_TX_FIX_VALUE_MASK_SFT                    (0xff << 24)
965 #define PCM2_FIX_VALUE_SEL_SFT                        23
966 #define PCM2_FIX_VALUE_SEL_MASK                       0x1
967 #define PCM2_FIX_VALUE_SEL_MASK_SFT                   (0x1 << 23)
968 #define PCM2_BUFFER_LOOPBACK_SFT                      22
969 #define PCM2_BUFFER_LOOPBACK_MASK                     0x1
970 #define PCM2_BUFFER_LOOPBACK_MASK_SFT                 (0x1 << 22)
971 #define PCM2_PARALLEL_LOOPBACK_SFT                    21
972 #define PCM2_PARALLEL_LOOPBACK_MASK                   0x1
973 #define PCM2_PARALLEL_LOOPBACK_MASK_SFT               (0x1 << 21)
974 #define PCM2_SERIAL_LOOPBACK_SFT                      20
975 #define PCM2_SERIAL_LOOPBACK_MASK                     0x1
976 #define PCM2_SERIAL_LOOPBACK_MASK_SFT                 (0x1 << 20)
977 #define PCM2_DAI_PCM_LOOPBACK_SFT                     19
978 #define PCM2_DAI_PCM_LOOPBACK_MASK                    0x1
979 #define PCM2_DAI_PCM_LOOPBACK_MASK_SFT                (0x1 << 19)
980 #define PCM2_I2S_PCM_LOOPBACK_SFT                     18
981 #define PCM2_I2S_PCM_LOOPBACK_MASK                    0x1
982 #define PCM2_I2S_PCM_LOOPBACK_MASK_SFT                (0x1 << 18)
983 #define PCM2_SYNC_DELSEL_SFT                          17
984 #define PCM2_SYNC_DELSEL_MASK                         0x1
985 #define PCM2_SYNC_DELSEL_MASK_SFT                     (0x1 << 17)
986 #define PCM2_TX_LR_SWAP_SFT                           16
987 #define PCM2_TX_LR_SWAP_MASK                          0x1
988 #define PCM2_TX_LR_SWAP_MASK_SFT                      (0x1 << 16)
989 #define PCM2_SYNC_IN_INV_SFT                          15
990 #define PCM2_SYNC_IN_INV_MASK                         0x1
991 #define PCM2_SYNC_IN_INV_MASK_SFT                     (0x1 << 15)
992 #define PCM2_BCLK_IN_INV_SFT                          14
993 #define PCM2_BCLK_IN_INV_MASK                         0x1
994 #define PCM2_BCLK_IN_INV_MASK_SFT                     (0x1 << 14)
995 #define PCM2_TX_LCH_RPT_SFT                           13
996 #define PCM2_TX_LCH_RPT_MASK                          0x1
997 #define PCM2_TX_LCH_RPT_MASK_SFT                      (0x1 << 13)
998 #define PCM2_VBT_16K_MODE_SFT                         12
999 #define PCM2_VBT_16K_MODE_MASK                        0x1
1000 #define PCM2_VBT_16K_MODE_MASK_SFT                    (0x1 << 12)
1001 #define PCM2_LOOPBACK_CH_SEL_SFT                      10
1002 #define PCM2_LOOPBACK_CH_SEL_MASK                     0x3
1003 #define PCM2_LOOPBACK_CH_SEL_MASK_SFT                 (0x3 << 10)
1004 #define PCM2_TX2_BT_MODE_SFT                          8
1005 #define PCM2_TX2_BT_MODE_MASK                         0x1
1006 #define PCM2_TX2_BT_MODE_MASK_SFT                     (0x1 << 8)
1007 #define PCM2_BT_MODE_SFT                              7
1008 #define PCM2_BT_MODE_MASK                             0x1
1009 #define PCM2_BT_MODE_MASK_SFT                         (0x1 << 7)
1010 #define PCM2_AFIFO_SFT                                6
1011 #define PCM2_AFIFO_MASK                               0x1
1012 #define PCM2_AFIFO_MASK_SFT                           (0x1 << 6)
1013 #define PCM2_WLEN_SFT                                 5
1014 #define PCM2_WLEN_MASK                                0x1
1015 #define PCM2_WLEN_MASK_SFT                            (0x1 << 5)
1016 #define PCM2_MODE_SFT                                 3
1017 #define PCM2_MODE_MASK                                0x3
1018 #define PCM2_MODE_MASK_SFT                            (0x3 << 3)
1019 #define PCM2_FMT_SFT                                  1
1020 #define PCM2_FMT_MASK                                 0x3
1021 #define PCM2_FMT_MASK_SFT                             (0x3 << 1)
1022 #define PCM2_EN_SFT                                   0
1023 #define PCM2_EN_MASK                                  0x1
1024 #define PCM2_EN_MASK_SFT                              (0x1 << 0)
1025 
1026 /* AFE_ADDA_MTKAIF_CFG0 */
1027 #define MTKAIF_RXIF_CLKINV_ADC_SFT                    31
1028 #define MTKAIF_RXIF_CLKINV_ADC_MASK                   0x1
1029 #define MTKAIF_RXIF_CLKINV_ADC_MASK_SFT               (0x1 << 31)
1030 #define MTKAIF_RXIF_BYPASS_SRC_SFT                    17
1031 #define MTKAIF_RXIF_BYPASS_SRC_MASK                   0x1
1032 #define MTKAIF_RXIF_BYPASS_SRC_MASK_SFT               (0x1 << 17)
1033 #define MTKAIF_RXIF_PROTOCOL2_SFT                     16
1034 #define MTKAIF_RXIF_PROTOCOL2_MASK                    0x1
1035 #define MTKAIF_RXIF_PROTOCOL2_MASK_SFT                (0x1 << 16)
1036 #define MTKAIF_TXIF_BYPASS_SRC_SFT                    5
1037 #define MTKAIF_TXIF_BYPASS_SRC_MASK                   0x1
1038 #define MTKAIF_TXIF_BYPASS_SRC_MASK_SFT               (0x1 << 5)
1039 #define MTKAIF_TXIF_PROTOCOL2_SFT                     4
1040 #define MTKAIF_TXIF_PROTOCOL2_MASK                    0x1
1041 #define MTKAIF_TXIF_PROTOCOL2_MASK_SFT                (0x1 << 4)
1042 #define MTKAIF_TXIF_8TO5_SFT                          2
1043 #define MTKAIF_TXIF_8TO5_MASK                         0x1
1044 #define MTKAIF_TXIF_8TO5_MASK_SFT                     (0x1 << 2)
1045 #define MTKAIF_RXIF_8TO5_SFT                          1
1046 #define MTKAIF_RXIF_8TO5_MASK                         0x1
1047 #define MTKAIF_RXIF_8TO5_MASK_SFT                     (0x1 << 1)
1048 #define MTKAIF_IF_LOOPBACK1_SFT                       0
1049 #define MTKAIF_IF_LOOPBACK1_MASK                      0x1
1050 #define MTKAIF_IF_LOOPBACK1_MASK_SFT                  (0x1 << 0)
1051 
1052 /* AFE_ADDA_MTKAIF_RX_CFG2 */
1053 #define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT           16
1054 #define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK          0x1
1055 #define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT      (0x1 << 16)
1056 #define MTKAIF_RXIF_DELAY_CYCLE_SFT                   12
1057 #define MTKAIF_RXIF_DELAY_CYCLE_MASK                  0xf
1058 #define MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT              (0xf << 12)
1059 #define MTKAIF_RXIF_DELAY_DATA_SFT                    8
1060 #define MTKAIF_RXIF_DELAY_DATA_MASK                   0x1
1061 #define MTKAIF_RXIF_DELAY_DATA_MASK_SFT               (0x1 << 8)
1062 #define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT            4
1063 #define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK           0x7
1064 #define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT       (0x7 << 4)
1065 
1066 /* AFE_ADDA_DL_SRC2_CON0 */
1067 #define DL_2_INPUT_MODE_CTL_SFT                       28
1068 #define DL_2_INPUT_MODE_CTL_MASK                      0xf
1069 #define DL_2_INPUT_MODE_CTL_MASK_SFT                  (0xf << 28)
1070 #define DL_2_CH1_SATURATION_EN_CTL_SFT                27
1071 #define DL_2_CH1_SATURATION_EN_CTL_MASK               0x1
1072 #define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT           (0x1 << 27)
1073 #define DL_2_CH2_SATURATION_EN_CTL_SFT                26
1074 #define DL_2_CH2_SATURATION_EN_CTL_MASK               0x1
1075 #define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT           (0x1 << 26)
1076 #define DL_2_OUTPUT_SEL_CTL_SFT                       24
1077 #define DL_2_OUTPUT_SEL_CTL_MASK                      0x3
1078 #define DL_2_OUTPUT_SEL_CTL_MASK_SFT                  (0x3 << 24)
1079 #define DL_2_FADEIN_0START_EN_SFT                     16
1080 #define DL_2_FADEIN_0START_EN_MASK                    0x3
1081 #define DL_2_FADEIN_0START_EN_MASK_SFT                (0x3 << 16)
1082 #define DL_DISABLE_HW_CG_CTL_SFT                      15
1083 #define DL_DISABLE_HW_CG_CTL_MASK                     0x1
1084 #define DL_DISABLE_HW_CG_CTL_MASK_SFT                 (0x1 << 15)
1085 #define C_DATA_EN_SEL_CTL_PRE_SFT                     14
1086 #define C_DATA_EN_SEL_CTL_PRE_MASK                    0x1
1087 #define C_DATA_EN_SEL_CTL_PRE_MASK_SFT                (0x1 << 14)
1088 #define DL_2_SIDE_TONE_ON_CTL_PRE_SFT                 13
1089 #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK                0x1
1090 #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT            (0x1 << 13)
1091 #define DL_2_MUTE_CH1_OFF_CTL_PRE_SFT                 12
1092 #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK                0x1
1093 #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT            (0x1 << 12)
1094 #define DL_2_MUTE_CH2_OFF_CTL_PRE_SFT                 11
1095 #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK                0x1
1096 #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT            (0x1 << 11)
1097 #define DL2_ARAMPSP_CTL_PRE_SFT                       9
1098 #define DL2_ARAMPSP_CTL_PRE_MASK                      0x3
1099 #define DL2_ARAMPSP_CTL_PRE_MASK_SFT                  (0x3 << 9)
1100 #define DL_2_IIRMODE_CTL_PRE_SFT                      6
1101 #define DL_2_IIRMODE_CTL_PRE_MASK                     0x7
1102 #define DL_2_IIRMODE_CTL_PRE_MASK_SFT                 (0x7 << 6)
1103 #define DL_2_VOICE_MODE_CTL_PRE_SFT                   5
1104 #define DL_2_VOICE_MODE_CTL_PRE_MASK                  0x1
1105 #define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT              (0x1 << 5)
1106 #define D2_2_MUTE_CH1_ON_CTL_PRE_SFT                  4
1107 #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK                 0x1
1108 #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT             (0x1 << 4)
1109 #define D2_2_MUTE_CH2_ON_CTL_PRE_SFT                  3
1110 #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK                 0x1
1111 #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT             (0x1 << 3)
1112 #define DL_2_IIR_ON_CTL_PRE_SFT                       2
1113 #define DL_2_IIR_ON_CTL_PRE_MASK                      0x1
1114 #define DL_2_IIR_ON_CTL_PRE_MASK_SFT                  (0x1 << 2)
1115 #define DL_2_GAIN_ON_CTL_PRE_SFT                      1
1116 #define DL_2_GAIN_ON_CTL_PRE_MASK                     0x1
1117 #define DL_2_GAIN_ON_CTL_PRE_MASK_SFT                 (0x1 << 1)
1118 #define DL_2_SRC_ON_TMP_CTL_PRE_SFT                   0
1119 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK                  0x1
1120 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT              (0x1 << 0)
1121 
1122 /* AFE_ADDA_DL_SRC2_CON1 */
1123 #define DL_2_GAIN_CTL_PRE_SFT                         16
1124 #define DL_2_GAIN_CTL_PRE_MASK                        0xffff
1125 #define DL_2_GAIN_CTL_PRE_MASK_SFT                    (0xffff << 16)
1126 #define DL_2_GAIN_MODE_CTL_SFT                        0
1127 #define DL_2_GAIN_MODE_CTL_MASK                       0x1
1128 #define DL_2_GAIN_MODE_CTL_MASK_SFT                   (0x1 << 0)
1129 
1130 /* AFE_ADDA_UL_SRC_CON0 */
1131 #define ULCF_CFG_EN_CTL_SFT                           31
1132 #define ULCF_CFG_EN_CTL_MASK                          0x1
1133 #define ULCF_CFG_EN_CTL_MASK_SFT                      (0x1 << 31)
1134 #define UL_MODE_3P25M_CH2_CTL_SFT                     22
1135 #define UL_MODE_3P25M_CH2_CTL_MASK                    0x1
1136 #define UL_MODE_3P25M_CH2_CTL_MASK_SFT                (0x1 << 22)
1137 #define UL_MODE_3P25M_CH1_CTL_SFT                     21
1138 #define UL_MODE_3P25M_CH1_CTL_MASK                    0x1
1139 #define UL_MODE_3P25M_CH1_CTL_MASK_SFT                (0x1 << 21)
1140 #define UL_VOICE_MODE_CH1_CH2_CTL_SFT                 17
1141 #define UL_VOICE_MODE_CH1_CH2_CTL_MASK                0x7
1142 #define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT            (0x7 << 17)
1143 #define DMIC_LOW_POWER_MODE_CTL_SFT                   14
1144 #define DMIC_LOW_POWER_MODE_CTL_MASK                  0x3
1145 #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT              (0x3 << 14)
1146 #define UL_DISABLE_HW_CG_CTL_SFT                      12
1147 #define UL_DISABLE_HW_CG_CTL_MASK                     0x1
1148 #define UL_DISABLE_HW_CG_CTL_MASK_SFT                 (0x1 << 12)
1149 #define UL_IIR_ON_TMP_CTL_SFT                         10
1150 #define UL_IIR_ON_TMP_CTL_MASK                        0x1
1151 #define UL_IIR_ON_TMP_CTL_MASK_SFT                    (0x1 << 10)
1152 #define UL_IIRMODE_CTL_SFT                            7
1153 #define UL_IIRMODE_CTL_MASK                           0x7
1154 #define UL_IIRMODE_CTL_MASK_SFT                       (0x7 << 7)
1155 #define DIGMIC_3P25M_1P625M_SEL_CTL_SFT               5
1156 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK              0x1
1157 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT          (0x1 << 5)
1158 #define UL_LOOP_BACK_MODE_CTL_SFT                     2
1159 #define UL_LOOP_BACK_MODE_CTL_MASK                    0x1
1160 #define UL_LOOP_BACK_MODE_CTL_MASK_SFT                (0x1 << 2)
1161 #define UL_SDM_3_LEVEL_CTL_SFT                        1
1162 #define UL_SDM_3_LEVEL_CTL_MASK                       0x1
1163 #define UL_SDM_3_LEVEL_CTL_MASK_SFT                   (0x1 << 1)
1164 #define UL_SRC_ON_TMP_CTL_SFT                         0
1165 #define UL_SRC_ON_TMP_CTL_MASK                        0x1
1166 #define UL_SRC_ON_TMP_CTL_MASK_SFT                    (0x1 << 0)
1167 
1168 /* AFE_ADDA_UL_SRC_CON1 */
1169 #define C_DAC_EN_CTL_SFT                              27
1170 #define C_DAC_EN_CTL_MASK                             0x1
1171 #define C_DAC_EN_CTL_MASK_SFT                         (0x1 << 27)
1172 #define C_MUTE_SW_CTL_SFT                             26
1173 #define C_MUTE_SW_CTL_MASK                            0x1
1174 #define C_MUTE_SW_CTL_MASK_SFT                        (0x1 << 26)
1175 #define ASDM_SRC_SEL_CTL_SFT                          25
1176 #define ASDM_SRC_SEL_CTL_MASK                         0x1
1177 #define ASDM_SRC_SEL_CTL_MASK_SFT                     (0x1 << 25)
1178 #define C_AMP_DIV_CH2_CTL_SFT                         21
1179 #define C_AMP_DIV_CH2_CTL_MASK                        0x7
1180 #define C_AMP_DIV_CH2_CTL_MASK_SFT                    (0x7 << 21)
1181 #define C_FREQ_DIV_CH2_CTL_SFT                        16
1182 #define C_FREQ_DIV_CH2_CTL_MASK                       0x1f
1183 #define C_FREQ_DIV_CH2_CTL_MASK_SFT                   (0x1f << 16)
1184 #define C_SINE_MODE_CH2_CTL_SFT                       12
1185 #define C_SINE_MODE_CH2_CTL_MASK                      0xf
1186 #define C_SINE_MODE_CH2_CTL_MASK_SFT                  (0xf << 12)
1187 #define C_AMP_DIV_CH1_CTL_SFT                         9
1188 #define C_AMP_DIV_CH1_CTL_MASK                        0x7
1189 #define C_AMP_DIV_CH1_CTL_MASK_SFT                    (0x7 << 9)
1190 #define C_FREQ_DIV_CH1_CTL_SFT                        4
1191 #define C_FREQ_DIV_CH1_CTL_MASK                       0x1f
1192 #define C_FREQ_DIV_CH1_CTL_MASK_SFT                   (0x1f << 4)
1193 #define C_SINE_MODE_CH1_CTL_SFT                       0
1194 #define C_SINE_MODE_CH1_CTL_MASK                      0xf
1195 #define C_SINE_MODE_CH1_CTL_MASK_SFT                  (0xf << 0)
1196 
1197 /* AFE_ADDA_TOP_CON0 */
1198 #define C_LOOP_BACK_MODE_CTL_SFT                      12
1199 #define C_LOOP_BACK_MODE_CTL_MASK                     0xf
1200 #define C_LOOP_BACK_MODE_CTL_MASK_SFT                 (0xf << 12)
1201 #define C_EXT_ADC_CTL_SFT                             0
1202 #define C_EXT_ADC_CTL_MASK                            0x1
1203 #define C_EXT_ADC_CTL_MASK_SFT                        (0x1 << 0)
1204 
1205 /* AFE_ADDA_UL_DL_CON0 */
1206 #define AFE_ADDA6_UL_LR_SWAP_SFT                      15
1207 #define AFE_ADDA6_UL_LR_SWAP_MASK                     0x1
1208 #define AFE_ADDA6_UL_LR_SWAP_MASK_SFT                 (0x1 << 15)
1209 #define AFE_ADDA6_CKDIV_RST_SFT                       14
1210 #define AFE_ADDA6_CKDIV_RST_MASK                      0x1
1211 #define AFE_ADDA6_CKDIV_RST_MASK_SFT                  (0x1 << 14)
1212 #define AFE_ADDA6_FIFO_AUTO_RST_SFT                   13
1213 #define AFE_ADDA6_FIFO_AUTO_RST_MASK                  0x1
1214 #define AFE_ADDA6_FIFO_AUTO_RST_MASK_SFT              (0x1 << 13)
1215 #define UL_FIFO_DIGMIC_TESTIN_SFT                     5
1216 #define UL_FIFO_DIGMIC_TESTIN_MASK                    0x3
1217 #define UL_FIFO_DIGMIC_TESTIN_MASK_SFT                (0x3 << 5)
1218 #define UL_FIFO_DIGMIC_WDATA_TESTEN_SFT               4
1219 #define UL_FIFO_DIGMIC_WDATA_TESTEN_MASK              0x1
1220 #define UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT          (0x1 << 4)
1221 #define ADDA_AFE_ON_SFT                               0
1222 #define ADDA_AFE_ON_MASK                              0x1
1223 #define ADDA_AFE_ON_MASK_SFT                          (0x1 << 0)
1224 
1225 /* AFE_SIDETONE_CON0 */
1226 #define R_RDY_SFT                                     30
1227 #define R_RDY_MASK                                    0x1
1228 #define R_RDY_MASK_SFT                                (0x1 << 30)
1229 #define W_RDY_SFT                                     29
1230 #define W_RDY_MASK                                    0x1
1231 #define W_RDY_MASK_SFT                                (0x1 << 29)
1232 #define R_W_EN_SFT                                    25
1233 #define R_W_EN_MASK                                   0x1
1234 #define R_W_EN_MASK_SFT                               (0x1 << 25)
1235 #define R_W_SEL_SFT                                   24
1236 #define R_W_SEL_MASK                                  0x1
1237 #define R_W_SEL_MASK_SFT                              (0x1 << 24)
1238 #define SEL_CH2_SFT                                   23
1239 #define SEL_CH2_MASK                                  0x1
1240 #define SEL_CH2_MASK_SFT                              (0x1 << 23)
1241 #define SIDE_TONE_COEFFICIENT_ADDR_SFT                16
1242 #define SIDE_TONE_COEFFICIENT_ADDR_MASK               0x1f
1243 #define SIDE_TONE_COEFFICIENT_ADDR_MASK_SFT           (0x1f << 16)
1244 #define SIDE_TONE_COEFFICIENT_SFT                     0
1245 #define SIDE_TONE_COEFFICIENT_MASK                    0xffff
1246 #define SIDE_TONE_COEFFICIENT_MASK_SFT                (0xffff << 0)
1247 
1248 /* AFE_SIDETONE_COEFF */
1249 #define SIDE_TONE_COEFF_SFT                           0
1250 #define SIDE_TONE_COEFF_MASK                          0xffff
1251 #define SIDE_TONE_COEFF_MASK_SFT                      (0xffff << 0)
1252 
1253 /* AFE_SIDETONE_CON1 */
1254 #define STF_BYPASS_MODE_SFT                           31
1255 #define STF_BYPASS_MODE_MASK                          0x1
1256 #define STF_BYPASS_MODE_MASK_SFT                      (0x1 << 31)
1257 #define STF_BYPASS_MODE_O28_O29_SFT                   30
1258 #define STF_BYPASS_MODE_O28_O29_MASK                  0x1
1259 #define STF_BYPASS_MODE_O28_O29_MASK_SFT              (0x1 << 30)
1260 #define STF_BYPASS_MODE_I2S4_SFT                      29
1261 #define STF_BYPASS_MODE_I2S4_MASK                     0x1
1262 #define STF_BYPASS_MODE_I2S4_MASK_SFT                 (0x1 << 29)
1263 #define STF_BYPASS_MODE_I2S5_SFT                      28
1264 #define STF_BYPASS_MODE_I2S5_MASK                     0x1
1265 #define STF_BYPASS_MODE_I2S5_MASK_SFT                 (0x1 << 28)
1266 #define STF_INPUT_EN_SEL_SFT                          13
1267 #define STF_INPUT_EN_SEL_MASK                         0x1
1268 #define STF_INPUT_EN_SEL_MASK_SFT                     (0x1 << 13)
1269 #define STF_SOURCE_FROM_O19O20_SFT                    12
1270 #define STF_SOURCE_FROM_O19O20_MASK                   0x1
1271 #define STF_SOURCE_FROM_O19O20_MASK_SFT               (0x1 << 12)
1272 #define SIDE_TONE_ON_SFT                              8
1273 #define SIDE_TONE_ON_MASK                             0x1
1274 #define SIDE_TONE_ON_MASK_SFT                         (0x1 << 8)
1275 #define SIDE_TONE_HALF_TAP_NUM_SFT                    0
1276 #define SIDE_TONE_HALF_TAP_NUM_MASK                   0x3f
1277 #define SIDE_TONE_HALF_TAP_NUM_MASK_SFT               (0x3f << 0)
1278 
1279 /* AFE_SIDETONE_GAIN */
1280 #define POSITIVE_GAIN_SFT                             16
1281 #define POSITIVE_GAIN_MASK                            0x7
1282 #define POSITIVE_GAIN_MASK_SFT                        (0x7 << 16)
1283 #define SIDE_TONE_GAIN_SFT                            0
1284 #define SIDE_TONE_GAIN_MASK                           0xffff
1285 #define SIDE_TONE_GAIN_MASK_SFT                       (0xffff << 0)
1286 
1287 /* AFE_ADDA_DL_SDM_DCCOMP_CON */
1288 #define AUD_DC_COMP_EN_SFT                            8
1289 #define AUD_DC_COMP_EN_MASK                           0x1
1290 #define AUD_DC_COMP_EN_MASK_SFT                       (0x1 << 8)
1291 #define ATTGAIN_CTL_SFT                               0
1292 #define ATTGAIN_CTL_MASK                              0x3f
1293 #define ATTGAIN_CTL_MASK_SFT                          (0x3f << 0)
1294 
1295 /* AFE_SINEGEN_CON0 */
1296 #define DAC_EN_SFT                                    26
1297 #define DAC_EN_MASK                                   0x1
1298 #define DAC_EN_MASK_SFT                               (0x1 << 26)
1299 #define MUTE_SW_CH2_SFT                               25
1300 #define MUTE_SW_CH2_MASK                              0x1
1301 #define MUTE_SW_CH2_MASK_SFT                          (0x1 << 25)
1302 #define MUTE_SW_CH1_SFT                               24
1303 #define MUTE_SW_CH1_MASK                              0x1
1304 #define MUTE_SW_CH1_MASK_SFT                          (0x1 << 24)
1305 #define SINE_MODE_CH2_SFT                             20
1306 #define SINE_MODE_CH2_MASK                            0xf
1307 #define SINE_MODE_CH2_MASK_SFT                        (0xf << 20)
1308 #define AMP_DIV_CH2_SFT                               17
1309 #define AMP_DIV_CH2_MASK                              0x7
1310 #define AMP_DIV_CH2_MASK_SFT                          (0x7 << 17)
1311 #define FREQ_DIV_CH2_SFT                              12
1312 #define FREQ_DIV_CH2_MASK                             0x1f
1313 #define FREQ_DIV_CH2_MASK_SFT                         (0x1f << 12)
1314 #define SINE_MODE_CH1_SFT                             8
1315 #define SINE_MODE_CH1_MASK                            0xf
1316 #define SINE_MODE_CH1_MASK_SFT                        (0xf << 8)
1317 #define AMP_DIV_CH1_SFT                               5
1318 #define AMP_DIV_CH1_MASK                              0x7
1319 #define AMP_DIV_CH1_MASK_SFT                          (0x7 << 5)
1320 #define FREQ_DIV_CH1_SFT                              0
1321 #define FREQ_DIV_CH1_MASK                             0x1f
1322 #define FREQ_DIV_CH1_MASK_SFT                         (0x1f << 0)
1323 
1324 /* AFE_SINEGEN_CON2 */
1325 #define INNER_LOOP_BACK_MODE_SFT                      0
1326 #define INNER_LOOP_BACK_MODE_MASK                     0x3f
1327 #define INNER_LOOP_BACK_MODE_MASK_SFT                 (0x3f << 0)
1328 
1329 /* AFE_MEMIF_MINLEN */
1330 #define HDMI_MINLEN_SFT                               24
1331 #define HDMI_MINLEN_MASK                              0xf
1332 #define HDMI_MINLEN_MASK_SFT                          (0xf << 24)
1333 #define DL3_MINLEN_SFT                                12
1334 #define DL3_MINLEN_MASK                               0xf
1335 #define DL3_MINLEN_MASK_SFT                           (0xf << 12)
1336 #define DL2_MINLEN_SFT                                8
1337 #define DL2_MINLEN_MASK                               0xf
1338 #define DL2_MINLEN_MASK_SFT                           (0xf << 8)
1339 #define DL1_DATA2_MINLEN_SFT                          4
1340 #define DL1_DATA2_MINLEN_MASK                         0xf
1341 #define DL1_DATA2_MINLEN_MASK_SFT                     (0xf << 4)
1342 #define DL1_MINLEN_SFT                                0
1343 #define DL1_MINLEN_MASK                               0xf
1344 #define DL1_MINLEN_MASK_SFT                           (0xf << 0)
1345 
1346 /* AFE_MEMIF_MAXLEN */
1347 #define HDMI_MAXLEN_SFT                               24
1348 #define HDMI_MAXLEN_MASK                              0xf
1349 #define HDMI_MAXLEN_MASK_SFT                          (0xf << 24)
1350 #define DL3_MAXLEN_SFT                                8
1351 #define DL3_MAXLEN_MASK                               0xf
1352 #define DL3_MAXLEN_MASK_SFT                           (0xf << 8)
1353 #define DL2_MAXLEN_SFT                                4
1354 #define DL2_MAXLEN_MASK                               0xf
1355 #define DL2_MAXLEN_MASK_SFT                           (0xf << 4)
1356 #define DL1_MAXLEN_SFT                                0
1357 #define DL1_MAXLEN_MASK                               0x3
1358 #define DL1_MAXLEN_MASK_SFT                           (0x3 << 0)
1359 
1360 /* AFE_MEMIF_PBUF_SIZE */
1361 #define VUL12_4CH_SFT                                 17
1362 #define VUL12_4CH_MASK                                0x1
1363 #define VUL12_4CH_MASK_SFT                            (0x1 << 17)
1364 #define DL3_PBUF_SIZE_SFT                             10
1365 #define DL3_PBUF_SIZE_MASK                            0x3
1366 #define DL3_PBUF_SIZE_MASK_SFT                        (0x3 << 10)
1367 #define HDMI_PBUF_SIZE_SFT                            4
1368 #define HDMI_PBUF_SIZE_MASK                           0x3
1369 #define HDMI_PBUF_SIZE_MASK_SFT                       (0x3 << 4)
1370 #define DL2_PBUF_SIZE_SFT                             2
1371 #define DL2_PBUF_SIZE_MASK                            0x3
1372 #define DL2_PBUF_SIZE_MASK_SFT                        (0x3 << 2)
1373 #define DL1_PBUF_SIZE_SFT                             0
1374 #define DL1_PBUF_SIZE_MASK                            0x3
1375 #define DL1_PBUF_SIZE_MASK_SFT                        (0x3 << 0)
1376 
1377 /* AFE_HD_ENGEN_ENABLE */
1378 #define AFE_24M_ON_SFT                                1
1379 #define AFE_24M_ON_MASK                               0x1
1380 #define AFE_24M_ON_MASK_SFT                           (0x1 << 1)
1381 #define AFE_22M_ON_SFT                                0
1382 #define AFE_22M_ON_MASK                               0x1
1383 #define AFE_22M_ON_MASK_SFT                           (0x1 << 0)
1384 
1385 /* AFE_IRQ_MCU_CON0 */
1386 #define IRQ12_MCU_ON_SFT                              12
1387 #define IRQ12_MCU_ON_MASK                             0x1
1388 #define IRQ12_MCU_ON_MASK_SFT                         (0x1 << 12)
1389 #define IRQ11_MCU_ON_SFT                              11
1390 #define IRQ11_MCU_ON_MASK                             0x1
1391 #define IRQ11_MCU_ON_MASK_SFT                         (0x1 << 11)
1392 #define IRQ10_MCU_ON_SFT                              10
1393 #define IRQ10_MCU_ON_MASK                             0x1
1394 #define IRQ10_MCU_ON_MASK_SFT                         (0x1 << 10)
1395 #define IRQ9_MCU_ON_SFT                               9
1396 #define IRQ9_MCU_ON_MASK                              0x1
1397 #define IRQ9_MCU_ON_MASK_SFT                          (0x1 << 9)
1398 #define IRQ8_MCU_ON_SFT                               8
1399 #define IRQ8_MCU_ON_MASK                              0x1
1400 #define IRQ8_MCU_ON_MASK_SFT                          (0x1 << 8)
1401 #define IRQ7_MCU_ON_SFT                               7
1402 #define IRQ7_MCU_ON_MASK                              0x1
1403 #define IRQ7_MCU_ON_MASK_SFT                          (0x1 << 7)
1404 #define IRQ6_MCU_ON_SFT                               6
1405 #define IRQ6_MCU_ON_MASK                              0x1
1406 #define IRQ6_MCU_ON_MASK_SFT                          (0x1 << 6)
1407 #define IRQ5_MCU_ON_SFT                               5
1408 #define IRQ5_MCU_ON_MASK                              0x1
1409 #define IRQ5_MCU_ON_MASK_SFT                          (0x1 << 5)
1410 #define IRQ4_MCU_ON_SFT                               4
1411 #define IRQ4_MCU_ON_MASK                              0x1
1412 #define IRQ4_MCU_ON_MASK_SFT                          (0x1 << 4)
1413 #define IRQ3_MCU_ON_SFT                               3
1414 #define IRQ3_MCU_ON_MASK                              0x1
1415 #define IRQ3_MCU_ON_MASK_SFT                          (0x1 << 3)
1416 #define IRQ2_MCU_ON_SFT                               2
1417 #define IRQ2_MCU_ON_MASK                              0x1
1418 #define IRQ2_MCU_ON_MASK_SFT                          (0x1 << 2)
1419 #define IRQ1_MCU_ON_SFT                               1
1420 #define IRQ1_MCU_ON_MASK                              0x1
1421 #define IRQ1_MCU_ON_MASK_SFT                          (0x1 << 1)
1422 #define IRQ0_MCU_ON_SFT                               0
1423 #define IRQ0_MCU_ON_MASK                              0x1
1424 #define IRQ0_MCU_ON_MASK_SFT                          (0x1 << 0)
1425 
1426 /* AFE_IRQ_MCU_CON1 */
1427 #define IRQ7_MCU_MODE_SFT                             28
1428 #define IRQ7_MCU_MODE_MASK                            0xf
1429 #define IRQ7_MCU_MODE_MASK_SFT                        (0xf << 28)
1430 #define IRQ6_MCU_MODE_SFT                             24
1431 #define IRQ6_MCU_MODE_MASK                            0xf
1432 #define IRQ6_MCU_MODE_MASK_SFT                        (0xf << 24)
1433 #define IRQ5_MCU_MODE_SFT                             20
1434 #define IRQ5_MCU_MODE_MASK                            0xf
1435 #define IRQ5_MCU_MODE_MASK_SFT                        (0xf << 20)
1436 #define IRQ4_MCU_MODE_SFT                             16
1437 #define IRQ4_MCU_MODE_MASK                            0xf
1438 #define IRQ4_MCU_MODE_MASK_SFT                        (0xf << 16)
1439 #define IRQ3_MCU_MODE_SFT                             12
1440 #define IRQ3_MCU_MODE_MASK                            0xf
1441 #define IRQ3_MCU_MODE_MASK_SFT                        (0xf << 12)
1442 #define IRQ2_MCU_MODE_SFT                             8
1443 #define IRQ2_MCU_MODE_MASK                            0xf
1444 #define IRQ2_MCU_MODE_MASK_SFT                        (0xf << 8)
1445 #define IRQ1_MCU_MODE_SFT                             4
1446 #define IRQ1_MCU_MODE_MASK                            0xf
1447 #define IRQ1_MCU_MODE_MASK_SFT                        (0xf << 4)
1448 #define IRQ0_MCU_MODE_SFT                             0
1449 #define IRQ0_MCU_MODE_MASK                            0xf
1450 #define IRQ0_MCU_MODE_MASK_SFT                        (0xf << 0)
1451 
1452 /* AFE_IRQ_MCU_CON2 */
1453 #define IRQ12_MCU_MODE_SFT                            4
1454 #define IRQ12_MCU_MODE_MASK                           0xf
1455 #define IRQ12_MCU_MODE_MASK_SFT                       (0xf << 4)
1456 #define IRQ11_MCU_MODE_SFT                            0
1457 #define IRQ11_MCU_MODE_MASK                           0xf
1458 #define IRQ11_MCU_MODE_MASK_SFT                       (0xf << 0)
1459 
1460 /* AFE_IRQ_MCU_CLR */
1461 #define IRQ12_MCU_MISS_CNT_CLR_SFT                    28
1462 #define IRQ12_MCU_MISS_CNT_CLR_MASK                   0x1
1463 #define IRQ12_MCU_MISS_CNT_CLR_MASK_SFT               (0x1 << 28)
1464 #define IRQ11_MCU_MISS_CNT_CLR_SFT                    27
1465 #define IRQ11_MCU_MISS_CNT_CLR_MASK                   0x1
1466 #define IRQ11_MCU_MISS_CNT_CLR_MASK_SFT               (0x1 << 27)
1467 #define IRQ10_MCU_MISS_CLR_SFT                        26
1468 #define IRQ10_MCU_MISS_CLR_MASK                       0x1
1469 #define IRQ10_MCU_MISS_CLR_MASK_SFT                   (0x1 << 26)
1470 #define IRQ9_MCU_MISS_CLR_SFT                         25
1471 #define IRQ9_MCU_MISS_CLR_MASK                        0x1
1472 #define IRQ9_MCU_MISS_CLR_MASK_SFT                    (0x1 << 25)
1473 #define IRQ8_MCU_MISS_CLR_SFT                         24
1474 #define IRQ8_MCU_MISS_CLR_MASK                        0x1
1475 #define IRQ8_MCU_MISS_CLR_MASK_SFT                    (0x1 << 24)
1476 #define IRQ7_MCU_MISS_CLR_SFT                         23
1477 #define IRQ7_MCU_MISS_CLR_MASK                        0x1
1478 #define IRQ7_MCU_MISS_CLR_MASK_SFT                    (0x1 << 23)
1479 #define IRQ6_MCU_MISS_CLR_SFT                         22
1480 #define IRQ6_MCU_MISS_CLR_MASK                        0x1
1481 #define IRQ6_MCU_MISS_CLR_MASK_SFT                    (0x1 << 22)
1482 #define IRQ5_MCU_MISS_CLR_SFT                         21
1483 #define IRQ5_MCU_MISS_CLR_MASK                        0x1
1484 #define IRQ5_MCU_MISS_CLR_MASK_SFT                    (0x1 << 21)
1485 #define IRQ4_MCU_MISS_CLR_SFT                         20
1486 #define IRQ4_MCU_MISS_CLR_MASK                        0x1
1487 #define IRQ4_MCU_MISS_CLR_MASK_SFT                    (0x1 << 20)
1488 #define IRQ3_MCU_MISS_CLR_SFT                         19
1489 #define IRQ3_MCU_MISS_CLR_MASK                        0x1
1490 #define IRQ3_MCU_MISS_CLR_MASK_SFT                    (0x1 << 19)
1491 #define IRQ2_MCU_MISS_CLR_SFT                         18
1492 #define IRQ2_MCU_MISS_CLR_MASK                        0x1
1493 #define IRQ2_MCU_MISS_CLR_MASK_SFT                    (0x1 << 18)
1494 #define IRQ1_MCU_MISS_CLR_SFT                         17
1495 #define IRQ1_MCU_MISS_CLR_MASK                        0x1
1496 #define IRQ1_MCU_MISS_CLR_MASK_SFT                    (0x1 << 17)
1497 #define IRQ0_MCU_MISS_CLR_SFT                         16
1498 #define IRQ0_MCU_MISS_CLR_MASK                        0x1
1499 #define IRQ0_MCU_MISS_CLR_MASK_SFT                    (0x1 << 16)
1500 #define IRQ12_MCU_CLR_SFT                             12
1501 #define IRQ12_MCU_CLR_MASK                            0x1
1502 #define IRQ12_MCU_CLR_MASK_SFT                        (0x1 << 12)
1503 #define IRQ11_MCU_CLR_SFT                             11
1504 #define IRQ11_MCU_CLR_MASK                            0x1
1505 #define IRQ11_MCU_CLR_MASK_SFT                        (0x1 << 11)
1506 #define IRQ10_MCU_CLR_SFT                             10
1507 #define IRQ10_MCU_CLR_MASK                            0x1
1508 #define IRQ10_MCU_CLR_MASK_SFT                        (0x1 << 10)
1509 #define IRQ9_MCU_CLR_SFT                              9
1510 #define IRQ9_MCU_CLR_MASK                             0x1
1511 #define IRQ9_MCU_CLR_MASK_SFT                         (0x1 << 9)
1512 #define IRQ8_MCU_CLR_SFT                              8
1513 #define IRQ8_MCU_CLR_MASK                             0x1
1514 #define IRQ8_MCU_CLR_MASK_SFT                         (0x1 << 8)
1515 #define IRQ7_MCU_CLR_SFT                              7
1516 #define IRQ7_MCU_CLR_MASK                             0x1
1517 #define IRQ7_MCU_CLR_MASK_SFT                         (0x1 << 7)
1518 #define IRQ6_MCU_CLR_SFT                              6
1519 #define IRQ6_MCU_CLR_MASK                             0x1
1520 #define IRQ6_MCU_CLR_MASK_SFT                         (0x1 << 6)
1521 #define IRQ5_MCU_CLR_SFT                              5
1522 #define IRQ5_MCU_CLR_MASK                             0x1
1523 #define IRQ5_MCU_CLR_MASK_SFT                         (0x1 << 5)
1524 #define IRQ4_MCU_CLR_SFT                              4
1525 #define IRQ4_MCU_CLR_MASK                             0x1
1526 #define IRQ4_MCU_CLR_MASK_SFT                         (0x1 << 4)
1527 #define IRQ3_MCU_CLR_SFT                              3
1528 #define IRQ3_MCU_CLR_MASK                             0x1
1529 #define IRQ3_MCU_CLR_MASK_SFT                         (0x1 << 3)
1530 #define IRQ2_MCU_CLR_SFT                              2
1531 #define IRQ2_MCU_CLR_MASK                             0x1
1532 #define IRQ2_MCU_CLR_MASK_SFT                         (0x1 << 2)
1533 #define IRQ1_MCU_CLR_SFT                              1
1534 #define IRQ1_MCU_CLR_MASK                             0x1
1535 #define IRQ1_MCU_CLR_MASK_SFT                         (0x1 << 1)
1536 #define IRQ0_MCU_CLR_SFT                              0
1537 #define IRQ0_MCU_CLR_MASK                             0x1
1538 #define IRQ0_MCU_CLR_MASK_SFT                         (0x1 << 0)
1539 
1540 /* AFE_MEMIF_MSB */
1541 #define CPU_COMPACT_MODE_SFT                          29
1542 #define CPU_COMPACT_MODE_MASK                         0x1
1543 #define CPU_COMPACT_MODE_MASK_SFT                     (0x1 << 29)
1544 #define CPU_HD_ALIGN_SFT                              28
1545 #define CPU_HD_ALIGN_MASK                             0x1
1546 #define CPU_HD_ALIGN_MASK_SFT                         (0x1 << 28)
1547 #define AWB2_AXI_WR_SIGN_SFT                          24
1548 #define AWB2_AXI_WR_SIGN_MASK                         0x1
1549 #define AWB2_AXI_WR_SIGN_MASK_SFT                     (0x1 << 24)
1550 #define VUL2_AXI_WR_SIGN_SFT                          22
1551 #define VUL2_AXI_WR_SIGN_MASK                         0x1
1552 #define VUL2_AXI_WR_SIGN_MASK_SFT                     (0x1 << 22)
1553 #define VUL12_AXI_WR_SIGN_SFT                         21
1554 #define VUL12_AXI_WR_SIGN_MASK                        0x1
1555 #define VUL12_AXI_WR_SIGN_MASK_SFT                    (0x1 << 21)
1556 #define VUL_AXI_WR_SIGN_SFT                           20
1557 #define VUL_AXI_WR_SIGN_MASK                          0x1
1558 #define VUL_AXI_WR_SIGN_MASK_SFT                      (0x1 << 20)
1559 #define MOD_DAI_AXI_WR_SIGN_SFT                       18
1560 #define MOD_DAI_AXI_WR_SIGN_MASK                      0x1
1561 #define MOD_DAI_AXI_WR_SIGN_MASK_SFT                  (0x1 << 18)
1562 #define AWB_MSTR_SIGN_SFT                             17
1563 #define AWB_MSTR_SIGN_MASK                            0x1
1564 #define AWB_MSTR_SIGN_MASK_SFT                        (0x1 << 17)
1565 #define SYSRAM_SIGN_SFT                               16
1566 #define SYSRAM_SIGN_MASK                              0x1
1567 #define SYSRAM_SIGN_MASK_SFT                          (0x1 << 16)
1568 
1569 /* AFE_HDMI_CONN0 */
1570 #define HDMI_O_7_SFT                                  21
1571 #define HDMI_O_7_MASK                                 0x7
1572 #define HDMI_O_7_MASK_SFT                             (0x7 << 21)
1573 #define HDMI_O_6_SFT                                  18
1574 #define HDMI_O_6_MASK                                 0x7
1575 #define HDMI_O_6_MASK_SFT                             (0x7 << 18)
1576 #define HDMI_O_5_SFT                                  15
1577 #define HDMI_O_5_MASK                                 0x7
1578 #define HDMI_O_5_MASK_SFT                             (0x7 << 15)
1579 #define HDMI_O_4_SFT                                  12
1580 #define HDMI_O_4_MASK                                 0x7
1581 #define HDMI_O_4_MASK_SFT                             (0x7 << 12)
1582 #define HDMI_O_3_SFT                                  9
1583 #define HDMI_O_3_MASK                                 0x7
1584 #define HDMI_O_3_MASK_SFT                             (0x7 << 9)
1585 #define HDMI_O_2_SFT                                  6
1586 #define HDMI_O_2_MASK                                 0x7
1587 #define HDMI_O_2_MASK_SFT                             (0x7 << 6)
1588 #define HDMI_O_1_SFT                                  3
1589 #define HDMI_O_1_MASK                                 0x7
1590 #define HDMI_O_1_MASK_SFT                             (0x7 << 3)
1591 #define HDMI_O_0_SFT                                  0
1592 #define HDMI_O_0_MASK                                 0x7
1593 #define HDMI_O_0_MASK_SFT                             (0x7 << 0)
1594 
1595 /* AFE_TDM_CON1 */
1596 #define TDM_EN_SFT                                    0
1597 #define TDM_EN_MASK                                   0x1
1598 #define TDM_EN_MASK_SFT                               (0x1 << 0)
1599 #define BCK_INVERSE_SFT                               1
1600 #define BCK_INVERSE_MASK                              0x1
1601 #define BCK_INVERSE_MASK_SFT                          (0x1 << 1)
1602 #define LRCK_INVERSE_SFT                              2
1603 #define LRCK_INVERSE_MASK                             0x1
1604 #define LRCK_INVERSE_MASK_SFT                         (0x1 << 2)
1605 #define DELAY_DATA_SFT                                3
1606 #define DELAY_DATA_MASK                               0x1
1607 #define DELAY_DATA_MASK_SFT                           (0x1 << 3)
1608 #define LEFT_ALIGN_SFT                                4
1609 #define LEFT_ALIGN_MASK                               0x1
1610 #define LEFT_ALIGN_MASK_SFT                           (0x1 << 4)
1611 #define WLEN_SFT                                      8
1612 #define WLEN_MASK                                     0x3
1613 #define WLEN_MASK_SFT                                 (0x3 << 8)
1614 #define CHANNEL_NUM_SFT                               10
1615 #define CHANNEL_NUM_MASK                              0x3
1616 #define CHANNEL_NUM_MASK_SFT                          (0x3 << 10)
1617 #define CHANNEL_BCK_CYCLES_SFT                        12
1618 #define CHANNEL_BCK_CYCLES_MASK                       0x3
1619 #define CHANNEL_BCK_CYCLES_MASK_SFT                   (0x3 << 12)
1620 #define DAC_BIT_NUM_SFT                               16
1621 #define DAC_BIT_NUM_MASK                              0x1f
1622 #define DAC_BIT_NUM_MASK_SFT                          (0x1f << 16)
1623 #define LRCK_TDM_WIDTH_SFT                            24
1624 #define LRCK_TDM_WIDTH_MASK                           0xff
1625 #define LRCK_TDM_WIDTH_MASK_SFT                       (0xff << 24)
1626 
1627 /* AFE_TDM_CON2 */
1628 #define ST_CH_PAIR_SOUT0_SFT                          0
1629 #define ST_CH_PAIR_SOUT0_MASK                         0x7
1630 #define ST_CH_PAIR_SOUT0_MASK_SFT                     (0x7 << 0)
1631 #define ST_CH_PAIR_SOUT1_SFT                          4
1632 #define ST_CH_PAIR_SOUT1_MASK                         0x7
1633 #define ST_CH_PAIR_SOUT1_MASK_SFT                     (0x7 << 4)
1634 #define ST_CH_PAIR_SOUT2_SFT                          8
1635 #define ST_CH_PAIR_SOUT2_MASK                         0x7
1636 #define ST_CH_PAIR_SOUT2_MASK_SFT                     (0x7 << 8)
1637 #define ST_CH_PAIR_SOUT3_SFT                          12
1638 #define ST_CH_PAIR_SOUT3_MASK                         0x7
1639 #define ST_CH_PAIR_SOUT3_MASK_SFT                     (0x7 << 12)
1640 #define TDM_FIX_VALUE_SEL_SFT                         16
1641 #define TDM_FIX_VALUE_SEL_MASK                        0x1
1642 #define TDM_FIX_VALUE_SEL_MASK_SFT                    (0x1 << 16)
1643 #define TDM_I2S_LOOPBACK_SFT                          20
1644 #define TDM_I2S_LOOPBACK_MASK                         0x1
1645 #define TDM_I2S_LOOPBACK_MASK_SFT                     (0x1 << 20)
1646 #define TDM_I2S_LOOPBACK_CH_SFT                       21
1647 #define TDM_I2S_LOOPBACK_CH_MASK                      0x3
1648 #define TDM_I2S_LOOPBACK_CH_MASK_SFT                  (0x3 << 21)
1649 #define TDM_FIX_VALUE_SFT                             24
1650 #define TDM_FIX_VALUE_MASK                            0xff
1651 #define TDM_FIX_VALUE_MASK_SFT                        (0xff << 24)
1652 
1653 /* AFE_HDMI_OUT_CON0 */
1654 #define AFE_HDMI_OUT_ON_RETM_SFT                      8
1655 #define AFE_HDMI_OUT_ON_RETM_MASK                     0x1
1656 #define AFE_HDMI_OUT_ON_RETM_MASK_SFT                 (0x1 << 8)
1657 #define AFE_HDMI_OUT_CH_NUM_SFT                       4
1658 #define AFE_HDMI_OUT_CH_NUM_MASK                      0xf
1659 #define AFE_HDMI_OUT_CH_NUM_MASK_SFT                  (0xf << 4)
1660 #define AFE_HDMI_OUT_BIT_WIDTH_SFT                    1
1661 #define AFE_HDMI_OUT_BIT_WIDTH_MASK                   0x1
1662 #define AFE_HDMI_OUT_BIT_WIDTH_MASK_SFT               (0x1 << 1)
1663 #define AFE_HDMI_OUT_ON_SFT                           0
1664 #define AFE_HDMI_OUT_ON_MASK                          0x1
1665 #define AFE_HDMI_OUT_ON_MASK_SFT                      (0x1 << 0)
1666 #endif
1667