1a94aec03SShunli Wang /* SPDX-License-Identifier: GPL-2.0 */ 2a94aec03SShunli Wang /* 3a94aec03SShunli Wang * Mediatek MT8183 audio driver interconnection definition 4a94aec03SShunli Wang * 5a94aec03SShunli Wang * Copyright (c) 2018 MediaTek Inc. 6a94aec03SShunli Wang * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7a94aec03SShunli Wang */ 8a94aec03SShunli Wang 9a94aec03SShunli Wang #ifndef _MT8183_INTERCONNECTION_H_ 10a94aec03SShunli Wang #define _MT8183_INTERCONNECTION_H_ 11a94aec03SShunli Wang 12a94aec03SShunli Wang #define I_I2S0_CH1 0 13a94aec03SShunli Wang #define I_I2S0_CH2 1 14a94aec03SShunli Wang #define I_ADDA_UL_CH1 3 15a94aec03SShunli Wang #define I_ADDA_UL_CH2 4 16a94aec03SShunli Wang #define I_DL1_CH1 5 17a94aec03SShunli Wang #define I_DL1_CH2 6 18a94aec03SShunli Wang #define I_DL2_CH1 7 19a94aec03SShunli Wang #define I_DL2_CH2 8 20a94aec03SShunli Wang #define I_PCM_1_CAP_CH1 9 21a94aec03SShunli Wang #define I_GAIN1_OUT_CH1 10 22a94aec03SShunli Wang #define I_GAIN1_OUT_CH2 11 23a94aec03SShunli Wang #define I_GAIN2_OUT_CH1 12 24a94aec03SShunli Wang #define I_GAIN2_OUT_CH2 13 25a94aec03SShunli Wang #define I_PCM_2_CAP_CH1 14 26a94aec03SShunli Wang #define I_PCM_2_CAP_CH2 21 27a94aec03SShunli Wang #define I_PCM_1_CAP_CH2 22 28a94aec03SShunli Wang #define I_DL3_CH1 23 29a94aec03SShunli Wang #define I_DL3_CH2 24 30a94aec03SShunli Wang #define I_I2S2_CH1 25 31a94aec03SShunli Wang #define I_I2S2_CH2 26 32a94aec03SShunli Wang 33a94aec03SShunli Wang #endif 34