1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // MediaTek ALSA SoC Audio DAI ADDA Control 4 // 5 // Copyright (c) 2018 MediaTek Inc. 6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7 8 #include <linux/regmap.h> 9 #include <linux/delay.h> 10 #include "mt8183-afe-common.h" 11 #include "mt8183-interconnection.h" 12 #include "mt8183-reg.h" 13 14 enum { 15 AUDIO_SDM_LEVEL_MUTE = 0, 16 AUDIO_SDM_LEVEL_NORMAL = 0x1d, 17 /* if you change level normal */ 18 /* you need to change formula of hp impedance and dc trim too */ 19 }; 20 21 enum { 22 DELAY_DATA_MISO1 = 0, 23 DELAY_DATA_MISO2, 24 }; 25 26 enum { 27 MTK_AFE_ADDA_DL_RATE_8K = 0, 28 MTK_AFE_ADDA_DL_RATE_11K = 1, 29 MTK_AFE_ADDA_DL_RATE_12K = 2, 30 MTK_AFE_ADDA_DL_RATE_16K = 3, 31 MTK_AFE_ADDA_DL_RATE_22K = 4, 32 MTK_AFE_ADDA_DL_RATE_24K = 5, 33 MTK_AFE_ADDA_DL_RATE_32K = 6, 34 MTK_AFE_ADDA_DL_RATE_44K = 7, 35 MTK_AFE_ADDA_DL_RATE_48K = 8, 36 MTK_AFE_ADDA_DL_RATE_96K = 9, 37 MTK_AFE_ADDA_DL_RATE_192K = 10, 38 }; 39 40 enum { 41 MTK_AFE_ADDA_UL_RATE_8K = 0, 42 MTK_AFE_ADDA_UL_RATE_16K = 1, 43 MTK_AFE_ADDA_UL_RATE_32K = 2, 44 MTK_AFE_ADDA_UL_RATE_48K = 3, 45 MTK_AFE_ADDA_UL_RATE_96K = 4, 46 MTK_AFE_ADDA_UL_RATE_192K = 5, 47 MTK_AFE_ADDA_UL_RATE_48K_HD = 6, 48 }; 49 50 static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe, 51 unsigned int rate) 52 { 53 switch (rate) { 54 case 8000: 55 return MTK_AFE_ADDA_DL_RATE_8K; 56 case 11025: 57 return MTK_AFE_ADDA_DL_RATE_11K; 58 case 12000: 59 return MTK_AFE_ADDA_DL_RATE_12K; 60 case 16000: 61 return MTK_AFE_ADDA_DL_RATE_16K; 62 case 22050: 63 return MTK_AFE_ADDA_DL_RATE_22K; 64 case 24000: 65 return MTK_AFE_ADDA_DL_RATE_24K; 66 case 32000: 67 return MTK_AFE_ADDA_DL_RATE_32K; 68 case 44100: 69 return MTK_AFE_ADDA_DL_RATE_44K; 70 case 48000: 71 return MTK_AFE_ADDA_DL_RATE_48K; 72 case 96000: 73 return MTK_AFE_ADDA_DL_RATE_96K; 74 case 192000: 75 return MTK_AFE_ADDA_DL_RATE_192K; 76 default: 77 dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n", 78 __func__, rate); 79 return MTK_AFE_ADDA_DL_RATE_48K; 80 } 81 } 82 83 static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe, 84 unsigned int rate) 85 { 86 switch (rate) { 87 case 8000: 88 return MTK_AFE_ADDA_UL_RATE_8K; 89 case 16000: 90 return MTK_AFE_ADDA_UL_RATE_16K; 91 case 32000: 92 return MTK_AFE_ADDA_UL_RATE_32K; 93 case 48000: 94 return MTK_AFE_ADDA_UL_RATE_48K; 95 case 96000: 96 return MTK_AFE_ADDA_UL_RATE_96K; 97 case 192000: 98 return MTK_AFE_ADDA_UL_RATE_192K; 99 default: 100 dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n", 101 __func__, rate); 102 return MTK_AFE_ADDA_UL_RATE_48K; 103 } 104 } 105 106 /* dai component */ 107 static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = { 108 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0), 109 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0), 110 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0), 111 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3, 112 I_ADDA_UL_CH2, 1, 0), 113 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3, 114 I_ADDA_UL_CH1, 1, 0), 115 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3, 116 I_PCM_1_CAP_CH1, 1, 0), 117 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3, 118 I_PCM_2_CAP_CH1, 1, 0), 119 }; 120 121 static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = { 122 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0), 123 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0), 124 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0), 125 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0), 126 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0), 127 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0), 128 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4, 129 I_ADDA_UL_CH2, 1, 0), 130 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4, 131 I_ADDA_UL_CH1, 1, 0), 132 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4, 133 I_PCM_1_CAP_CH1, 1, 0), 134 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4, 135 I_PCM_2_CAP_CH1, 1, 0), 136 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4, 137 I_PCM_1_CAP_CH2, 1, 0), 138 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4, 139 I_PCM_2_CAP_CH2, 1, 0), 140 }; 141 142 static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w, 143 struct snd_kcontrol *kcontrol, 144 int event) 145 { 146 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 147 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 148 struct mt8183_afe_private *afe_priv = afe->platform_priv; 149 150 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 151 __func__, w->name, event); 152 153 switch (event) { 154 case SND_SOC_DAPM_PRE_PMU: 155 /* update setting to dmic */ 156 if (afe_priv->mtkaif_dmic) { 157 /* mtkaif_rxif_data_mode = 1, dmic */ 158 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, 159 0x1, 0x1); 160 161 /* dmic mode, 3.25M*/ 162 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, 163 0x0, 0xf << 20); 164 regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0, 165 0x0, 0x1 << 5); 166 regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0, 167 0x0, 0x3 << 14); 168 169 /* turn on dmic, ch1, ch2 */ 170 regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0, 171 0x1 << 1, 0x1 << 1); 172 regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0, 173 0x3 << 21, 0x3 << 21); 174 } 175 break; 176 case SND_SOC_DAPM_POST_PMD: 177 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 178 usleep_range(125, 135); 179 180 /* reset dmic */ 181 afe_priv->mtkaif_dmic = 0; 182 break; 183 default: 184 break; 185 } 186 187 return 0; 188 } 189 190 /* mtkaif dmic */ 191 static const char * const mt8183_adda_off_on_str[] = { 192 "Off", "On" 193 }; 194 195 static const struct soc_enum mt8183_adda_enum[] = { 196 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8183_adda_off_on_str), 197 mt8183_adda_off_on_str), 198 }; 199 200 static int mt8183_adda_dmic_get(struct snd_kcontrol *kcontrol, 201 struct snd_ctl_elem_value *ucontrol) 202 { 203 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 204 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 205 struct mt8183_afe_private *afe_priv = afe->platform_priv; 206 207 ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic; 208 209 return 0; 210 } 211 212 static int mt8183_adda_dmic_set(struct snd_kcontrol *kcontrol, 213 struct snd_ctl_elem_value *ucontrol) 214 { 215 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 216 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 217 struct mt8183_afe_private *afe_priv = afe->platform_priv; 218 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 219 220 if (ucontrol->value.enumerated.item[0] >= e->items) 221 return -EINVAL; 222 223 afe_priv->mtkaif_dmic = ucontrol->value.integer.value[0]; 224 225 dev_info(afe->dev, "%s(), kcontrol name %s, mtkaif_dmic %d\n", 226 __func__, kcontrol->id.name, afe_priv->mtkaif_dmic); 227 228 return 0; 229 } 230 231 static const struct snd_kcontrol_new mtk_adda_controls[] = { 232 SOC_ENUM_EXT("MTKAIF_DMIC", mt8183_adda_enum[0], 233 mt8183_adda_dmic_get, mt8183_adda_dmic_set), 234 }; 235 236 enum { 237 SUPPLY_SEQ_ADDA_AFE_ON, 238 SUPPLY_SEQ_ADDA_DL_ON, 239 SUPPLY_SEQ_ADDA_UL_ON, 240 }; 241 242 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = { 243 /* adda */ 244 SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0, 245 mtk_adda_dl_ch1_mix, 246 ARRAY_SIZE(mtk_adda_dl_ch1_mix)), 247 SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0, 248 mtk_adda_dl_ch2_mix, 249 ARRAY_SIZE(mtk_adda_dl_ch2_mix)), 250 251 SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON, 252 AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0, 253 NULL, 0), 254 255 SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON, 256 AFE_ADDA_DL_SRC2_CON0, 257 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, 258 NULL, 0), 259 260 SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON, 261 AFE_ADDA_UL_SRC_CON0, 262 UL_SRC_ON_TMP_CTL_SFT, 0, 263 mtk_adda_ul_event, 264 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 265 266 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"), 267 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"), 268 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"), 269 SND_SOC_DAPM_CLOCK_SUPPLY("mtkaif_26m_clk"), 270 }; 271 272 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = { 273 /* playback */ 274 {"ADDA_DL_CH1", "DL1_CH1", "DL1"}, 275 {"ADDA_DL_CH2", "DL1_CH1", "DL1"}, 276 {"ADDA_DL_CH2", "DL1_CH2", "DL1"}, 277 278 {"ADDA_DL_CH1", "DL2_CH1", "DL2"}, 279 {"ADDA_DL_CH2", "DL2_CH1", "DL2"}, 280 {"ADDA_DL_CH2", "DL2_CH2", "DL2"}, 281 282 {"ADDA_DL_CH1", "DL3_CH1", "DL3"}, 283 {"ADDA_DL_CH2", "DL3_CH1", "DL3"}, 284 {"ADDA_DL_CH2", "DL3_CH2", "DL3"}, 285 286 {"ADDA Playback", NULL, "ADDA_DL_CH1"}, 287 {"ADDA Playback", NULL, "ADDA_DL_CH2"}, 288 289 /* adda enable */ 290 {"ADDA Playback", NULL, "ADDA Enable"}, 291 {"ADDA Playback", NULL, "ADDA Playback Enable"}, 292 {"ADDA Capture", NULL, "ADDA Enable"}, 293 {"ADDA Capture", NULL, "ADDA Capture Enable"}, 294 295 /* clk */ 296 {"ADDA Playback", NULL, "mtkaif_26m_clk"}, 297 {"ADDA Playback", NULL, "aud_dac_clk"}, 298 {"ADDA Playback", NULL, "aud_dac_predis_clk"}, 299 300 {"ADDA Capture", NULL, "mtkaif_26m_clk"}, 301 {"ADDA Capture", NULL, "aud_adc_clk"}, 302 }; 303 304 static int set_mtkaif_rx(struct mtk_base_afe *afe) 305 { 306 struct mt8183_afe_private *afe_priv = afe->platform_priv; 307 int delay_data; 308 int delay_cycle; 309 310 switch (afe_priv->mtkaif_protocol) { 311 case MT8183_MTKAIF_PROTOCOL_2_CLK_P2: 312 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x38); 313 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x39); 314 /* mtkaif_rxif_clkinv_adc inverse for calibration */ 315 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 316 0x80010000); 317 318 if (afe_priv->mtkaif_phase_cycle[0] >= 319 afe_priv->mtkaif_phase_cycle[1]) { 320 delay_data = DELAY_DATA_MISO1; 321 delay_cycle = afe_priv->mtkaif_phase_cycle[0] - 322 afe_priv->mtkaif_phase_cycle[1]; 323 } else { 324 delay_data = DELAY_DATA_MISO2; 325 delay_cycle = afe_priv->mtkaif_phase_cycle[1] - 326 afe_priv->mtkaif_phase_cycle[0]; 327 } 328 329 regmap_update_bits(afe->regmap, 330 AFE_ADDA_MTKAIF_RX_CFG2, 331 MTKAIF_RXIF_DELAY_DATA_MASK_SFT, 332 delay_data << MTKAIF_RXIF_DELAY_DATA_SFT); 333 334 regmap_update_bits(afe->regmap, 335 AFE_ADDA_MTKAIF_RX_CFG2, 336 MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT, 337 delay_cycle << MTKAIF_RXIF_DELAY_CYCLE_SFT); 338 break; 339 case MT8183_MTKAIF_PROTOCOL_2: 340 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31); 341 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 342 0x00010000); 343 break; 344 case MT8183_MTKAIF_PROTOCOL_1: 345 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31); 346 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x0); 347 default: 348 break; 349 } 350 351 return 0; 352 } 353 354 /* dai ops */ 355 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream, 356 struct snd_pcm_hw_params *params, 357 struct snd_soc_dai *dai) 358 { 359 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 360 unsigned int rate = params_rate(params); 361 362 dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n", 363 __func__, dai->id, substream->stream, rate); 364 365 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 366 unsigned int dl_src2_con0 = 0; 367 unsigned int dl_src2_con1 = 0; 368 369 /* clean predistortion */ 370 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0); 371 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0); 372 373 /* set sampling rate */ 374 dl_src2_con0 = adda_dl_rate_transform(afe, rate) << 28; 375 376 /* set output mode */ 377 switch (rate) { 378 case 192000: 379 dl_src2_con0 |= (0x1 << 24); /* UP_SAMPLING_RATE_X2 */ 380 dl_src2_con0 |= 1 << 14; 381 break; 382 case 96000: 383 dl_src2_con0 |= (0x2 << 24); /* UP_SAMPLING_RATE_X4 */ 384 dl_src2_con0 |= 1 << 14; 385 break; 386 default: 387 dl_src2_con0 |= (0x3 << 24); /* UP_SAMPLING_RATE_X8 */ 388 break; 389 } 390 391 /* turn off mute function */ 392 dl_src2_con0 |= (0x03 << 11); 393 394 /* set voice input data if input sample rate is 8k or 16k */ 395 if (rate == 8000 || rate == 16000) 396 dl_src2_con0 |= 0x01 << 5; 397 398 /* SA suggest apply -0.3db to audio/speech path */ 399 dl_src2_con1 = 0xf74f0000; 400 401 /* turn on down-link gain */ 402 dl_src2_con0 = dl_src2_con0 | (0x01 << 1); 403 404 regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON0, dl_src2_con0); 405 regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON1, dl_src2_con1); 406 407 /* set sdm gain */ 408 regmap_update_bits(afe->regmap, 409 AFE_ADDA_DL_SDM_DCCOMP_CON, 410 ATTGAIN_CTL_MASK_SFT, 411 AUDIO_SDM_LEVEL_NORMAL << ATTGAIN_CTL_SFT); 412 } else { 413 unsigned int voice_mode = 0; 414 unsigned int ul_src_con0 = 0; /* default value */ 415 416 /* set mtkaif protocol */ 417 set_mtkaif_rx(afe); 418 419 /* Using Internal ADC */ 420 regmap_update_bits(afe->regmap, 421 AFE_ADDA_TOP_CON0, 422 0x1 << 0, 423 0x0 << 0); 424 425 voice_mode = adda_ul_rate_transform(afe, rate); 426 427 ul_src_con0 |= (voice_mode << 17) & (0x7 << 17); 428 429 regmap_write(afe->regmap, AFE_ADDA_UL_SRC_CON0, ul_src_con0); 430 431 /* mtkaif_rxif_data_mode = 0, amic */ 432 regmap_update_bits(afe->regmap, 433 AFE_ADDA_MTKAIF_RX_CFG0, 434 0x1 << 0, 435 0x0 << 0); 436 } 437 438 return 0; 439 } 440 441 static const struct snd_soc_dai_ops mtk_dai_adda_ops = { 442 .hw_params = mtk_dai_adda_hw_params, 443 }; 444 445 /* dai driver */ 446 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\ 447 SNDRV_PCM_RATE_96000 |\ 448 SNDRV_PCM_RATE_192000) 449 450 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 451 SNDRV_PCM_RATE_16000 |\ 452 SNDRV_PCM_RATE_32000 |\ 453 SNDRV_PCM_RATE_48000) 454 455 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 456 SNDRV_PCM_FMTBIT_S24_LE |\ 457 SNDRV_PCM_FMTBIT_S32_LE) 458 459 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = { 460 { 461 .name = "ADDA", 462 .id = MT8183_DAI_ADDA, 463 .playback = { 464 .stream_name = "ADDA Playback", 465 .channels_min = 1, 466 .channels_max = 2, 467 .rates = MTK_ADDA_PLAYBACK_RATES, 468 .formats = MTK_ADDA_FORMATS, 469 }, 470 .capture = { 471 .stream_name = "ADDA Capture", 472 .channels_min = 1, 473 .channels_max = 2, 474 .rates = MTK_ADDA_CAPTURE_RATES, 475 .formats = MTK_ADDA_FORMATS, 476 }, 477 .ops = &mtk_dai_adda_ops, 478 }, 479 }; 480 481 int mt8183_dai_adda_register(struct mtk_base_afe *afe) 482 { 483 struct mtk_base_afe_dai *dai; 484 485 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 486 if (!dai) 487 return -ENOMEM; 488 489 list_add(&dai->list, &afe->sub_dais); 490 491 dai->dai_drivers = mtk_dai_adda_driver; 492 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver); 493 494 dai->controls = mtk_adda_controls; 495 dai->num_controls = ARRAY_SIZE(mtk_adda_controls); 496 dai->dapm_widgets = mtk_dai_adda_widgets; 497 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets); 498 dai->dapm_routes = mtk_dai_adda_routes; 499 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes); 500 return 0; 501 } 502