1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Mediatek ALSA SoC AFE platform driver for 8183
4 //
5 // Copyright (c) 2018 MediaTek Inc.
6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7 
8 #include <linux/delay.h>
9 #include <linux/module.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/reset.h>
15 
16 #include "mt8183-afe-common.h"
17 #include "mt8183-afe-clk.h"
18 #include "mt8183-interconnection.h"
19 #include "mt8183-reg.h"
20 #include "../common/mtk-afe-platform-driver.h"
21 #include "../common/mtk-afe-fe-dai.h"
22 
23 enum {
24 	MTK_AFE_RATE_8K = 0,
25 	MTK_AFE_RATE_11K = 1,
26 	MTK_AFE_RATE_12K = 2,
27 	MTK_AFE_RATE_384K = 3,
28 	MTK_AFE_RATE_16K = 4,
29 	MTK_AFE_RATE_22K = 5,
30 	MTK_AFE_RATE_24K = 6,
31 	MTK_AFE_RATE_130K = 7,
32 	MTK_AFE_RATE_32K = 8,
33 	MTK_AFE_RATE_44K = 9,
34 	MTK_AFE_RATE_48K = 10,
35 	MTK_AFE_RATE_88K = 11,
36 	MTK_AFE_RATE_96K = 12,
37 	MTK_AFE_RATE_176K = 13,
38 	MTK_AFE_RATE_192K = 14,
39 	MTK_AFE_RATE_260K = 15,
40 };
41 
42 enum {
43 	MTK_AFE_DAI_MEMIF_RATE_8K = 0,
44 	MTK_AFE_DAI_MEMIF_RATE_16K = 1,
45 	MTK_AFE_DAI_MEMIF_RATE_32K = 2,
46 	MTK_AFE_DAI_MEMIF_RATE_48K = 3,
47 };
48 
49 enum {
50 	MTK_AFE_PCM_RATE_8K = 0,
51 	MTK_AFE_PCM_RATE_16K = 1,
52 	MTK_AFE_PCM_RATE_32K = 2,
53 	MTK_AFE_PCM_RATE_48K = 3,
54 };
55 
56 unsigned int mt8183_general_rate_transform(struct device *dev,
57 					   unsigned int rate)
58 {
59 	switch (rate) {
60 	case 8000:
61 		return MTK_AFE_RATE_8K;
62 	case 11025:
63 		return MTK_AFE_RATE_11K;
64 	case 12000:
65 		return MTK_AFE_RATE_12K;
66 	case 16000:
67 		return MTK_AFE_RATE_16K;
68 	case 22050:
69 		return MTK_AFE_RATE_22K;
70 	case 24000:
71 		return MTK_AFE_RATE_24K;
72 	case 32000:
73 		return MTK_AFE_RATE_32K;
74 	case 44100:
75 		return MTK_AFE_RATE_44K;
76 	case 48000:
77 		return MTK_AFE_RATE_48K;
78 	case 88200:
79 		return MTK_AFE_RATE_88K;
80 	case 96000:
81 		return MTK_AFE_RATE_96K;
82 	case 130000:
83 		return MTK_AFE_RATE_130K;
84 	case 176400:
85 		return MTK_AFE_RATE_176K;
86 	case 192000:
87 		return MTK_AFE_RATE_192K;
88 	case 260000:
89 		return MTK_AFE_RATE_260K;
90 	default:
91 		dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
92 			 __func__, rate, MTK_AFE_RATE_48K);
93 		return MTK_AFE_RATE_48K;
94 	}
95 }
96 
97 static unsigned int dai_memif_rate_transform(struct device *dev,
98 					     unsigned int rate)
99 {
100 	switch (rate) {
101 	case 8000:
102 		return MTK_AFE_DAI_MEMIF_RATE_8K;
103 	case 16000:
104 		return MTK_AFE_DAI_MEMIF_RATE_16K;
105 	case 32000:
106 		return MTK_AFE_DAI_MEMIF_RATE_32K;
107 	case 48000:
108 		return MTK_AFE_DAI_MEMIF_RATE_48K;
109 	default:
110 		dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
111 			 __func__, rate, MTK_AFE_DAI_MEMIF_RATE_16K);
112 		return MTK_AFE_DAI_MEMIF_RATE_16K;
113 	}
114 }
115 
116 unsigned int mt8183_rate_transform(struct device *dev,
117 				   unsigned int rate, int aud_blk)
118 {
119 	switch (aud_blk) {
120 	case MT8183_MEMIF_MOD_DAI:
121 		return dai_memif_rate_transform(dev, rate);
122 	default:
123 		return mt8183_general_rate_transform(dev, rate);
124 	}
125 }
126 
127 static const struct snd_pcm_hardware mt8183_afe_hardware = {
128 	.info = SNDRV_PCM_INFO_MMAP |
129 		SNDRV_PCM_INFO_INTERLEAVED |
130 		SNDRV_PCM_INFO_MMAP_VALID,
131 	.formats = SNDRV_PCM_FMTBIT_S16_LE |
132 		   SNDRV_PCM_FMTBIT_S24_LE |
133 		   SNDRV_PCM_FMTBIT_S32_LE,
134 	.period_bytes_min = 256,
135 	.period_bytes_max = 4 * 48 * 1024,
136 	.periods_min = 2,
137 	.periods_max = 256,
138 	.buffer_bytes_max = 8 * 48 * 1024,
139 	.fifo_size = 0,
140 };
141 
142 static int mt8183_memif_fs(struct snd_pcm_substream *substream,
143 			   unsigned int rate)
144 {
145 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
146 	struct snd_soc_component *component =
147 		snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
148 	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
149 	int id = asoc_rtd_to_cpu(rtd, 0)->id;
150 
151 	return mt8183_rate_transform(afe->dev, rate, id);
152 }
153 
154 static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
155 {
156 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
157 	struct snd_soc_component *component =
158 		snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
159 	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
160 
161 	return mt8183_general_rate_transform(afe->dev, rate);
162 }
163 
164 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
165 		       SNDRV_PCM_RATE_88200 |\
166 		       SNDRV_PCM_RATE_96000 |\
167 		       SNDRV_PCM_RATE_176400 |\
168 		       SNDRV_PCM_RATE_192000)
169 
170 #define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\
171 			   SNDRV_PCM_RATE_16000 |\
172 			   SNDRV_PCM_RATE_32000 |\
173 			   SNDRV_PCM_RATE_48000)
174 
175 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
176 			 SNDRV_PCM_FMTBIT_S24_LE |\
177 			 SNDRV_PCM_FMTBIT_S32_LE)
178 
179 static struct snd_soc_dai_driver mt8183_memif_dai_driver[] = {
180 	/* FE DAIs: memory intefaces to CPU */
181 	{
182 		.name = "DL1",
183 		.id = MT8183_MEMIF_DL1,
184 		.playback = {
185 			.stream_name = "DL1",
186 			.channels_min = 1,
187 			.channels_max = 2,
188 			.rates = MTK_PCM_RATES,
189 			.formats = MTK_PCM_FORMATS,
190 		},
191 		.ops = &mtk_afe_fe_ops,
192 	},
193 	{
194 		.name = "DL2",
195 		.id = MT8183_MEMIF_DL2,
196 		.playback = {
197 			.stream_name = "DL2",
198 			.channels_min = 1,
199 			.channels_max = 2,
200 			.rates = MTK_PCM_RATES,
201 			.formats = MTK_PCM_FORMATS,
202 		},
203 		.ops = &mtk_afe_fe_ops,
204 	},
205 	{
206 		.name = "DL3",
207 		.id = MT8183_MEMIF_DL3,
208 		.playback = {
209 			.stream_name = "DL3",
210 			.channels_min = 1,
211 			.channels_max = 2,
212 			.rates = MTK_PCM_RATES,
213 			.formats = MTK_PCM_FORMATS,
214 		},
215 		.ops = &mtk_afe_fe_ops,
216 	},
217 	{
218 		.name = "UL1",
219 		.id = MT8183_MEMIF_VUL12,
220 		.capture = {
221 			.stream_name = "UL1",
222 			.channels_min = 1,
223 			.channels_max = 2,
224 			.rates = MTK_PCM_RATES,
225 			.formats = MTK_PCM_FORMATS,
226 		},
227 		.ops = &mtk_afe_fe_ops,
228 	},
229 	{
230 		.name = "UL2",
231 		.id = MT8183_MEMIF_AWB,
232 		.capture = {
233 			.stream_name = "UL2",
234 			.channels_min = 1,
235 			.channels_max = 2,
236 			.rates = MTK_PCM_RATES,
237 			.formats = MTK_PCM_FORMATS,
238 		},
239 		.ops = &mtk_afe_fe_ops,
240 	},
241 	{
242 		.name = "UL3",
243 		.id = MT8183_MEMIF_VUL2,
244 		.capture = {
245 			.stream_name = "UL3",
246 			.channels_min = 1,
247 			.channels_max = 2,
248 			.rates = MTK_PCM_RATES,
249 			.formats = MTK_PCM_FORMATS,
250 		},
251 		.ops = &mtk_afe_fe_ops,
252 	},
253 	{
254 		.name = "UL4",
255 		.id = MT8183_MEMIF_AWB2,
256 		.capture = {
257 			.stream_name = "UL4",
258 			.channels_min = 1,
259 			.channels_max = 2,
260 			.rates = MTK_PCM_RATES,
261 			.formats = MTK_PCM_FORMATS,
262 		},
263 		.ops = &mtk_afe_fe_ops,
264 	},
265 	{
266 		.name = "UL_MONO_1",
267 		.id = MT8183_MEMIF_MOD_DAI,
268 		.capture = {
269 			.stream_name = "UL_MONO_1",
270 			.channels_min = 1,
271 			.channels_max = 1,
272 			.rates = MTK_PCM_DAI_RATES,
273 			.formats = MTK_PCM_FORMATS,
274 		},
275 		.ops = &mtk_afe_fe_ops,
276 	},
277 	{
278 		.name = "HDMI",
279 		.id = MT8183_MEMIF_HDMI,
280 		.playback = {
281 			.stream_name = "HDMI",
282 			.channels_min = 2,
283 			.channels_max = 8,
284 			.rates = MTK_PCM_RATES,
285 			.formats = MTK_PCM_FORMATS,
286 		},
287 		.ops = &mtk_afe_fe_ops,
288 	},
289 };
290 
291 /* dma widget & routes*/
292 static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
293 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21,
294 				    I_ADDA_UL_CH1, 1, 0),
295 	SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN21,
296 				    I_I2S0_CH1, 1, 0),
297 };
298 
299 static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
300 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22,
301 				    I_ADDA_UL_CH2, 1, 0),
302 	SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN21,
303 				    I_I2S0_CH2, 1, 0),
304 };
305 
306 static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
307 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN5,
308 				    I_ADDA_UL_CH1, 1, 0),
309 	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5,
310 				    I_DL1_CH1, 1, 0),
311 	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5,
312 				    I_DL2_CH1, 1, 0),
313 	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5,
314 				    I_DL3_CH1, 1, 0),
315 	SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN5,
316 				    I_I2S2_CH1, 1, 0),
317 };
318 
319 static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
320 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN6,
321 				    I_ADDA_UL_CH2, 1, 0),
322 	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6,
323 				    I_DL1_CH2, 1, 0),
324 	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6,
325 				    I_DL2_CH2, 1, 0),
326 	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6,
327 				    I_DL3_CH2, 1, 0),
328 	SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN6,
329 				    I_I2S2_CH2, 1, 0),
330 };
331 
332 static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
333 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN32,
334 				    I_ADDA_UL_CH1, 1, 0),
335 	SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN32,
336 				    I_I2S2_CH1, 1, 0),
337 };
338 
339 static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
340 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN33,
341 				    I_ADDA_UL_CH2, 1, 0),
342 	SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN33,
343 				    I_I2S2_CH2, 1, 0),
344 };
345 
346 static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = {
347 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN38,
348 				    I_ADDA_UL_CH1, 1, 0),
349 };
350 
351 static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = {
352 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN39,
353 				    I_ADDA_UL_CH2, 1, 0),
354 };
355 
356 static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = {
357 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN12,
358 				    I_ADDA_UL_CH1, 1, 0),
359 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN12,
360 				    I_ADDA_UL_CH2, 1, 0),
361 };
362 
363 static const struct snd_soc_dapm_widget mt8183_memif_widgets[] = {
364 	/* memif */
365 	SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
366 			   memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
367 	SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
368 			   memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
369 
370 	SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
371 			   memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
372 	SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
373 			   memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
374 
375 	SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
376 			   memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
377 	SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
378 			   memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
379 
380 	SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0,
381 			   memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)),
382 	SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0,
383 			   memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)),
384 
385 	SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0,
386 			   memif_ul_mono_1_mix,
387 			   ARRAY_SIZE(memif_ul_mono_1_mix)),
388 };
389 
390 static const struct snd_soc_dapm_route mt8183_memif_routes[] = {
391 	/* capture */
392 	{"UL1", NULL, "UL1_CH1"},
393 	{"UL1", NULL, "UL1_CH2"},
394 	{"UL1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
395 	{"UL1_CH2", "ADDA_UL_CH2", "ADDA Capture"},
396 	{"UL1_CH1", "I2S0_CH1", "I2S0"},
397 	{"UL1_CH2", "I2S0_CH2", "I2S0"},
398 
399 	{"UL2", NULL, "UL2_CH1"},
400 	{"UL2", NULL, "UL2_CH2"},
401 	{"UL2_CH1", "ADDA_UL_CH1", "ADDA Capture"},
402 	{"UL2_CH2", "ADDA_UL_CH2", "ADDA Capture"},
403 	{"UL2_CH1", "I2S2_CH1", "I2S2"},
404 	{"UL2_CH2", "I2S2_CH2", "I2S2"},
405 
406 	{"UL3", NULL, "UL3_CH1"},
407 	{"UL3", NULL, "UL3_CH2"},
408 	{"UL3_CH1", "ADDA_UL_CH1", "ADDA Capture"},
409 	{"UL3_CH2", "ADDA_UL_CH2", "ADDA Capture"},
410 	{"UL3_CH1", "I2S2_CH1", "I2S2"},
411 	{"UL3_CH2", "I2S2_CH2", "I2S2"},
412 
413 	{"UL4", NULL, "UL4_CH1"},
414 	{"UL4", NULL, "UL4_CH2"},
415 	{"UL4_CH1", "ADDA_UL_CH1", "ADDA Capture"},
416 	{"UL4_CH2", "ADDA_UL_CH2", "ADDA Capture"},
417 
418 	{"UL_MONO_1", NULL, "UL_MONO_1_CH1"},
419 	{"UL_MONO_1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
420 	{"UL_MONO_1_CH1", "ADDA_UL_CH2", "ADDA Capture"},
421 };
422 
423 static const struct snd_soc_component_driver mt8183_afe_pcm_dai_component = {
424 	.name = "mt8183-afe-pcm-dai",
425 };
426 
427 static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
428 	[MT8183_MEMIF_DL1] = {
429 		.name = "DL1",
430 		.id = MT8183_MEMIF_DL1,
431 		.reg_ofs_base = AFE_DL1_BASE,
432 		.reg_ofs_cur = AFE_DL1_CUR,
433 		.fs_reg = AFE_DAC_CON1,
434 		.fs_shift = DL1_MODE_SFT,
435 		.fs_maskbit = DL1_MODE_MASK,
436 		.mono_reg = AFE_DAC_CON1,
437 		.mono_shift = DL1_DATA_SFT,
438 		.enable_reg = AFE_DAC_CON0,
439 		.enable_shift = DL1_ON_SFT,
440 		.hd_reg = AFE_MEMIF_HD_MODE,
441 		.hd_align_reg = AFE_MEMIF_HDALIGN,
442 		.hd_shift = DL1_HD_SFT,
443 		.hd_align_mshift = DL1_HD_ALIGN_SFT,
444 		.agent_disable_reg = -1,
445 		.agent_disable_shift = -1,
446 		.msb_reg = -1,
447 		.msb_shift = -1,
448 	},
449 	[MT8183_MEMIF_DL2] = {
450 		.name = "DL2",
451 		.id = MT8183_MEMIF_DL2,
452 		.reg_ofs_base = AFE_DL2_BASE,
453 		.reg_ofs_cur = AFE_DL2_CUR,
454 		.fs_reg = AFE_DAC_CON1,
455 		.fs_shift = DL2_MODE_SFT,
456 		.fs_maskbit = DL2_MODE_MASK,
457 		.mono_reg = AFE_DAC_CON1,
458 		.mono_shift = DL2_DATA_SFT,
459 		.enable_reg = AFE_DAC_CON0,
460 		.enable_shift = DL2_ON_SFT,
461 		.hd_reg = AFE_MEMIF_HD_MODE,
462 		.hd_align_reg = AFE_MEMIF_HDALIGN,
463 		.hd_shift = DL2_HD_SFT,
464 		.hd_align_mshift = DL2_HD_ALIGN_SFT,
465 		.agent_disable_reg = -1,
466 		.agent_disable_shift = -1,
467 		.msb_reg = -1,
468 		.msb_shift = -1,
469 	},
470 	[MT8183_MEMIF_DL3] = {
471 		.name = "DL3",
472 		.id = MT8183_MEMIF_DL3,
473 		.reg_ofs_base = AFE_DL3_BASE,
474 		.reg_ofs_cur = AFE_DL3_CUR,
475 		.fs_reg = AFE_DAC_CON2,
476 		.fs_shift = DL3_MODE_SFT,
477 		.fs_maskbit = DL3_MODE_MASK,
478 		.mono_reg = AFE_DAC_CON1,
479 		.mono_shift = DL3_DATA_SFT,
480 		.enable_reg = AFE_DAC_CON0,
481 		.enable_shift = DL3_ON_SFT,
482 		.hd_reg = AFE_MEMIF_HD_MODE,
483 		.hd_align_reg = AFE_MEMIF_HDALIGN,
484 		.hd_shift = DL3_HD_SFT,
485 		.hd_align_mshift = DL3_HD_ALIGN_SFT,
486 		.agent_disable_reg = -1,
487 		.agent_disable_shift = -1,
488 		.msb_reg = -1,
489 		.msb_shift = -1,
490 	},
491 	[MT8183_MEMIF_VUL2] = {
492 		.name = "VUL2",
493 		.id = MT8183_MEMIF_VUL2,
494 		.reg_ofs_base = AFE_VUL2_BASE,
495 		.reg_ofs_cur = AFE_VUL2_CUR,
496 		.fs_reg = AFE_DAC_CON2,
497 		.fs_shift = VUL2_MODE_SFT,
498 		.fs_maskbit = VUL2_MODE_MASK,
499 		.mono_reg = AFE_DAC_CON2,
500 		.mono_shift = VUL2_DATA_SFT,
501 		.enable_reg = AFE_DAC_CON0,
502 		.enable_shift = VUL2_ON_SFT,
503 		.hd_reg = AFE_MEMIF_HD_MODE,
504 		.hd_align_reg = AFE_MEMIF_HDALIGN,
505 		.hd_shift = VUL2_HD_SFT,
506 		.hd_align_mshift = VUL2_HD_ALIGN_SFT,
507 		.agent_disable_reg = -1,
508 		.agent_disable_shift = -1,
509 		.msb_reg = -1,
510 		.msb_shift = -1,
511 	},
512 	[MT8183_MEMIF_AWB] = {
513 		.name = "AWB",
514 		.id = MT8183_MEMIF_AWB,
515 		.reg_ofs_base = AFE_AWB_BASE,
516 		.reg_ofs_cur = AFE_AWB_CUR,
517 		.fs_reg = AFE_DAC_CON1,
518 		.fs_shift = AWB_MODE_SFT,
519 		.fs_maskbit = AWB_MODE_MASK,
520 		.mono_reg = AFE_DAC_CON1,
521 		.mono_shift = AWB_DATA_SFT,
522 		.enable_reg = AFE_DAC_CON0,
523 		.enable_shift = AWB_ON_SFT,
524 		.hd_reg = AFE_MEMIF_HD_MODE,
525 		.hd_align_reg = AFE_MEMIF_HDALIGN,
526 		.hd_shift = AWB_HD_SFT,
527 		.hd_align_mshift = AWB_HD_ALIGN_SFT,
528 		.agent_disable_reg = -1,
529 		.agent_disable_shift = -1,
530 		.msb_reg = -1,
531 		.msb_shift = -1,
532 	},
533 	[MT8183_MEMIF_AWB2] = {
534 		.name = "AWB2",
535 		.id = MT8183_MEMIF_AWB2,
536 		.reg_ofs_base = AFE_AWB2_BASE,
537 		.reg_ofs_cur = AFE_AWB2_CUR,
538 		.fs_reg = AFE_DAC_CON2,
539 		.fs_shift = AWB2_MODE_SFT,
540 		.fs_maskbit = AWB2_MODE_MASK,
541 		.mono_reg = AFE_DAC_CON2,
542 		.mono_shift = AWB2_DATA_SFT,
543 		.enable_reg = AFE_DAC_CON0,
544 		.enable_shift = AWB2_ON_SFT,
545 		.hd_reg = AFE_MEMIF_HD_MODE,
546 		.hd_align_reg = AFE_MEMIF_HDALIGN,
547 		.hd_shift = AWB2_HD_SFT,
548 		.hd_align_mshift = AWB2_ALIGN_SFT,
549 		.agent_disable_reg = -1,
550 		.agent_disable_shift = -1,
551 		.msb_reg = -1,
552 		.msb_shift = -1,
553 	},
554 	[MT8183_MEMIF_VUL12] = {
555 		.name = "VUL12",
556 		.id = MT8183_MEMIF_VUL12,
557 		.reg_ofs_base = AFE_VUL_D2_BASE,
558 		.reg_ofs_cur = AFE_VUL_D2_CUR,
559 		.fs_reg = AFE_DAC_CON0,
560 		.fs_shift = VUL12_MODE_SFT,
561 		.fs_maskbit = VUL12_MODE_MASK,
562 		.mono_reg = AFE_DAC_CON0,
563 		.mono_shift = VUL12_MONO_SFT,
564 		.enable_reg = AFE_DAC_CON0,
565 		.enable_shift = VUL12_ON_SFT,
566 		.hd_reg = AFE_MEMIF_HD_MODE,
567 		.hd_align_reg = AFE_MEMIF_HDALIGN,
568 		.hd_shift = VUL12_HD_SFT,
569 		.hd_align_mshift = VUL12_HD_ALIGN_SFT,
570 		.agent_disable_reg = -1,
571 		.agent_disable_shift = -1,
572 		.msb_reg = -1,
573 		.msb_shift = -1,
574 	},
575 	[MT8183_MEMIF_MOD_DAI] = {
576 		.name = "MOD_DAI",
577 		.id = MT8183_MEMIF_MOD_DAI,
578 		.reg_ofs_base = AFE_MOD_DAI_BASE,
579 		.reg_ofs_cur = AFE_MOD_DAI_CUR,
580 		.fs_reg = AFE_DAC_CON1,
581 		.fs_shift = MOD_DAI_MODE_SFT,
582 		.fs_maskbit = MOD_DAI_MODE_MASK,
583 		.mono_reg = -1,
584 		.mono_shift = 0,
585 		.enable_reg = AFE_DAC_CON0,
586 		.enable_shift = MOD_DAI_ON_SFT,
587 		.hd_reg = AFE_MEMIF_HD_MODE,
588 		.hd_align_reg = AFE_MEMIF_HDALIGN,
589 		.hd_shift = MOD_DAI_HD_SFT,
590 		.hd_align_mshift = MOD_DAI_HD_ALIGN_SFT,
591 		.agent_disable_reg = -1,
592 		.agent_disable_shift = -1,
593 		.msb_reg = -1,
594 		.msb_shift = -1,
595 	},
596 	[MT8183_MEMIF_HDMI] = {
597 		.name = "HDMI",
598 		.id = MT8183_MEMIF_HDMI,
599 		.reg_ofs_base = AFE_HDMI_OUT_BASE,
600 		.reg_ofs_cur = AFE_HDMI_OUT_CUR,
601 		.fs_reg = -1,
602 		.fs_shift = -1,
603 		.fs_maskbit = -1,
604 		.mono_reg = -1,
605 		.mono_shift = -1,
606 		.enable_reg = -1,	/* control in tdm for sync start */
607 		.enable_shift = -1,
608 		.hd_reg = AFE_MEMIF_HD_MODE,
609 		.hd_align_reg = AFE_MEMIF_HDALIGN,
610 		.hd_shift = HDMI_HD_SFT,
611 		.hd_align_mshift = HDMI_HD_ALIGN_SFT,
612 		.agent_disable_reg = -1,
613 		.agent_disable_shift = -1,
614 		.msb_reg = -1,
615 		.msb_shift = -1,
616 	},
617 };
618 
619 static const struct mtk_base_irq_data irq_data[MT8183_IRQ_NUM] = {
620 	[MT8183_IRQ_0] = {
621 		.id = MT8183_IRQ_0,
622 		.irq_cnt_reg = AFE_IRQ_MCU_CNT0,
623 		.irq_cnt_shift = 0,
624 		.irq_cnt_maskbit = 0x3ffff,
625 		.irq_fs_reg = AFE_IRQ_MCU_CON1,
626 		.irq_fs_shift = IRQ0_MCU_MODE_SFT,
627 		.irq_fs_maskbit = IRQ0_MCU_MODE_MASK,
628 		.irq_en_reg = AFE_IRQ_MCU_CON0,
629 		.irq_en_shift = IRQ0_MCU_ON_SFT,
630 		.irq_clr_reg = AFE_IRQ_MCU_CLR,
631 		.irq_clr_shift = IRQ0_MCU_CLR_SFT,
632 	},
633 	[MT8183_IRQ_1] = {
634 		.id = MT8183_IRQ_1,
635 		.irq_cnt_reg = AFE_IRQ_MCU_CNT1,
636 		.irq_cnt_shift = 0,
637 		.irq_cnt_maskbit = 0x3ffff,
638 		.irq_fs_reg = AFE_IRQ_MCU_CON1,
639 		.irq_fs_shift = IRQ1_MCU_MODE_SFT,
640 		.irq_fs_maskbit = IRQ1_MCU_MODE_MASK,
641 		.irq_en_reg = AFE_IRQ_MCU_CON0,
642 		.irq_en_shift = IRQ1_MCU_ON_SFT,
643 		.irq_clr_reg = AFE_IRQ_MCU_CLR,
644 		.irq_clr_shift = IRQ1_MCU_CLR_SFT,
645 	},
646 	[MT8183_IRQ_2] = {
647 		.id = MT8183_IRQ_2,
648 		.irq_cnt_reg = AFE_IRQ_MCU_CNT2,
649 		.irq_cnt_shift = 0,
650 		.irq_cnt_maskbit = 0x3ffff,
651 		.irq_fs_reg = AFE_IRQ_MCU_CON1,
652 		.irq_fs_shift = IRQ2_MCU_MODE_SFT,
653 		.irq_fs_maskbit = IRQ2_MCU_MODE_MASK,
654 		.irq_en_reg = AFE_IRQ_MCU_CON0,
655 		.irq_en_shift = IRQ2_MCU_ON_SFT,
656 		.irq_clr_reg = AFE_IRQ_MCU_CLR,
657 		.irq_clr_shift = IRQ2_MCU_CLR_SFT,
658 	},
659 	[MT8183_IRQ_3] = {
660 		.id = MT8183_IRQ_3,
661 		.irq_cnt_reg = AFE_IRQ_MCU_CNT3,
662 		.irq_cnt_shift = 0,
663 		.irq_cnt_maskbit = 0x3ffff,
664 		.irq_fs_reg = AFE_IRQ_MCU_CON1,
665 		.irq_fs_shift = IRQ3_MCU_MODE_SFT,
666 		.irq_fs_maskbit = IRQ3_MCU_MODE_MASK,
667 		.irq_en_reg = AFE_IRQ_MCU_CON0,
668 		.irq_en_shift = IRQ3_MCU_ON_SFT,
669 		.irq_clr_reg = AFE_IRQ_MCU_CLR,
670 		.irq_clr_shift = IRQ3_MCU_CLR_SFT,
671 	},
672 	[MT8183_IRQ_4] = {
673 		.id = MT8183_IRQ_4,
674 		.irq_cnt_reg = AFE_IRQ_MCU_CNT4,
675 		.irq_cnt_shift = 0,
676 		.irq_cnt_maskbit = 0x3ffff,
677 		.irq_fs_reg = AFE_IRQ_MCU_CON1,
678 		.irq_fs_shift = IRQ4_MCU_MODE_SFT,
679 		.irq_fs_maskbit = IRQ4_MCU_MODE_MASK,
680 		.irq_en_reg = AFE_IRQ_MCU_CON0,
681 		.irq_en_shift = IRQ4_MCU_ON_SFT,
682 		.irq_clr_reg = AFE_IRQ_MCU_CLR,
683 		.irq_clr_shift = IRQ4_MCU_CLR_SFT,
684 	},
685 	[MT8183_IRQ_5] = {
686 		.id = MT8183_IRQ_5,
687 		.irq_cnt_reg = AFE_IRQ_MCU_CNT5,
688 		.irq_cnt_shift = 0,
689 		.irq_cnt_maskbit = 0x3ffff,
690 		.irq_fs_reg = AFE_IRQ_MCU_CON1,
691 		.irq_fs_shift = IRQ5_MCU_MODE_SFT,
692 		.irq_fs_maskbit = IRQ5_MCU_MODE_MASK,
693 		.irq_en_reg = AFE_IRQ_MCU_CON0,
694 		.irq_en_shift = IRQ5_MCU_ON_SFT,
695 		.irq_clr_reg = AFE_IRQ_MCU_CLR,
696 		.irq_clr_shift = IRQ5_MCU_CLR_SFT,
697 	},
698 	[MT8183_IRQ_6] = {
699 		.id = MT8183_IRQ_6,
700 		.irq_cnt_reg = AFE_IRQ_MCU_CNT6,
701 		.irq_cnt_shift = 0,
702 		.irq_cnt_maskbit = 0x3ffff,
703 		.irq_fs_reg = AFE_IRQ_MCU_CON1,
704 		.irq_fs_shift = IRQ6_MCU_MODE_SFT,
705 		.irq_fs_maskbit = IRQ6_MCU_MODE_MASK,
706 		.irq_en_reg = AFE_IRQ_MCU_CON0,
707 		.irq_en_shift = IRQ6_MCU_ON_SFT,
708 		.irq_clr_reg = AFE_IRQ_MCU_CLR,
709 		.irq_clr_shift = IRQ6_MCU_CLR_SFT,
710 	},
711 	[MT8183_IRQ_7] = {
712 		.id = MT8183_IRQ_7,
713 		.irq_cnt_reg = AFE_IRQ_MCU_CNT7,
714 		.irq_cnt_shift = 0,
715 		.irq_cnt_maskbit = 0x3ffff,
716 		.irq_fs_reg = AFE_IRQ_MCU_CON1,
717 		.irq_fs_shift = IRQ7_MCU_MODE_SFT,
718 		.irq_fs_maskbit = IRQ7_MCU_MODE_MASK,
719 		.irq_en_reg = AFE_IRQ_MCU_CON0,
720 		.irq_en_shift = IRQ7_MCU_ON_SFT,
721 		.irq_clr_reg = AFE_IRQ_MCU_CLR,
722 		.irq_clr_shift = IRQ7_MCU_CLR_SFT,
723 	},
724 	[MT8183_IRQ_8] = {
725 		.id = MT8183_IRQ_8,
726 		.irq_cnt_reg = AFE_IRQ_MCU_CNT8,
727 		.irq_cnt_shift = 0,
728 		.irq_cnt_maskbit = 0x3ffff,
729 		.irq_fs_reg = -1,
730 		.irq_fs_shift = -1,
731 		.irq_fs_maskbit = -1,
732 		.irq_en_reg = AFE_IRQ_MCU_CON0,
733 		.irq_en_shift = IRQ8_MCU_ON_SFT,
734 		.irq_clr_reg = AFE_IRQ_MCU_CLR,
735 		.irq_clr_shift = IRQ8_MCU_CLR_SFT,
736 	},
737 	[MT8183_IRQ_11] = {
738 		.id = MT8183_IRQ_11,
739 		.irq_cnt_reg = AFE_IRQ_MCU_CNT11,
740 		.irq_cnt_shift = 0,
741 		.irq_cnt_maskbit = 0x3ffff,
742 		.irq_fs_reg = AFE_IRQ_MCU_CON2,
743 		.irq_fs_shift = IRQ11_MCU_MODE_SFT,
744 		.irq_fs_maskbit = IRQ11_MCU_MODE_MASK,
745 		.irq_en_reg = AFE_IRQ_MCU_CON0,
746 		.irq_en_shift = IRQ11_MCU_ON_SFT,
747 		.irq_clr_reg = AFE_IRQ_MCU_CLR,
748 		.irq_clr_shift = IRQ11_MCU_CLR_SFT,
749 	},
750 	[MT8183_IRQ_12] = {
751 		.id = MT8183_IRQ_12,
752 		.irq_cnt_reg = AFE_IRQ_MCU_CNT12,
753 		.irq_cnt_shift = 0,
754 		.irq_cnt_maskbit = 0x3ffff,
755 		.irq_fs_reg = AFE_IRQ_MCU_CON2,
756 		.irq_fs_shift = IRQ12_MCU_MODE_SFT,
757 		.irq_fs_maskbit = IRQ12_MCU_MODE_MASK,
758 		.irq_en_reg = AFE_IRQ_MCU_CON0,
759 		.irq_en_shift = IRQ12_MCU_ON_SFT,
760 		.irq_clr_reg = AFE_IRQ_MCU_CLR,
761 		.irq_clr_shift = IRQ12_MCU_CLR_SFT,
762 	},
763 };
764 
765 static bool mt8183_is_volatile_reg(struct device *dev, unsigned int reg)
766 {
767 	/* these auto-gen reg has read-only bit, so put it as volatile */
768 	/* volatile reg cannot be cached, so cannot be set when power off */
769 	switch (reg) {
770 	case AUDIO_TOP_CON0:	/* reg bit controlled by CCF */
771 	case AUDIO_TOP_CON1:	/* reg bit controlled by CCF */
772 	case AUDIO_TOP_CON3:
773 	case AFE_DL1_CUR:
774 	case AFE_DL1_END:
775 	case AFE_DL2_CUR:
776 	case AFE_DL2_END:
777 	case AFE_AWB_END:
778 	case AFE_AWB_CUR:
779 	case AFE_VUL_END:
780 	case AFE_VUL_CUR:
781 	case AFE_MEMIF_MON0:
782 	case AFE_MEMIF_MON1:
783 	case AFE_MEMIF_MON2:
784 	case AFE_MEMIF_MON3:
785 	case AFE_MEMIF_MON4:
786 	case AFE_MEMIF_MON5:
787 	case AFE_MEMIF_MON6:
788 	case AFE_MEMIF_MON7:
789 	case AFE_MEMIF_MON8:
790 	case AFE_MEMIF_MON9:
791 	case AFE_ADDA_SRC_DEBUG_MON0:
792 	case AFE_ADDA_SRC_DEBUG_MON1:
793 	case AFE_ADDA_UL_SRC_MON0:
794 	case AFE_ADDA_UL_SRC_MON1:
795 	case AFE_SIDETONE_MON:
796 	case AFE_SIDETONE_CON0:
797 	case AFE_SIDETONE_COEFF:
798 	case AFE_BUS_MON0:
799 	case AFE_MRGIF_MON0:
800 	case AFE_MRGIF_MON1:
801 	case AFE_MRGIF_MON2:
802 	case AFE_I2S_MON:
803 	case AFE_DAC_MON:
804 	case AFE_VUL2_END:
805 	case AFE_VUL2_CUR:
806 	case AFE_IRQ0_MCU_CNT_MON:
807 	case AFE_IRQ6_MCU_CNT_MON:
808 	case AFE_MOD_DAI_END:
809 	case AFE_MOD_DAI_CUR:
810 	case AFE_VUL_D2_END:
811 	case AFE_VUL_D2_CUR:
812 	case AFE_DL3_CUR:
813 	case AFE_DL3_END:
814 	case AFE_HDMI_OUT_CON0:
815 	case AFE_HDMI_OUT_CUR:
816 	case AFE_HDMI_OUT_END:
817 	case AFE_IRQ3_MCU_CNT_MON:
818 	case AFE_IRQ4_MCU_CNT_MON:
819 	case AFE_IRQ_MCU_STATUS:
820 	case AFE_IRQ_MCU_CLR:
821 	case AFE_IRQ_MCU_MON2:
822 	case AFE_IRQ1_MCU_CNT_MON:
823 	case AFE_IRQ2_MCU_CNT_MON:
824 	case AFE_IRQ1_MCU_EN_CNT_MON:
825 	case AFE_IRQ5_MCU_CNT_MON:
826 	case AFE_IRQ7_MCU_CNT_MON:
827 	case AFE_GAIN1_CUR:
828 	case AFE_GAIN2_CUR:
829 	case AFE_SRAM_DELSEL_CON0:
830 	case AFE_SRAM_DELSEL_CON2:
831 	case AFE_SRAM_DELSEL_CON3:
832 	case AFE_ASRC_2CH_CON12:
833 	case AFE_ASRC_2CH_CON13:
834 	case PCM_INTF_CON2:
835 	case FPGA_CFG0:
836 	case FPGA_CFG1:
837 	case FPGA_CFG2:
838 	case FPGA_CFG3:
839 	case AUDIO_TOP_DBG_MON0:
840 	case AUDIO_TOP_DBG_MON1:
841 	case AFE_IRQ8_MCU_CNT_MON:
842 	case AFE_IRQ11_MCU_CNT_MON:
843 	case AFE_IRQ12_MCU_CNT_MON:
844 	case AFE_CBIP_MON0:
845 	case AFE_CBIP_SLV_MUX_MON0:
846 	case AFE_CBIP_SLV_DECODER_MON0:
847 	case AFE_ADDA6_SRC_DEBUG_MON0:
848 	case AFE_ADD6A_UL_SRC_MON0:
849 	case AFE_ADDA6_UL_SRC_MON1:
850 	case AFE_DL1_CUR_MSB:
851 	case AFE_DL2_CUR_MSB:
852 	case AFE_AWB_CUR_MSB:
853 	case AFE_VUL_CUR_MSB:
854 	case AFE_VUL2_CUR_MSB:
855 	case AFE_MOD_DAI_CUR_MSB:
856 	case AFE_VUL_D2_CUR_MSB:
857 	case AFE_DL3_CUR_MSB:
858 	case AFE_HDMI_OUT_CUR_MSB:
859 	case AFE_AWB2_END:
860 	case AFE_AWB2_CUR:
861 	case AFE_AWB2_CUR_MSB:
862 	case AFE_ADDA_DL_SDM_FIFO_MON:
863 	case AFE_ADDA_DL_SRC_LCH_MON:
864 	case AFE_ADDA_DL_SRC_RCH_MON:
865 	case AFE_ADDA_DL_SDM_OUT_MON:
866 	case AFE_CONNSYS_I2S_MON:
867 	case AFE_ASRC_2CH_CON0:
868 	case AFE_ASRC_2CH_CON2:
869 	case AFE_ASRC_2CH_CON3:
870 	case AFE_ASRC_2CH_CON4:
871 	case AFE_ASRC_2CH_CON5:
872 	case AFE_ASRC_2CH_CON7:
873 	case AFE_ASRC_2CH_CON8:
874 	case AFE_MEMIF_MON12:
875 	case AFE_MEMIF_MON13:
876 	case AFE_MEMIF_MON14:
877 	case AFE_MEMIF_MON15:
878 	case AFE_MEMIF_MON16:
879 	case AFE_MEMIF_MON17:
880 	case AFE_MEMIF_MON18:
881 	case AFE_MEMIF_MON19:
882 	case AFE_MEMIF_MON20:
883 	case AFE_MEMIF_MON21:
884 	case AFE_MEMIF_MON22:
885 	case AFE_MEMIF_MON23:
886 	case AFE_MEMIF_MON24:
887 	case AFE_ADDA_MTKAIF_MON0:
888 	case AFE_ADDA_MTKAIF_MON1:
889 	case AFE_AUD_PAD_TOP:
890 	case AFE_GENERAL1_ASRC_2CH_CON0:
891 	case AFE_GENERAL1_ASRC_2CH_CON2:
892 	case AFE_GENERAL1_ASRC_2CH_CON3:
893 	case AFE_GENERAL1_ASRC_2CH_CON4:
894 	case AFE_GENERAL1_ASRC_2CH_CON5:
895 	case AFE_GENERAL1_ASRC_2CH_CON7:
896 	case AFE_GENERAL1_ASRC_2CH_CON8:
897 	case AFE_GENERAL1_ASRC_2CH_CON12:
898 	case AFE_GENERAL1_ASRC_2CH_CON13:
899 	case AFE_GENERAL2_ASRC_2CH_CON0:
900 	case AFE_GENERAL2_ASRC_2CH_CON2:
901 	case AFE_GENERAL2_ASRC_2CH_CON3:
902 	case AFE_GENERAL2_ASRC_2CH_CON4:
903 	case AFE_GENERAL2_ASRC_2CH_CON5:
904 	case AFE_GENERAL2_ASRC_2CH_CON7:
905 	case AFE_GENERAL2_ASRC_2CH_CON8:
906 	case AFE_GENERAL2_ASRC_2CH_CON12:
907 	case AFE_GENERAL2_ASRC_2CH_CON13:
908 		return true;
909 	default:
910 		return false;
911 	};
912 }
913 
914 static const struct regmap_config mt8183_afe_regmap_config = {
915 	.reg_bits = 32,
916 	.reg_stride = 4,
917 	.val_bits = 32,
918 
919 	.volatile_reg = mt8183_is_volatile_reg,
920 
921 	.max_register = AFE_MAX_REGISTER,
922 	.num_reg_defaults_raw = AFE_MAX_REGISTER,
923 
924 	.cache_type = REGCACHE_FLAT,
925 };
926 
927 static irqreturn_t mt8183_afe_irq_handler(int irq_id, void *dev)
928 {
929 	struct mtk_base_afe *afe = dev;
930 	struct mtk_base_afe_irq *irq;
931 	unsigned int status;
932 	unsigned int status_mcu;
933 	unsigned int mcu_en;
934 	int ret;
935 	int i;
936 	irqreturn_t irq_ret = IRQ_HANDLED;
937 
938 	/* get irq that is sent to MCU */
939 	regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
940 
941 	ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
942 	/* only care IRQ which is sent to MCU */
943 	status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
944 
945 	if (ret || status_mcu == 0) {
946 		dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
947 			__func__, ret, status, mcu_en);
948 
949 		irq_ret = IRQ_NONE;
950 		goto err_irq;
951 	}
952 
953 	for (i = 0; i < MT8183_MEMIF_NUM; i++) {
954 		struct mtk_base_afe_memif *memif = &afe->memif[i];
955 
956 		if (!memif->substream)
957 			continue;
958 
959 		if (memif->irq_usage < 0)
960 			continue;
961 
962 		irq = &afe->irqs[memif->irq_usage];
963 
964 		if (status_mcu & (1 << irq->irq_data->irq_en_shift))
965 			snd_pcm_period_elapsed(memif->substream);
966 	}
967 
968 err_irq:
969 	/* clear irq */
970 	regmap_write(afe->regmap,
971 		     AFE_IRQ_MCU_CLR,
972 		     status_mcu);
973 
974 	return irq_ret;
975 }
976 
977 static int mt8183_afe_runtime_suspend(struct device *dev)
978 {
979 	struct mtk_base_afe *afe = dev_get_drvdata(dev);
980 	struct mt8183_afe_private *afe_priv = afe->platform_priv;
981 	unsigned int value;
982 	int ret;
983 
984 	if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
985 		goto skip_regmap;
986 
987 	/* disable AFE */
988 	regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0);
989 
990 	ret = regmap_read_poll_timeout(afe->regmap,
991 				       AFE_DAC_MON,
992 				       value,
993 				       (value & AFE_ON_RETM_MASK_SFT) == 0,
994 				       20,
995 				       1 * 1000 * 1000);
996 	if (ret)
997 		dev_warn(afe->dev, "%s(), ret %d\n", __func__, ret);
998 
999 	/* make sure all irq status are cleared, twice intended */
1000 	regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
1001 	regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
1002 
1003 	/* cache only */
1004 	regcache_cache_only(afe->regmap, true);
1005 	regcache_mark_dirty(afe->regmap);
1006 
1007 skip_regmap:
1008 	return mt8183_afe_disable_clock(afe);
1009 }
1010 
1011 static int mt8183_afe_runtime_resume(struct device *dev)
1012 {
1013 	struct mtk_base_afe *afe = dev_get_drvdata(dev);
1014 	struct mt8183_afe_private *afe_priv = afe->platform_priv;
1015 	int ret;
1016 
1017 	ret = mt8183_afe_enable_clock(afe);
1018 	if (ret)
1019 		return ret;
1020 
1021 	if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
1022 		goto skip_regmap;
1023 
1024 	regcache_cache_only(afe->regmap, false);
1025 	regcache_sync(afe->regmap);
1026 
1027 	/* enable audio sys DCM for power saving */
1028 	regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 0x1 << 29, 0x1 << 29);
1029 
1030 	/* force cpu use 8_24 format when writing 32bit data */
1031 	regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
1032 			   CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT);
1033 
1034 	/* set all output port to 24bit */
1035 	regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff);
1036 	regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff);
1037 
1038 	/* enable AFE */
1039 	regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
1040 
1041 skip_regmap:
1042 	return 0;
1043 }
1044 
1045 static int mt8183_afe_component_probe(struct snd_soc_component *component)
1046 {
1047 	return mtk_afe_add_sub_dai_control(component);
1048 }
1049 
1050 static const struct snd_soc_component_driver mt8183_afe_component = {
1051 	.name		= AFE_PCM_NAME,
1052 	.probe		= mt8183_afe_component_probe,
1053 	.pointer	= mtk_afe_pcm_pointer,
1054 	.pcm_construct	= mtk_afe_pcm_new,
1055 };
1056 
1057 static int mt8183_dai_memif_register(struct mtk_base_afe *afe)
1058 {
1059 	struct mtk_base_afe_dai *dai;
1060 
1061 	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
1062 	if (!dai)
1063 		return -ENOMEM;
1064 
1065 	list_add(&dai->list, &afe->sub_dais);
1066 
1067 	dai->dai_drivers = mt8183_memif_dai_driver;
1068 	dai->num_dai_drivers = ARRAY_SIZE(mt8183_memif_dai_driver);
1069 
1070 	dai->dapm_widgets = mt8183_memif_widgets;
1071 	dai->num_dapm_widgets = ARRAY_SIZE(mt8183_memif_widgets);
1072 	dai->dapm_routes = mt8183_memif_routes;
1073 	dai->num_dapm_routes = ARRAY_SIZE(mt8183_memif_routes);
1074 	return 0;
1075 }
1076 
1077 typedef int (*dai_register_cb)(struct mtk_base_afe *);
1078 static const dai_register_cb dai_register_cbs[] = {
1079 	mt8183_dai_adda_register,
1080 	mt8183_dai_i2s_register,
1081 	mt8183_dai_pcm_register,
1082 	mt8183_dai_tdm_register,
1083 	mt8183_dai_hostless_register,
1084 	mt8183_dai_memif_register,
1085 };
1086 
1087 static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev)
1088 {
1089 	struct mtk_base_afe *afe;
1090 	struct mt8183_afe_private *afe_priv;
1091 	struct device *dev;
1092 	struct reset_control *rstc;
1093 	int i, irq_id, ret;
1094 
1095 	afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1096 	if (!afe)
1097 		return -ENOMEM;
1098 	platform_set_drvdata(pdev, afe);
1099 
1100 	afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
1101 					  GFP_KERNEL);
1102 	if (!afe->platform_priv)
1103 		return -ENOMEM;
1104 
1105 	afe_priv = afe->platform_priv;
1106 	afe->dev = &pdev->dev;
1107 	dev = afe->dev;
1108 
1109 	/* initial audio related clock */
1110 	ret = mt8183_init_clock(afe);
1111 	if (ret) {
1112 		dev_err(dev, "init clock error\n");
1113 		return ret;
1114 	}
1115 
1116 	pm_runtime_enable(dev);
1117 
1118 	/* regmap init */
1119 	afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
1120 	if (IS_ERR(afe->regmap)) {
1121 		dev_err(dev, "could not get regmap from parent\n");
1122 		return PTR_ERR(afe->regmap);
1123 	}
1124 	ret = regmap_attach_dev(dev, afe->regmap, &mt8183_afe_regmap_config);
1125 	if (ret) {
1126 		dev_warn(dev, "regmap_attach_dev fail, ret %d\n", ret);
1127 		return ret;
1128 	}
1129 
1130 	rstc = devm_reset_control_get(dev, "audiosys");
1131 	if (IS_ERR(rstc)) {
1132 		ret = PTR_ERR(rstc);
1133 		dev_err(dev, "could not get audiosys reset:%d\n", ret);
1134 		return ret;
1135 	}
1136 
1137 	ret = reset_control_reset(rstc);
1138 	if (ret) {
1139 		dev_err(dev, "failed to trigger audio reset:%d\n", ret);
1140 		return ret;
1141 	}
1142 
1143 	/* enable clock for regcache get default value from hw */
1144 	afe_priv->pm_runtime_bypass_reg_ctl = true;
1145 	pm_runtime_get_sync(&pdev->dev);
1146 
1147 	ret = regmap_reinit_cache(afe->regmap, &mt8183_afe_regmap_config);
1148 	if (ret) {
1149 		dev_err(dev, "regmap_reinit_cache fail, ret %d\n", ret);
1150 		return ret;
1151 	}
1152 
1153 	pm_runtime_put_sync(&pdev->dev);
1154 	afe_priv->pm_runtime_bypass_reg_ctl = false;
1155 
1156 	regcache_cache_only(afe->regmap, true);
1157 	regcache_mark_dirty(afe->regmap);
1158 
1159 	/* init memif */
1160 	afe->memif_size = MT8183_MEMIF_NUM;
1161 	afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
1162 				  GFP_KERNEL);
1163 	if (!afe->memif)
1164 		return -ENOMEM;
1165 
1166 	for (i = 0; i < afe->memif_size; i++) {
1167 		afe->memif[i].data = &memif_data[i];
1168 		afe->memif[i].irq_usage = -1;
1169 	}
1170 
1171 	afe->memif[MT8183_MEMIF_HDMI].irq_usage = MT8183_IRQ_8;
1172 	afe->memif[MT8183_MEMIF_HDMI].const_irq = 1;
1173 
1174 	mutex_init(&afe->irq_alloc_lock);
1175 
1176 	/* init memif */
1177 	/* irq initialize */
1178 	afe->irqs_size = MT8183_IRQ_NUM;
1179 	afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
1180 				 GFP_KERNEL);
1181 	if (!afe->irqs)
1182 		return -ENOMEM;
1183 
1184 	for (i = 0; i < afe->irqs_size; i++)
1185 		afe->irqs[i].irq_data = &irq_data[i];
1186 
1187 	/* request irq */
1188 	irq_id = platform_get_irq(pdev, 0);
1189 	if (irq_id < 0)
1190 		return irq_id;
1191 
1192 	ret = devm_request_irq(dev, irq_id, mt8183_afe_irq_handler,
1193 			       IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
1194 	if (ret) {
1195 		dev_err(dev, "could not request_irq for asys-isr\n");
1196 		return ret;
1197 	}
1198 
1199 	/* init sub_dais */
1200 	INIT_LIST_HEAD(&afe->sub_dais);
1201 
1202 	for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
1203 		ret = dai_register_cbs[i](afe);
1204 		if (ret) {
1205 			dev_warn(afe->dev, "dai register i %d fail, ret %d\n",
1206 				 i, ret);
1207 			return ret;
1208 		}
1209 	}
1210 
1211 	/* init dai_driver and component_driver */
1212 	ret = mtk_afe_combine_sub_dai(afe);
1213 	if (ret) {
1214 		dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n",
1215 			 ret);
1216 		return ret;
1217 	}
1218 
1219 	afe->mtk_afe_hardware = &mt8183_afe_hardware;
1220 	afe->memif_fs = mt8183_memif_fs;
1221 	afe->irq_fs = mt8183_irq_fs;
1222 
1223 	afe->runtime_resume = mt8183_afe_runtime_resume;
1224 	afe->runtime_suspend = mt8183_afe_runtime_suspend;
1225 
1226 	/* register component */
1227 	ret = devm_snd_soc_register_component(&pdev->dev,
1228 					      &mt8183_afe_component,
1229 					      NULL, 0);
1230 	if (ret) {
1231 		dev_warn(dev, "err_platform\n");
1232 		return ret;
1233 	}
1234 
1235 	ret = devm_snd_soc_register_component(afe->dev,
1236 					      &mt8183_afe_pcm_dai_component,
1237 					      afe->dai_drivers,
1238 					      afe->num_dai_drivers);
1239 	if (ret) {
1240 		dev_warn(dev, "err_dai_component\n");
1241 		return ret;
1242 	}
1243 
1244 	return ret;
1245 }
1246 
1247 static int mt8183_afe_pcm_dev_remove(struct platform_device *pdev)
1248 {
1249 	pm_runtime_disable(&pdev->dev);
1250 	if (!pm_runtime_status_suspended(&pdev->dev))
1251 		mt8183_afe_runtime_suspend(&pdev->dev);
1252 
1253 	return 0;
1254 }
1255 
1256 static const struct of_device_id mt8183_afe_pcm_dt_match[] = {
1257 	{ .compatible = "mediatek,mt8183-audio", },
1258 	{},
1259 };
1260 MODULE_DEVICE_TABLE(of, mt8183_afe_pcm_dt_match);
1261 
1262 static const struct dev_pm_ops mt8183_afe_pm_ops = {
1263 	SET_RUNTIME_PM_OPS(mt8183_afe_runtime_suspend,
1264 			   mt8183_afe_runtime_resume, NULL)
1265 };
1266 
1267 static struct platform_driver mt8183_afe_pcm_driver = {
1268 	.driver = {
1269 		   .name = "mt8183-audio",
1270 		   .of_match_table = mt8183_afe_pcm_dt_match,
1271 #ifdef CONFIG_PM
1272 		   .pm = &mt8183_afe_pm_ops,
1273 #endif
1274 	},
1275 	.probe = mt8183_afe_pcm_dev_probe,
1276 	.remove = mt8183_afe_pcm_dev_remove,
1277 };
1278 
1279 module_platform_driver(mt8183_afe_pcm_driver);
1280 
1281 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8183");
1282 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
1283 MODULE_LICENSE("GPL v2");
1284