1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Mediatek ALSA SoC AFE platform driver for 8183 4 // 5 // Copyright (c) 2018 MediaTek Inc. 6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7 8 #include <linux/delay.h> 9 #include <linux/module.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/pm_runtime.h> 14 15 #include "mt8183-afe-common.h" 16 #include "mt8183-afe-clk.h" 17 #include "mt8183-interconnection.h" 18 #include "mt8183-reg.h" 19 #include "../common/mtk-afe-platform-driver.h" 20 #include "../common/mtk-afe-fe-dai.h" 21 22 enum { 23 MTK_AFE_RATE_8K = 0, 24 MTK_AFE_RATE_11K = 1, 25 MTK_AFE_RATE_12K = 2, 26 MTK_AFE_RATE_384K = 3, 27 MTK_AFE_RATE_16K = 4, 28 MTK_AFE_RATE_22K = 5, 29 MTK_AFE_RATE_24K = 6, 30 MTK_AFE_RATE_130K = 7, 31 MTK_AFE_RATE_32K = 8, 32 MTK_AFE_RATE_44K = 9, 33 MTK_AFE_RATE_48K = 10, 34 MTK_AFE_RATE_88K = 11, 35 MTK_AFE_RATE_96K = 12, 36 MTK_AFE_RATE_176K = 13, 37 MTK_AFE_RATE_192K = 14, 38 MTK_AFE_RATE_260K = 15, 39 }; 40 41 enum { 42 MTK_AFE_DAI_MEMIF_RATE_8K = 0, 43 MTK_AFE_DAI_MEMIF_RATE_16K = 1, 44 MTK_AFE_DAI_MEMIF_RATE_32K = 2, 45 MTK_AFE_DAI_MEMIF_RATE_48K = 3, 46 }; 47 48 enum { 49 MTK_AFE_PCM_RATE_8K = 0, 50 MTK_AFE_PCM_RATE_16K = 1, 51 MTK_AFE_PCM_RATE_32K = 2, 52 MTK_AFE_PCM_RATE_48K = 3, 53 }; 54 55 unsigned int mt8183_general_rate_transform(struct device *dev, 56 unsigned int rate) 57 { 58 switch (rate) { 59 case 8000: 60 return MTK_AFE_RATE_8K; 61 case 11025: 62 return MTK_AFE_RATE_11K; 63 case 12000: 64 return MTK_AFE_RATE_12K; 65 case 16000: 66 return MTK_AFE_RATE_16K; 67 case 22050: 68 return MTK_AFE_RATE_22K; 69 case 24000: 70 return MTK_AFE_RATE_24K; 71 case 32000: 72 return MTK_AFE_RATE_32K; 73 case 44100: 74 return MTK_AFE_RATE_44K; 75 case 48000: 76 return MTK_AFE_RATE_48K; 77 case 88200: 78 return MTK_AFE_RATE_88K; 79 case 96000: 80 return MTK_AFE_RATE_96K; 81 case 130000: 82 return MTK_AFE_RATE_130K; 83 case 176400: 84 return MTK_AFE_RATE_176K; 85 case 192000: 86 return MTK_AFE_RATE_192K; 87 case 260000: 88 return MTK_AFE_RATE_260K; 89 default: 90 dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n", 91 __func__, rate, MTK_AFE_RATE_48K); 92 return MTK_AFE_RATE_48K; 93 } 94 } 95 96 static unsigned int dai_memif_rate_transform(struct device *dev, 97 unsigned int rate) 98 { 99 switch (rate) { 100 case 8000: 101 return MTK_AFE_DAI_MEMIF_RATE_8K; 102 case 16000: 103 return MTK_AFE_DAI_MEMIF_RATE_16K; 104 case 32000: 105 return MTK_AFE_DAI_MEMIF_RATE_32K; 106 case 48000: 107 return MTK_AFE_DAI_MEMIF_RATE_48K; 108 default: 109 dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n", 110 __func__, rate, MTK_AFE_DAI_MEMIF_RATE_16K); 111 return MTK_AFE_DAI_MEMIF_RATE_16K; 112 } 113 } 114 115 unsigned int mt8183_rate_transform(struct device *dev, 116 unsigned int rate, int aud_blk) 117 { 118 switch (aud_blk) { 119 case MT8183_MEMIF_MOD_DAI: 120 return dai_memif_rate_transform(dev, rate); 121 default: 122 return mt8183_general_rate_transform(dev, rate); 123 } 124 } 125 126 static const struct snd_pcm_hardware mt8183_afe_hardware = { 127 .info = SNDRV_PCM_INFO_MMAP | 128 SNDRV_PCM_INFO_INTERLEAVED | 129 SNDRV_PCM_INFO_MMAP_VALID, 130 .formats = SNDRV_PCM_FMTBIT_S16_LE | 131 SNDRV_PCM_FMTBIT_S24_LE | 132 SNDRV_PCM_FMTBIT_S32_LE, 133 .period_bytes_min = 256, 134 .period_bytes_max = 4 * 48 * 1024, 135 .periods_min = 2, 136 .periods_max = 256, 137 .buffer_bytes_max = 8 * 48 * 1024, 138 .fifo_size = 0, 139 }; 140 141 static int mt8183_memif_fs(struct snd_pcm_substream *substream, 142 unsigned int rate) 143 { 144 struct snd_soc_pcm_runtime *rtd = substream->private_data; 145 struct snd_soc_component *component = 146 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 147 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 148 int id = rtd->cpu_dai->id; 149 150 return mt8183_rate_transform(afe->dev, rate, id); 151 } 152 153 static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) 154 { 155 struct snd_soc_pcm_runtime *rtd = substream->private_data; 156 struct snd_soc_component *component = 157 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 158 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 159 160 return mt8183_general_rate_transform(afe->dev, rate); 161 } 162 163 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\ 164 SNDRV_PCM_RATE_88200 |\ 165 SNDRV_PCM_RATE_96000 |\ 166 SNDRV_PCM_RATE_176400 |\ 167 SNDRV_PCM_RATE_192000) 168 169 #define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\ 170 SNDRV_PCM_RATE_16000 |\ 171 SNDRV_PCM_RATE_32000 |\ 172 SNDRV_PCM_RATE_48000) 173 174 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 175 SNDRV_PCM_FMTBIT_S24_LE |\ 176 SNDRV_PCM_FMTBIT_S32_LE) 177 178 static struct snd_soc_dai_driver mt8183_memif_dai_driver[] = { 179 /* FE DAIs: memory intefaces to CPU */ 180 { 181 .name = "DL1", 182 .id = MT8183_MEMIF_DL1, 183 .playback = { 184 .stream_name = "DL1", 185 .channels_min = 1, 186 .channels_max = 2, 187 .rates = MTK_PCM_RATES, 188 .formats = MTK_PCM_FORMATS, 189 }, 190 .ops = &mtk_afe_fe_ops, 191 }, 192 { 193 .name = "DL2", 194 .id = MT8183_MEMIF_DL2, 195 .playback = { 196 .stream_name = "DL2", 197 .channels_min = 1, 198 .channels_max = 2, 199 .rates = MTK_PCM_RATES, 200 .formats = MTK_PCM_FORMATS, 201 }, 202 .ops = &mtk_afe_fe_ops, 203 }, 204 { 205 .name = "DL3", 206 .id = MT8183_MEMIF_DL3, 207 .playback = { 208 .stream_name = "DL3", 209 .channels_min = 1, 210 .channels_max = 2, 211 .rates = MTK_PCM_RATES, 212 .formats = MTK_PCM_FORMATS, 213 }, 214 .ops = &mtk_afe_fe_ops, 215 }, 216 { 217 .name = "UL1", 218 .id = MT8183_MEMIF_VUL12, 219 .capture = { 220 .stream_name = "UL1", 221 .channels_min = 1, 222 .channels_max = 2, 223 .rates = MTK_PCM_RATES, 224 .formats = MTK_PCM_FORMATS, 225 }, 226 .ops = &mtk_afe_fe_ops, 227 }, 228 { 229 .name = "UL2", 230 .id = MT8183_MEMIF_AWB, 231 .capture = { 232 .stream_name = "UL2", 233 .channels_min = 1, 234 .channels_max = 2, 235 .rates = MTK_PCM_RATES, 236 .formats = MTK_PCM_FORMATS, 237 }, 238 .ops = &mtk_afe_fe_ops, 239 }, 240 { 241 .name = "UL3", 242 .id = MT8183_MEMIF_VUL2, 243 .capture = { 244 .stream_name = "UL3", 245 .channels_min = 1, 246 .channels_max = 2, 247 .rates = MTK_PCM_RATES, 248 .formats = MTK_PCM_FORMATS, 249 }, 250 .ops = &mtk_afe_fe_ops, 251 }, 252 { 253 .name = "UL4", 254 .id = MT8183_MEMIF_AWB2, 255 .capture = { 256 .stream_name = "UL4", 257 .channels_min = 1, 258 .channels_max = 2, 259 .rates = MTK_PCM_RATES, 260 .formats = MTK_PCM_FORMATS, 261 }, 262 .ops = &mtk_afe_fe_ops, 263 }, 264 { 265 .name = "UL_MONO_1", 266 .id = MT8183_MEMIF_MOD_DAI, 267 .capture = { 268 .stream_name = "UL_MONO_1", 269 .channels_min = 1, 270 .channels_max = 1, 271 .rates = MTK_PCM_DAI_RATES, 272 .formats = MTK_PCM_FORMATS, 273 }, 274 .ops = &mtk_afe_fe_ops, 275 }, 276 { 277 .name = "HDMI", 278 .id = MT8183_MEMIF_HDMI, 279 .playback = { 280 .stream_name = "HDMI", 281 .channels_min = 2, 282 .channels_max = 8, 283 .rates = MTK_PCM_RATES, 284 .formats = MTK_PCM_FORMATS, 285 }, 286 .ops = &mtk_afe_fe_ops, 287 }, 288 }; 289 290 /* dma widget & routes*/ 291 static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = { 292 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21, 293 I_ADDA_UL_CH1, 1, 0), 294 }; 295 296 static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = { 297 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22, 298 I_ADDA_UL_CH2, 1, 0), 299 }; 300 301 static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = { 302 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN5, 303 I_ADDA_UL_CH1, 1, 0), 304 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5, 305 I_DL1_CH1, 1, 0), 306 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5, 307 I_DL2_CH1, 1, 0), 308 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5, 309 I_DL3_CH1, 1, 0), 310 }; 311 312 static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = { 313 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN6, 314 I_ADDA_UL_CH2, 1, 0), 315 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6, 316 I_DL1_CH2, 1, 0), 317 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6, 318 I_DL2_CH2, 1, 0), 319 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6, 320 I_DL3_CH2, 1, 0), 321 }; 322 323 static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = { 324 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN32, 325 I_ADDA_UL_CH1, 1, 0), 326 }; 327 328 static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = { 329 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN33, 330 I_ADDA_UL_CH2, 1, 0), 331 }; 332 333 static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = { 334 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN38, 335 I_ADDA_UL_CH1, 1, 0), 336 }; 337 338 static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = { 339 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN39, 340 I_ADDA_UL_CH2, 1, 0), 341 }; 342 343 static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = { 344 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN12, 345 I_ADDA_UL_CH1, 1, 0), 346 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN12, 347 I_ADDA_UL_CH2, 1, 0), 348 }; 349 350 static const struct snd_soc_dapm_widget mt8183_memif_widgets[] = { 351 /* memif */ 352 SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0, 353 memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)), 354 SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0, 355 memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)), 356 357 SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0, 358 memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)), 359 SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0, 360 memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)), 361 362 SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0, 363 memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)), 364 SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0, 365 memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)), 366 367 SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0, 368 memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)), 369 SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0, 370 memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)), 371 372 SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0, 373 memif_ul_mono_1_mix, 374 ARRAY_SIZE(memif_ul_mono_1_mix)), 375 }; 376 377 static const struct snd_soc_dapm_route mt8183_memif_routes[] = { 378 /* capture */ 379 {"UL1", NULL, "UL1_CH1"}, 380 {"UL1", NULL, "UL1_CH2"}, 381 {"UL1_CH1", "ADDA_UL_CH1", "ADDA Capture"}, 382 {"UL1_CH2", "ADDA_UL_CH2", "ADDA Capture"}, 383 384 {"UL2", NULL, "UL2_CH1"}, 385 {"UL2", NULL, "UL2_CH2"}, 386 {"UL2_CH1", "ADDA_UL_CH1", "ADDA Capture"}, 387 {"UL2_CH2", "ADDA_UL_CH2", "ADDA Capture"}, 388 389 {"UL3", NULL, "UL3_CH1"}, 390 {"UL3", NULL, "UL3_CH2"}, 391 {"UL3_CH1", "ADDA_UL_CH1", "ADDA Capture"}, 392 {"UL3_CH2", "ADDA_UL_CH2", "ADDA Capture"}, 393 394 {"UL4", NULL, "UL4_CH1"}, 395 {"UL4", NULL, "UL4_CH2"}, 396 {"UL4_CH1", "ADDA_UL_CH1", "ADDA Capture"}, 397 {"UL4_CH2", "ADDA_UL_CH2", "ADDA Capture"}, 398 399 {"UL_MONO_1", NULL, "UL_MONO_1_CH1"}, 400 {"UL_MONO_1_CH1", "ADDA_UL_CH1", "ADDA Capture"}, 401 {"UL_MONO_1_CH1", "ADDA_UL_CH2", "ADDA Capture"}, 402 }; 403 404 static const struct snd_soc_component_driver mt8183_afe_pcm_dai_component = { 405 .name = "mt8183-afe-pcm-dai", 406 }; 407 408 static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { 409 [MT8183_MEMIF_DL1] = { 410 .name = "DL1", 411 .id = MT8183_MEMIF_DL1, 412 .reg_ofs_base = AFE_DL1_BASE, 413 .reg_ofs_cur = AFE_DL1_CUR, 414 .fs_reg = AFE_DAC_CON1, 415 .fs_shift = DL1_MODE_SFT, 416 .fs_maskbit = DL1_MODE_MASK, 417 .mono_reg = AFE_DAC_CON1, 418 .mono_shift = DL1_DATA_SFT, 419 .enable_reg = AFE_DAC_CON0, 420 .enable_shift = DL1_ON_SFT, 421 .hd_reg = AFE_MEMIF_HD_MODE, 422 .hd_shift = DL1_HD_SFT, 423 .agent_disable_reg = -1, 424 .agent_disable_shift = -1, 425 .msb_reg = -1, 426 .msb_shift = -1, 427 }, 428 [MT8183_MEMIF_DL2] = { 429 .name = "DL2", 430 .id = MT8183_MEMIF_DL2, 431 .reg_ofs_base = AFE_DL2_BASE, 432 .reg_ofs_cur = AFE_DL2_CUR, 433 .fs_reg = AFE_DAC_CON1, 434 .fs_shift = DL2_MODE_SFT, 435 .fs_maskbit = DL2_MODE_MASK, 436 .mono_reg = AFE_DAC_CON1, 437 .mono_shift = DL2_DATA_SFT, 438 .enable_reg = AFE_DAC_CON0, 439 .enable_shift = DL2_ON_SFT, 440 .hd_reg = AFE_MEMIF_HD_MODE, 441 .hd_shift = DL2_HD_SFT, 442 .agent_disable_reg = -1, 443 .agent_disable_shift = -1, 444 .msb_reg = -1, 445 .msb_shift = -1, 446 }, 447 [MT8183_MEMIF_DL3] = { 448 .name = "DL3", 449 .id = MT8183_MEMIF_DL3, 450 .reg_ofs_base = AFE_DL3_BASE, 451 .reg_ofs_cur = AFE_DL3_CUR, 452 .fs_reg = AFE_DAC_CON2, 453 .fs_shift = DL3_MODE_SFT, 454 .fs_maskbit = DL3_MODE_MASK, 455 .mono_reg = AFE_DAC_CON1, 456 .mono_shift = DL3_DATA_SFT, 457 .enable_reg = AFE_DAC_CON0, 458 .enable_shift = DL3_ON_SFT, 459 .hd_reg = AFE_MEMIF_HD_MODE, 460 .hd_shift = DL3_HD_SFT, 461 .agent_disable_reg = -1, 462 .agent_disable_shift = -1, 463 .msb_reg = -1, 464 .msb_shift = -1, 465 }, 466 [MT8183_MEMIF_VUL2] = { 467 .name = "VUL2", 468 .id = MT8183_MEMIF_VUL2, 469 .reg_ofs_base = AFE_VUL2_BASE, 470 .reg_ofs_cur = AFE_VUL2_CUR, 471 .fs_reg = AFE_DAC_CON2, 472 .fs_shift = VUL2_MODE_SFT, 473 .fs_maskbit = VUL2_MODE_MASK, 474 .mono_reg = AFE_DAC_CON2, 475 .mono_shift = VUL2_DATA_SFT, 476 .enable_reg = AFE_DAC_CON0, 477 .enable_shift = VUL2_ON_SFT, 478 .hd_reg = AFE_MEMIF_HD_MODE, 479 .hd_shift = VUL2_HD_SFT, 480 .agent_disable_reg = -1, 481 .agent_disable_shift = -1, 482 .msb_reg = -1, 483 .msb_shift = -1, 484 }, 485 [MT8183_MEMIF_AWB] = { 486 .name = "AWB", 487 .id = MT8183_MEMIF_AWB, 488 .reg_ofs_base = AFE_AWB_BASE, 489 .reg_ofs_cur = AFE_AWB_CUR, 490 .fs_reg = AFE_DAC_CON1, 491 .fs_shift = AWB_MODE_SFT, 492 .fs_maskbit = AWB_MODE_MASK, 493 .mono_reg = AFE_DAC_CON1, 494 .mono_shift = AWB_DATA_SFT, 495 .enable_reg = AFE_DAC_CON0, 496 .enable_shift = AWB_ON_SFT, 497 .hd_reg = AFE_MEMIF_HD_MODE, 498 .hd_shift = AWB_HD_SFT, 499 .agent_disable_reg = -1, 500 .agent_disable_shift = -1, 501 .msb_reg = -1, 502 .msb_shift = -1, 503 }, 504 [MT8183_MEMIF_AWB2] = { 505 .name = "AWB2", 506 .id = MT8183_MEMIF_AWB2, 507 .reg_ofs_base = AFE_AWB2_BASE, 508 .reg_ofs_cur = AFE_AWB2_CUR, 509 .fs_reg = AFE_DAC_CON2, 510 .fs_shift = AWB2_MODE_SFT, 511 .fs_maskbit = AWB2_MODE_MASK, 512 .mono_reg = AFE_DAC_CON2, 513 .mono_shift = AWB2_DATA_SFT, 514 .enable_reg = AFE_DAC_CON0, 515 .enable_shift = AWB2_ON_SFT, 516 .hd_reg = AFE_MEMIF_HD_MODE, 517 .hd_shift = AWB2_HD_SFT, 518 .agent_disable_reg = -1, 519 .agent_disable_shift = -1, 520 .msb_reg = -1, 521 .msb_shift = -1, 522 }, 523 [MT8183_MEMIF_VUL12] = { 524 .name = "VUL12", 525 .id = MT8183_MEMIF_VUL12, 526 .reg_ofs_base = AFE_VUL_D2_BASE, 527 .reg_ofs_cur = AFE_VUL_D2_CUR, 528 .fs_reg = AFE_DAC_CON0, 529 .fs_shift = VUL12_MODE_SFT, 530 .fs_maskbit = VUL12_MODE_MASK, 531 .mono_reg = AFE_DAC_CON0, 532 .mono_shift = VUL12_MONO_SFT, 533 .enable_reg = AFE_DAC_CON0, 534 .enable_shift = VUL12_ON_SFT, 535 .hd_reg = AFE_MEMIF_HD_MODE, 536 .hd_shift = VUL12_HD_SFT, 537 .agent_disable_reg = -1, 538 .agent_disable_shift = -1, 539 .msb_reg = -1, 540 .msb_shift = -1, 541 }, 542 [MT8183_MEMIF_MOD_DAI] = { 543 .name = "MOD_DAI", 544 .id = MT8183_MEMIF_MOD_DAI, 545 .reg_ofs_base = AFE_MOD_DAI_BASE, 546 .reg_ofs_cur = AFE_MOD_DAI_CUR, 547 .fs_reg = AFE_DAC_CON1, 548 .fs_shift = MOD_DAI_MODE_SFT, 549 .fs_maskbit = MOD_DAI_MODE_MASK, 550 .mono_reg = -1, 551 .mono_shift = 0, 552 .enable_reg = AFE_DAC_CON0, 553 .enable_shift = MOD_DAI_ON_SFT, 554 .hd_reg = AFE_MEMIF_HD_MODE, 555 .hd_shift = MOD_DAI_HD_SFT, 556 .agent_disable_reg = -1, 557 .agent_disable_shift = -1, 558 .msb_reg = -1, 559 .msb_shift = -1, 560 }, 561 [MT8183_MEMIF_HDMI] = { 562 .name = "HDMI", 563 .id = MT8183_MEMIF_HDMI, 564 .reg_ofs_base = AFE_HDMI_OUT_BASE, 565 .reg_ofs_cur = AFE_HDMI_OUT_CUR, 566 .fs_reg = -1, 567 .fs_shift = -1, 568 .fs_maskbit = -1, 569 .mono_reg = -1, 570 .mono_shift = -1, 571 .enable_reg = -1, /* control in tdm for sync start */ 572 .enable_shift = -1, 573 .hd_reg = AFE_MEMIF_HD_MODE, 574 .hd_shift = HDMI_HD_SFT, 575 .agent_disable_reg = -1, 576 .agent_disable_shift = -1, 577 .msb_reg = -1, 578 .msb_shift = -1, 579 }, 580 }; 581 582 static const struct mtk_base_irq_data irq_data[MT8183_IRQ_NUM] = { 583 [MT8183_IRQ_0] = { 584 .id = MT8183_IRQ_0, 585 .irq_cnt_reg = AFE_IRQ_MCU_CNT0, 586 .irq_cnt_shift = 0, 587 .irq_cnt_maskbit = 0x3ffff, 588 .irq_fs_reg = AFE_IRQ_MCU_CON1, 589 .irq_fs_shift = IRQ0_MCU_MODE_SFT, 590 .irq_fs_maskbit = IRQ0_MCU_MODE_MASK, 591 .irq_en_reg = AFE_IRQ_MCU_CON0, 592 .irq_en_shift = IRQ0_MCU_ON_SFT, 593 .irq_clr_reg = AFE_IRQ_MCU_CLR, 594 .irq_clr_shift = IRQ0_MCU_CLR_SFT, 595 }, 596 [MT8183_IRQ_1] = { 597 .id = MT8183_IRQ_1, 598 .irq_cnt_reg = AFE_IRQ_MCU_CNT1, 599 .irq_cnt_shift = 0, 600 .irq_cnt_maskbit = 0x3ffff, 601 .irq_fs_reg = AFE_IRQ_MCU_CON1, 602 .irq_fs_shift = IRQ1_MCU_MODE_SFT, 603 .irq_fs_maskbit = IRQ1_MCU_MODE_MASK, 604 .irq_en_reg = AFE_IRQ_MCU_CON0, 605 .irq_en_shift = IRQ1_MCU_ON_SFT, 606 .irq_clr_reg = AFE_IRQ_MCU_CLR, 607 .irq_clr_shift = IRQ1_MCU_CLR_SFT, 608 }, 609 [MT8183_IRQ_2] = { 610 .id = MT8183_IRQ_2, 611 .irq_cnt_reg = AFE_IRQ_MCU_CNT2, 612 .irq_cnt_shift = 0, 613 .irq_cnt_maskbit = 0x3ffff, 614 .irq_fs_reg = AFE_IRQ_MCU_CON1, 615 .irq_fs_shift = IRQ2_MCU_MODE_SFT, 616 .irq_fs_maskbit = IRQ2_MCU_MODE_MASK, 617 .irq_en_reg = AFE_IRQ_MCU_CON0, 618 .irq_en_shift = IRQ2_MCU_ON_SFT, 619 .irq_clr_reg = AFE_IRQ_MCU_CLR, 620 .irq_clr_shift = IRQ2_MCU_CLR_SFT, 621 }, 622 [MT8183_IRQ_3] = { 623 .id = MT8183_IRQ_3, 624 .irq_cnt_reg = AFE_IRQ_MCU_CNT3, 625 .irq_cnt_shift = 0, 626 .irq_cnt_maskbit = 0x3ffff, 627 .irq_fs_reg = AFE_IRQ_MCU_CON1, 628 .irq_fs_shift = IRQ3_MCU_MODE_SFT, 629 .irq_fs_maskbit = IRQ3_MCU_MODE_MASK, 630 .irq_en_reg = AFE_IRQ_MCU_CON0, 631 .irq_en_shift = IRQ3_MCU_ON_SFT, 632 .irq_clr_reg = AFE_IRQ_MCU_CLR, 633 .irq_clr_shift = IRQ3_MCU_CLR_SFT, 634 }, 635 [MT8183_IRQ_4] = { 636 .id = MT8183_IRQ_4, 637 .irq_cnt_reg = AFE_IRQ_MCU_CNT4, 638 .irq_cnt_shift = 0, 639 .irq_cnt_maskbit = 0x3ffff, 640 .irq_fs_reg = AFE_IRQ_MCU_CON1, 641 .irq_fs_shift = IRQ4_MCU_MODE_SFT, 642 .irq_fs_maskbit = IRQ4_MCU_MODE_MASK, 643 .irq_en_reg = AFE_IRQ_MCU_CON0, 644 .irq_en_shift = IRQ4_MCU_ON_SFT, 645 .irq_clr_reg = AFE_IRQ_MCU_CLR, 646 .irq_clr_shift = IRQ4_MCU_CLR_SFT, 647 }, 648 [MT8183_IRQ_5] = { 649 .id = MT8183_IRQ_5, 650 .irq_cnt_reg = AFE_IRQ_MCU_CNT5, 651 .irq_cnt_shift = 0, 652 .irq_cnt_maskbit = 0x3ffff, 653 .irq_fs_reg = AFE_IRQ_MCU_CON1, 654 .irq_fs_shift = IRQ5_MCU_MODE_SFT, 655 .irq_fs_maskbit = IRQ5_MCU_MODE_MASK, 656 .irq_en_reg = AFE_IRQ_MCU_CON0, 657 .irq_en_shift = IRQ5_MCU_ON_SFT, 658 .irq_clr_reg = AFE_IRQ_MCU_CLR, 659 .irq_clr_shift = IRQ5_MCU_CLR_SFT, 660 }, 661 [MT8183_IRQ_6] = { 662 .id = MT8183_IRQ_6, 663 .irq_cnt_reg = AFE_IRQ_MCU_CNT6, 664 .irq_cnt_shift = 0, 665 .irq_cnt_maskbit = 0x3ffff, 666 .irq_fs_reg = AFE_IRQ_MCU_CON1, 667 .irq_fs_shift = IRQ6_MCU_MODE_SFT, 668 .irq_fs_maskbit = IRQ6_MCU_MODE_MASK, 669 .irq_en_reg = AFE_IRQ_MCU_CON0, 670 .irq_en_shift = IRQ6_MCU_ON_SFT, 671 .irq_clr_reg = AFE_IRQ_MCU_CLR, 672 .irq_clr_shift = IRQ6_MCU_CLR_SFT, 673 }, 674 [MT8183_IRQ_7] = { 675 .id = MT8183_IRQ_7, 676 .irq_cnt_reg = AFE_IRQ_MCU_CNT7, 677 .irq_cnt_shift = 0, 678 .irq_cnt_maskbit = 0x3ffff, 679 .irq_fs_reg = AFE_IRQ_MCU_CON1, 680 .irq_fs_shift = IRQ7_MCU_MODE_SFT, 681 .irq_fs_maskbit = IRQ7_MCU_MODE_MASK, 682 .irq_en_reg = AFE_IRQ_MCU_CON0, 683 .irq_en_shift = IRQ7_MCU_ON_SFT, 684 .irq_clr_reg = AFE_IRQ_MCU_CLR, 685 .irq_clr_shift = IRQ7_MCU_CLR_SFT, 686 }, 687 [MT8183_IRQ_8] = { 688 .id = MT8183_IRQ_8, 689 .irq_cnt_reg = AFE_IRQ_MCU_CNT8, 690 .irq_cnt_shift = 0, 691 .irq_cnt_maskbit = 0x3ffff, 692 .irq_fs_reg = -1, 693 .irq_fs_shift = -1, 694 .irq_fs_maskbit = -1, 695 .irq_en_reg = AFE_IRQ_MCU_CON0, 696 .irq_en_shift = IRQ8_MCU_ON_SFT, 697 .irq_clr_reg = AFE_IRQ_MCU_CLR, 698 .irq_clr_shift = IRQ8_MCU_CLR_SFT, 699 }, 700 [MT8183_IRQ_11] = { 701 .id = MT8183_IRQ_11, 702 .irq_cnt_reg = AFE_IRQ_MCU_CNT11, 703 .irq_cnt_shift = 0, 704 .irq_cnt_maskbit = 0x3ffff, 705 .irq_fs_reg = AFE_IRQ_MCU_CON2, 706 .irq_fs_shift = IRQ11_MCU_MODE_SFT, 707 .irq_fs_maskbit = IRQ11_MCU_MODE_MASK, 708 .irq_en_reg = AFE_IRQ_MCU_CON0, 709 .irq_en_shift = IRQ11_MCU_ON_SFT, 710 .irq_clr_reg = AFE_IRQ_MCU_CLR, 711 .irq_clr_shift = IRQ11_MCU_CLR_SFT, 712 }, 713 [MT8183_IRQ_12] = { 714 .id = MT8183_IRQ_12, 715 .irq_cnt_reg = AFE_IRQ_MCU_CNT12, 716 .irq_cnt_shift = 0, 717 .irq_cnt_maskbit = 0x3ffff, 718 .irq_fs_reg = AFE_IRQ_MCU_CON2, 719 .irq_fs_shift = IRQ12_MCU_MODE_SFT, 720 .irq_fs_maskbit = IRQ12_MCU_MODE_MASK, 721 .irq_en_reg = AFE_IRQ_MCU_CON0, 722 .irq_en_shift = IRQ12_MCU_ON_SFT, 723 .irq_clr_reg = AFE_IRQ_MCU_CLR, 724 .irq_clr_shift = IRQ12_MCU_CLR_SFT, 725 }, 726 }; 727 728 static bool mt8183_is_volatile_reg(struct device *dev, unsigned int reg) 729 { 730 /* these auto-gen reg has read-only bit, so put it as volatile */ 731 /* volatile reg cannot be cached, so cannot be set when power off */ 732 switch (reg) { 733 case AUDIO_TOP_CON0: /* reg bit controlled by CCF */ 734 case AUDIO_TOP_CON1: /* reg bit controlled by CCF */ 735 case AUDIO_TOP_CON3: 736 case AFE_DL1_CUR: 737 case AFE_DL1_END: 738 case AFE_DL2_CUR: 739 case AFE_DL2_END: 740 case AFE_AWB_END: 741 case AFE_AWB_CUR: 742 case AFE_VUL_END: 743 case AFE_VUL_CUR: 744 case AFE_MEMIF_MON0: 745 case AFE_MEMIF_MON1: 746 case AFE_MEMIF_MON2: 747 case AFE_MEMIF_MON3: 748 case AFE_MEMIF_MON4: 749 case AFE_MEMIF_MON5: 750 case AFE_MEMIF_MON6: 751 case AFE_MEMIF_MON7: 752 case AFE_MEMIF_MON8: 753 case AFE_MEMIF_MON9: 754 case AFE_ADDA_SRC_DEBUG_MON0: 755 case AFE_ADDA_SRC_DEBUG_MON1: 756 case AFE_ADDA_UL_SRC_MON0: 757 case AFE_ADDA_UL_SRC_MON1: 758 case AFE_SIDETONE_MON: 759 case AFE_SIDETONE_CON0: 760 case AFE_SIDETONE_COEFF: 761 case AFE_BUS_MON0: 762 case AFE_MRGIF_MON0: 763 case AFE_MRGIF_MON1: 764 case AFE_MRGIF_MON2: 765 case AFE_I2S_MON: 766 case AFE_DAC_MON: 767 case AFE_VUL2_END: 768 case AFE_VUL2_CUR: 769 case AFE_IRQ0_MCU_CNT_MON: 770 case AFE_IRQ6_MCU_CNT_MON: 771 case AFE_MOD_DAI_END: 772 case AFE_MOD_DAI_CUR: 773 case AFE_VUL_D2_END: 774 case AFE_VUL_D2_CUR: 775 case AFE_DL3_CUR: 776 case AFE_DL3_END: 777 case AFE_HDMI_OUT_CON0: 778 case AFE_HDMI_OUT_CUR: 779 case AFE_HDMI_OUT_END: 780 case AFE_IRQ3_MCU_CNT_MON: 781 case AFE_IRQ4_MCU_CNT_MON: 782 case AFE_IRQ_MCU_STATUS: 783 case AFE_IRQ_MCU_CLR: 784 case AFE_IRQ_MCU_MON2: 785 case AFE_IRQ1_MCU_CNT_MON: 786 case AFE_IRQ2_MCU_CNT_MON: 787 case AFE_IRQ1_MCU_EN_CNT_MON: 788 case AFE_IRQ5_MCU_CNT_MON: 789 case AFE_IRQ7_MCU_CNT_MON: 790 case AFE_GAIN1_CUR: 791 case AFE_GAIN2_CUR: 792 case AFE_SRAM_DELSEL_CON0: 793 case AFE_SRAM_DELSEL_CON2: 794 case AFE_SRAM_DELSEL_CON3: 795 case AFE_ASRC_2CH_CON12: 796 case AFE_ASRC_2CH_CON13: 797 case PCM_INTF_CON2: 798 case FPGA_CFG0: 799 case FPGA_CFG1: 800 case FPGA_CFG2: 801 case FPGA_CFG3: 802 case AUDIO_TOP_DBG_MON0: 803 case AUDIO_TOP_DBG_MON1: 804 case AFE_IRQ8_MCU_CNT_MON: 805 case AFE_IRQ11_MCU_CNT_MON: 806 case AFE_IRQ12_MCU_CNT_MON: 807 case AFE_CBIP_MON0: 808 case AFE_CBIP_SLV_MUX_MON0: 809 case AFE_CBIP_SLV_DECODER_MON0: 810 case AFE_ADDA6_SRC_DEBUG_MON0: 811 case AFE_ADD6A_UL_SRC_MON0: 812 case AFE_ADDA6_UL_SRC_MON1: 813 case AFE_DL1_CUR_MSB: 814 case AFE_DL2_CUR_MSB: 815 case AFE_AWB_CUR_MSB: 816 case AFE_VUL_CUR_MSB: 817 case AFE_VUL2_CUR_MSB: 818 case AFE_MOD_DAI_CUR_MSB: 819 case AFE_VUL_D2_CUR_MSB: 820 case AFE_DL3_CUR_MSB: 821 case AFE_HDMI_OUT_CUR_MSB: 822 case AFE_AWB2_END: 823 case AFE_AWB2_CUR: 824 case AFE_AWB2_CUR_MSB: 825 case AFE_ADDA_DL_SDM_FIFO_MON: 826 case AFE_ADDA_DL_SRC_LCH_MON: 827 case AFE_ADDA_DL_SRC_RCH_MON: 828 case AFE_ADDA_DL_SDM_OUT_MON: 829 case AFE_CONNSYS_I2S_MON: 830 case AFE_ASRC_2CH_CON0: 831 case AFE_ASRC_2CH_CON2: 832 case AFE_ASRC_2CH_CON3: 833 case AFE_ASRC_2CH_CON4: 834 case AFE_ASRC_2CH_CON5: 835 case AFE_ASRC_2CH_CON7: 836 case AFE_ASRC_2CH_CON8: 837 case AFE_MEMIF_MON12: 838 case AFE_MEMIF_MON13: 839 case AFE_MEMIF_MON14: 840 case AFE_MEMIF_MON15: 841 case AFE_MEMIF_MON16: 842 case AFE_MEMIF_MON17: 843 case AFE_MEMIF_MON18: 844 case AFE_MEMIF_MON19: 845 case AFE_MEMIF_MON20: 846 case AFE_MEMIF_MON21: 847 case AFE_MEMIF_MON22: 848 case AFE_MEMIF_MON23: 849 case AFE_MEMIF_MON24: 850 case AFE_ADDA_MTKAIF_MON0: 851 case AFE_ADDA_MTKAIF_MON1: 852 case AFE_AUD_PAD_TOP: 853 case AFE_GENERAL1_ASRC_2CH_CON0: 854 case AFE_GENERAL1_ASRC_2CH_CON2: 855 case AFE_GENERAL1_ASRC_2CH_CON3: 856 case AFE_GENERAL1_ASRC_2CH_CON4: 857 case AFE_GENERAL1_ASRC_2CH_CON5: 858 case AFE_GENERAL1_ASRC_2CH_CON7: 859 case AFE_GENERAL1_ASRC_2CH_CON8: 860 case AFE_GENERAL1_ASRC_2CH_CON12: 861 case AFE_GENERAL1_ASRC_2CH_CON13: 862 case AFE_GENERAL2_ASRC_2CH_CON0: 863 case AFE_GENERAL2_ASRC_2CH_CON2: 864 case AFE_GENERAL2_ASRC_2CH_CON3: 865 case AFE_GENERAL2_ASRC_2CH_CON4: 866 case AFE_GENERAL2_ASRC_2CH_CON5: 867 case AFE_GENERAL2_ASRC_2CH_CON7: 868 case AFE_GENERAL2_ASRC_2CH_CON8: 869 case AFE_GENERAL2_ASRC_2CH_CON12: 870 case AFE_GENERAL2_ASRC_2CH_CON13: 871 return true; 872 default: 873 return false; 874 }; 875 } 876 877 static const struct regmap_config mt8183_afe_regmap_config = { 878 .reg_bits = 32, 879 .reg_stride = 4, 880 .val_bits = 32, 881 882 .volatile_reg = mt8183_is_volatile_reg, 883 884 .max_register = AFE_MAX_REGISTER, 885 .num_reg_defaults_raw = AFE_MAX_REGISTER, 886 887 .cache_type = REGCACHE_FLAT, 888 }; 889 890 static irqreturn_t mt8183_afe_irq_handler(int irq_id, void *dev) 891 { 892 struct mtk_base_afe *afe = dev; 893 struct mtk_base_afe_irq *irq; 894 unsigned int status; 895 unsigned int status_mcu; 896 unsigned int mcu_en; 897 int ret; 898 int i; 899 irqreturn_t irq_ret = IRQ_HANDLED; 900 901 /* get irq that is sent to MCU */ 902 regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en); 903 904 ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status); 905 /* only care IRQ which is sent to MCU */ 906 status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS; 907 908 if (ret || status_mcu == 0) { 909 dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n", 910 __func__, ret, status, mcu_en); 911 912 irq_ret = IRQ_NONE; 913 goto err_irq; 914 } 915 916 for (i = 0; i < MT8183_MEMIF_NUM; i++) { 917 struct mtk_base_afe_memif *memif = &afe->memif[i]; 918 919 if (!memif->substream) 920 continue; 921 922 if (memif->irq_usage < 0) 923 continue; 924 925 irq = &afe->irqs[memif->irq_usage]; 926 927 if (status_mcu & (1 << irq->irq_data->irq_en_shift)) 928 snd_pcm_period_elapsed(memif->substream); 929 } 930 931 err_irq: 932 /* clear irq */ 933 regmap_write(afe->regmap, 934 AFE_IRQ_MCU_CLR, 935 status_mcu); 936 937 return irq_ret; 938 } 939 940 static int mt8183_afe_runtime_suspend(struct device *dev) 941 { 942 struct mtk_base_afe *afe = dev_get_drvdata(dev); 943 struct mt8183_afe_private *afe_priv = afe->platform_priv; 944 unsigned int value; 945 int ret; 946 947 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) 948 goto skip_regmap; 949 950 /* disable AFE */ 951 regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0); 952 953 ret = regmap_read_poll_timeout(afe->regmap, 954 AFE_DAC_MON, 955 value, 956 (value & AFE_ON_RETM_MASK_SFT) == 0, 957 20, 958 1 * 1000 * 1000); 959 if (ret) 960 dev_warn(afe->dev, "%s(), ret %d\n", __func__, ret); 961 962 /* make sure all irq status are cleared, twice intended */ 963 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff); 964 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff); 965 966 /* cache only */ 967 regcache_cache_only(afe->regmap, true); 968 regcache_mark_dirty(afe->regmap); 969 970 skip_regmap: 971 return mt8183_afe_disable_clock(afe); 972 } 973 974 static int mt8183_afe_runtime_resume(struct device *dev) 975 { 976 struct mtk_base_afe *afe = dev_get_drvdata(dev); 977 struct mt8183_afe_private *afe_priv = afe->platform_priv; 978 int ret; 979 980 ret = mt8183_afe_enable_clock(afe); 981 if (ret) 982 return ret; 983 984 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) 985 goto skip_regmap; 986 987 regcache_cache_only(afe->regmap, false); 988 regcache_sync(afe->regmap); 989 990 /* enable audio sys DCM for power saving */ 991 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 0x1 << 29, 0x1 << 29); 992 993 /* force cpu use 8_24 format when writing 32bit data */ 994 regmap_update_bits(afe->regmap, AFE_MEMIF_MSB, 995 CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT); 996 997 /* set all output port to 24bit */ 998 regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff); 999 regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff); 1000 1001 /* enable AFE */ 1002 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1); 1003 1004 skip_regmap: 1005 return 0; 1006 } 1007 1008 static int mt8183_afe_component_probe(struct snd_soc_component *component) 1009 { 1010 return mtk_afe_add_sub_dai_control(component); 1011 } 1012 1013 static const struct snd_soc_component_driver mt8183_afe_component = { 1014 .name = AFE_PCM_NAME, 1015 .ops = &mtk_afe_pcm_ops, 1016 .pcm_new = mtk_afe_pcm_new, 1017 .pcm_free = mtk_afe_pcm_free, 1018 .probe = mt8183_afe_component_probe, 1019 }; 1020 1021 static int mt8183_dai_memif_register(struct mtk_base_afe *afe) 1022 { 1023 struct mtk_base_afe_dai *dai; 1024 1025 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 1026 if (!dai) 1027 return -ENOMEM; 1028 1029 list_add(&dai->list, &afe->sub_dais); 1030 1031 dai->dai_drivers = mt8183_memif_dai_driver; 1032 dai->num_dai_drivers = ARRAY_SIZE(mt8183_memif_dai_driver); 1033 1034 dai->dapm_widgets = mt8183_memif_widgets; 1035 dai->num_dapm_widgets = ARRAY_SIZE(mt8183_memif_widgets); 1036 dai->dapm_routes = mt8183_memif_routes; 1037 dai->num_dapm_routes = ARRAY_SIZE(mt8183_memif_routes); 1038 return 0; 1039 } 1040 1041 typedef int (*dai_register_cb)(struct mtk_base_afe *); 1042 static const dai_register_cb dai_register_cbs[] = { 1043 mt8183_dai_adda_register, 1044 mt8183_dai_i2s_register, 1045 mt8183_dai_pcm_register, 1046 mt8183_dai_tdm_register, 1047 mt8183_dai_hostless_register, 1048 mt8183_dai_memif_register, 1049 }; 1050 1051 static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev) 1052 { 1053 struct mtk_base_afe *afe; 1054 struct mt8183_afe_private *afe_priv; 1055 struct device *dev; 1056 int i, irq_id, ret; 1057 1058 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); 1059 if (!afe) 1060 return -ENOMEM; 1061 platform_set_drvdata(pdev, afe); 1062 1063 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv), 1064 GFP_KERNEL); 1065 if (!afe->platform_priv) 1066 return -ENOMEM; 1067 1068 afe_priv = afe->platform_priv; 1069 afe->dev = &pdev->dev; 1070 dev = afe->dev; 1071 1072 /* initial audio related clock */ 1073 ret = mt8183_init_clock(afe); 1074 if (ret) { 1075 dev_err(dev, "init clock error\n"); 1076 return ret; 1077 } 1078 1079 pm_runtime_enable(dev); 1080 1081 /* regmap init */ 1082 afe->regmap = syscon_node_to_regmap(dev->parent->of_node); 1083 if (IS_ERR(afe->regmap)) { 1084 dev_err(dev, "could not get regmap from parent\n"); 1085 return PTR_ERR(afe->regmap); 1086 } 1087 ret = regmap_attach_dev(dev, afe->regmap, &mt8183_afe_regmap_config); 1088 if (ret) { 1089 dev_warn(dev, "regmap_attach_dev fail, ret %d\n", ret); 1090 return ret; 1091 } 1092 1093 /* enable clock for regcache get default value from hw */ 1094 afe_priv->pm_runtime_bypass_reg_ctl = true; 1095 pm_runtime_get_sync(&pdev->dev); 1096 1097 ret = regmap_reinit_cache(afe->regmap, &mt8183_afe_regmap_config); 1098 if (ret) { 1099 dev_err(dev, "regmap_reinit_cache fail, ret %d\n", ret); 1100 return ret; 1101 } 1102 1103 pm_runtime_put_sync(&pdev->dev); 1104 afe_priv->pm_runtime_bypass_reg_ctl = false; 1105 1106 regcache_cache_only(afe->regmap, true); 1107 regcache_mark_dirty(afe->regmap); 1108 1109 pm_runtime_get_sync(&pdev->dev); 1110 1111 /* init memif */ 1112 afe->memif_size = MT8183_MEMIF_NUM; 1113 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), 1114 GFP_KERNEL); 1115 if (!afe->memif) 1116 return -ENOMEM; 1117 1118 for (i = 0; i < afe->memif_size; i++) { 1119 afe->memif[i].data = &memif_data[i]; 1120 afe->memif[i].irq_usage = -1; 1121 } 1122 1123 afe->memif[MT8183_MEMIF_HDMI].irq_usage = MT8183_IRQ_8; 1124 afe->memif[MT8183_MEMIF_HDMI].const_irq = 1; 1125 1126 mutex_init(&afe->irq_alloc_lock); 1127 1128 /* init memif */ 1129 /* irq initialize */ 1130 afe->irqs_size = MT8183_IRQ_NUM; 1131 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), 1132 GFP_KERNEL); 1133 if (!afe->irqs) 1134 return -ENOMEM; 1135 1136 for (i = 0; i < afe->irqs_size; i++) 1137 afe->irqs[i].irq_data = &irq_data[i]; 1138 1139 /* request irq */ 1140 irq_id = platform_get_irq(pdev, 0); 1141 if (!irq_id) { 1142 dev_err(dev, "%pOFn no irq found\n", dev->of_node); 1143 return -ENXIO; 1144 } 1145 ret = devm_request_irq(dev, irq_id, mt8183_afe_irq_handler, 1146 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe); 1147 if (ret) { 1148 dev_err(dev, "could not request_irq for asys-isr\n"); 1149 return ret; 1150 } 1151 1152 /* init sub_dais */ 1153 INIT_LIST_HEAD(&afe->sub_dais); 1154 1155 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) { 1156 ret = dai_register_cbs[i](afe); 1157 if (ret) { 1158 dev_warn(afe->dev, "dai register i %d fail, ret %d\n", 1159 i, ret); 1160 return ret; 1161 } 1162 } 1163 1164 /* init dai_driver and component_driver */ 1165 ret = mtk_afe_combine_sub_dai(afe); 1166 if (ret) { 1167 dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n", 1168 ret); 1169 return ret; 1170 } 1171 1172 afe->mtk_afe_hardware = &mt8183_afe_hardware; 1173 afe->memif_fs = mt8183_memif_fs; 1174 afe->irq_fs = mt8183_irq_fs; 1175 1176 afe->runtime_resume = mt8183_afe_runtime_resume; 1177 afe->runtime_suspend = mt8183_afe_runtime_suspend; 1178 1179 /* register component */ 1180 ret = devm_snd_soc_register_component(&pdev->dev, 1181 &mt8183_afe_component, 1182 NULL, 0); 1183 if (ret) { 1184 dev_warn(dev, "err_platform\n"); 1185 return ret; 1186 } 1187 1188 ret = devm_snd_soc_register_component(afe->dev, 1189 &mt8183_afe_pcm_dai_component, 1190 afe->dai_drivers, 1191 afe->num_dai_drivers); 1192 if (ret) { 1193 dev_warn(dev, "err_dai_component\n"); 1194 return ret; 1195 } 1196 1197 return ret; 1198 } 1199 1200 static int mt8183_afe_pcm_dev_remove(struct platform_device *pdev) 1201 { 1202 pm_runtime_put_sync(&pdev->dev); 1203 1204 pm_runtime_disable(&pdev->dev); 1205 if (!pm_runtime_status_suspended(&pdev->dev)) 1206 mt8183_afe_runtime_suspend(&pdev->dev); 1207 return 0; 1208 } 1209 1210 static const struct of_device_id mt8183_afe_pcm_dt_match[] = { 1211 { .compatible = "mediatek,mt8183-audio", }, 1212 {}, 1213 }; 1214 MODULE_DEVICE_TABLE(of, mt8183_afe_pcm_dt_match); 1215 1216 static const struct dev_pm_ops mt8183_afe_pm_ops = { 1217 SET_RUNTIME_PM_OPS(mt8183_afe_runtime_suspend, 1218 mt8183_afe_runtime_resume, NULL) 1219 }; 1220 1221 static struct platform_driver mt8183_afe_pcm_driver = { 1222 .driver = { 1223 .name = "mt8183-audio", 1224 .of_match_table = mt8183_afe_pcm_dt_match, 1225 #ifdef CONFIG_PM 1226 .pm = &mt8183_afe_pm_ops, 1227 #endif 1228 }, 1229 .probe = mt8183_afe_pcm_dev_probe, 1230 .remove = mt8183_afe_pcm_dev_remove, 1231 }; 1232 1233 module_platform_driver(mt8183_afe_pcm_driver); 1234 1235 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8183"); 1236 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>"); 1237 MODULE_LICENSE("GPL v2"); 1238