1 /* 2 * Mediatek 8173 ALSA SoC AFE platform driver 3 * 4 * Copyright (c) 2015 MediaTek Inc. 5 * Author: Koro Chen <koro.chen@mediatek.com> 6 * Sascha Hauer <s.hauer@pengutronix.de> 7 * Hidalgo Huang <hidalgo.huang@mediatek.com> 8 * Ir Lian <ir.lian@mediatek.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 and 12 * only version 2 as published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/pm_runtime.h> 26 #include <sound/soc.h> 27 #include "mt8173-afe-common.h" 28 #include "../common/mtk-base-afe.h" 29 #include "../common/mtk-afe-platform-driver.h" 30 #include "../common/mtk-afe-fe-dai.h" 31 32 /***************************************************************************** 33 * R E G I S T E R D E F I N I T I O N 34 *****************************************************************************/ 35 #define AUDIO_TOP_CON0 0x0000 36 #define AUDIO_TOP_CON1 0x0004 37 #define AFE_DAC_CON0 0x0010 38 #define AFE_DAC_CON1 0x0014 39 #define AFE_I2S_CON1 0x0034 40 #define AFE_I2S_CON2 0x0038 41 #define AFE_CONN_24BIT 0x006c 42 #define AFE_MEMIF_MSB 0x00cc 43 44 #define AFE_CONN1 0x0024 45 #define AFE_CONN2 0x0028 46 #define AFE_CONN3 0x002c 47 #define AFE_CONN7 0x0460 48 #define AFE_CONN8 0x0464 49 #define AFE_HDMI_CONN0 0x0390 50 51 /* Memory interface */ 52 #define AFE_DL1_BASE 0x0040 53 #define AFE_DL1_CUR 0x0044 54 #define AFE_DL1_END 0x0048 55 #define AFE_DL2_BASE 0x0050 56 #define AFE_DL2_CUR 0x0054 57 #define AFE_AWB_BASE 0x0070 58 #define AFE_AWB_CUR 0x007c 59 #define AFE_VUL_BASE 0x0080 60 #define AFE_VUL_CUR 0x008c 61 #define AFE_VUL_END 0x0088 62 #define AFE_DAI_BASE 0x0090 63 #define AFE_DAI_CUR 0x009c 64 #define AFE_MOD_PCM_BASE 0x0330 65 #define AFE_MOD_PCM_CUR 0x033c 66 #define AFE_HDMI_OUT_BASE 0x0374 67 #define AFE_HDMI_OUT_CUR 0x0378 68 #define AFE_HDMI_OUT_END 0x037c 69 70 #define AFE_ADDA_TOP_CON0 0x0120 71 #define AFE_ADDA2_TOP_CON0 0x0600 72 73 #define AFE_HDMI_OUT_CON0 0x0370 74 75 #define AFE_IRQ_MCU_CON 0x03a0 76 #define AFE_IRQ_STATUS 0x03a4 77 #define AFE_IRQ_CLR 0x03a8 78 #define AFE_IRQ_CNT1 0x03ac 79 #define AFE_IRQ_CNT2 0x03b0 80 #define AFE_IRQ_MCU_EN 0x03b4 81 #define AFE_IRQ_CNT5 0x03bc 82 #define AFE_IRQ_CNT7 0x03dc 83 84 #define AFE_TDM_CON1 0x0548 85 #define AFE_TDM_CON2 0x054c 86 87 #define AFE_IRQ_STATUS_BITS 0xff 88 89 /* AUDIO_TOP_CON0 (0x0000) */ 90 #define AUD_TCON0_PDN_SPDF (0x1 << 21) 91 #define AUD_TCON0_PDN_HDMI (0x1 << 20) 92 #define AUD_TCON0_PDN_24M (0x1 << 9) 93 #define AUD_TCON0_PDN_22M (0x1 << 8) 94 #define AUD_TCON0_PDN_AFE (0x1 << 2) 95 96 /* AFE_I2S_CON1 (0x0034) */ 97 #define AFE_I2S_CON1_LOW_JITTER_CLK (0x1 << 12) 98 #define AFE_I2S_CON1_RATE(x) (((x) & 0xf) << 8) 99 #define AFE_I2S_CON1_FORMAT_I2S (0x1 << 3) 100 #define AFE_I2S_CON1_EN (0x1 << 0) 101 102 /* AFE_I2S_CON2 (0x0038) */ 103 #define AFE_I2S_CON2_LOW_JITTER_CLK (0x1 << 12) 104 #define AFE_I2S_CON2_RATE(x) (((x) & 0xf) << 8) 105 #define AFE_I2S_CON2_FORMAT_I2S (0x1 << 3) 106 #define AFE_I2S_CON2_EN (0x1 << 0) 107 108 /* AFE_CONN_24BIT (0x006c) */ 109 #define AFE_CONN_24BIT_O04 (0x1 << 4) 110 #define AFE_CONN_24BIT_O03 (0x1 << 3) 111 112 /* AFE_HDMI_CONN0 (0x0390) */ 113 #define AFE_HDMI_CONN0_O37_I37 (0x7 << 21) 114 #define AFE_HDMI_CONN0_O36_I36 (0x6 << 18) 115 #define AFE_HDMI_CONN0_O35_I33 (0x3 << 15) 116 #define AFE_HDMI_CONN0_O34_I32 (0x2 << 12) 117 #define AFE_HDMI_CONN0_O33_I35 (0x5 << 9) 118 #define AFE_HDMI_CONN0_O32_I34 (0x4 << 6) 119 #define AFE_HDMI_CONN0_O31_I31 (0x1 << 3) 120 #define AFE_HDMI_CONN0_O30_I30 (0x0 << 0) 121 122 /* AFE_TDM_CON1 (0x0548) */ 123 #define AFE_TDM_CON1_LRCK_WIDTH(x) (((x) - 1) << 24) 124 #define AFE_TDM_CON1_32_BCK_CYCLES (0x2 << 12) 125 #define AFE_TDM_CON1_WLEN_32BIT (0x2 << 8) 126 #define AFE_TDM_CON1_MSB_ALIGNED (0x1 << 4) 127 #define AFE_TDM_CON1_1_BCK_DELAY (0x1 << 3) 128 #define AFE_TDM_CON1_LRCK_INV (0x1 << 2) 129 #define AFE_TDM_CON1_BCK_INV (0x1 << 1) 130 #define AFE_TDM_CON1_EN (0x1 << 0) 131 132 enum afe_tdm_ch_start { 133 AFE_TDM_CH_START_O30_O31 = 0, 134 AFE_TDM_CH_START_O32_O33, 135 AFE_TDM_CH_START_O34_O35, 136 AFE_TDM_CH_START_O36_O37, 137 AFE_TDM_CH_ZERO, 138 }; 139 140 static const unsigned int mt8173_afe_backup_list[] = { 141 AUDIO_TOP_CON0, 142 AFE_CONN1, 143 AFE_CONN2, 144 AFE_CONN7, 145 AFE_CONN8, 146 AFE_DAC_CON1, 147 AFE_DL1_BASE, 148 AFE_DL1_END, 149 AFE_VUL_BASE, 150 AFE_VUL_END, 151 AFE_HDMI_OUT_BASE, 152 AFE_HDMI_OUT_END, 153 AFE_HDMI_CONN0, 154 AFE_DAC_CON0, 155 }; 156 157 struct mt8173_afe_private { 158 struct clk *clocks[MT8173_CLK_NUM]; 159 }; 160 161 static const struct snd_pcm_hardware mt8173_afe_hardware = { 162 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 163 SNDRV_PCM_INFO_MMAP_VALID), 164 .buffer_bytes_max = 256 * 1024, 165 .period_bytes_min = 512, 166 .period_bytes_max = 128 * 1024, 167 .periods_min = 2, 168 .periods_max = 256, 169 .fifo_size = 0, 170 }; 171 172 struct mt8173_afe_rate { 173 unsigned int rate; 174 unsigned int regvalue; 175 }; 176 177 static const struct mt8173_afe_rate mt8173_afe_i2s_rates[] = { 178 { .rate = 8000, .regvalue = 0 }, 179 { .rate = 11025, .regvalue = 1 }, 180 { .rate = 12000, .regvalue = 2 }, 181 { .rate = 16000, .regvalue = 4 }, 182 { .rate = 22050, .regvalue = 5 }, 183 { .rate = 24000, .regvalue = 6 }, 184 { .rate = 32000, .regvalue = 8 }, 185 { .rate = 44100, .regvalue = 9 }, 186 { .rate = 48000, .regvalue = 10 }, 187 { .rate = 88000, .regvalue = 11 }, 188 { .rate = 96000, .regvalue = 12 }, 189 { .rate = 174000, .regvalue = 13 }, 190 { .rate = 192000, .regvalue = 14 }, 191 }; 192 193 static int mt8173_afe_i2s_fs(unsigned int sample_rate) 194 { 195 int i; 196 197 for (i = 0; i < ARRAY_SIZE(mt8173_afe_i2s_rates); i++) 198 if (mt8173_afe_i2s_rates[i].rate == sample_rate) 199 return mt8173_afe_i2s_rates[i].regvalue; 200 201 return -EINVAL; 202 } 203 204 static int mt8173_afe_set_i2s(struct mtk_base_afe *afe, unsigned int rate) 205 { 206 unsigned int val; 207 int fs = mt8173_afe_i2s_fs(rate); 208 209 if (fs < 0) 210 return -EINVAL; 211 212 /* from external ADC */ 213 regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, 0x1, 0x1); 214 regmap_update_bits(afe->regmap, AFE_ADDA2_TOP_CON0, 0x1, 0x1); 215 216 /* set input */ 217 val = AFE_I2S_CON2_LOW_JITTER_CLK | 218 AFE_I2S_CON2_RATE(fs) | 219 AFE_I2S_CON2_FORMAT_I2S; 220 221 regmap_update_bits(afe->regmap, AFE_I2S_CON2, ~AFE_I2S_CON2_EN, val); 222 223 /* set output */ 224 val = AFE_I2S_CON1_LOW_JITTER_CLK | 225 AFE_I2S_CON1_RATE(fs) | 226 AFE_I2S_CON1_FORMAT_I2S; 227 228 regmap_update_bits(afe->regmap, AFE_I2S_CON1, ~AFE_I2S_CON1_EN, val); 229 return 0; 230 } 231 232 static void mt8173_afe_set_i2s_enable(struct mtk_base_afe *afe, bool enable) 233 { 234 unsigned int val; 235 236 regmap_read(afe->regmap, AFE_I2S_CON2, &val); 237 if (!!(val & AFE_I2S_CON2_EN) == enable) 238 return; 239 240 /* input */ 241 regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable); 242 243 /* output */ 244 regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable); 245 } 246 247 static int mt8173_afe_dais_enable_clks(struct mtk_base_afe *afe, 248 struct clk *m_ck, struct clk *b_ck) 249 { 250 int ret; 251 252 if (m_ck) { 253 ret = clk_prepare_enable(m_ck); 254 if (ret) { 255 dev_err(afe->dev, "Failed to enable m_ck\n"); 256 return ret; 257 } 258 } 259 260 if (b_ck) { 261 ret = clk_prepare_enable(b_ck); 262 if (ret) { 263 dev_err(afe->dev, "Failed to enable b_ck\n"); 264 return ret; 265 } 266 } 267 return 0; 268 } 269 270 static int mt8173_afe_dais_set_clks(struct mtk_base_afe *afe, 271 struct clk *m_ck, unsigned int mck_rate, 272 struct clk *b_ck, unsigned int bck_rate) 273 { 274 int ret; 275 276 if (m_ck) { 277 ret = clk_set_rate(m_ck, mck_rate); 278 if (ret) { 279 dev_err(afe->dev, "Failed to set m_ck rate\n"); 280 return ret; 281 } 282 } 283 284 if (b_ck) { 285 ret = clk_set_rate(b_ck, bck_rate); 286 if (ret) { 287 dev_err(afe->dev, "Failed to set b_ck rate\n"); 288 return ret; 289 } 290 } 291 return 0; 292 } 293 294 static void mt8173_afe_dais_disable_clks(struct mtk_base_afe *afe, 295 struct clk *m_ck, struct clk *b_ck) 296 { 297 if (m_ck) 298 clk_disable_unprepare(m_ck); 299 if (b_ck) 300 clk_disable_unprepare(b_ck); 301 } 302 303 static int mt8173_afe_i2s_startup(struct snd_pcm_substream *substream, 304 struct snd_soc_dai *dai) 305 { 306 struct snd_soc_pcm_runtime *rtd = substream->private_data; 307 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 308 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 309 310 if (dai->active) 311 return 0; 312 313 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 314 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0); 315 return 0; 316 } 317 318 static void mt8173_afe_i2s_shutdown(struct snd_pcm_substream *substream, 319 struct snd_soc_dai *dai) 320 { 321 struct snd_soc_pcm_runtime *rtd = substream->private_data; 322 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 323 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 324 325 if (dai->active) 326 return; 327 328 mt8173_afe_set_i2s_enable(afe, false); 329 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 330 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 331 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M); 332 } 333 334 static int mt8173_afe_i2s_prepare(struct snd_pcm_substream *substream, 335 struct snd_soc_dai *dai) 336 { 337 struct snd_soc_pcm_runtime *rtd = substream->private_data; 338 struct snd_pcm_runtime * const runtime = substream->runtime; 339 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 340 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 341 struct mt8173_afe_private *afe_priv = afe->platform_priv; 342 int ret; 343 344 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S1_M], 345 runtime->rate * 256, NULL, 0); 346 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S2_M], 347 runtime->rate * 256, NULL, 0); 348 /* config I2S */ 349 ret = mt8173_afe_set_i2s(afe, substream->runtime->rate); 350 if (ret) 351 return ret; 352 353 mt8173_afe_set_i2s_enable(afe, true); 354 355 return 0; 356 } 357 358 static int mt8173_afe_hdmi_startup(struct snd_pcm_substream *substream, 359 struct snd_soc_dai *dai) 360 { 361 struct snd_soc_pcm_runtime *rtd = substream->private_data; 362 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 363 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 364 struct mt8173_afe_private *afe_priv = afe->platform_priv; 365 366 if (dai->active) 367 return 0; 368 369 mt8173_afe_dais_enable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], 370 afe_priv->clocks[MT8173_CLK_I2S3_B]); 371 return 0; 372 } 373 374 static void mt8173_afe_hdmi_shutdown(struct snd_pcm_substream *substream, 375 struct snd_soc_dai *dai) 376 { 377 struct snd_soc_pcm_runtime *rtd = substream->private_data; 378 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 379 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 380 struct mt8173_afe_private *afe_priv = afe->platform_priv; 381 382 if (dai->active) 383 return; 384 385 mt8173_afe_dais_disable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], 386 afe_priv->clocks[MT8173_CLK_I2S3_B]); 387 } 388 389 static int mt8173_afe_hdmi_prepare(struct snd_pcm_substream *substream, 390 struct snd_soc_dai *dai) 391 { 392 struct snd_soc_pcm_runtime *rtd = substream->private_data; 393 struct snd_pcm_runtime * const runtime = substream->runtime; 394 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 395 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 396 struct mt8173_afe_private *afe_priv = afe->platform_priv; 397 398 unsigned int val; 399 400 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], 401 runtime->rate * 128, 402 afe_priv->clocks[MT8173_CLK_I2S3_B], 403 runtime->rate * runtime->channels * 32); 404 405 val = AFE_TDM_CON1_BCK_INV | 406 AFE_TDM_CON1_LRCK_INV | 407 AFE_TDM_CON1_1_BCK_DELAY | 408 AFE_TDM_CON1_MSB_ALIGNED | /* I2S mode */ 409 AFE_TDM_CON1_WLEN_32BIT | 410 AFE_TDM_CON1_32_BCK_CYCLES | 411 AFE_TDM_CON1_LRCK_WIDTH(32); 412 regmap_update_bits(afe->regmap, AFE_TDM_CON1, ~AFE_TDM_CON1_EN, val); 413 414 /* set tdm2 config */ 415 switch (runtime->channels) { 416 case 1: 417 case 2: 418 val = AFE_TDM_CH_START_O30_O31; 419 val |= (AFE_TDM_CH_ZERO << 4); 420 val |= (AFE_TDM_CH_ZERO << 8); 421 val |= (AFE_TDM_CH_ZERO << 12); 422 break; 423 case 3: 424 case 4: 425 val = AFE_TDM_CH_START_O30_O31; 426 val |= (AFE_TDM_CH_START_O32_O33 << 4); 427 val |= (AFE_TDM_CH_ZERO << 8); 428 val |= (AFE_TDM_CH_ZERO << 12); 429 break; 430 case 5: 431 case 6: 432 val = AFE_TDM_CH_START_O30_O31; 433 val |= (AFE_TDM_CH_START_O32_O33 << 4); 434 val |= (AFE_TDM_CH_START_O34_O35 << 8); 435 val |= (AFE_TDM_CH_ZERO << 12); 436 break; 437 case 7: 438 case 8: 439 val = AFE_TDM_CH_START_O30_O31; 440 val |= (AFE_TDM_CH_START_O32_O33 << 4); 441 val |= (AFE_TDM_CH_START_O34_O35 << 8); 442 val |= (AFE_TDM_CH_START_O36_O37 << 12); 443 break; 444 default: 445 val = 0; 446 } 447 regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val); 448 449 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 450 0x000000f0, runtime->channels << 4); 451 return 0; 452 } 453 454 static int mt8173_afe_hdmi_trigger(struct snd_pcm_substream *substream, int cmd, 455 struct snd_soc_dai *dai) 456 { 457 struct snd_soc_pcm_runtime *rtd = substream->private_data; 458 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 459 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 460 461 dev_info(afe->dev, "%s cmd=%d %s\n", __func__, cmd, dai->name); 462 463 switch (cmd) { 464 case SNDRV_PCM_TRIGGER_START: 465 case SNDRV_PCM_TRIGGER_RESUME: 466 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 467 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 0); 468 469 /* set connections: O30~O37: L/R/LS/RS/C/LFE/CH7/CH8 */ 470 regmap_write(afe->regmap, AFE_HDMI_CONN0, 471 AFE_HDMI_CONN0_O30_I30 | 472 AFE_HDMI_CONN0_O31_I31 | 473 AFE_HDMI_CONN0_O32_I34 | 474 AFE_HDMI_CONN0_O33_I35 | 475 AFE_HDMI_CONN0_O34_I32 | 476 AFE_HDMI_CONN0_O35_I33 | 477 AFE_HDMI_CONN0_O36_I36 | 478 AFE_HDMI_CONN0_O37_I37); 479 480 /* enable Out control */ 481 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0x1); 482 483 /* enable tdm */ 484 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0x1); 485 486 return 0; 487 case SNDRV_PCM_TRIGGER_STOP: 488 case SNDRV_PCM_TRIGGER_SUSPEND: 489 /* disable tdm */ 490 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0); 491 492 /* disable Out control */ 493 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0); 494 495 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 496 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 497 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF); 498 return 0; 499 default: 500 return -EINVAL; 501 } 502 } 503 504 static int mt8173_memif_fs(struct snd_pcm_substream *substream, 505 unsigned int rate) 506 { 507 struct snd_soc_pcm_runtime *rtd = substream->private_data; 508 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 509 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 510 struct mtk_base_afe_memif *memif = &afe->memif[rtd->cpu_dai->id]; 511 int fs; 512 513 if (memif->data->id == MT8173_AFE_MEMIF_DAI || 514 memif->data->id == MT8173_AFE_MEMIF_MOD_DAI) { 515 switch (rate) { 516 case 8000: 517 fs = 0; 518 break; 519 case 16000: 520 fs = 1; 521 break; 522 case 32000: 523 fs = 2; 524 break; 525 default: 526 return -EINVAL; 527 } 528 } else { 529 fs = mt8173_afe_i2s_fs(rate); 530 } 531 return fs; 532 } 533 534 static int mt8173_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) 535 { 536 return mt8173_afe_i2s_fs(rate); 537 } 538 539 /* BE DAIs */ 540 static const struct snd_soc_dai_ops mt8173_afe_i2s_ops = { 541 .startup = mt8173_afe_i2s_startup, 542 .shutdown = mt8173_afe_i2s_shutdown, 543 .prepare = mt8173_afe_i2s_prepare, 544 }; 545 546 static const struct snd_soc_dai_ops mt8173_afe_hdmi_ops = { 547 .startup = mt8173_afe_hdmi_startup, 548 .shutdown = mt8173_afe_hdmi_shutdown, 549 .prepare = mt8173_afe_hdmi_prepare, 550 .trigger = mt8173_afe_hdmi_trigger, 551 }; 552 553 static struct snd_soc_dai_driver mt8173_afe_pcm_dais[] = { 554 /* FE DAIs: memory intefaces to CPU */ 555 { 556 .name = "DL1", /* downlink 1 */ 557 .id = MT8173_AFE_MEMIF_DL1, 558 .suspend = mtk_afe_dai_suspend, 559 .resume = mtk_afe_dai_resume, 560 .playback = { 561 .stream_name = "DL1", 562 .channels_min = 1, 563 .channels_max = 2, 564 .rates = SNDRV_PCM_RATE_8000_48000, 565 .formats = SNDRV_PCM_FMTBIT_S16_LE, 566 }, 567 .ops = &mtk_afe_fe_ops, 568 }, { 569 .name = "VUL", /* voice uplink */ 570 .id = MT8173_AFE_MEMIF_VUL, 571 .suspend = mtk_afe_dai_suspend, 572 .resume = mtk_afe_dai_resume, 573 .capture = { 574 .stream_name = "VUL", 575 .channels_min = 1, 576 .channels_max = 2, 577 .rates = SNDRV_PCM_RATE_8000_48000, 578 .formats = SNDRV_PCM_FMTBIT_S16_LE, 579 }, 580 .ops = &mtk_afe_fe_ops, 581 }, { 582 /* BE DAIs */ 583 .name = "I2S", 584 .id = MT8173_AFE_IO_I2S, 585 .playback = { 586 .stream_name = "I2S Playback", 587 .channels_min = 1, 588 .channels_max = 2, 589 .rates = SNDRV_PCM_RATE_8000_48000, 590 .formats = SNDRV_PCM_FMTBIT_S16_LE, 591 }, 592 .capture = { 593 .stream_name = "I2S Capture", 594 .channels_min = 1, 595 .channels_max = 2, 596 .rates = SNDRV_PCM_RATE_8000_48000, 597 .formats = SNDRV_PCM_FMTBIT_S16_LE, 598 }, 599 .ops = &mt8173_afe_i2s_ops, 600 .symmetric_rates = 1, 601 }, 602 }; 603 604 static struct snd_soc_dai_driver mt8173_afe_hdmi_dais[] = { 605 /* FE DAIs */ 606 { 607 .name = "HDMI", 608 .id = MT8173_AFE_MEMIF_HDMI, 609 .suspend = mtk_afe_dai_suspend, 610 .resume = mtk_afe_dai_resume, 611 .playback = { 612 .stream_name = "HDMI", 613 .channels_min = 2, 614 .channels_max = 8, 615 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 616 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 617 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 618 SNDRV_PCM_RATE_192000, 619 .formats = SNDRV_PCM_FMTBIT_S16_LE, 620 }, 621 .ops = &mtk_afe_fe_ops, 622 }, { 623 /* BE DAIs */ 624 .name = "HDMIO", 625 .id = MT8173_AFE_IO_HDMI, 626 .playback = { 627 .stream_name = "HDMIO Playback", 628 .channels_min = 2, 629 .channels_max = 8, 630 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 631 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 632 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 633 SNDRV_PCM_RATE_192000, 634 .formats = SNDRV_PCM_FMTBIT_S16_LE, 635 }, 636 .ops = &mt8173_afe_hdmi_ops, 637 }, 638 }; 639 640 static const struct snd_kcontrol_new mt8173_afe_o03_mix[] = { 641 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1, 21, 1, 0), 642 }; 643 644 static const struct snd_kcontrol_new mt8173_afe_o04_mix[] = { 645 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2, 6, 1, 0), 646 }; 647 648 static const struct snd_kcontrol_new mt8173_afe_o09_mix[] = { 649 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 0, 1, 0), 650 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7, 30, 1, 0), 651 }; 652 653 static const struct snd_kcontrol_new mt8173_afe_o10_mix[] = { 654 SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN3, 3, 1, 0), 655 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8, 0, 1, 0), 656 }; 657 658 static const struct snd_soc_dapm_widget mt8173_afe_pcm_widgets[] = { 659 /* inter-connections */ 660 SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0), 661 SND_SOC_DAPM_MIXER("I04", SND_SOC_NOPM, 0, 0, NULL, 0), 662 SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0), 663 SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0), 664 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0), 665 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0), 666 667 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0, 668 mt8173_afe_o03_mix, ARRAY_SIZE(mt8173_afe_o03_mix)), 669 SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0, 670 mt8173_afe_o04_mix, ARRAY_SIZE(mt8173_afe_o04_mix)), 671 SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0, 672 mt8173_afe_o09_mix, ARRAY_SIZE(mt8173_afe_o09_mix)), 673 SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0, 674 mt8173_afe_o10_mix, ARRAY_SIZE(mt8173_afe_o10_mix)), 675 }; 676 677 static const struct snd_soc_dapm_route mt8173_afe_pcm_routes[] = { 678 {"I05", NULL, "DL1"}, 679 {"I06", NULL, "DL1"}, 680 {"I2S Playback", NULL, "O03"}, 681 {"I2S Playback", NULL, "O04"}, 682 {"VUL", NULL, "O09"}, 683 {"VUL", NULL, "O10"}, 684 {"I03", NULL, "I2S Capture"}, 685 {"I04", NULL, "I2S Capture"}, 686 {"I17", NULL, "I2S Capture"}, 687 {"I18", NULL, "I2S Capture"}, 688 { "O03", "I05 Switch", "I05" }, 689 { "O04", "I06 Switch", "I06" }, 690 { "O09", "I17 Switch", "I17" }, 691 { "O09", "I03 Switch", "I03" }, 692 { "O10", "I18 Switch", "I18" }, 693 { "O10", "I04 Switch", "I04" }, 694 }; 695 696 static const struct snd_soc_dapm_route mt8173_afe_hdmi_routes[] = { 697 {"HDMIO Playback", NULL, "HDMI"}, 698 }; 699 700 static const struct snd_soc_component_driver mt8173_afe_pcm_dai_component = { 701 .name = "mt8173-afe-pcm-dai", 702 .dapm_widgets = mt8173_afe_pcm_widgets, 703 .num_dapm_widgets = ARRAY_SIZE(mt8173_afe_pcm_widgets), 704 .dapm_routes = mt8173_afe_pcm_routes, 705 .num_dapm_routes = ARRAY_SIZE(mt8173_afe_pcm_routes), 706 }; 707 708 static const struct snd_soc_component_driver mt8173_afe_hdmi_dai_component = { 709 .name = "mt8173-afe-hdmi-dai", 710 .dapm_routes = mt8173_afe_hdmi_routes, 711 .num_dapm_routes = ARRAY_SIZE(mt8173_afe_hdmi_routes), 712 }; 713 714 static const char *aud_clks[MT8173_CLK_NUM] = { 715 [MT8173_CLK_INFRASYS_AUD] = "infra_sys_audio_clk", 716 [MT8173_CLK_TOP_PDN_AUD] = "top_pdn_audio", 717 [MT8173_CLK_TOP_PDN_AUD_BUS] = "top_pdn_aud_intbus", 718 [MT8173_CLK_I2S0_M] = "i2s0_m", 719 [MT8173_CLK_I2S1_M] = "i2s1_m", 720 [MT8173_CLK_I2S2_M] = "i2s2_m", 721 [MT8173_CLK_I2S3_M] = "i2s3_m", 722 [MT8173_CLK_I2S3_B] = "i2s3_b", 723 [MT8173_CLK_BCK0] = "bck0", 724 [MT8173_CLK_BCK1] = "bck1", 725 }; 726 727 static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = { 728 { 729 .name = "DL1", 730 .id = MT8173_AFE_MEMIF_DL1, 731 .reg_ofs_base = AFE_DL1_BASE, 732 .reg_ofs_cur = AFE_DL1_CUR, 733 .fs_reg = AFE_DAC_CON1, 734 .fs_shift = 0, 735 .fs_maskbit = 0xf, 736 .mono_reg = AFE_DAC_CON1, 737 .mono_shift = 21, 738 .hd_reg = -1, 739 .hd_shift = -1, 740 .enable_reg = AFE_DAC_CON0, 741 .enable_shift = 1, 742 .msb_reg = AFE_MEMIF_MSB, 743 .msb_shift = 0, 744 .agent_disable_reg = -1, 745 .agent_disable_shift = -1, 746 }, { 747 .name = "DL2", 748 .id = MT8173_AFE_MEMIF_DL2, 749 .reg_ofs_base = AFE_DL2_BASE, 750 .reg_ofs_cur = AFE_DL2_CUR, 751 .fs_reg = AFE_DAC_CON1, 752 .fs_shift = 4, 753 .fs_maskbit = 0xf, 754 .mono_reg = AFE_DAC_CON1, 755 .mono_shift = 22, 756 .hd_reg = -1, 757 .hd_shift = -1, 758 .enable_reg = AFE_DAC_CON0, 759 .enable_shift = 2, 760 .msb_reg = AFE_MEMIF_MSB, 761 .msb_shift = 1, 762 .agent_disable_reg = -1, 763 .agent_disable_shift = -1, 764 }, { 765 .name = "VUL", 766 .id = MT8173_AFE_MEMIF_VUL, 767 .reg_ofs_base = AFE_VUL_BASE, 768 .reg_ofs_cur = AFE_VUL_CUR, 769 .fs_reg = AFE_DAC_CON1, 770 .fs_shift = 16, 771 .fs_maskbit = 0xf, 772 .mono_reg = AFE_DAC_CON1, 773 .mono_shift = 27, 774 .hd_reg = -1, 775 .hd_shift = -1, 776 .enable_reg = AFE_DAC_CON0, 777 .enable_shift = 3, 778 .msb_reg = AFE_MEMIF_MSB, 779 .msb_shift = 6, 780 .agent_disable_reg = -1, 781 .agent_disable_shift = -1, 782 }, { 783 .name = "DAI", 784 .id = MT8173_AFE_MEMIF_DAI, 785 .reg_ofs_base = AFE_DAI_BASE, 786 .reg_ofs_cur = AFE_DAI_CUR, 787 .fs_reg = AFE_DAC_CON0, 788 .fs_shift = 24, 789 .fs_maskbit = 0x3, 790 .mono_reg = -1, 791 .mono_shift = -1, 792 .hd_reg = -1, 793 .hd_shift = -1, 794 .enable_reg = AFE_DAC_CON0, 795 .enable_shift = 4, 796 .msb_reg = AFE_MEMIF_MSB, 797 .msb_shift = 5, 798 .agent_disable_reg = -1, 799 .agent_disable_shift = -1, 800 }, { 801 .name = "AWB", 802 .id = MT8173_AFE_MEMIF_AWB, 803 .reg_ofs_base = AFE_AWB_BASE, 804 .reg_ofs_cur = AFE_AWB_CUR, 805 .fs_reg = AFE_DAC_CON1, 806 .fs_shift = 12, 807 .fs_maskbit = 0xf, 808 .mono_reg = AFE_DAC_CON1, 809 .mono_shift = 24, 810 .hd_reg = -1, 811 .hd_shift = -1, 812 .enable_reg = AFE_DAC_CON0, 813 .enable_shift = 6, 814 .msb_reg = AFE_MEMIF_MSB, 815 .msb_shift = 3, 816 .agent_disable_reg = -1, 817 .agent_disable_shift = -1, 818 }, { 819 .name = "MOD_DAI", 820 .id = MT8173_AFE_MEMIF_MOD_DAI, 821 .reg_ofs_base = AFE_MOD_PCM_BASE, 822 .reg_ofs_cur = AFE_MOD_PCM_CUR, 823 .fs_reg = AFE_DAC_CON1, 824 .fs_shift = 30, 825 .fs_maskbit = 0x3, 826 .mono_reg = AFE_DAC_CON1, 827 .mono_shift = 30, 828 .hd_reg = -1, 829 .hd_shift = -1, 830 .enable_reg = AFE_DAC_CON0, 831 .enable_shift = 7, 832 .msb_reg = AFE_MEMIF_MSB, 833 .msb_shift = 4, 834 .agent_disable_reg = -1, 835 .agent_disable_shift = -1, 836 }, { 837 .name = "HDMI", 838 .id = MT8173_AFE_MEMIF_HDMI, 839 .reg_ofs_base = AFE_HDMI_OUT_BASE, 840 .reg_ofs_cur = AFE_HDMI_OUT_CUR, 841 .fs_reg = -1, 842 .fs_shift = -1, 843 .fs_maskbit = -1, 844 .mono_reg = -1, 845 .mono_shift = -1, 846 .hd_reg = -1, 847 .hd_shift = -1, 848 .enable_reg = -1, 849 .enable_shift = -1, 850 .msb_reg = AFE_MEMIF_MSB, 851 .msb_shift = 8, 852 .agent_disable_reg = -1, 853 .agent_disable_shift = -1, 854 }, 855 }; 856 857 static const struct mtk_base_irq_data irq_data[MT8173_AFE_IRQ_NUM] = { 858 { 859 .id = MT8173_AFE_IRQ_DL1, 860 .irq_cnt_reg = AFE_IRQ_CNT1, 861 .irq_cnt_shift = 0, 862 .irq_cnt_maskbit = 0x3ffff, 863 .irq_en_reg = AFE_IRQ_MCU_CON, 864 .irq_en_shift = 0, 865 .irq_fs_reg = AFE_IRQ_MCU_CON, 866 .irq_fs_shift = 4, 867 .irq_fs_maskbit = 0xf, 868 .irq_clr_reg = AFE_IRQ_CLR, 869 .irq_clr_shift = 0, 870 }, { 871 .id = MT8173_AFE_IRQ_DL2, 872 .irq_cnt_reg = AFE_IRQ_CNT1, 873 .irq_cnt_shift = 20, 874 .irq_cnt_maskbit = 0x3ffff, 875 .irq_en_reg = AFE_IRQ_MCU_CON, 876 .irq_en_shift = 2, 877 .irq_fs_reg = AFE_IRQ_MCU_CON, 878 .irq_fs_shift = 16, 879 .irq_fs_maskbit = 0xf, 880 .irq_clr_reg = AFE_IRQ_CLR, 881 .irq_clr_shift = 2, 882 883 }, { 884 .id = MT8173_AFE_IRQ_VUL, 885 .irq_cnt_reg = AFE_IRQ_CNT2, 886 .irq_cnt_shift = 0, 887 .irq_cnt_maskbit = 0x3ffff, 888 .irq_en_reg = AFE_IRQ_MCU_CON, 889 .irq_en_shift = 1, 890 .irq_fs_reg = AFE_IRQ_MCU_CON, 891 .irq_fs_shift = 8, 892 .irq_fs_maskbit = 0xf, 893 .irq_clr_reg = AFE_IRQ_CLR, 894 .irq_clr_shift = 1, 895 }, { 896 .id = MT8173_AFE_IRQ_DAI, 897 .irq_cnt_reg = AFE_IRQ_CNT2, 898 .irq_cnt_shift = 20, 899 .irq_cnt_maskbit = 0x3ffff, 900 .irq_en_reg = AFE_IRQ_MCU_CON, 901 .irq_en_shift = 3, 902 .irq_fs_reg = AFE_IRQ_MCU_CON, 903 .irq_fs_shift = 20, 904 .irq_fs_maskbit = 0xf, 905 .irq_clr_reg = AFE_IRQ_CLR, 906 .irq_clr_shift = 3, 907 }, { 908 .id = MT8173_AFE_IRQ_AWB, 909 .irq_cnt_reg = AFE_IRQ_CNT7, 910 .irq_cnt_shift = 0, 911 .irq_cnt_maskbit = 0x3ffff, 912 .irq_en_reg = AFE_IRQ_MCU_CON, 913 .irq_en_shift = 14, 914 .irq_fs_reg = AFE_IRQ_MCU_CON, 915 .irq_fs_shift = 24, 916 .irq_fs_maskbit = 0xf, 917 .irq_clr_reg = AFE_IRQ_CLR, 918 .irq_clr_shift = 6, 919 }, { 920 .id = MT8173_AFE_IRQ_DAI, 921 .irq_cnt_reg = AFE_IRQ_CNT2, 922 .irq_cnt_shift = 20, 923 .irq_cnt_maskbit = 0x3ffff, 924 .irq_en_reg = AFE_IRQ_MCU_CON, 925 .irq_en_shift = 3, 926 .irq_fs_reg = AFE_IRQ_MCU_CON, 927 .irq_fs_shift = 20, 928 .irq_fs_maskbit = 0xf, 929 .irq_clr_reg = AFE_IRQ_CLR, 930 .irq_clr_shift = 3, 931 }, { 932 .id = MT8173_AFE_IRQ_HDMI, 933 .irq_cnt_reg = AFE_IRQ_CNT5, 934 .irq_cnt_shift = 0, 935 .irq_cnt_maskbit = 0x3ffff, 936 .irq_en_reg = AFE_IRQ_MCU_CON, 937 .irq_en_shift = 12, 938 .irq_fs_reg = -1, 939 .irq_fs_shift = -1, 940 .irq_fs_maskbit = -1, 941 .irq_clr_reg = AFE_IRQ_CLR, 942 .irq_clr_shift = 4, 943 }, 944 }; 945 946 static const struct regmap_config mt8173_afe_regmap_config = { 947 .reg_bits = 32, 948 .reg_stride = 4, 949 .val_bits = 32, 950 .max_register = AFE_ADDA2_TOP_CON0, 951 .cache_type = REGCACHE_NONE, 952 }; 953 954 static irqreturn_t mt8173_afe_irq_handler(int irq, void *dev_id) 955 { 956 struct mtk_base_afe *afe = dev_id; 957 unsigned int reg_value; 958 int i, ret; 959 960 ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, ®_value); 961 if (ret) { 962 dev_err(afe->dev, "%s irq status err\n", __func__); 963 reg_value = AFE_IRQ_STATUS_BITS; 964 goto err_irq; 965 } 966 967 for (i = 0; i < MT8173_AFE_MEMIF_NUM; i++) { 968 struct mtk_base_afe_memif *memif = &afe->memif[i]; 969 struct mtk_base_afe_irq *irq; 970 971 if (memif->irq_usage < 0) 972 continue; 973 974 irq = &afe->irqs[memif->irq_usage]; 975 976 if (!(reg_value & (1 << irq->irq_data->irq_clr_shift))) 977 continue; 978 979 snd_pcm_period_elapsed(memif->substream); 980 } 981 982 err_irq: 983 /* clear irq */ 984 regmap_write(afe->regmap, AFE_IRQ_CLR, 985 reg_value & AFE_IRQ_STATUS_BITS); 986 987 return IRQ_HANDLED; 988 } 989 990 static int mt8173_afe_runtime_suspend(struct device *dev) 991 { 992 struct mtk_base_afe *afe = dev_get_drvdata(dev); 993 struct mt8173_afe_private *afe_priv = afe->platform_priv; 994 995 /* disable AFE */ 996 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0); 997 998 /* disable AFE clk */ 999 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 1000 AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE); 1001 1002 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]); 1003 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]); 1004 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]); 1005 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK1]); 1006 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]); 1007 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]); 1008 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]); 1009 return 0; 1010 } 1011 1012 static int mt8173_afe_runtime_resume(struct device *dev) 1013 { 1014 struct mtk_base_afe *afe = dev_get_drvdata(dev); 1015 struct mt8173_afe_private *afe_priv = afe->platform_priv; 1016 int ret; 1017 1018 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]); 1019 if (ret) 1020 return ret; 1021 1022 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]); 1023 if (ret) 1024 goto err_infra; 1025 1026 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]); 1027 if (ret) 1028 goto err_top_aud_bus; 1029 1030 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK0]); 1031 if (ret) 1032 goto err_top_aud; 1033 1034 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK1]); 1035 if (ret) 1036 goto err_bck0; 1037 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S1_M]); 1038 if (ret) 1039 goto err_i2s1_m; 1040 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S2_M]); 1041 if (ret) 1042 goto err_i2s2_m; 1043 1044 /* enable AFE clk */ 1045 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0); 1046 1047 /* set O3/O4 16bits */ 1048 regmap_update_bits(afe->regmap, AFE_CONN_24BIT, 1049 AFE_CONN_24BIT_O03 | AFE_CONN_24BIT_O04, 0); 1050 1051 /* unmask all IRQs */ 1052 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 0xff, 0xff); 1053 1054 /* enable AFE */ 1055 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1); 1056 return 0; 1057 1058 err_i2s1_m: 1059 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]); 1060 err_i2s2_m: 1061 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]); 1062 err_bck0: 1063 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]); 1064 err_top_aud: 1065 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]); 1066 err_top_aud_bus: 1067 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]); 1068 err_infra: 1069 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]); 1070 return ret; 1071 } 1072 1073 static int mt8173_afe_init_audio_clk(struct mtk_base_afe *afe) 1074 { 1075 size_t i; 1076 struct mt8173_afe_private *afe_priv = afe->platform_priv; 1077 1078 for (i = 0; i < ARRAY_SIZE(aud_clks); i++) { 1079 afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]); 1080 if (IS_ERR(afe_priv->clocks[i])) { 1081 dev_err(afe->dev, "%s devm_clk_get %s fail\n", 1082 __func__, aud_clks[i]); 1083 return PTR_ERR(afe_priv->clocks[i]); 1084 } 1085 } 1086 clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK0], 22579200); /* 22M */ 1087 clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK1], 24576000); /* 24M */ 1088 return 0; 1089 } 1090 1091 static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev) 1092 { 1093 int ret, i; 1094 int irq_id; 1095 struct mtk_base_afe *afe; 1096 struct mt8173_afe_private *afe_priv; 1097 struct resource *res; 1098 1099 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33)); 1100 if (ret) 1101 return ret; 1102 1103 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); 1104 if (!afe) 1105 return -ENOMEM; 1106 1107 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv), 1108 GFP_KERNEL); 1109 afe_priv = afe->platform_priv; 1110 if (!afe_priv) 1111 return -ENOMEM; 1112 1113 afe->dev = &pdev->dev; 1114 1115 irq_id = platform_get_irq(pdev, 0); 1116 if (irq_id <= 0) { 1117 dev_err(afe->dev, "np %s no irq\n", afe->dev->of_node->name); 1118 return irq_id < 0 ? irq_id : -ENXIO; 1119 } 1120 ret = devm_request_irq(afe->dev, irq_id, mt8173_afe_irq_handler, 1121 0, "Afe_ISR_Handle", (void *)afe); 1122 if (ret) { 1123 dev_err(afe->dev, "could not request_irq\n"); 1124 return ret; 1125 } 1126 1127 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1128 afe->base_addr = devm_ioremap_resource(&pdev->dev, res); 1129 if (IS_ERR(afe->base_addr)) 1130 return PTR_ERR(afe->base_addr); 1131 1132 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr, 1133 &mt8173_afe_regmap_config); 1134 if (IS_ERR(afe->regmap)) 1135 return PTR_ERR(afe->regmap); 1136 1137 /* initial audio related clock */ 1138 ret = mt8173_afe_init_audio_clk(afe); 1139 if (ret) { 1140 dev_err(afe->dev, "mt8173_afe_init_audio_clk fail\n"); 1141 return ret; 1142 } 1143 1144 /* memif % irq initialize*/ 1145 afe->memif_size = MT8173_AFE_MEMIF_NUM; 1146 afe->memif = devm_kcalloc(afe->dev, afe->memif_size, 1147 sizeof(*afe->memif), GFP_KERNEL); 1148 if (!afe->memif) 1149 return -ENOMEM; 1150 1151 afe->irqs_size = MT8173_AFE_IRQ_NUM; 1152 afe->irqs = devm_kcalloc(afe->dev, afe->irqs_size, 1153 sizeof(*afe->irqs), GFP_KERNEL); 1154 if (!afe->irqs) 1155 return -ENOMEM; 1156 1157 for (i = 0; i < afe->irqs_size; i++) { 1158 afe->memif[i].data = &memif_data[i]; 1159 afe->irqs[i].irq_data = &irq_data[i]; 1160 afe->irqs[i].irq_occupyed = true; 1161 afe->memif[i].irq_usage = i; 1162 afe->memif[i].const_irq = 1; 1163 } 1164 1165 afe->mtk_afe_hardware = &mt8173_afe_hardware; 1166 afe->memif_fs = mt8173_memif_fs; 1167 afe->irq_fs = mt8173_irq_fs; 1168 1169 platform_set_drvdata(pdev, afe); 1170 1171 pm_runtime_enable(&pdev->dev); 1172 if (!pm_runtime_enabled(&pdev->dev)) { 1173 ret = mt8173_afe_runtime_resume(&pdev->dev); 1174 if (ret) 1175 goto err_pm_disable; 1176 } 1177 1178 afe->reg_back_up_list = mt8173_afe_backup_list; 1179 afe->reg_back_up_list_num = ARRAY_SIZE(mt8173_afe_backup_list); 1180 afe->runtime_resume = mt8173_afe_runtime_resume; 1181 afe->runtime_suspend = mt8173_afe_runtime_suspend; 1182 1183 ret = devm_snd_soc_register_component(&pdev->dev, 1184 &mtk_afe_pcm_platform, 1185 NULL, 0); 1186 if (ret) 1187 goto err_pm_disable; 1188 1189 ret = devm_snd_soc_register_component(&pdev->dev, 1190 &mt8173_afe_pcm_dai_component, 1191 mt8173_afe_pcm_dais, 1192 ARRAY_SIZE(mt8173_afe_pcm_dais)); 1193 if (ret) 1194 goto err_pm_disable; 1195 1196 ret = devm_snd_soc_register_component(&pdev->dev, 1197 &mt8173_afe_hdmi_dai_component, 1198 mt8173_afe_hdmi_dais, 1199 ARRAY_SIZE(mt8173_afe_hdmi_dais)); 1200 if (ret) 1201 goto err_pm_disable; 1202 1203 dev_info(&pdev->dev, "MT8173 AFE driver initialized.\n"); 1204 return 0; 1205 1206 err_pm_disable: 1207 pm_runtime_disable(&pdev->dev); 1208 return ret; 1209 } 1210 1211 static int mt8173_afe_pcm_dev_remove(struct platform_device *pdev) 1212 { 1213 pm_runtime_disable(&pdev->dev); 1214 if (!pm_runtime_status_suspended(&pdev->dev)) 1215 mt8173_afe_runtime_suspend(&pdev->dev); 1216 return 0; 1217 } 1218 1219 static const struct of_device_id mt8173_afe_pcm_dt_match[] = { 1220 { .compatible = "mediatek,mt8173-afe-pcm", }, 1221 { } 1222 }; 1223 MODULE_DEVICE_TABLE(of, mt8173_afe_pcm_dt_match); 1224 1225 static const struct dev_pm_ops mt8173_afe_pm_ops = { 1226 SET_RUNTIME_PM_OPS(mt8173_afe_runtime_suspend, 1227 mt8173_afe_runtime_resume, NULL) 1228 }; 1229 1230 static struct platform_driver mt8173_afe_pcm_driver = { 1231 .driver = { 1232 .name = "mt8173-afe-pcm", 1233 .of_match_table = mt8173_afe_pcm_dt_match, 1234 .pm = &mt8173_afe_pm_ops, 1235 }, 1236 .probe = mt8173_afe_pcm_dev_probe, 1237 .remove = mt8173_afe_pcm_dev_remove, 1238 }; 1239 1240 module_platform_driver(mt8173_afe_pcm_driver); 1241 1242 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver"); 1243 MODULE_AUTHOR("Koro Chen <koro.chen@mediatek.com>"); 1244 MODULE_LICENSE("GPL v2"); 1245