1*c4c3c32dSMaso Huang /* SPDX-License-Identifier: GPL-2.0 */ 2*c4c3c32dSMaso Huang /* 3*c4c3c32dSMaso Huang * mt7986-reg.h -- MediaTek 7986 audio driver reg definition 4*c4c3c32dSMaso Huang * 5*c4c3c32dSMaso Huang * Copyright (c) 2023 MediaTek Inc. 6*c4c3c32dSMaso Huang * Authors: Vic Wu <vic.wu@mediatek.com> 7*c4c3c32dSMaso Huang * Maso Huang <maso.huang@mediatek.com> 8*c4c3c32dSMaso Huang */ 9*c4c3c32dSMaso Huang 10*c4c3c32dSMaso Huang #ifndef _MT7986_REG_H_ 11*c4c3c32dSMaso Huang #define _MT7986_REG_H_ 12*c4c3c32dSMaso Huang 13*c4c3c32dSMaso Huang #define AUDIO_TOP_CON2 0x0008 14*c4c3c32dSMaso Huang #define AUDIO_TOP_CON4 0x0010 15*c4c3c32dSMaso Huang #define AUDIO_ENGEN_CON0 0x0014 16*c4c3c32dSMaso Huang #define AFE_IRQ_MCU_EN 0x0100 17*c4c3c32dSMaso Huang #define AFE_IRQ_MCU_STATUS 0x0120 18*c4c3c32dSMaso Huang #define AFE_IRQ_MCU_CLR 0x0128 19*c4c3c32dSMaso Huang #define AFE_IRQ0_MCU_CFG0 0x0140 20*c4c3c32dSMaso Huang #define AFE_IRQ0_MCU_CFG1 0x0144 21*c4c3c32dSMaso Huang #define AFE_IRQ1_MCU_CFG0 0x0148 22*c4c3c32dSMaso Huang #define AFE_IRQ1_MCU_CFG1 0x014c 23*c4c3c32dSMaso Huang #define AFE_IRQ2_MCU_CFG0 0x0150 24*c4c3c32dSMaso Huang #define AFE_IRQ2_MCU_CFG1 0x0154 25*c4c3c32dSMaso Huang #define ETDM_IN5_CON0 0x13f0 26*c4c3c32dSMaso Huang #define ETDM_IN5_CON1 0x13f4 27*c4c3c32dSMaso Huang #define ETDM_IN5_CON2 0x13f8 28*c4c3c32dSMaso Huang #define ETDM_IN5_CON3 0x13fc 29*c4c3c32dSMaso Huang #define ETDM_IN5_CON4 0x1400 30*c4c3c32dSMaso Huang #define ETDM_OUT5_CON0 0x1570 31*c4c3c32dSMaso Huang #define ETDM_OUT5_CON4 0x1580 32*c4c3c32dSMaso Huang #define ETDM_OUT5_CON5 0x1584 33*c4c3c32dSMaso Huang #define ETDM_4_7_COWORK_CON0 0x15e0 34*c4c3c32dSMaso Huang #define ETDM_4_7_COWORK_CON1 0x15e4 35*c4c3c32dSMaso Huang #define AFE_CONN018_1 0x1b44 36*c4c3c32dSMaso Huang #define AFE_CONN018_4 0x1b50 37*c4c3c32dSMaso Huang #define AFE_CONN019_1 0x1b64 38*c4c3c32dSMaso Huang #define AFE_CONN019_4 0x1b70 39*c4c3c32dSMaso Huang #define AFE_CONN124_1 0x2884 40*c4c3c32dSMaso Huang #define AFE_CONN124_4 0x2890 41*c4c3c32dSMaso Huang #define AFE_CONN125_1 0x28a4 42*c4c3c32dSMaso Huang #define AFE_CONN125_4 0x28b0 43*c4c3c32dSMaso Huang #define AFE_CONN_RS_0 0x3920 44*c4c3c32dSMaso Huang #define AFE_CONN_RS_3 0x392c 45*c4c3c32dSMaso Huang #define AFE_CONN_16BIT_0 0x3960 46*c4c3c32dSMaso Huang #define AFE_CONN_16BIT_3 0x396c 47*c4c3c32dSMaso Huang #define AFE_CONN_24BIT_0 0x3980 48*c4c3c32dSMaso Huang #define AFE_CONN_24BIT_3 0x398c 49*c4c3c32dSMaso Huang #define AFE_MEMIF_CON0 0x3d98 50*c4c3c32dSMaso Huang #define AFE_MEMIF_RD_MON 0x3da0 51*c4c3c32dSMaso Huang #define AFE_MEMIF_WR_MON 0x3da4 52*c4c3c32dSMaso Huang #define AFE_DL0_BASE_MSB 0x3e40 53*c4c3c32dSMaso Huang #define AFE_DL0_BASE 0x3e44 54*c4c3c32dSMaso Huang #define AFE_DL0_CUR_MSB 0x3e48 55*c4c3c32dSMaso Huang #define AFE_DL0_CUR 0x3e4c 56*c4c3c32dSMaso Huang #define AFE_DL0_END_MSB 0x3e50 57*c4c3c32dSMaso Huang #define AFE_DL0_END 0x3e54 58*c4c3c32dSMaso Huang #define AFE_DL0_RCH_MON 0x3e58 59*c4c3c32dSMaso Huang #define AFE_DL0_LCH_MON 0x3e5c 60*c4c3c32dSMaso Huang #define AFE_DL0_CON0 0x3e60 61*c4c3c32dSMaso Huang #define AFE_VUL0_BASE_MSB 0x4220 62*c4c3c32dSMaso Huang #define AFE_VUL0_BASE 0x4224 63*c4c3c32dSMaso Huang #define AFE_VUL0_CUR_MSB 0x4228 64*c4c3c32dSMaso Huang #define AFE_VUL0_CUR 0x422c 65*c4c3c32dSMaso Huang #define AFE_VUL0_END_MSB 0x4230 66*c4c3c32dSMaso Huang #define AFE_VUL0_END 0x4234 67*c4c3c32dSMaso Huang #define AFE_VUL0_CON0 0x4238 68*c4c3c32dSMaso Huang 69*c4c3c32dSMaso Huang #define AFE_MAX_REGISTER AFE_VUL0_CON0 70*c4c3c32dSMaso Huang #define AFE_IRQ_STATUS_BITS 0x7 71*c4c3c32dSMaso Huang #define AFE_IRQ_CNT_SHIFT 0 72*c4c3c32dSMaso Huang #define AFE_IRQ_CNT_MASK 0xffffff 73*c4c3c32dSMaso Huang 74*c4c3c32dSMaso Huang /* AUDIO_TOP_CON2 */ 75*c4c3c32dSMaso Huang #define CLK_OUT5_PDN BIT(14) 76*c4c3c32dSMaso Huang #define CLK_OUT5_PDN_MASK BIT(14) 77*c4c3c32dSMaso Huang #define CLK_IN5_PDN BIT(7) 78*c4c3c32dSMaso Huang #define CLK_IN5_PDN_MASK BIT(7) 79*c4c3c32dSMaso Huang 80*c4c3c32dSMaso Huang /* AUDIO_TOP_CON4 */ 81*c4c3c32dSMaso Huang #define PDN_APLL_TUNER2 BIT(12) 82*c4c3c32dSMaso Huang #define PDN_APLL_TUNER2_MASK BIT(12) 83*c4c3c32dSMaso Huang 84*c4c3c32dSMaso Huang /* AUDIO_ENGEN_CON0 */ 85*c4c3c32dSMaso Huang #define AUD_APLL2_EN BIT(3) 86*c4c3c32dSMaso Huang #define AUD_APLL2_EN_MASK BIT(3) 87*c4c3c32dSMaso Huang #define AUD_26M_EN BIT(0) 88*c4c3c32dSMaso Huang #define AUD_26M_EN_MASK BIT(0) 89*c4c3c32dSMaso Huang 90*c4c3c32dSMaso Huang /* AFE_DL0_CON0 */ 91*c4c3c32dSMaso Huang #define DL0_ON_SFT 28 92*c4c3c32dSMaso Huang #define DL0_ON_MASK 0x1 93*c4c3c32dSMaso Huang #define DL0_ON_MASK_SFT BIT(28) 94*c4c3c32dSMaso Huang #define DL0_MINLEN_SFT 20 95*c4c3c32dSMaso Huang #define DL0_MINLEN_MASK 0xf 96*c4c3c32dSMaso Huang #define DL0_MINLEN_MASK_SFT (0xf << 20) 97*c4c3c32dSMaso Huang #define DL0_MODE_SFT 8 98*c4c3c32dSMaso Huang #define DL0_MODE_MASK 0x1f 99*c4c3c32dSMaso Huang #define DL0_MODE_MASK_SFT (0x1f << 8) 100*c4c3c32dSMaso Huang #define DL0_PBUF_SIZE_SFT 5 101*c4c3c32dSMaso Huang #define DL0_PBUF_SIZE_MASK 0x3 102*c4c3c32dSMaso Huang #define DL0_PBUF_SIZE_MASK_SFT (0x3 << 5) 103*c4c3c32dSMaso Huang #define DL0_MONO_SFT 4 104*c4c3c32dSMaso Huang #define DL0_MONO_MASK 0x1 105*c4c3c32dSMaso Huang #define DL0_MONO_MASK_SFT BIT(4) 106*c4c3c32dSMaso Huang #define DL0_HALIGN_SFT 2 107*c4c3c32dSMaso Huang #define DL0_HALIGN_MASK 0x1 108*c4c3c32dSMaso Huang #define DL0_HALIGN_MASK_SFT BIT(2) 109*c4c3c32dSMaso Huang #define DL0_HD_MODE_SFT 0 110*c4c3c32dSMaso Huang #define DL0_HD_MODE_MASK 0x3 111*c4c3c32dSMaso Huang #define DL0_HD_MODE_MASK_SFT (0x3 << 0) 112*c4c3c32dSMaso Huang 113*c4c3c32dSMaso Huang /* AFE_VUL0_CON0 */ 114*c4c3c32dSMaso Huang #define VUL0_ON_SFT 28 115*c4c3c32dSMaso Huang #define VUL0_ON_MASK 0x1 116*c4c3c32dSMaso Huang #define VUL0_ON_MASK_SFT BIT(28) 117*c4c3c32dSMaso Huang #define VUL0_MODE_SFT 8 118*c4c3c32dSMaso Huang #define VUL0_MODE_MASK 0x1f 119*c4c3c32dSMaso Huang #define VUL0_MODE_MASK_SFT (0x1f << 8) 120*c4c3c32dSMaso Huang #define VUL0_MONO_SFT 4 121*c4c3c32dSMaso Huang #define VUL0_MONO_MASK 0x1 122*c4c3c32dSMaso Huang #define VUL0_MONO_MASK_SFT BIT(4) 123*c4c3c32dSMaso Huang #define VUL0_HALIGN_SFT 2 124*c4c3c32dSMaso Huang #define VUL0_HALIGN_MASK 0x1 125*c4c3c32dSMaso Huang #define VUL0_HALIGN_MASK_SFT BIT(2) 126*c4c3c32dSMaso Huang #define VUL0_HD_MODE_SFT 0 127*c4c3c32dSMaso Huang #define VUL0_HD_MODE_MASK 0x3 128*c4c3c32dSMaso Huang #define VUL0_HD_MODE_MASK_SFT (0x3 << 0) 129*c4c3c32dSMaso Huang 130*c4c3c32dSMaso Huang /* AFE_IRQ_MCU_CON */ 131*c4c3c32dSMaso Huang #define IRQ_MCU_MODE_SFT 4 132*c4c3c32dSMaso Huang #define IRQ_MCU_MODE_MASK 0x1f 133*c4c3c32dSMaso Huang #define IRQ_MCU_MODE_MASK_SFT (0x1f << 4) 134*c4c3c32dSMaso Huang #define IRQ_MCU_ON_SFT 0 135*c4c3c32dSMaso Huang #define IRQ_MCU_ON_MASK 0x1 136*c4c3c32dSMaso Huang #define IRQ_MCU_ON_MASK_SFT BIT(0) 137*c4c3c32dSMaso Huang #define IRQ0_MCU_CLR_SFT 0 138*c4c3c32dSMaso Huang #define IRQ0_MCU_CLR_MASK 0x1 139*c4c3c32dSMaso Huang #define IRQ0_MCU_CLR_MASK_SFT BIT(0) 140*c4c3c32dSMaso Huang #define IRQ1_MCU_CLR_SFT 1 141*c4c3c32dSMaso Huang #define IRQ1_MCU_CLR_MASK 0x1 142*c4c3c32dSMaso Huang #define IRQ1_MCU_CLR_MASK_SFT BIT(1) 143*c4c3c32dSMaso Huang #define IRQ2_MCU_CLR_SFT 2 144*c4c3c32dSMaso Huang #define IRQ2_MCU_CLR_MASK 0x1 145*c4c3c32dSMaso Huang #define IRQ2_MCU_CLR_MASK_SFT BIT(2) 146*c4c3c32dSMaso Huang 147*c4c3c32dSMaso Huang /* ETDM_IN5_CON2 */ 148*c4c3c32dSMaso Huang #define IN_CLK_SRC(x) ((x) << 10) 149*c4c3c32dSMaso Huang #define IN_CLK_SRC_SFT 10 150*c4c3c32dSMaso Huang #define IN_CLK_SRC_MASK GENMASK(12, 10) 151*c4c3c32dSMaso Huang 152*c4c3c32dSMaso Huang /* ETDM_IN5_CON3 */ 153*c4c3c32dSMaso Huang #define IN_SEL_FS(x) ((x) << 26) 154*c4c3c32dSMaso Huang #define IN_SEL_FS_SFT 26 155*c4c3c32dSMaso Huang #define IN_SEL_FS_MASK GENMASK(30, 26) 156*c4c3c32dSMaso Huang 157*c4c3c32dSMaso Huang /* ETDM_IN5_CON4 */ 158*c4c3c32dSMaso Huang #define IN_RELATCH(x) ((x) << 20) 159*c4c3c32dSMaso Huang #define IN_RELATCH_SFT 20 160*c4c3c32dSMaso Huang #define IN_RELATCH_MASK GENMASK(24, 20) 161*c4c3c32dSMaso Huang #define IN_CLK_INV BIT(18) 162*c4c3c32dSMaso Huang #define IN_CLK_INV_MASK BIT(18) 163*c4c3c32dSMaso Huang 164*c4c3c32dSMaso Huang /* ETDM_IN5_CON0 & ETDM_OUT5_CON0 */ 165*c4c3c32dSMaso Huang #define RELATCH_SRC_MASK GENMASK(30, 28) 166*c4c3c32dSMaso Huang #define ETDM_CH_NUM_MASK GENMASK(27, 23) 167*c4c3c32dSMaso Huang #define ETDM_WRD_LEN_MASK GENMASK(20, 16) 168*c4c3c32dSMaso Huang #define ETDM_BIT_LEN_MASK GENMASK(15, 11) 169*c4c3c32dSMaso Huang #define ETDM_FMT_MASK GENMASK(8, 6) 170*c4c3c32dSMaso Huang #define ETDM_SYNC BIT(1) 171*c4c3c32dSMaso Huang #define ETDM_SYNC_MASK BIT(1) 172*c4c3c32dSMaso Huang #define ETDM_EN BIT(0) 173*c4c3c32dSMaso Huang #define ETDM_EN_MASK BIT(0) 174*c4c3c32dSMaso Huang 175*c4c3c32dSMaso Huang /* ETDM_OUT5_CON4 */ 176*c4c3c32dSMaso Huang #define OUT_RELATCH(x) ((x) << 24) 177*c4c3c32dSMaso Huang #define OUT_RELATCH_SFT 24 178*c4c3c32dSMaso Huang #define OUT_RELATCH_MASK GENMASK(28, 24) 179*c4c3c32dSMaso Huang #define OUT_CLK_SRC(x) ((x) << 6) 180*c4c3c32dSMaso Huang #define OUT_CLK_SRC_SFT 6 181*c4c3c32dSMaso Huang #define OUT_CLK_SRC_MASK GENMASK(8, 6) 182*c4c3c32dSMaso Huang #define OUT_SEL_FS(x) (x) 183*c4c3c32dSMaso Huang #define OUT_SEL_FS_SFT 0 184*c4c3c32dSMaso Huang #define OUT_SEL_FS_MASK GENMASK(4, 0) 185*c4c3c32dSMaso Huang 186*c4c3c32dSMaso Huang /* ETDM_OUT5_CON5 */ 187*c4c3c32dSMaso Huang #define ETDM_CLK_DIV BIT(12) 188*c4c3c32dSMaso Huang #define ETDM_CLK_DIV_MASK BIT(12) 189*c4c3c32dSMaso Huang #define OUT_CLK_INV BIT(9) 190*c4c3c32dSMaso Huang #define OUT_CLK_INV_MASK BIT(9) 191*c4c3c32dSMaso Huang 192*c4c3c32dSMaso Huang /* ETDM_4_7_COWORK_CON0 */ 193*c4c3c32dSMaso Huang #define OUT_SEL(x) ((x) << 12) 194*c4c3c32dSMaso Huang #define OUT_SEL_SFT 12 195*c4c3c32dSMaso Huang #define OUT_SEL_MASK GENMASK(15, 12) 196*c4c3c32dSMaso Huang #endif 197