14135d8b6SKai Chieh Chuang /* SPDX-License-Identifier: GPL-2.0 */ 2c5e7fca9SKai Chieh Chuang /* 3c5e7fca9SKai Chieh Chuang * Mediatek MT6797 audio driver interconnection definition 4c5e7fca9SKai Chieh Chuang * 5c5e7fca9SKai Chieh Chuang * Copyright (c) 2018 MediaTek Inc. 6c5e7fca9SKai Chieh Chuang * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7c5e7fca9SKai Chieh Chuang */ 8c5e7fca9SKai Chieh Chuang 9c5e7fca9SKai Chieh Chuang #ifndef _MT6797_INTERCONNECTION_H_ 10c5e7fca9SKai Chieh Chuang #define _MT6797_INTERCONNECTION_H_ 11c5e7fca9SKai Chieh Chuang 12c5e7fca9SKai Chieh Chuang #define I_I2S0_CH1 0 13c5e7fca9SKai Chieh Chuang #define I_I2S0_CH2 1 14c5e7fca9SKai Chieh Chuang #define I_ADDA_UL_CH1 3 15c5e7fca9SKai Chieh Chuang #define I_ADDA_UL_CH2 4 16c5e7fca9SKai Chieh Chuang #define I_DL1_CH1 5 17c5e7fca9SKai Chieh Chuang #define I_DL1_CH2 6 18c5e7fca9SKai Chieh Chuang #define I_DL2_CH1 7 19c5e7fca9SKai Chieh Chuang #define I_DL2_CH2 8 20c5e7fca9SKai Chieh Chuang #define I_PCM_1_CAP_CH1 9 21c5e7fca9SKai Chieh Chuang #define I_GAIN1_OUT_CH1 10 22c5e7fca9SKai Chieh Chuang #define I_GAIN1_OUT_CH2 11 23c5e7fca9SKai Chieh Chuang #define I_GAIN2_OUT_CH1 12 24c5e7fca9SKai Chieh Chuang #define I_GAIN2_OUT_CH2 13 25c5e7fca9SKai Chieh Chuang #define I_PCM_2_CAP_CH1 14 26c5e7fca9SKai Chieh Chuang #define I_PCM_2_CAP_CH2 21 27c5e7fca9SKai Chieh Chuang #define I_PCM_1_CAP_CH2 22 28c5e7fca9SKai Chieh Chuang #define I_DL3_CH1 23 29c5e7fca9SKai Chieh Chuang #define I_DL3_CH2 24 30c5e7fca9SKai Chieh Chuang #define I_I2S2_CH1 25 31c5e7fca9SKai Chieh Chuang #define I_I2S2_CH2 26 32c5e7fca9SKai Chieh Chuang 33c5e7fca9SKai Chieh Chuang #endif 34