1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Mediatek ALSA SoC AFE platform driver for 6797 4 // 5 // Copyright (c) 2018 MediaTek Inc. 6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7 8 #include <linux/delay.h> 9 #include <linux/module.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/pm_runtime.h> 14 15 #include "mt6797-afe-common.h" 16 #include "mt6797-afe-clk.h" 17 #include "mt6797-interconnection.h" 18 #include "mt6797-reg.h" 19 #include "../common/mtk-afe-platform-driver.h" 20 #include "../common/mtk-afe-fe-dai.h" 21 22 enum { 23 MTK_AFE_RATE_8K = 0, 24 MTK_AFE_RATE_11K = 1, 25 MTK_AFE_RATE_12K = 2, 26 MTK_AFE_RATE_384K = 3, 27 MTK_AFE_RATE_16K = 4, 28 MTK_AFE_RATE_22K = 5, 29 MTK_AFE_RATE_24K = 6, 30 MTK_AFE_RATE_130K = 7, 31 MTK_AFE_RATE_32K = 8, 32 MTK_AFE_RATE_44K = 9, 33 MTK_AFE_RATE_48K = 10, 34 MTK_AFE_RATE_88K = 11, 35 MTK_AFE_RATE_96K = 12, 36 MTK_AFE_RATE_174K = 13, 37 MTK_AFE_RATE_192K = 14, 38 MTK_AFE_RATE_260K = 15, 39 }; 40 41 enum { 42 MTK_AFE_DAI_MEMIF_RATE_8K = 0, 43 MTK_AFE_DAI_MEMIF_RATE_16K = 1, 44 MTK_AFE_DAI_MEMIF_RATE_32K = 2, 45 }; 46 47 enum { 48 MTK_AFE_PCM_RATE_8K = 0, 49 MTK_AFE_PCM_RATE_16K = 1, 50 MTK_AFE_PCM_RATE_32K = 2, 51 MTK_AFE_PCM_RATE_48K = 3, 52 }; 53 54 unsigned int mt6797_general_rate_transform(struct device *dev, 55 unsigned int rate) 56 { 57 switch (rate) { 58 case 8000: 59 return MTK_AFE_RATE_8K; 60 case 11025: 61 return MTK_AFE_RATE_11K; 62 case 12000: 63 return MTK_AFE_RATE_12K; 64 case 16000: 65 return MTK_AFE_RATE_16K; 66 case 22050: 67 return MTK_AFE_RATE_22K; 68 case 24000: 69 return MTK_AFE_RATE_24K; 70 case 32000: 71 return MTK_AFE_RATE_32K; 72 case 44100: 73 return MTK_AFE_RATE_44K; 74 case 48000: 75 return MTK_AFE_RATE_48K; 76 case 88200: 77 return MTK_AFE_RATE_88K; 78 case 96000: 79 return MTK_AFE_RATE_96K; 80 case 130000: 81 return MTK_AFE_RATE_130K; 82 case 176400: 83 return MTK_AFE_RATE_174K; 84 case 192000: 85 return MTK_AFE_RATE_192K; 86 case 260000: 87 return MTK_AFE_RATE_260K; 88 default: 89 dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n", 90 __func__, rate, MTK_AFE_RATE_48K); 91 return MTK_AFE_RATE_48K; 92 } 93 } 94 95 static unsigned int dai_memif_rate_transform(struct device *dev, 96 unsigned int rate) 97 { 98 switch (rate) { 99 case 8000: 100 return MTK_AFE_DAI_MEMIF_RATE_8K; 101 case 16000: 102 return MTK_AFE_DAI_MEMIF_RATE_16K; 103 case 32000: 104 return MTK_AFE_DAI_MEMIF_RATE_32K; 105 default: 106 dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n", 107 __func__, rate, MTK_AFE_DAI_MEMIF_RATE_16K); 108 return MTK_AFE_DAI_MEMIF_RATE_16K; 109 } 110 } 111 112 unsigned int mt6797_rate_transform(struct device *dev, 113 unsigned int rate, int aud_blk) 114 { 115 switch (aud_blk) { 116 case MT6797_MEMIF_DAI: 117 case MT6797_MEMIF_MOD_DAI: 118 return dai_memif_rate_transform(dev, rate); 119 default: 120 return mt6797_general_rate_transform(dev, rate); 121 } 122 } 123 124 static const struct snd_pcm_hardware mt6797_afe_hardware = { 125 .info = SNDRV_PCM_INFO_MMAP | 126 SNDRV_PCM_INFO_INTERLEAVED | 127 SNDRV_PCM_INFO_MMAP_VALID, 128 .formats = SNDRV_PCM_FMTBIT_S16_LE | 129 SNDRV_PCM_FMTBIT_S24_LE | 130 SNDRV_PCM_FMTBIT_S32_LE, 131 .period_bytes_min = 256, 132 .period_bytes_max = 4 * 48 * 1024, 133 .periods_min = 2, 134 .periods_max = 256, 135 .buffer_bytes_max = 8 * 48 * 1024, 136 .fifo_size = 0, 137 }; 138 139 static int mt6797_memif_fs(struct snd_pcm_substream *substream, 140 unsigned int rate) 141 { 142 struct snd_soc_pcm_runtime *rtd = substream->private_data; 143 struct snd_soc_component *component = 144 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 145 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 146 int id = rtd->cpu_dai->id; 147 148 return mt6797_rate_transform(afe->dev, rate, id); 149 } 150 151 static int mt6797_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) 152 { 153 struct snd_soc_pcm_runtime *rtd = substream->private_data; 154 struct snd_soc_component *component = 155 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 156 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 157 158 return mt6797_general_rate_transform(afe->dev, rate); 159 } 160 161 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\ 162 SNDRV_PCM_RATE_88200 |\ 163 SNDRV_PCM_RATE_96000 |\ 164 SNDRV_PCM_RATE_176400 |\ 165 SNDRV_PCM_RATE_192000) 166 167 #define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\ 168 SNDRV_PCM_RATE_16000 |\ 169 SNDRV_PCM_RATE_32000) 170 171 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 172 SNDRV_PCM_FMTBIT_S24_LE |\ 173 SNDRV_PCM_FMTBIT_S32_LE) 174 175 static struct snd_soc_dai_driver mt6797_memif_dai_driver[] = { 176 /* FE DAIs: memory intefaces to CPU */ 177 { 178 .name = "DL1", 179 .id = MT6797_MEMIF_DL1, 180 .playback = { 181 .stream_name = "DL1", 182 .channels_min = 1, 183 .channels_max = 2, 184 .rates = MTK_PCM_RATES, 185 .formats = MTK_PCM_FORMATS, 186 }, 187 .ops = &mtk_afe_fe_ops, 188 }, 189 { 190 .name = "DL2", 191 .id = MT6797_MEMIF_DL2, 192 .playback = { 193 .stream_name = "DL2", 194 .channels_min = 1, 195 .channels_max = 2, 196 .rates = MTK_PCM_RATES, 197 .formats = MTK_PCM_FORMATS, 198 }, 199 .ops = &mtk_afe_fe_ops, 200 }, 201 { 202 .name = "DL3", 203 .id = MT6797_MEMIF_DL3, 204 .playback = { 205 .stream_name = "DL3", 206 .channels_min = 1, 207 .channels_max = 2, 208 .rates = MTK_PCM_RATES, 209 .formats = MTK_PCM_FORMATS, 210 }, 211 .ops = &mtk_afe_fe_ops, 212 }, 213 { 214 .name = "UL1", 215 .id = MT6797_MEMIF_VUL12, 216 .capture = { 217 .stream_name = "UL1", 218 .channels_min = 1, 219 .channels_max = 2, 220 .rates = MTK_PCM_RATES, 221 .formats = MTK_PCM_FORMATS, 222 }, 223 .ops = &mtk_afe_fe_ops, 224 }, 225 { 226 .name = "UL2", 227 .id = MT6797_MEMIF_AWB, 228 .capture = { 229 .stream_name = "UL2", 230 .channels_min = 1, 231 .channels_max = 2, 232 .rates = MTK_PCM_RATES, 233 .formats = MTK_PCM_FORMATS, 234 }, 235 .ops = &mtk_afe_fe_ops, 236 }, 237 { 238 .name = "UL3", 239 .id = MT6797_MEMIF_VUL, 240 .capture = { 241 .stream_name = "UL3", 242 .channels_min = 1, 243 .channels_max = 2, 244 .rates = MTK_PCM_RATES, 245 .formats = MTK_PCM_FORMATS, 246 }, 247 .ops = &mtk_afe_fe_ops, 248 }, 249 { 250 .name = "UL_MONO_1", 251 .id = MT6797_MEMIF_MOD_DAI, 252 .capture = { 253 .stream_name = "UL_MONO_1", 254 .channels_min = 1, 255 .channels_max = 1, 256 .rates = MTK_PCM_DAI_RATES, 257 .formats = MTK_PCM_FORMATS, 258 }, 259 .ops = &mtk_afe_fe_ops, 260 }, 261 { 262 .name = "UL_MONO_2", 263 .id = MT6797_MEMIF_DAI, 264 .capture = { 265 .stream_name = "UL_MONO_2", 266 .channels_min = 1, 267 .channels_max = 1, 268 .rates = MTK_PCM_DAI_RATES, 269 .formats = MTK_PCM_FORMATS, 270 }, 271 .ops = &mtk_afe_fe_ops, 272 }, 273 }; 274 275 /* dma widget & routes*/ 276 static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = { 277 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21, 278 I_ADDA_UL_CH1, 1, 0), 279 }; 280 281 static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = { 282 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22, 283 I_ADDA_UL_CH2, 1, 0), 284 }; 285 286 static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = { 287 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN5, 288 I_ADDA_UL_CH1, 1, 0), 289 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5, 290 I_DL1_CH1, 1, 0), 291 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5, 292 I_DL2_CH1, 1, 0), 293 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5, 294 I_DL3_CH1, 1, 0), 295 }; 296 297 static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = { 298 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN6, 299 I_ADDA_UL_CH2, 1, 0), 300 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6, 301 I_DL1_CH2, 1, 0), 302 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6, 303 I_DL2_CH2, 1, 0), 304 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6, 305 I_DL3_CH2, 1, 0), 306 }; 307 308 static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = { 309 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN9, 310 I_ADDA_UL_CH1, 1, 0), 311 }; 312 313 static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = { 314 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN10, 315 I_ADDA_UL_CH2, 1, 0), 316 }; 317 318 static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = { 319 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN12, 320 I_ADDA_UL_CH1, 1, 0), 321 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN12, 322 I_ADDA_UL_CH2, 1, 0), 323 }; 324 325 static const struct snd_kcontrol_new memif_ul_mono_2_mix[] = { 326 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN11, 327 I_ADDA_UL_CH1, 1, 0), 328 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN11, 329 I_ADDA_UL_CH2, 1, 0), 330 }; 331 332 static const struct snd_soc_dapm_widget mt6797_memif_widgets[] = { 333 /* memif */ 334 SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0, 335 memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)), 336 SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0, 337 memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)), 338 339 SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0, 340 memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)), 341 SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0, 342 memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)), 343 344 SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0, 345 memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)), 346 SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0, 347 memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)), 348 349 SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0, 350 memif_ul_mono_1_mix, 351 ARRAY_SIZE(memif_ul_mono_1_mix)), 352 353 SND_SOC_DAPM_MIXER("UL_MONO_2_CH1", SND_SOC_NOPM, 0, 0, 354 memif_ul_mono_2_mix, 355 ARRAY_SIZE(memif_ul_mono_2_mix)), 356 }; 357 358 static const struct snd_soc_dapm_route mt6797_memif_routes[] = { 359 /* capture */ 360 {"UL1", NULL, "UL1_CH1"}, 361 {"UL1", NULL, "UL1_CH2"}, 362 {"UL1_CH1", "ADDA_UL_CH1", "ADDA Capture"}, 363 {"UL1_CH2", "ADDA_UL_CH2", "ADDA Capture"}, 364 365 {"UL2", NULL, "UL2_CH1"}, 366 {"UL2", NULL, "UL2_CH2"}, 367 {"UL2_CH1", "ADDA_UL_CH1", "ADDA Capture"}, 368 {"UL2_CH2", "ADDA_UL_CH2", "ADDA Capture"}, 369 370 {"UL3", NULL, "UL3_CH1"}, 371 {"UL3", NULL, "UL3_CH2"}, 372 {"UL3_CH1", "ADDA_UL_CH1", "ADDA Capture"}, 373 {"UL3_CH2", "ADDA_UL_CH2", "ADDA Capture"}, 374 375 {"UL_MONO_1", NULL, "UL_MONO_1_CH1"}, 376 {"UL_MONO_1_CH1", "ADDA_UL_CH1", "ADDA Capture"}, 377 {"UL_MONO_1_CH1", "ADDA_UL_CH2", "ADDA Capture"}, 378 379 {"UL_MONO_2", NULL, "UL_MONO_2_CH1"}, 380 {"UL_MONO_2_CH1", "ADDA_UL_CH1", "ADDA Capture"}, 381 {"UL_MONO_2_CH1", "ADDA_UL_CH2", "ADDA Capture"}, 382 }; 383 384 static const struct snd_soc_component_driver mt6797_afe_pcm_dai_component = { 385 .name = "mt6797-afe-pcm-dai", 386 }; 387 388 static const struct mtk_base_memif_data memif_data[MT6797_MEMIF_NUM] = { 389 [MT6797_MEMIF_DL1] = { 390 .name = "DL1", 391 .id = MT6797_MEMIF_DL1, 392 .reg_ofs_base = AFE_DL1_BASE, 393 .reg_ofs_cur = AFE_DL1_CUR, 394 .fs_reg = AFE_DAC_CON1, 395 .fs_shift = DL1_MODE_SFT, 396 .fs_maskbit = DL1_MODE_MASK, 397 .mono_reg = AFE_DAC_CON1, 398 .mono_shift = DL1_DATA_SFT, 399 .enable_reg = AFE_DAC_CON0, 400 .enable_shift = DL1_ON_SFT, 401 .hd_reg = AFE_MEMIF_HD_MODE, 402 .hd_shift = DL1_HD_SFT, 403 .agent_disable_reg = -1, 404 .agent_disable_shift = -1, 405 .msb_reg = -1, 406 .msb_shift = -1, 407 }, 408 [MT6797_MEMIF_DL2] = { 409 .name = "DL2", 410 .id = MT6797_MEMIF_DL2, 411 .reg_ofs_base = AFE_DL2_BASE, 412 .reg_ofs_cur = AFE_DL2_CUR, 413 .fs_reg = AFE_DAC_CON1, 414 .fs_shift = DL2_MODE_SFT, 415 .fs_maskbit = DL2_MODE_MASK, 416 .mono_reg = AFE_DAC_CON1, 417 .mono_shift = DL2_DATA_SFT, 418 .enable_reg = AFE_DAC_CON0, 419 .enable_shift = DL2_ON_SFT, 420 .hd_reg = AFE_MEMIF_HD_MODE, 421 .hd_shift = DL2_HD_SFT, 422 .agent_disable_reg = -1, 423 .agent_disable_shift = -1, 424 .msb_reg = -1, 425 .msb_shift = -1, 426 }, 427 [MT6797_MEMIF_DL3] = { 428 .name = "DL3", 429 .id = MT6797_MEMIF_DL3, 430 .reg_ofs_base = AFE_DL3_BASE, 431 .reg_ofs_cur = AFE_DL3_CUR, 432 .fs_reg = AFE_DAC_CON0, 433 .fs_shift = DL3_MODE_SFT, 434 .fs_maskbit = DL3_MODE_MASK, 435 .mono_reg = AFE_DAC_CON1, 436 .mono_shift = DL3_DATA_SFT, 437 .enable_reg = AFE_DAC_CON0, 438 .enable_shift = DL3_ON_SFT, 439 .hd_reg = AFE_MEMIF_HD_MODE, 440 .hd_shift = DL3_HD_SFT, 441 .agent_disable_reg = -1, 442 .agent_disable_shift = -1, 443 .msb_reg = -1, 444 .msb_shift = -1, 445 }, 446 [MT6797_MEMIF_VUL] = { 447 .name = "VUL", 448 .id = MT6797_MEMIF_VUL, 449 .reg_ofs_base = AFE_VUL_BASE, 450 .reg_ofs_cur = AFE_VUL_CUR, 451 .fs_reg = AFE_DAC_CON1, 452 .fs_shift = VUL_MODE_SFT, 453 .fs_maskbit = VUL_MODE_MASK, 454 .mono_reg = AFE_DAC_CON1, 455 .mono_shift = VUL_DATA_SFT, 456 .enable_reg = AFE_DAC_CON0, 457 .enable_shift = VUL_ON_SFT, 458 .hd_reg = AFE_MEMIF_HD_MODE, 459 .hd_shift = VUL_HD_SFT, 460 .agent_disable_reg = -1, 461 .agent_disable_shift = -1, 462 .msb_reg = -1, 463 .msb_shift = -1, 464 }, 465 [MT6797_MEMIF_AWB] = { 466 .name = "AWB", 467 .id = MT6797_MEMIF_AWB, 468 .reg_ofs_base = AFE_AWB_BASE, 469 .reg_ofs_cur = AFE_AWB_CUR, 470 .fs_reg = AFE_DAC_CON1, 471 .fs_shift = AWB_MODE_SFT, 472 .fs_maskbit = AWB_MODE_MASK, 473 .mono_reg = AFE_DAC_CON1, 474 .mono_shift = AWB_DATA_SFT, 475 .enable_reg = AFE_DAC_CON0, 476 .enable_shift = AWB_ON_SFT, 477 .hd_reg = AFE_MEMIF_HD_MODE, 478 .hd_shift = AWB_HD_SFT, 479 .agent_disable_reg = -1, 480 .agent_disable_shift = -1, 481 .msb_reg = -1, 482 .msb_shift = -1, 483 }, 484 [MT6797_MEMIF_VUL12] = { 485 .name = "VUL12", 486 .id = MT6797_MEMIF_VUL12, 487 .reg_ofs_base = AFE_VUL_D2_BASE, 488 .reg_ofs_cur = AFE_VUL_D2_CUR, 489 .fs_reg = AFE_DAC_CON0, 490 .fs_shift = VUL_DATA2_MODE_SFT, 491 .fs_maskbit = VUL_DATA2_MODE_MASK, 492 .mono_reg = AFE_DAC_CON0, 493 .mono_shift = VUL_DATA2_DATA_SFT, 494 .enable_reg = AFE_DAC_CON0, 495 .enable_shift = VUL_DATA2_ON_SFT, 496 .hd_reg = AFE_MEMIF_HD_MODE, 497 .hd_shift = VUL_DATA2_HD_SFT, 498 .agent_disable_reg = -1, 499 .agent_disable_shift = -1, 500 .msb_reg = -1, 501 .msb_shift = -1, 502 }, 503 [MT6797_MEMIF_DAI] = { 504 .name = "DAI", 505 .id = MT6797_MEMIF_DAI, 506 .reg_ofs_base = AFE_DAI_BASE, 507 .reg_ofs_cur = AFE_DAI_CUR, 508 .fs_reg = AFE_DAC_CON0, 509 .fs_shift = DAI_MODE_SFT, 510 .fs_maskbit = DAI_MODE_MASK, 511 .mono_reg = -1, 512 .mono_shift = 0, 513 .enable_reg = AFE_DAC_CON0, 514 .enable_shift = DAI_ON_SFT, 515 .hd_reg = AFE_MEMIF_HD_MODE, 516 .hd_shift = DAI_HD_SFT, 517 .agent_disable_reg = -1, 518 .agent_disable_shift = -1, 519 .msb_reg = -1, 520 .msb_shift = -1, 521 }, 522 [MT6797_MEMIF_MOD_DAI] = { 523 .name = "MOD_DAI", 524 .id = MT6797_MEMIF_MOD_DAI, 525 .reg_ofs_base = AFE_MOD_DAI_BASE, 526 .reg_ofs_cur = AFE_MOD_DAI_CUR, 527 .fs_reg = AFE_DAC_CON1, 528 .fs_shift = MOD_DAI_MODE_SFT, 529 .fs_maskbit = MOD_DAI_MODE_MASK, 530 .mono_reg = -1, 531 .mono_shift = 0, 532 .enable_reg = AFE_DAC_CON0, 533 .enable_shift = MOD_DAI_ON_SFT, 534 .hd_reg = AFE_MEMIF_HD_MODE, 535 .hd_shift = MOD_DAI_HD_SFT, 536 .agent_disable_reg = -1, 537 .agent_disable_shift = -1, 538 .msb_reg = -1, 539 .msb_shift = -1, 540 }, 541 }; 542 543 static const struct mtk_base_irq_data irq_data[MT6797_IRQ_NUM] = { 544 [MT6797_IRQ_1] = { 545 .id = MT6797_IRQ_1, 546 .irq_cnt_reg = AFE_IRQ_MCU_CNT1, 547 .irq_cnt_shift = AFE_IRQ_MCU_CNT1_SFT, 548 .irq_cnt_maskbit = AFE_IRQ_MCU_CNT1_MASK, 549 .irq_fs_reg = AFE_IRQ_MCU_CON, 550 .irq_fs_shift = IRQ1_MCU_MODE_SFT, 551 .irq_fs_maskbit = IRQ1_MCU_MODE_MASK, 552 .irq_en_reg = AFE_IRQ_MCU_CON, 553 .irq_en_shift = IRQ1_MCU_ON_SFT, 554 .irq_clr_reg = AFE_IRQ_MCU_CLR, 555 .irq_clr_shift = IRQ1_MCU_CLR_SFT, 556 }, 557 [MT6797_IRQ_2] = { 558 .id = MT6797_IRQ_2, 559 .irq_cnt_reg = AFE_IRQ_MCU_CNT2, 560 .irq_cnt_shift = AFE_IRQ_MCU_CNT2_SFT, 561 .irq_cnt_maskbit = AFE_IRQ_MCU_CNT2_MASK, 562 .irq_fs_reg = AFE_IRQ_MCU_CON, 563 .irq_fs_shift = IRQ2_MCU_MODE_SFT, 564 .irq_fs_maskbit = IRQ2_MCU_MODE_MASK, 565 .irq_en_reg = AFE_IRQ_MCU_CON, 566 .irq_en_shift = IRQ2_MCU_ON_SFT, 567 .irq_clr_reg = AFE_IRQ_MCU_CLR, 568 .irq_clr_shift = IRQ2_MCU_CLR_SFT, 569 }, 570 [MT6797_IRQ_3] = { 571 .id = MT6797_IRQ_3, 572 .irq_cnt_reg = AFE_IRQ_MCU_CNT3, 573 .irq_cnt_shift = AFE_IRQ_MCU_CNT3_SFT, 574 .irq_cnt_maskbit = AFE_IRQ_MCU_CNT3_MASK, 575 .irq_fs_reg = AFE_IRQ_MCU_CON, 576 .irq_fs_shift = IRQ3_MCU_MODE_SFT, 577 .irq_fs_maskbit = IRQ3_MCU_MODE_MASK, 578 .irq_en_reg = AFE_IRQ_MCU_CON, 579 .irq_en_shift = IRQ3_MCU_ON_SFT, 580 .irq_clr_reg = AFE_IRQ_MCU_CLR, 581 .irq_clr_shift = IRQ3_MCU_CLR_SFT, 582 }, 583 [MT6797_IRQ_4] = { 584 .id = MT6797_IRQ_4, 585 .irq_cnt_reg = AFE_IRQ_MCU_CNT4, 586 .irq_cnt_shift = AFE_IRQ_MCU_CNT4_SFT, 587 .irq_cnt_maskbit = AFE_IRQ_MCU_CNT4_MASK, 588 .irq_fs_reg = AFE_IRQ_MCU_CON, 589 .irq_fs_shift = IRQ4_MCU_MODE_SFT, 590 .irq_fs_maskbit = IRQ4_MCU_MODE_MASK, 591 .irq_en_reg = AFE_IRQ_MCU_CON, 592 .irq_en_shift = IRQ4_MCU_ON_SFT, 593 .irq_clr_reg = AFE_IRQ_MCU_CLR, 594 .irq_clr_shift = IRQ4_MCU_CLR_SFT, 595 }, 596 [MT6797_IRQ_7] = { 597 .id = MT6797_IRQ_7, 598 .irq_cnt_reg = AFE_IRQ_MCU_CNT7, 599 .irq_cnt_shift = AFE_IRQ_MCU_CNT7_SFT, 600 .irq_cnt_maskbit = AFE_IRQ_MCU_CNT7_MASK, 601 .irq_fs_reg = AFE_IRQ_MCU_CON, 602 .irq_fs_shift = IRQ7_MCU_MODE_SFT, 603 .irq_fs_maskbit = IRQ7_MCU_MODE_MASK, 604 .irq_en_reg = AFE_IRQ_MCU_CON, 605 .irq_en_shift = IRQ7_MCU_ON_SFT, 606 .irq_clr_reg = AFE_IRQ_MCU_CLR, 607 .irq_clr_shift = IRQ7_MCU_CLR_SFT, 608 }, 609 }; 610 611 static const struct regmap_config mt6797_afe_regmap_config = { 612 .reg_bits = 32, 613 .reg_stride = 4, 614 .val_bits = 32, 615 .max_register = AFE_MAX_REGISTER, 616 }; 617 618 static irqreturn_t mt6797_afe_irq_handler(int irq_id, void *dev) 619 { 620 struct mtk_base_afe *afe = dev; 621 struct mtk_base_afe_irq *irq; 622 unsigned int status; 623 unsigned int mcu_en; 624 int ret; 625 int i; 626 irqreturn_t irq_ret = IRQ_HANDLED; 627 628 /* get irq that is sent to MCU */ 629 regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en); 630 631 ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status); 632 if (ret || (status & mcu_en) == 0) { 633 dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n", 634 __func__, ret, status, mcu_en); 635 636 /* only clear IRQ which is sent to MCU */ 637 status = mcu_en & AFE_IRQ_STATUS_BITS; 638 639 irq_ret = IRQ_NONE; 640 goto err_irq; 641 } 642 643 for (i = 0; i < MT6797_MEMIF_NUM; i++) { 644 struct mtk_base_afe_memif *memif = &afe->memif[i]; 645 646 if (!memif->substream) 647 continue; 648 649 irq = &afe->irqs[memif->irq_usage]; 650 651 if (status & (1 << irq->irq_data->irq_en_shift)) 652 snd_pcm_period_elapsed(memif->substream); 653 } 654 655 err_irq: 656 /* clear irq */ 657 regmap_write(afe->regmap, 658 AFE_IRQ_MCU_CLR, 659 status & AFE_IRQ_STATUS_BITS); 660 661 return irq_ret; 662 } 663 664 static int mt6797_afe_runtime_suspend(struct device *dev) 665 { 666 struct mtk_base_afe *afe = dev_get_drvdata(dev); 667 unsigned int afe_on_retm; 668 int retry = 0; 669 670 /* disable AFE */ 671 regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0); 672 do { 673 regmap_read(afe->regmap, AFE_DAC_CON0, &afe_on_retm); 674 if ((afe_on_retm & AFE_ON_RETM_MASK_SFT) == 0) 675 break; 676 677 udelay(10); 678 } while (++retry < 100000); 679 680 if (retry) 681 dev_warn(afe->dev, "%s(), retry %d\n", __func__, retry); 682 683 /* make sure all irq status are cleared */ 684 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff); 685 686 return mt6797_afe_disable_clock(afe); 687 } 688 689 static int mt6797_afe_runtime_resume(struct device *dev) 690 { 691 struct mtk_base_afe *afe = dev_get_drvdata(dev); 692 int ret; 693 694 ret = mt6797_afe_enable_clock(afe); 695 if (ret) 696 return ret; 697 698 /* irq signal to mcu only */ 699 regmap_write(afe->regmap, AFE_IRQ_MCU_EN, AFE_IRQ_MCU_EN_MASK_SFT); 700 701 /* force all memif use normal mode */ 702 regmap_update_bits(afe->regmap, AFE_MEMIF_HDALIGN, 703 0x7ff << 16, 0x7ff << 16); 704 /* force cpu use normal mode when access sram data */ 705 regmap_update_bits(afe->regmap, AFE_MEMIF_MSB, 706 CPU_COMPACT_MODE_MASK_SFT, 0); 707 /* force cpu use 8_24 format when writing 32bit data */ 708 regmap_update_bits(afe->regmap, AFE_MEMIF_MSB, 709 CPU_HD_ALIGN_MASK_SFT, 0); 710 711 /* set all output port to 24bit */ 712 regmap_update_bits(afe->regmap, AFE_CONN_24BIT, 713 0x3fffffff, 0x3fffffff); 714 715 /* enable AFE */ 716 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 717 AFE_ON_MASK_SFT, 718 0x1 << AFE_ON_SFT); 719 720 return 0; 721 } 722 723 static int mt6797_afe_component_probe(struct snd_soc_component *component) 724 { 725 return mtk_afe_add_sub_dai_control(component); 726 } 727 728 static const struct snd_soc_component_driver mt6797_afe_component = { 729 .name = AFE_PCM_NAME, 730 .ops = &mtk_afe_pcm_ops, 731 .pcm_new = mtk_afe_pcm_new, 732 .pcm_free = mtk_afe_pcm_free, 733 .probe = mt6797_afe_component_probe, 734 }; 735 736 static int mt6797_dai_memif_register(struct mtk_base_afe *afe) 737 { 738 struct mtk_base_afe_dai *dai; 739 740 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 741 if (!dai) 742 return -ENOMEM; 743 744 list_add(&dai->list, &afe->sub_dais); 745 746 dai->dai_drivers = mt6797_memif_dai_driver; 747 dai->num_dai_drivers = ARRAY_SIZE(mt6797_memif_dai_driver); 748 749 dai->dapm_widgets = mt6797_memif_widgets; 750 dai->num_dapm_widgets = ARRAY_SIZE(mt6797_memif_widgets); 751 dai->dapm_routes = mt6797_memif_routes; 752 dai->num_dapm_routes = ARRAY_SIZE(mt6797_memif_routes); 753 return 0; 754 } 755 756 typedef int (*dai_register_cb)(struct mtk_base_afe *); 757 static const dai_register_cb dai_register_cbs[] = { 758 mt6797_dai_adda_register, 759 mt6797_dai_pcm_register, 760 mt6797_dai_hostless_register, 761 mt6797_dai_memif_register, 762 }; 763 764 static int mt6797_afe_pcm_dev_probe(struct platform_device *pdev) 765 { 766 struct mtk_base_afe *afe; 767 struct mt6797_afe_private *afe_priv; 768 struct resource *res; 769 struct device *dev; 770 int i, irq_id, ret; 771 772 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); 773 if (!afe) 774 return -ENOMEM; 775 776 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv), 777 GFP_KERNEL); 778 if (!afe->platform_priv) 779 return -ENOMEM; 780 781 afe_priv = afe->platform_priv; 782 afe->dev = &pdev->dev; 783 dev = afe->dev; 784 785 /* initial audio related clock */ 786 ret = mt6797_init_clock(afe); 787 if (ret) { 788 dev_err(dev, "init clock error\n"); 789 return ret; 790 } 791 792 /* regmap init */ 793 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 794 795 afe->base_addr = devm_ioremap_resource(&pdev->dev, res); 796 if (IS_ERR(afe->base_addr)) 797 return PTR_ERR(afe->base_addr); 798 799 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr, 800 &mt6797_afe_regmap_config); 801 if (IS_ERR(afe->regmap)) 802 return PTR_ERR(afe->regmap); 803 804 /* init memif */ 805 afe->memif_size = MT6797_MEMIF_NUM; 806 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), 807 GFP_KERNEL); 808 if (!afe->memif) 809 return -ENOMEM; 810 811 for (i = 0; i < afe->memif_size; i++) { 812 afe->memif[i].data = &memif_data[i]; 813 afe->memif[i].irq_usage = -1; 814 } 815 816 mutex_init(&afe->irq_alloc_lock); 817 818 /* irq initialize */ 819 afe->irqs_size = MT6797_IRQ_NUM; 820 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), 821 GFP_KERNEL); 822 if (!afe->irqs) 823 return -ENOMEM; 824 825 for (i = 0; i < afe->irqs_size; i++) 826 afe->irqs[i].irq_data = &irq_data[i]; 827 828 /* request irq */ 829 irq_id = platform_get_irq(pdev, 0); 830 if (!irq_id) { 831 dev_err(dev, "%pOFn no irq found\n", dev->of_node); 832 return -ENXIO; 833 } 834 ret = devm_request_irq(dev, irq_id, mt6797_afe_irq_handler, 835 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe); 836 if (ret) { 837 dev_err(dev, "could not request_irq for asys-isr\n"); 838 return ret; 839 } 840 841 /* init sub_dais */ 842 INIT_LIST_HEAD(&afe->sub_dais); 843 844 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) { 845 ret = dai_register_cbs[i](afe); 846 if (ret) { 847 dev_warn(afe->dev, "dai register i %d fail, ret %d\n", 848 i, ret); 849 return ret; 850 } 851 } 852 853 /* init dai_driver and component_driver */ 854 ret = mtk_afe_combine_sub_dai(afe); 855 if (ret) { 856 dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n", 857 ret); 858 return ret; 859 } 860 861 afe->mtk_afe_hardware = &mt6797_afe_hardware; 862 afe->memif_fs = mt6797_memif_fs; 863 afe->irq_fs = mt6797_irq_fs; 864 865 afe->runtime_resume = mt6797_afe_runtime_resume; 866 afe->runtime_suspend = mt6797_afe_runtime_suspend; 867 868 platform_set_drvdata(pdev, afe); 869 870 pm_runtime_enable(dev); 871 if (!pm_runtime_enabled(dev)) 872 goto err_pm_disable; 873 pm_runtime_get_sync(&pdev->dev); 874 875 /* register component */ 876 ret = devm_snd_soc_register_component(dev, &mt6797_afe_component, 877 NULL, 0); 878 if (ret) { 879 dev_warn(dev, "err_platform\n"); 880 goto err_pm_disable; 881 } 882 883 ret = devm_snd_soc_register_component(afe->dev, 884 &mt6797_afe_pcm_dai_component, 885 afe->dai_drivers, 886 afe->num_dai_drivers); 887 if (ret) { 888 dev_warn(dev, "err_dai_component\n"); 889 goto err_pm_disable; 890 } 891 892 return 0; 893 894 err_pm_disable: 895 pm_runtime_disable(dev); 896 897 return ret; 898 } 899 900 static int mt6797_afe_pcm_dev_remove(struct platform_device *pdev) 901 { 902 pm_runtime_disable(&pdev->dev); 903 if (!pm_runtime_status_suspended(&pdev->dev)) 904 mt6797_afe_runtime_suspend(&pdev->dev); 905 pm_runtime_put_sync(&pdev->dev); 906 907 return 0; 908 } 909 910 static const struct of_device_id mt6797_afe_pcm_dt_match[] = { 911 { .compatible = "mediatek,mt6797-audio", }, 912 {}, 913 }; 914 MODULE_DEVICE_TABLE(of, mt6797_afe_pcm_dt_match); 915 916 static const struct dev_pm_ops mt6797_afe_pm_ops = { 917 SET_RUNTIME_PM_OPS(mt6797_afe_runtime_suspend, 918 mt6797_afe_runtime_resume, NULL) 919 }; 920 921 static struct platform_driver mt6797_afe_pcm_driver = { 922 .driver = { 923 .name = "mt6797-audio", 924 .of_match_table = mt6797_afe_pcm_dt_match, 925 #ifdef CONFIG_PM 926 .pm = &mt6797_afe_pm_ops, 927 #endif 928 }, 929 .probe = mt6797_afe_pcm_dev_probe, 930 .remove = mt6797_afe_pcm_dev_remove, 931 }; 932 933 module_platform_driver(mt6797_afe_pcm_driver); 934 935 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 6797"); 936 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>"); 937 MODULE_LICENSE("GPL v2"); 938