1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Mediatek ALSA SoC AFE platform driver for 6797
4 //
5 // Copyright (c) 2018 MediaTek Inc.
6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7 
8 #include <linux/delay.h>
9 #include <linux/module.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <linux/pm_runtime.h>
14 
15 #include "mt6797-afe-common.h"
16 #include "mt6797-afe-clk.h"
17 #include "mt6797-interconnection.h"
18 #include "mt6797-reg.h"
19 #include "../common/mtk-afe-platform-driver.h"
20 #include "../common/mtk-afe-fe-dai.h"
21 
22 enum {
23 	MTK_AFE_RATE_8K = 0,
24 	MTK_AFE_RATE_11K = 1,
25 	MTK_AFE_RATE_12K = 2,
26 	MTK_AFE_RATE_384K = 3,
27 	MTK_AFE_RATE_16K = 4,
28 	MTK_AFE_RATE_22K = 5,
29 	MTK_AFE_RATE_24K = 6,
30 	MTK_AFE_RATE_130K = 7,
31 	MTK_AFE_RATE_32K = 8,
32 	MTK_AFE_RATE_44K = 9,
33 	MTK_AFE_RATE_48K = 10,
34 	MTK_AFE_RATE_88K = 11,
35 	MTK_AFE_RATE_96K = 12,
36 	MTK_AFE_RATE_174K = 13,
37 	MTK_AFE_RATE_192K = 14,
38 	MTK_AFE_RATE_260K = 15,
39 };
40 
41 enum {
42 	MTK_AFE_DAI_MEMIF_RATE_8K = 0,
43 	MTK_AFE_DAI_MEMIF_RATE_16K = 1,
44 	MTK_AFE_DAI_MEMIF_RATE_32K = 2,
45 };
46 
47 enum {
48 	MTK_AFE_PCM_RATE_8K = 0,
49 	MTK_AFE_PCM_RATE_16K = 1,
50 	MTK_AFE_PCM_RATE_32K = 2,
51 	MTK_AFE_PCM_RATE_48K = 3,
52 };
53 
54 unsigned int mt6797_general_rate_transform(struct device *dev,
55 					   unsigned int rate)
56 {
57 	switch (rate) {
58 	case 8000:
59 		return MTK_AFE_RATE_8K;
60 	case 11025:
61 		return MTK_AFE_RATE_11K;
62 	case 12000:
63 		return MTK_AFE_RATE_12K;
64 	case 16000:
65 		return MTK_AFE_RATE_16K;
66 	case 22050:
67 		return MTK_AFE_RATE_22K;
68 	case 24000:
69 		return MTK_AFE_RATE_24K;
70 	case 32000:
71 		return MTK_AFE_RATE_32K;
72 	case 44100:
73 		return MTK_AFE_RATE_44K;
74 	case 48000:
75 		return MTK_AFE_RATE_48K;
76 	case 88200:
77 		return MTK_AFE_RATE_88K;
78 	case 96000:
79 		return MTK_AFE_RATE_96K;
80 	case 130000:
81 		return MTK_AFE_RATE_130K;
82 	case 176400:
83 		return MTK_AFE_RATE_174K;
84 	case 192000:
85 		return MTK_AFE_RATE_192K;
86 	case 260000:
87 		return MTK_AFE_RATE_260K;
88 	default:
89 		dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
90 			 __func__, rate, MTK_AFE_RATE_48K);
91 		return MTK_AFE_RATE_48K;
92 	}
93 }
94 
95 static unsigned int dai_memif_rate_transform(struct device *dev,
96 					     unsigned int rate)
97 {
98 	switch (rate) {
99 	case 8000:
100 		return MTK_AFE_DAI_MEMIF_RATE_8K;
101 	case 16000:
102 		return MTK_AFE_DAI_MEMIF_RATE_16K;
103 	case 32000:
104 		return MTK_AFE_DAI_MEMIF_RATE_32K;
105 	default:
106 		dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
107 			 __func__, rate, MTK_AFE_DAI_MEMIF_RATE_16K);
108 		return MTK_AFE_DAI_MEMIF_RATE_16K;
109 	}
110 }
111 
112 unsigned int mt6797_rate_transform(struct device *dev,
113 				   unsigned int rate, int aud_blk)
114 {
115 	switch (aud_blk) {
116 	case MT6797_MEMIF_DAI:
117 	case MT6797_MEMIF_MOD_DAI:
118 		return dai_memif_rate_transform(dev, rate);
119 	default:
120 		return mt6797_general_rate_transform(dev, rate);
121 	}
122 }
123 
124 static const struct snd_pcm_hardware mt6797_afe_hardware = {
125 	.info = SNDRV_PCM_INFO_MMAP |
126 		SNDRV_PCM_INFO_INTERLEAVED |
127 		SNDRV_PCM_INFO_MMAP_VALID,
128 	.formats = SNDRV_PCM_FMTBIT_S16_LE |
129 		   SNDRV_PCM_FMTBIT_S24_LE |
130 		   SNDRV_PCM_FMTBIT_S32_LE,
131 	.period_bytes_min = 256,
132 	.period_bytes_max = 4 * 48 * 1024,
133 	.periods_min = 2,
134 	.periods_max = 256,
135 	.buffer_bytes_max = 8 * 48 * 1024,
136 	.fifo_size = 0,
137 };
138 
139 static int mt6797_memif_fs(struct snd_pcm_substream *substream,
140 			   unsigned int rate)
141 {
142 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
143 	struct snd_soc_component *component =
144 		snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
145 	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
146 	int id = asoc_rtd_to_cpu(rtd, 0)->id;
147 
148 	return mt6797_rate_transform(afe->dev, rate, id);
149 }
150 
151 static int mt6797_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
152 {
153 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
154 	struct snd_soc_component *component =
155 		snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
156 	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
157 
158 	return mt6797_general_rate_transform(afe->dev, rate);
159 }
160 
161 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
162 		       SNDRV_PCM_RATE_88200 |\
163 		       SNDRV_PCM_RATE_96000 |\
164 		       SNDRV_PCM_RATE_176400 |\
165 		       SNDRV_PCM_RATE_192000)
166 
167 #define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\
168 			   SNDRV_PCM_RATE_16000 |\
169 			   SNDRV_PCM_RATE_32000)
170 
171 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
172 			 SNDRV_PCM_FMTBIT_S24_LE |\
173 			 SNDRV_PCM_FMTBIT_S32_LE)
174 
175 static struct snd_soc_dai_driver mt6797_memif_dai_driver[] = {
176 	/* FE DAIs: memory intefaces to CPU */
177 	{
178 		.name = "DL1",
179 		.id = MT6797_MEMIF_DL1,
180 		.playback = {
181 			.stream_name = "DL1",
182 			.channels_min = 1,
183 			.channels_max = 2,
184 			.rates = MTK_PCM_RATES,
185 			.formats = MTK_PCM_FORMATS,
186 		},
187 		.ops = &mtk_afe_fe_ops,
188 	},
189 	{
190 		.name = "DL2",
191 		.id = MT6797_MEMIF_DL2,
192 		.playback = {
193 			.stream_name = "DL2",
194 			.channels_min = 1,
195 			.channels_max = 2,
196 			.rates = MTK_PCM_RATES,
197 			.formats = MTK_PCM_FORMATS,
198 		},
199 		.ops = &mtk_afe_fe_ops,
200 	},
201 	{
202 		.name = "DL3",
203 		.id = MT6797_MEMIF_DL3,
204 		.playback = {
205 			.stream_name = "DL3",
206 			.channels_min = 1,
207 			.channels_max = 2,
208 			.rates = MTK_PCM_RATES,
209 			.formats = MTK_PCM_FORMATS,
210 		},
211 		.ops = &mtk_afe_fe_ops,
212 	},
213 	{
214 		.name = "UL1",
215 		.id = MT6797_MEMIF_VUL12,
216 		.capture = {
217 			.stream_name = "UL1",
218 			.channels_min = 1,
219 			.channels_max = 2,
220 			.rates = MTK_PCM_RATES,
221 			.formats = MTK_PCM_FORMATS,
222 		},
223 		.ops = &mtk_afe_fe_ops,
224 	},
225 	{
226 		.name = "UL2",
227 		.id = MT6797_MEMIF_AWB,
228 		.capture = {
229 			.stream_name = "UL2",
230 			.channels_min = 1,
231 			.channels_max = 2,
232 			.rates = MTK_PCM_RATES,
233 			.formats = MTK_PCM_FORMATS,
234 		},
235 		.ops = &mtk_afe_fe_ops,
236 	},
237 	{
238 		.name = "UL3",
239 		.id = MT6797_MEMIF_VUL,
240 		.capture = {
241 			.stream_name = "UL3",
242 			.channels_min = 1,
243 			.channels_max = 2,
244 			.rates = MTK_PCM_RATES,
245 			.formats = MTK_PCM_FORMATS,
246 		},
247 		.ops = &mtk_afe_fe_ops,
248 	},
249 	{
250 		.name = "UL_MONO_1",
251 		.id = MT6797_MEMIF_MOD_DAI,
252 		.capture = {
253 			.stream_name = "UL_MONO_1",
254 			.channels_min = 1,
255 			.channels_max = 1,
256 			.rates = MTK_PCM_DAI_RATES,
257 			.formats = MTK_PCM_FORMATS,
258 		},
259 		.ops = &mtk_afe_fe_ops,
260 	},
261 	{
262 		.name = "UL_MONO_2",
263 		.id = MT6797_MEMIF_DAI,
264 		.capture = {
265 			.stream_name = "UL_MONO_2",
266 			.channels_min = 1,
267 			.channels_max = 1,
268 			.rates = MTK_PCM_DAI_RATES,
269 			.formats = MTK_PCM_FORMATS,
270 		},
271 		.ops = &mtk_afe_fe_ops,
272 	},
273 };
274 
275 /* dma widget & routes*/
276 static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
277 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21,
278 				    I_ADDA_UL_CH1, 1, 0),
279 };
280 
281 static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
282 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22,
283 				    I_ADDA_UL_CH2, 1, 0),
284 };
285 
286 static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
287 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN5,
288 				    I_ADDA_UL_CH1, 1, 0),
289 	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5,
290 				    I_DL1_CH1, 1, 0),
291 	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5,
292 				    I_DL2_CH1, 1, 0),
293 	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5,
294 				    I_DL3_CH1, 1, 0),
295 };
296 
297 static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
298 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN6,
299 				    I_ADDA_UL_CH2, 1, 0),
300 	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6,
301 				    I_DL1_CH2, 1, 0),
302 	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6,
303 				    I_DL2_CH2, 1, 0),
304 	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6,
305 				    I_DL3_CH2, 1, 0),
306 };
307 
308 static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
309 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN9,
310 				    I_ADDA_UL_CH1, 1, 0),
311 };
312 
313 static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
314 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN10,
315 				    I_ADDA_UL_CH2, 1, 0),
316 };
317 
318 static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = {
319 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN12,
320 				    I_ADDA_UL_CH1, 1, 0),
321 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN12,
322 				    I_ADDA_UL_CH2, 1, 0),
323 };
324 
325 static const struct snd_kcontrol_new memif_ul_mono_2_mix[] = {
326 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN11,
327 				    I_ADDA_UL_CH1, 1, 0),
328 	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN11,
329 				    I_ADDA_UL_CH2, 1, 0),
330 };
331 
332 static const struct snd_soc_dapm_widget mt6797_memif_widgets[] = {
333 	/* memif */
334 	SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
335 			   memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
336 	SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
337 			   memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
338 
339 	SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
340 			   memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
341 	SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
342 			   memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
343 
344 	SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
345 			   memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
346 	SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
347 			   memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
348 
349 	SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0,
350 			   memif_ul_mono_1_mix,
351 			   ARRAY_SIZE(memif_ul_mono_1_mix)),
352 
353 	SND_SOC_DAPM_MIXER("UL_MONO_2_CH1", SND_SOC_NOPM, 0, 0,
354 			   memif_ul_mono_2_mix,
355 			   ARRAY_SIZE(memif_ul_mono_2_mix)),
356 };
357 
358 static const struct snd_soc_dapm_route mt6797_memif_routes[] = {
359 	/* capture */
360 	{"UL1", NULL, "UL1_CH1"},
361 	{"UL1", NULL, "UL1_CH2"},
362 	{"UL1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
363 	{"UL1_CH2", "ADDA_UL_CH2", "ADDA Capture"},
364 
365 	{"UL2", NULL, "UL2_CH1"},
366 	{"UL2", NULL, "UL2_CH2"},
367 	{"UL2_CH1", "ADDA_UL_CH1", "ADDA Capture"},
368 	{"UL2_CH2", "ADDA_UL_CH2", "ADDA Capture"},
369 
370 	{"UL3", NULL, "UL3_CH1"},
371 	{"UL3", NULL, "UL3_CH2"},
372 	{"UL3_CH1", "ADDA_UL_CH1", "ADDA Capture"},
373 	{"UL3_CH2", "ADDA_UL_CH2", "ADDA Capture"},
374 
375 	{"UL_MONO_1", NULL, "UL_MONO_1_CH1"},
376 	{"UL_MONO_1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
377 	{"UL_MONO_1_CH1", "ADDA_UL_CH2", "ADDA Capture"},
378 
379 	{"UL_MONO_2", NULL, "UL_MONO_2_CH1"},
380 	{"UL_MONO_2_CH1", "ADDA_UL_CH1", "ADDA Capture"},
381 	{"UL_MONO_2_CH1", "ADDA_UL_CH2", "ADDA Capture"},
382 };
383 
384 static const struct snd_soc_component_driver mt6797_afe_pcm_dai_component = {
385 	.name = "mt6797-afe-pcm-dai",
386 };
387 
388 static const struct mtk_base_memif_data memif_data[MT6797_MEMIF_NUM] = {
389 	[MT6797_MEMIF_DL1] = {
390 		.name = "DL1",
391 		.id = MT6797_MEMIF_DL1,
392 		.reg_ofs_base = AFE_DL1_BASE,
393 		.reg_ofs_cur = AFE_DL1_CUR,
394 		.fs_reg = AFE_DAC_CON1,
395 		.fs_shift = DL1_MODE_SFT,
396 		.fs_maskbit = DL1_MODE_MASK,
397 		.mono_reg = AFE_DAC_CON1,
398 		.mono_shift = DL1_DATA_SFT,
399 		.enable_reg = AFE_DAC_CON0,
400 		.enable_shift = DL1_ON_SFT,
401 		.hd_reg = AFE_MEMIF_HD_MODE,
402 		.hd_shift = DL1_HD_SFT,
403 		.agent_disable_reg = -1,
404 		.msb_reg = -1,
405 	},
406 	[MT6797_MEMIF_DL2] = {
407 		.name = "DL2",
408 		.id = MT6797_MEMIF_DL2,
409 		.reg_ofs_base = AFE_DL2_BASE,
410 		.reg_ofs_cur = AFE_DL2_CUR,
411 		.fs_reg = AFE_DAC_CON1,
412 		.fs_shift = DL2_MODE_SFT,
413 		.fs_maskbit = DL2_MODE_MASK,
414 		.mono_reg = AFE_DAC_CON1,
415 		.mono_shift = DL2_DATA_SFT,
416 		.enable_reg = AFE_DAC_CON0,
417 		.enable_shift = DL2_ON_SFT,
418 		.hd_reg = AFE_MEMIF_HD_MODE,
419 		.hd_shift = DL2_HD_SFT,
420 		.agent_disable_reg = -1,
421 		.msb_reg = -1,
422 	},
423 	[MT6797_MEMIF_DL3] = {
424 		.name = "DL3",
425 		.id = MT6797_MEMIF_DL3,
426 		.reg_ofs_base = AFE_DL3_BASE,
427 		.reg_ofs_cur = AFE_DL3_CUR,
428 		.fs_reg = AFE_DAC_CON0,
429 		.fs_shift = DL3_MODE_SFT,
430 		.fs_maskbit = DL3_MODE_MASK,
431 		.mono_reg = AFE_DAC_CON1,
432 		.mono_shift = DL3_DATA_SFT,
433 		.enable_reg = AFE_DAC_CON0,
434 		.enable_shift = DL3_ON_SFT,
435 		.hd_reg = AFE_MEMIF_HD_MODE,
436 		.hd_shift = DL3_HD_SFT,
437 		.agent_disable_reg = -1,
438 		.msb_reg = -1,
439 	},
440 	[MT6797_MEMIF_VUL] = {
441 		.name = "VUL",
442 		.id = MT6797_MEMIF_VUL,
443 		.reg_ofs_base = AFE_VUL_BASE,
444 		.reg_ofs_cur = AFE_VUL_CUR,
445 		.fs_reg = AFE_DAC_CON1,
446 		.fs_shift = VUL_MODE_SFT,
447 		.fs_maskbit = VUL_MODE_MASK,
448 		.mono_reg = AFE_DAC_CON1,
449 		.mono_shift = VUL_DATA_SFT,
450 		.enable_reg = AFE_DAC_CON0,
451 		.enable_shift = VUL_ON_SFT,
452 		.hd_reg = AFE_MEMIF_HD_MODE,
453 		.hd_shift = VUL_HD_SFT,
454 		.agent_disable_reg = -1,
455 		.msb_reg = -1,
456 	},
457 	[MT6797_MEMIF_AWB] = {
458 		.name = "AWB",
459 		.id = MT6797_MEMIF_AWB,
460 		.reg_ofs_base = AFE_AWB_BASE,
461 		.reg_ofs_cur = AFE_AWB_CUR,
462 		.fs_reg = AFE_DAC_CON1,
463 		.fs_shift = AWB_MODE_SFT,
464 		.fs_maskbit = AWB_MODE_MASK,
465 		.mono_reg = AFE_DAC_CON1,
466 		.mono_shift = AWB_DATA_SFT,
467 		.enable_reg = AFE_DAC_CON0,
468 		.enable_shift = AWB_ON_SFT,
469 		.hd_reg = AFE_MEMIF_HD_MODE,
470 		.hd_shift = AWB_HD_SFT,
471 		.agent_disable_reg = -1,
472 		.msb_reg = -1,
473 	},
474 	[MT6797_MEMIF_VUL12] = {
475 		.name = "VUL12",
476 		.id = MT6797_MEMIF_VUL12,
477 		.reg_ofs_base = AFE_VUL_D2_BASE,
478 		.reg_ofs_cur = AFE_VUL_D2_CUR,
479 		.fs_reg = AFE_DAC_CON0,
480 		.fs_shift = VUL_DATA2_MODE_SFT,
481 		.fs_maskbit = VUL_DATA2_MODE_MASK,
482 		.mono_reg = AFE_DAC_CON0,
483 		.mono_shift = VUL_DATA2_DATA_SFT,
484 		.enable_reg = AFE_DAC_CON0,
485 		.enable_shift = VUL_DATA2_ON_SFT,
486 		.hd_reg = AFE_MEMIF_HD_MODE,
487 		.hd_shift = VUL_DATA2_HD_SFT,
488 		.agent_disable_reg = -1,
489 		.msb_reg = -1,
490 	},
491 	[MT6797_MEMIF_DAI] = {
492 		.name = "DAI",
493 		.id = MT6797_MEMIF_DAI,
494 		.reg_ofs_base = AFE_DAI_BASE,
495 		.reg_ofs_cur = AFE_DAI_CUR,
496 		.fs_reg = AFE_DAC_CON0,
497 		.fs_shift = DAI_MODE_SFT,
498 		.fs_maskbit = DAI_MODE_MASK,
499 		.mono_reg = -1,
500 		.mono_shift = 0,
501 		.enable_reg = AFE_DAC_CON0,
502 		.enable_shift = DAI_ON_SFT,
503 		.hd_reg = AFE_MEMIF_HD_MODE,
504 		.hd_shift = DAI_HD_SFT,
505 		.agent_disable_reg = -1,
506 		.msb_reg = -1,
507 	},
508 	[MT6797_MEMIF_MOD_DAI] = {
509 		.name = "MOD_DAI",
510 		.id = MT6797_MEMIF_MOD_DAI,
511 		.reg_ofs_base = AFE_MOD_DAI_BASE,
512 		.reg_ofs_cur = AFE_MOD_DAI_CUR,
513 		.fs_reg = AFE_DAC_CON1,
514 		.fs_shift = MOD_DAI_MODE_SFT,
515 		.fs_maskbit = MOD_DAI_MODE_MASK,
516 		.mono_reg = -1,
517 		.mono_shift = 0,
518 		.enable_reg = AFE_DAC_CON0,
519 		.enable_shift = MOD_DAI_ON_SFT,
520 		.hd_reg = AFE_MEMIF_HD_MODE,
521 		.hd_shift = MOD_DAI_HD_SFT,
522 		.agent_disable_reg = -1,
523 		.msb_reg = -1,
524 	},
525 };
526 
527 static const struct mtk_base_irq_data irq_data[MT6797_IRQ_NUM] = {
528 	[MT6797_IRQ_1] = {
529 		.id = MT6797_IRQ_1,
530 		.irq_cnt_reg = AFE_IRQ_MCU_CNT1,
531 		.irq_cnt_shift = AFE_IRQ_MCU_CNT1_SFT,
532 		.irq_cnt_maskbit = AFE_IRQ_MCU_CNT1_MASK,
533 		.irq_fs_reg = AFE_IRQ_MCU_CON,
534 		.irq_fs_shift = IRQ1_MCU_MODE_SFT,
535 		.irq_fs_maskbit = IRQ1_MCU_MODE_MASK,
536 		.irq_en_reg = AFE_IRQ_MCU_CON,
537 		.irq_en_shift = IRQ1_MCU_ON_SFT,
538 		.irq_clr_reg = AFE_IRQ_MCU_CLR,
539 		.irq_clr_shift = IRQ1_MCU_CLR_SFT,
540 	},
541 	[MT6797_IRQ_2] = {
542 		.id = MT6797_IRQ_2,
543 		.irq_cnt_reg = AFE_IRQ_MCU_CNT2,
544 		.irq_cnt_shift = AFE_IRQ_MCU_CNT2_SFT,
545 		.irq_cnt_maskbit = AFE_IRQ_MCU_CNT2_MASK,
546 		.irq_fs_reg = AFE_IRQ_MCU_CON,
547 		.irq_fs_shift = IRQ2_MCU_MODE_SFT,
548 		.irq_fs_maskbit = IRQ2_MCU_MODE_MASK,
549 		.irq_en_reg = AFE_IRQ_MCU_CON,
550 		.irq_en_shift = IRQ2_MCU_ON_SFT,
551 		.irq_clr_reg = AFE_IRQ_MCU_CLR,
552 		.irq_clr_shift = IRQ2_MCU_CLR_SFT,
553 	},
554 	[MT6797_IRQ_3] = {
555 		.id = MT6797_IRQ_3,
556 		.irq_cnt_reg = AFE_IRQ_MCU_CNT3,
557 		.irq_cnt_shift = AFE_IRQ_MCU_CNT3_SFT,
558 		.irq_cnt_maskbit = AFE_IRQ_MCU_CNT3_MASK,
559 		.irq_fs_reg = AFE_IRQ_MCU_CON,
560 		.irq_fs_shift = IRQ3_MCU_MODE_SFT,
561 		.irq_fs_maskbit = IRQ3_MCU_MODE_MASK,
562 		.irq_en_reg = AFE_IRQ_MCU_CON,
563 		.irq_en_shift = IRQ3_MCU_ON_SFT,
564 		.irq_clr_reg = AFE_IRQ_MCU_CLR,
565 		.irq_clr_shift = IRQ3_MCU_CLR_SFT,
566 	},
567 	[MT6797_IRQ_4] = {
568 		.id = MT6797_IRQ_4,
569 		.irq_cnt_reg = AFE_IRQ_MCU_CNT4,
570 		.irq_cnt_shift = AFE_IRQ_MCU_CNT4_SFT,
571 		.irq_cnt_maskbit = AFE_IRQ_MCU_CNT4_MASK,
572 		.irq_fs_reg = AFE_IRQ_MCU_CON,
573 		.irq_fs_shift = IRQ4_MCU_MODE_SFT,
574 		.irq_fs_maskbit = IRQ4_MCU_MODE_MASK,
575 		.irq_en_reg = AFE_IRQ_MCU_CON,
576 		.irq_en_shift = IRQ4_MCU_ON_SFT,
577 		.irq_clr_reg = AFE_IRQ_MCU_CLR,
578 		.irq_clr_shift = IRQ4_MCU_CLR_SFT,
579 	},
580 	[MT6797_IRQ_7] = {
581 		.id = MT6797_IRQ_7,
582 		.irq_cnt_reg = AFE_IRQ_MCU_CNT7,
583 		.irq_cnt_shift = AFE_IRQ_MCU_CNT7_SFT,
584 		.irq_cnt_maskbit = AFE_IRQ_MCU_CNT7_MASK,
585 		.irq_fs_reg = AFE_IRQ_MCU_CON,
586 		.irq_fs_shift = IRQ7_MCU_MODE_SFT,
587 		.irq_fs_maskbit = IRQ7_MCU_MODE_MASK,
588 		.irq_en_reg = AFE_IRQ_MCU_CON,
589 		.irq_en_shift = IRQ7_MCU_ON_SFT,
590 		.irq_clr_reg = AFE_IRQ_MCU_CLR,
591 		.irq_clr_shift = IRQ7_MCU_CLR_SFT,
592 	},
593 };
594 
595 static const struct regmap_config mt6797_afe_regmap_config = {
596 	.reg_bits = 32,
597 	.reg_stride = 4,
598 	.val_bits = 32,
599 	.max_register = AFE_MAX_REGISTER,
600 };
601 
602 static irqreturn_t mt6797_afe_irq_handler(int irq_id, void *dev)
603 {
604 	struct mtk_base_afe *afe = dev;
605 	struct mtk_base_afe_irq *irq;
606 	unsigned int status;
607 	unsigned int mcu_en;
608 	int ret;
609 	int i;
610 	irqreturn_t irq_ret = IRQ_HANDLED;
611 
612 	/* get irq that is sent to MCU */
613 	regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
614 
615 	ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
616 	if (ret || (status & mcu_en) == 0) {
617 		dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
618 			__func__, ret, status, mcu_en);
619 
620 		/* only clear IRQ which is sent to MCU */
621 		status = mcu_en & AFE_IRQ_STATUS_BITS;
622 
623 		irq_ret = IRQ_NONE;
624 		goto err_irq;
625 	}
626 
627 	for (i = 0; i < MT6797_MEMIF_NUM; i++) {
628 		struct mtk_base_afe_memif *memif = &afe->memif[i];
629 
630 		if (!memif->substream)
631 			continue;
632 
633 		irq = &afe->irqs[memif->irq_usage];
634 
635 		if (status & (1 << irq->irq_data->irq_en_shift))
636 			snd_pcm_period_elapsed(memif->substream);
637 	}
638 
639 err_irq:
640 	/* clear irq */
641 	regmap_write(afe->regmap,
642 		     AFE_IRQ_MCU_CLR,
643 		     status & AFE_IRQ_STATUS_BITS);
644 
645 	return irq_ret;
646 }
647 
648 static int mt6797_afe_runtime_suspend(struct device *dev)
649 {
650 	struct mtk_base_afe *afe = dev_get_drvdata(dev);
651 	unsigned int afe_on_retm;
652 	int retry = 0;
653 
654 	/* disable AFE */
655 	regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0);
656 	do {
657 		regmap_read(afe->regmap, AFE_DAC_CON0, &afe_on_retm);
658 		if ((afe_on_retm & AFE_ON_RETM_MASK_SFT) == 0)
659 			break;
660 
661 		udelay(10);
662 	} while (++retry < 100000);
663 
664 	if (retry)
665 		dev_warn(afe->dev, "%s(), retry %d\n", __func__, retry);
666 
667 	/* make sure all irq status are cleared */
668 	regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
669 
670 	return mt6797_afe_disable_clock(afe);
671 }
672 
673 static int mt6797_afe_runtime_resume(struct device *dev)
674 {
675 	struct mtk_base_afe *afe = dev_get_drvdata(dev);
676 	int ret;
677 
678 	ret = mt6797_afe_enable_clock(afe);
679 	if (ret)
680 		return ret;
681 
682 	/* irq signal to mcu only */
683 	regmap_write(afe->regmap, AFE_IRQ_MCU_EN, AFE_IRQ_MCU_EN_MASK_SFT);
684 
685 	/* force all memif use normal mode */
686 	regmap_update_bits(afe->regmap, AFE_MEMIF_HDALIGN,
687 			   0x7ff << 16, 0x7ff << 16);
688 	/* force cpu use normal mode when access sram data */
689 	regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
690 			   CPU_COMPACT_MODE_MASK_SFT, 0);
691 	/* force cpu use 8_24 format when writing 32bit data */
692 	regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
693 			   CPU_HD_ALIGN_MASK_SFT, 0);
694 
695 	/* set all output port to 24bit */
696 	regmap_update_bits(afe->regmap, AFE_CONN_24BIT,
697 			   0x3fffffff, 0x3fffffff);
698 
699 	/* enable AFE */
700 	regmap_update_bits(afe->regmap, AFE_DAC_CON0,
701 			   AFE_ON_MASK_SFT,
702 			   0x1 << AFE_ON_SFT);
703 
704 	return 0;
705 }
706 
707 static int mt6797_afe_component_probe(struct snd_soc_component *component)
708 {
709 	return mtk_afe_add_sub_dai_control(component);
710 }
711 
712 static const struct snd_soc_component_driver mt6797_afe_component = {
713 	.name		= AFE_PCM_NAME,
714 	.probe		= mt6797_afe_component_probe,
715 	.pointer	= mtk_afe_pcm_pointer,
716 	.pcm_construct	= mtk_afe_pcm_new,
717 };
718 
719 static int mt6797_dai_memif_register(struct mtk_base_afe *afe)
720 {
721 	struct mtk_base_afe_dai *dai;
722 
723 	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
724 	if (!dai)
725 		return -ENOMEM;
726 
727 	list_add(&dai->list, &afe->sub_dais);
728 
729 	dai->dai_drivers = mt6797_memif_dai_driver;
730 	dai->num_dai_drivers = ARRAY_SIZE(mt6797_memif_dai_driver);
731 
732 	dai->dapm_widgets = mt6797_memif_widgets;
733 	dai->num_dapm_widgets = ARRAY_SIZE(mt6797_memif_widgets);
734 	dai->dapm_routes = mt6797_memif_routes;
735 	dai->num_dapm_routes = ARRAY_SIZE(mt6797_memif_routes);
736 	return 0;
737 }
738 
739 typedef int (*dai_register_cb)(struct mtk_base_afe *);
740 static const dai_register_cb dai_register_cbs[] = {
741 	mt6797_dai_adda_register,
742 	mt6797_dai_pcm_register,
743 	mt6797_dai_hostless_register,
744 	mt6797_dai_memif_register,
745 };
746 
747 static int mt6797_afe_pcm_dev_probe(struct platform_device *pdev)
748 {
749 	struct mtk_base_afe *afe;
750 	struct mt6797_afe_private *afe_priv;
751 	struct device *dev;
752 	int i, irq_id, ret;
753 
754 	afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
755 	if (!afe)
756 		return -ENOMEM;
757 
758 	afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
759 					  GFP_KERNEL);
760 	if (!afe->platform_priv)
761 		return -ENOMEM;
762 
763 	afe_priv = afe->platform_priv;
764 	afe->dev = &pdev->dev;
765 	dev = afe->dev;
766 
767 	/* initial audio related clock */
768 	ret = mt6797_init_clock(afe);
769 	if (ret) {
770 		dev_err(dev, "init clock error\n");
771 		return ret;
772 	}
773 
774 	/* regmap init */
775 	afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
776 	if (IS_ERR(afe->base_addr))
777 		return PTR_ERR(afe->base_addr);
778 
779 	afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
780 					    &mt6797_afe_regmap_config);
781 	if (IS_ERR(afe->regmap))
782 		return PTR_ERR(afe->regmap);
783 
784 	/* init memif */
785 	afe->memif_size = MT6797_MEMIF_NUM;
786 	afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
787 				  GFP_KERNEL);
788 	if (!afe->memif)
789 		return -ENOMEM;
790 
791 	for (i = 0; i < afe->memif_size; i++) {
792 		afe->memif[i].data = &memif_data[i];
793 		afe->memif[i].irq_usage = -1;
794 	}
795 
796 	mutex_init(&afe->irq_alloc_lock);
797 
798 	/* irq initialize */
799 	afe->irqs_size = MT6797_IRQ_NUM;
800 	afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
801 				 GFP_KERNEL);
802 	if (!afe->irqs)
803 		return -ENOMEM;
804 
805 	for (i = 0; i < afe->irqs_size; i++)
806 		afe->irqs[i].irq_data = &irq_data[i];
807 
808 	/* request irq */
809 	irq_id = platform_get_irq(pdev, 0);
810 	if (irq_id < 0)
811 		return irq_id;
812 
813 	ret = devm_request_irq(dev, irq_id, mt6797_afe_irq_handler,
814 			       IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
815 	if (ret) {
816 		dev_err(dev, "could not request_irq for asys-isr\n");
817 		return ret;
818 	}
819 
820 	/* init sub_dais */
821 	INIT_LIST_HEAD(&afe->sub_dais);
822 
823 	for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
824 		ret = dai_register_cbs[i](afe);
825 		if (ret) {
826 			dev_warn(afe->dev, "dai register i %d fail, ret %d\n",
827 				 i, ret);
828 			return ret;
829 		}
830 	}
831 
832 	/* init dai_driver and component_driver */
833 	ret = mtk_afe_combine_sub_dai(afe);
834 	if (ret) {
835 		dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n",
836 			 ret);
837 		return ret;
838 	}
839 
840 	afe->mtk_afe_hardware = &mt6797_afe_hardware;
841 	afe->memif_fs = mt6797_memif_fs;
842 	afe->irq_fs = mt6797_irq_fs;
843 
844 	afe->runtime_resume = mt6797_afe_runtime_resume;
845 	afe->runtime_suspend = mt6797_afe_runtime_suspend;
846 
847 	platform_set_drvdata(pdev, afe);
848 
849 	pm_runtime_enable(dev);
850 	if (!pm_runtime_enabled(dev))
851 		goto err_pm_disable;
852 	pm_runtime_get_sync(&pdev->dev);
853 
854 	/* register component */
855 	ret = devm_snd_soc_register_component(dev, &mt6797_afe_component,
856 					      NULL, 0);
857 	if (ret) {
858 		dev_warn(dev, "err_platform\n");
859 		goto err_pm_disable;
860 	}
861 
862 	ret = devm_snd_soc_register_component(afe->dev,
863 				     &mt6797_afe_pcm_dai_component,
864 				     afe->dai_drivers,
865 				     afe->num_dai_drivers);
866 	if (ret) {
867 		dev_warn(dev, "err_dai_component\n");
868 		goto err_pm_disable;
869 	}
870 
871 	return 0;
872 
873 err_pm_disable:
874 	pm_runtime_disable(dev);
875 
876 	return ret;
877 }
878 
879 static int mt6797_afe_pcm_dev_remove(struct platform_device *pdev)
880 {
881 	pm_runtime_disable(&pdev->dev);
882 	if (!pm_runtime_status_suspended(&pdev->dev))
883 		mt6797_afe_runtime_suspend(&pdev->dev);
884 	pm_runtime_put_sync(&pdev->dev);
885 
886 	return 0;
887 }
888 
889 static const struct of_device_id mt6797_afe_pcm_dt_match[] = {
890 	{ .compatible = "mediatek,mt6797-audio", },
891 	{},
892 };
893 MODULE_DEVICE_TABLE(of, mt6797_afe_pcm_dt_match);
894 
895 static const struct dev_pm_ops mt6797_afe_pm_ops = {
896 	SET_RUNTIME_PM_OPS(mt6797_afe_runtime_suspend,
897 			   mt6797_afe_runtime_resume, NULL)
898 };
899 
900 static struct platform_driver mt6797_afe_pcm_driver = {
901 	.driver = {
902 		   .name = "mt6797-audio",
903 		   .of_match_table = mt6797_afe_pcm_dt_match,
904 #ifdef CONFIG_PM
905 		   .pm = &mt6797_afe_pm_ops,
906 #endif
907 	},
908 	.probe = mt6797_afe_pcm_dev_probe,
909 	.remove = mt6797_afe_pcm_dev_remove,
910 };
911 
912 module_platform_driver(mt6797_afe_pcm_driver);
913 
914 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 6797");
915 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
916 MODULE_LICENSE("GPL v2");
917