1 /* 2 * mt2701-reg.h -- Mediatek 2701 audio driver reg definition 3 * 4 * Copyright (c) 2016 MediaTek Inc. 5 * Author: Garlic Tseng <garlic.tseng@mediatek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 and 9 * only version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #ifndef _MT2701_REG_H_ 18 #define _MT2701_REG_H_ 19 20 #include <linux/delay.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/pm_runtime.h> 25 #include <sound/soc.h> 26 #include "mt2701-afe-common.h" 27 28 /***************************************************************************** 29 * R E G I S T E R D E F I N I T I O N 30 *****************************************************************************/ 31 #define AUDIO_TOP_CON0 0x0000 32 #define AUDIO_TOP_CON4 0x0010 33 #define AUDIO_TOP_CON5 0x0014 34 #define AFE_DAIBT_CON0 0x001c 35 #define AFE_MRGIF_CON 0x003c 36 #define ASMI_TIMING_CON1 0x0100 37 #define ASMO_TIMING_CON1 0x0104 38 #define PWR1_ASM_CON1 0x0108 39 #define ASYS_TOP_CON 0x0600 40 #define ASYS_I2SIN1_CON 0x0604 41 #define ASYS_I2SIN2_CON 0x0608 42 #define ASYS_I2SIN3_CON 0x060c 43 #define ASYS_I2SIN4_CON 0x0610 44 #define ASYS_I2SIN5_CON 0x0614 45 #define ASYS_I2SO1_CON 0x061C 46 #define ASYS_I2SO2_CON 0x0620 47 #define ASYS_I2SO3_CON 0x0624 48 #define ASYS_I2SO4_CON 0x0628 49 #define ASYS_I2SO5_CON 0x062c 50 #define PWR2_TOP_CON 0x0634 51 #define AFE_CONN0 0x06c0 52 #define AFE_CONN1 0x06c4 53 #define AFE_CONN2 0x06c8 54 #define AFE_CONN3 0x06cc 55 #define AFE_CONN14 0x06f8 56 #define AFE_CONN15 0x06fc 57 #define AFE_CONN16 0x0700 58 #define AFE_CONN17 0x0704 59 #define AFE_CONN18 0x0708 60 #define AFE_CONN19 0x070c 61 #define AFE_CONN20 0x0710 62 #define AFE_CONN21 0x0714 63 #define AFE_CONN22 0x0718 64 #define AFE_CONN23 0x071c 65 #define AFE_CONN24 0x0720 66 #define AFE_CONN41 0x0764 67 #define ASYS_IRQ1_CON 0x0780 68 #define ASYS_IRQ2_CON 0x0784 69 #define ASYS_IRQ3_CON 0x0788 70 #define ASYS_IRQ_CLR 0x07c0 71 #define ASYS_IRQ_STATUS 0x07c4 72 #define PWR2_ASM_CON1 0x1070 73 #define AFE_DAC_CON0 0x1200 74 #define AFE_DAC_CON1 0x1204 75 #define AFE_DAC_CON2 0x1208 76 #define AFE_DAC_CON3 0x120c 77 #define AFE_DAC_CON4 0x1210 78 #define AFE_MEMIF_HD_CON1 0x121c 79 #define AFE_MEMIF_PBUF_SIZE 0x1238 80 #define AFE_MEMIF_HD_CON0 0x123c 81 #define AFE_DL1_BASE 0x1240 82 #define AFE_DL1_CUR 0x1244 83 #define AFE_DL2_BASE 0x1250 84 #define AFE_DL2_CUR 0x1254 85 #define AFE_DL3_BASE 0x1260 86 #define AFE_DL3_CUR 0x1264 87 #define AFE_DL4_BASE 0x1270 88 #define AFE_DL4_CUR 0x1274 89 #define AFE_DL5_BASE 0x1280 90 #define AFE_DL5_CUR 0x1284 91 #define AFE_DLMCH_BASE 0x12a0 92 #define AFE_DLMCH_CUR 0x12a4 93 #define AFE_ARB1_BASE 0x12b0 94 #define AFE_ARB1_CUR 0x12b4 95 #define AFE_VUL_BASE 0x1300 96 #define AFE_VUL_CUR 0x130c 97 #define AFE_UL2_BASE 0x1310 98 #define AFE_UL2_END 0x1318 99 #define AFE_UL2_CUR 0x131c 100 #define AFE_UL3_BASE 0x1320 101 #define AFE_UL3_END 0x1328 102 #define AFE_UL3_CUR 0x132c 103 #define AFE_UL4_BASE 0x1330 104 #define AFE_UL4_END 0x1338 105 #define AFE_UL4_CUR 0x133c 106 #define AFE_UL5_BASE 0x1340 107 #define AFE_UL5_END 0x1348 108 #define AFE_UL5_CUR 0x134c 109 #define AFE_DAI_BASE 0x1370 110 #define AFE_DAI_CUR 0x137c 111 112 /* AUDIO_TOP_CON0 (0x0000) */ 113 #define AUDIO_TOP_CON0_A1SYS_A2SYS_ON (0x3 << 0) 114 #define AUDIO_TOP_CON0_PDN_AFE (0x1 << 2) 115 #define AUDIO_TOP_CON0_PDN_APLL_CK (0x1 << 23) 116 117 /* AUDIO_TOP_CON4 (0x0010) */ 118 #define AUDIO_TOP_CON4_I2SO1_PWN (0x1 << 6) 119 #define AUDIO_TOP_CON4_PDN_A1SYS (0x1 << 21) 120 #define AUDIO_TOP_CON4_PDN_A2SYS (0x1 << 22) 121 #define AUDIO_TOP_CON4_PDN_AFE_CONN (0x1 << 23) 122 #define AUDIO_TOP_CON4_PDN_MRGIF (0x1 << 25) 123 124 /* AFE_DAIBT_CON0 (0x001c) */ 125 #define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0) 126 #define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1) 127 #define AFE_DAIBT_CON0_BT_FUNC_RDY (0x1 << 3) 128 #define AFE_DAIBT_CON0_BT_WIDE_MODE_EN (0x1 << 9) 129 #define AFE_DAIBT_CON0_MRG_USE (0x1 << 12) 130 131 /* PWR1_ASM_CON1 (0x0108) */ 132 #define PWR1_ASM_CON1_INIT_VAL (0x492) 133 134 /* AFE_MRGIF_CON (0x003c) */ 135 #define AFE_MRGIF_CON_MRG_EN (0x1 << 0) 136 #define AFE_MRGIF_CON_MRG_I2S_EN (0x1 << 16) 137 #define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20) 138 #define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20) 139 140 /* ASYS_I2SO1_CON (0x061c) */ 141 #define ASYS_I2SO1_CON_FS (0x1f << 8) 142 #define ASYS_I2SO1_CON_FS_SET(x) ((x) << 8) 143 #define ASYS_I2SO1_CON_MULTI_CH (0x1 << 16) 144 #define ASYS_I2SO1_CON_SIDEGEN (0x1 << 30) 145 #define ASYS_I2SO1_CON_I2S_EN (0x1 << 0) 146 /* 0:EIAJ 1:I2S */ 147 #define ASYS_I2SO1_CON_I2S_MODE (0x1 << 3) 148 #define ASYS_I2SO1_CON_WIDE_MODE (0x1 << 1) 149 #define ASYS_I2SO1_CON_WIDE_MODE_SET(x) ((x) << 1) 150 151 /* PWR2_TOP_CON (0x0634) */ 152 #define PWR2_TOP_CON_INIT_VAL (0xffe1ffff) 153 154 /* ASYS_IRQ_CLR (0x07c0) */ 155 #define ASYS_IRQ_CLR_ALL (0xffffffff) 156 157 /* PWR2_ASM_CON1 (0x1070) */ 158 #define PWR2_ASM_CON1_INIT_VAL (0x492492) 159 160 /* AFE_DAC_CON0 (0x1200) */ 161 #define AFE_DAC_CON0_AFE_ON (0x1 << 0) 162 163 /* AFE_MEMIF_PBUF_SIZE (0x1238) */ 164 #define AFE_MEMIF_PBUF_SIZE_DLM_MASK (0x1 << 29) 165 #define AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE (0x0 << 29) 166 #define AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE (0x1 << 29) 167 #define DLMCH_BIT_WIDTH_MASK (0x1 << 28) 168 #define AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK (0xf << 24) 169 #define AFE_MEMIF_PBUF_SIZE_DLM_CH(x) ((x) << 24) 170 #define AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK (0x3 << 12) 171 #define AFE_MEMIF_PBUF_SIZE_DLM_32BYTES (0x1 << 12) 172 173 /* I2S in/out register bit control */ 174 #define ASYS_I2S_CON_FS (0x1f << 8) 175 #define ASYS_I2S_CON_FS_SET(x) ((x) << 8) 176 #define ASYS_I2S_CON_RESET (0x1 << 30) 177 #define ASYS_I2S_CON_I2S_EN (0x1 << 0) 178 #define ASYS_I2S_CON_I2S_COUPLE_MODE (0x1 << 17) 179 /* 0:EIAJ 1:I2S */ 180 #define ASYS_I2S_CON_I2S_MODE (0x1 << 3) 181 #define ASYS_I2S_CON_WIDE_MODE (0x1 << 1) 182 #define ASYS_I2S_CON_WIDE_MODE_SET(x) ((x) << 1) 183 #define ASYS_I2S_IN_PHASE_FIX (0x1 << 31) 184 185 #define AFE_END_ADDR 0x15e0 186 #endif 187