11f458d53SGarlic Tseng /*
21f458d53SGarlic Tseng  * mt2701-cs42448.c  --  MT2701 CS42448 ALSA SoC machine driver
31f458d53SGarlic Tseng  *
41f458d53SGarlic Tseng  * Copyright (c) 2016 MediaTek Inc.
51f458d53SGarlic Tseng  * Author: Ir Lian <ir.lian@mediatek.com>
61f458d53SGarlic Tseng  *              Garlic Tseng <garlic.tseng@mediatek.com>
71f458d53SGarlic Tseng  *
81f458d53SGarlic Tseng  *
91f458d53SGarlic Tseng  * This program is free software; you can redistribute it and/or modify
101f458d53SGarlic Tseng  * it under the terms of the GNU General Public License version 2 and
111f458d53SGarlic Tseng  * only version 2 as published by the Free Software Foundation.
121f458d53SGarlic Tseng  *
131f458d53SGarlic Tseng  * This program is distributed in the hope that it will be useful,
141f458d53SGarlic Tseng  * but WITHOUT ANY WARRANTY; without even the implied warranty of
151f458d53SGarlic Tseng  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
161f458d53SGarlic Tseng  * GNU General Public License for more details.
171f458d53SGarlic Tseng  */
181f458d53SGarlic Tseng 
191f458d53SGarlic Tseng #include <linux/module.h>
201f458d53SGarlic Tseng #include <sound/soc.h>
211f458d53SGarlic Tseng #include <linux/delay.h>
221f458d53SGarlic Tseng #include <linux/gpio.h>
231f458d53SGarlic Tseng #include <linux/pinctrl/consumer.h>
241f458d53SGarlic Tseng #include <linux/of_gpio.h>
251f458d53SGarlic Tseng 
261f458d53SGarlic Tseng #include "mt2701-afe-common.h"
271f458d53SGarlic Tseng 
281f458d53SGarlic Tseng struct mt2701_cs42448_private {
291f458d53SGarlic Tseng 	int i2s1_in_mux;
301f458d53SGarlic Tseng 	int i2s1_in_mux_gpio_sel_1;
311f458d53SGarlic Tseng 	int i2s1_in_mux_gpio_sel_2;
321f458d53SGarlic Tseng };
331f458d53SGarlic Tseng 
341f458d53SGarlic Tseng static const char * const i2sin_mux_switch_text[] = {
351f458d53SGarlic Tseng 	"ADC_SDOUT2",
361f458d53SGarlic Tseng 	"ADC_SDOUT3",
371f458d53SGarlic Tseng 	"I2S_IN_1",
381f458d53SGarlic Tseng 	"I2S_IN_2",
391f458d53SGarlic Tseng };
401f458d53SGarlic Tseng 
411f458d53SGarlic Tseng static const struct soc_enum i2sin_mux_enum =
421f458d53SGarlic Tseng 	SOC_ENUM_SINGLE_EXT(4, i2sin_mux_switch_text);
431f458d53SGarlic Tseng 
441f458d53SGarlic Tseng static int mt2701_cs42448_i2sin1_mux_get(struct snd_kcontrol *kcontrol,
451f458d53SGarlic Tseng 					 struct snd_ctl_elem_value *ucontrol)
461f458d53SGarlic Tseng {
471f458d53SGarlic Tseng 	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
481f458d53SGarlic Tseng 	struct mt2701_cs42448_private *priv = snd_soc_card_get_drvdata(card);
491f458d53SGarlic Tseng 
501f458d53SGarlic Tseng 	ucontrol->value.integer.value[0] = priv->i2s1_in_mux;
511f458d53SGarlic Tseng 	return 0;
521f458d53SGarlic Tseng }
531f458d53SGarlic Tseng 
541f458d53SGarlic Tseng static int mt2701_cs42448_i2sin1_mux_set(struct snd_kcontrol *kcontrol,
551f458d53SGarlic Tseng 					 struct snd_ctl_elem_value *ucontrol)
561f458d53SGarlic Tseng {
571f458d53SGarlic Tseng 	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
581f458d53SGarlic Tseng 	struct mt2701_cs42448_private *priv = snd_soc_card_get_drvdata(card);
591f458d53SGarlic Tseng 
601f458d53SGarlic Tseng 	if (ucontrol->value.integer.value[0] == priv->i2s1_in_mux)
611f458d53SGarlic Tseng 		return 0;
621f458d53SGarlic Tseng 
631f458d53SGarlic Tseng 	switch (ucontrol->value.integer.value[0]) {
641f458d53SGarlic Tseng 	case 0:
651f458d53SGarlic Tseng 		gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 0);
661f458d53SGarlic Tseng 		gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 0);
671f458d53SGarlic Tseng 		break;
681f458d53SGarlic Tseng 	case 1:
691f458d53SGarlic Tseng 		gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 1);
701f458d53SGarlic Tseng 		gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 0);
711f458d53SGarlic Tseng 		break;
721f458d53SGarlic Tseng 	case 2:
731f458d53SGarlic Tseng 		gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 0);
741f458d53SGarlic Tseng 		gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 1);
751f458d53SGarlic Tseng 		break;
761f458d53SGarlic Tseng 	case 3:
771f458d53SGarlic Tseng 		gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 1);
781f458d53SGarlic Tseng 		gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 1);
791f458d53SGarlic Tseng 		break;
801f458d53SGarlic Tseng 	default:
811f458d53SGarlic Tseng 		dev_warn(card->dev, "%s invalid setting\n", __func__);
821f458d53SGarlic Tseng 	}
831f458d53SGarlic Tseng 
841f458d53SGarlic Tseng 	priv->i2s1_in_mux = ucontrol->value.integer.value[0];
851f458d53SGarlic Tseng 	return 0;
861f458d53SGarlic Tseng }
871f458d53SGarlic Tseng 
881f458d53SGarlic Tseng static const struct snd_soc_dapm_widget
891f458d53SGarlic Tseng 			mt2701_cs42448_asoc_card_dapm_widgets[] = {
901f458d53SGarlic Tseng 	SND_SOC_DAPM_LINE("Line Out Jack", NULL),
911f458d53SGarlic Tseng 	SND_SOC_DAPM_MIC("AMIC", NULL),
921f458d53SGarlic Tseng 	SND_SOC_DAPM_LINE("Tuner In", NULL),
931f458d53SGarlic Tseng 	SND_SOC_DAPM_LINE("Satellite Tuner In", NULL),
941f458d53SGarlic Tseng 	SND_SOC_DAPM_LINE("AUX In", NULL),
951f458d53SGarlic Tseng };
961f458d53SGarlic Tseng 
971f458d53SGarlic Tseng static const struct snd_kcontrol_new mt2701_cs42448_controls[] = {
981f458d53SGarlic Tseng 	SOC_DAPM_PIN_SWITCH("Line Out Jack"),
991f458d53SGarlic Tseng 	SOC_DAPM_PIN_SWITCH("AMIC"),
1001f458d53SGarlic Tseng 	SOC_DAPM_PIN_SWITCH("Tuner In"),
1011f458d53SGarlic Tseng 	SOC_DAPM_PIN_SWITCH("Satellite Tuner In"),
1021f458d53SGarlic Tseng 	SOC_DAPM_PIN_SWITCH("AUX In"),
1031f458d53SGarlic Tseng 	SOC_ENUM_EXT("I2SIN1_MUX_Switch", i2sin_mux_enum,
1041f458d53SGarlic Tseng 		     mt2701_cs42448_i2sin1_mux_get,
1051f458d53SGarlic Tseng 		     mt2701_cs42448_i2sin1_mux_set),
1061f458d53SGarlic Tseng };
1071f458d53SGarlic Tseng 
1081f458d53SGarlic Tseng static const unsigned int mt2701_cs42448_sampling_rates[] = {48000};
1091f458d53SGarlic Tseng 
110b02ee560STakashi Iwai static const struct snd_pcm_hw_constraint_list mt2701_cs42448_constraints_rates = {
1111f458d53SGarlic Tseng 		.count = ARRAY_SIZE(mt2701_cs42448_sampling_rates),
1121f458d53SGarlic Tseng 		.list = mt2701_cs42448_sampling_rates,
1131f458d53SGarlic Tseng 		.mask = 0,
1141f458d53SGarlic Tseng };
1151f458d53SGarlic Tseng 
1161f458d53SGarlic Tseng static int mt2701_cs42448_fe_ops_startup(struct snd_pcm_substream *substream)
1171f458d53SGarlic Tseng {
1181f458d53SGarlic Tseng 	int err;
1191f458d53SGarlic Tseng 
1201f458d53SGarlic Tseng 	err = snd_pcm_hw_constraint_list(substream->runtime, 0,
1211f458d53SGarlic Tseng 					 SNDRV_PCM_HW_PARAM_RATE,
1221f458d53SGarlic Tseng 					 &mt2701_cs42448_constraints_rates);
1231f458d53SGarlic Tseng 	if (err < 0) {
1241f458d53SGarlic Tseng 		dev_err(substream->pcm->card->dev,
1251f458d53SGarlic Tseng 			"%s snd_pcm_hw_constraint_list failed: 0x%x\n",
1261f458d53SGarlic Tseng 			__func__, err);
1271f458d53SGarlic Tseng 		return err;
1281f458d53SGarlic Tseng 	}
1291f458d53SGarlic Tseng 	return 0;
1301f458d53SGarlic Tseng }
1311f458d53SGarlic Tseng 
132424dfbf2SBhumika Goyal static const struct snd_soc_ops mt2701_cs42448_48k_fe_ops = {
1331f458d53SGarlic Tseng 	.startup = mt2701_cs42448_fe_ops_startup,
1341f458d53SGarlic Tseng };
1351f458d53SGarlic Tseng 
1361f458d53SGarlic Tseng static int mt2701_cs42448_be_ops_hw_params(struct snd_pcm_substream *substream,
1371f458d53SGarlic Tseng 					   struct snd_pcm_hw_params *params)
1381f458d53SGarlic Tseng {
1391f458d53SGarlic Tseng 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
1401f458d53SGarlic Tseng 	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
1411f458d53SGarlic Tseng 	struct snd_soc_dai *codec_dai = rtd->codec_dai;
1421f458d53SGarlic Tseng 	unsigned int mclk_rate;
1431f458d53SGarlic Tseng 	unsigned int rate = params_rate(params);
1441f458d53SGarlic Tseng 	unsigned int div_mclk_over_bck = rate > 192000 ? 2 : 4;
1451f458d53SGarlic Tseng 	unsigned int div_bck_over_lrck = 64;
1461f458d53SGarlic Tseng 
1471f458d53SGarlic Tseng 	mclk_rate = rate * div_bck_over_lrck * div_mclk_over_bck;
1481f458d53SGarlic Tseng 
1491f458d53SGarlic Tseng 	/* mt2701 mclk */
1501f458d53SGarlic Tseng 	snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_rate, SND_SOC_CLOCK_OUT);
1511f458d53SGarlic Tseng 
1521f458d53SGarlic Tseng 	/* codec mclk */
1531f458d53SGarlic Tseng 	snd_soc_dai_set_sysclk(codec_dai, 0, mclk_rate, SND_SOC_CLOCK_IN);
1541f458d53SGarlic Tseng 
1551f458d53SGarlic Tseng 	return 0;
1561f458d53SGarlic Tseng }
1571f458d53SGarlic Tseng 
1581f458d53SGarlic Tseng static struct snd_soc_ops mt2701_cs42448_be_ops = {
1591f458d53SGarlic Tseng 	.hw_params = mt2701_cs42448_be_ops_hw_params
1601f458d53SGarlic Tseng };
1611f458d53SGarlic Tseng 
1621f458d53SGarlic Tseng enum {
1631f458d53SGarlic Tseng 	DAI_LINK_FE_MULTI_CH_OUT,
1641f458d53SGarlic Tseng 	DAI_LINK_FE_PCM0_IN,
1651f458d53SGarlic Tseng 	DAI_LINK_FE_PCM1_IN,
1661f458d53SGarlic Tseng 	DAI_LINK_FE_BT_OUT,
1671f458d53SGarlic Tseng 	DAI_LINK_FE_BT_IN,
1681f458d53SGarlic Tseng 	DAI_LINK_BE_I2S0,
1691f458d53SGarlic Tseng 	DAI_LINK_BE_I2S1,
1701f458d53SGarlic Tseng 	DAI_LINK_BE_I2S2,
1711f458d53SGarlic Tseng 	DAI_LINK_BE_I2S3,
1721f458d53SGarlic Tseng 	DAI_LINK_BE_MRG_BT,
1731f458d53SGarlic Tseng };
1741f458d53SGarlic Tseng 
1751f458d53SGarlic Tseng static struct snd_soc_dai_link mt2701_cs42448_dai_links[] = {
1761f458d53SGarlic Tseng 	/* FE */
1771f458d53SGarlic Tseng 	[DAI_LINK_FE_MULTI_CH_OUT] = {
1781f458d53SGarlic Tseng 		.name = "mt2701-cs42448-multi-ch-out",
1791f458d53SGarlic Tseng 		.stream_name = "mt2701-cs42448-multi-ch-out",
1801f458d53SGarlic Tseng 		.cpu_dai_name = "PCM_multi",
1811f458d53SGarlic Tseng 		.codec_name = "snd-soc-dummy",
1821f458d53SGarlic Tseng 		.codec_dai_name = "snd-soc-dummy-dai",
1831f458d53SGarlic Tseng 		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
1841f458d53SGarlic Tseng 			    SND_SOC_DPCM_TRIGGER_POST},
1851f458d53SGarlic Tseng 		.ops = &mt2701_cs42448_48k_fe_ops,
1861f458d53SGarlic Tseng 		.dynamic = 1,
1871f458d53SGarlic Tseng 		.dpcm_playback = 1,
1881f458d53SGarlic Tseng 	},
1891f458d53SGarlic Tseng 	[DAI_LINK_FE_PCM0_IN] = {
1901f458d53SGarlic Tseng 		.name = "mt2701-cs42448-pcm0",
1911f458d53SGarlic Tseng 		.stream_name = "mt2701-cs42448-pcm0-data-UL",
1921f458d53SGarlic Tseng 		.cpu_dai_name = "PCM0",
1931f458d53SGarlic Tseng 		.codec_name = "snd-soc-dummy",
1941f458d53SGarlic Tseng 		.codec_dai_name = "snd-soc-dummy-dai",
1951f458d53SGarlic Tseng 		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
1961f458d53SGarlic Tseng 			    SND_SOC_DPCM_TRIGGER_POST},
1971f458d53SGarlic Tseng 		.ops = &mt2701_cs42448_48k_fe_ops,
1981f458d53SGarlic Tseng 		.dynamic = 1,
1991f458d53SGarlic Tseng 		.dpcm_capture = 1,
2001f458d53SGarlic Tseng 	},
2011f458d53SGarlic Tseng 	[DAI_LINK_FE_PCM1_IN] = {
2021f458d53SGarlic Tseng 		.name = "mt2701-cs42448-pcm1-data-UL",
2031f458d53SGarlic Tseng 		.stream_name = "mt2701-cs42448-pcm1-data-UL",
2041f458d53SGarlic Tseng 		.cpu_dai_name = "PCM1",
2051f458d53SGarlic Tseng 		.codec_name = "snd-soc-dummy",
2061f458d53SGarlic Tseng 		.codec_dai_name = "snd-soc-dummy-dai",
2071f458d53SGarlic Tseng 		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
2081f458d53SGarlic Tseng 			    SND_SOC_DPCM_TRIGGER_POST},
2091f458d53SGarlic Tseng 		.ops = &mt2701_cs42448_48k_fe_ops,
2101f458d53SGarlic Tseng 		.dynamic = 1,
2111f458d53SGarlic Tseng 		.dpcm_capture = 1,
2121f458d53SGarlic Tseng 	},
2131f458d53SGarlic Tseng 	[DAI_LINK_FE_BT_OUT] = {
2141f458d53SGarlic Tseng 		.name = "mt2701-cs42448-pcm-BT-out",
2151f458d53SGarlic Tseng 		.stream_name = "mt2701-cs42448-pcm-BT",
2161f458d53SGarlic Tseng 		.cpu_dai_name = "PCM_BT_DL",
2171f458d53SGarlic Tseng 		.codec_name = "snd-soc-dummy",
2181f458d53SGarlic Tseng 		.codec_dai_name = "snd-soc-dummy-dai",
2191f458d53SGarlic Tseng 		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
2201f458d53SGarlic Tseng 			    SND_SOC_DPCM_TRIGGER_POST},
2211f458d53SGarlic Tseng 		.dynamic = 1,
2221f458d53SGarlic Tseng 		.dpcm_playback = 1,
2231f458d53SGarlic Tseng 	},
2241f458d53SGarlic Tseng 	[DAI_LINK_FE_BT_IN] = {
2251f458d53SGarlic Tseng 		.name = "mt2701-cs42448-pcm-BT-in",
2261f458d53SGarlic Tseng 		.stream_name = "mt2701-cs42448-pcm-BT",
2271f458d53SGarlic Tseng 		.cpu_dai_name = "PCM_BT_UL",
2281f458d53SGarlic Tseng 		.codec_name = "snd-soc-dummy",
2291f458d53SGarlic Tseng 		.codec_dai_name = "snd-soc-dummy-dai",
2301f458d53SGarlic Tseng 		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
2311f458d53SGarlic Tseng 			    SND_SOC_DPCM_TRIGGER_POST},
2321f458d53SGarlic Tseng 		.dynamic = 1,
2331f458d53SGarlic Tseng 		.dpcm_capture = 1,
2341f458d53SGarlic Tseng 	},
2351f458d53SGarlic Tseng 	/* BE */
2361f458d53SGarlic Tseng 	[DAI_LINK_BE_I2S0] = {
2371f458d53SGarlic Tseng 		.name = "mt2701-cs42448-I2S0",
2381f458d53SGarlic Tseng 		.cpu_dai_name = "I2S0",
2391f458d53SGarlic Tseng 		.no_pcm = 1,
2401f458d53SGarlic Tseng 		.codec_dai_name = "cs42448",
2411f458d53SGarlic Tseng 		.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
2421f458d53SGarlic Tseng 			 | SND_SOC_DAIFMT_GATED,
2431f458d53SGarlic Tseng 		.ops = &mt2701_cs42448_be_ops,
2441f458d53SGarlic Tseng 		.dpcm_playback = 1,
2451f458d53SGarlic Tseng 		.dpcm_capture = 1,
2461f458d53SGarlic Tseng 	},
2471f458d53SGarlic Tseng 	[DAI_LINK_BE_I2S1] = {
2481f458d53SGarlic Tseng 		.name = "mt2701-cs42448-I2S1",
2491f458d53SGarlic Tseng 		.cpu_dai_name = "I2S1",
2501f458d53SGarlic Tseng 		.no_pcm = 1,
2511f458d53SGarlic Tseng 		.codec_dai_name = "cs42448",
2521f458d53SGarlic Tseng 		.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
2531f458d53SGarlic Tseng 			 | SND_SOC_DAIFMT_GATED,
2541f458d53SGarlic Tseng 		.ops = &mt2701_cs42448_be_ops,
2551f458d53SGarlic Tseng 		.dpcm_playback = 1,
2561f458d53SGarlic Tseng 		.dpcm_capture = 1,
2571f458d53SGarlic Tseng 	},
2581f458d53SGarlic Tseng 	[DAI_LINK_BE_I2S2] = {
2591f458d53SGarlic Tseng 		.name = "mt2701-cs42448-I2S2",
2601f458d53SGarlic Tseng 		.cpu_dai_name = "I2S2",
2611f458d53SGarlic Tseng 		.no_pcm = 1,
2621f458d53SGarlic Tseng 		.codec_dai_name = "cs42448",
2631f458d53SGarlic Tseng 		.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
2641f458d53SGarlic Tseng 			 | SND_SOC_DAIFMT_GATED,
2651f458d53SGarlic Tseng 		.ops = &mt2701_cs42448_be_ops,
2661f458d53SGarlic Tseng 		.dpcm_playback = 1,
2671f458d53SGarlic Tseng 		.dpcm_capture = 1,
2681f458d53SGarlic Tseng 	},
2691f458d53SGarlic Tseng 	[DAI_LINK_BE_I2S3] = {
2701f458d53SGarlic Tseng 		.name = "mt2701-cs42448-I2S3",
2711f458d53SGarlic Tseng 		.cpu_dai_name = "I2S3",
2721f458d53SGarlic Tseng 		.no_pcm = 1,
2731f458d53SGarlic Tseng 		.codec_dai_name = "cs42448",
2741f458d53SGarlic Tseng 		.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
2751f458d53SGarlic Tseng 			 | SND_SOC_DAIFMT_GATED,
2761f458d53SGarlic Tseng 		.ops = &mt2701_cs42448_be_ops,
2771f458d53SGarlic Tseng 		.dpcm_playback = 1,
2781f458d53SGarlic Tseng 		.dpcm_capture = 1,
2791f458d53SGarlic Tseng 	},
2801f458d53SGarlic Tseng 	[DAI_LINK_BE_MRG_BT] = {
2811f458d53SGarlic Tseng 		.name = "mt2701-cs42448-MRG-BT",
2821f458d53SGarlic Tseng 		.cpu_dai_name = "MRG BT",
2831f458d53SGarlic Tseng 		.no_pcm = 1,
2841f458d53SGarlic Tseng 		.codec_dai_name = "bt-sco-pcm-wb",
2851f458d53SGarlic Tseng 		.dpcm_playback = 1,
2861f458d53SGarlic Tseng 		.dpcm_capture = 1,
2871f458d53SGarlic Tseng 	},
2881f458d53SGarlic Tseng };
2891f458d53SGarlic Tseng 
2901f458d53SGarlic Tseng static struct snd_soc_card mt2701_cs42448_soc_card = {
2911f458d53SGarlic Tseng 	.name = "mt2701-cs42448",
2921f458d53SGarlic Tseng 	.owner = THIS_MODULE,
2931f458d53SGarlic Tseng 	.dai_link = mt2701_cs42448_dai_links,
2941f458d53SGarlic Tseng 	.num_links = ARRAY_SIZE(mt2701_cs42448_dai_links),
2951f458d53SGarlic Tseng 	.controls = mt2701_cs42448_controls,
2961f458d53SGarlic Tseng 	.num_controls = ARRAY_SIZE(mt2701_cs42448_controls),
2971f458d53SGarlic Tseng 	.dapm_widgets = mt2701_cs42448_asoc_card_dapm_widgets,
2981f458d53SGarlic Tseng 	.num_dapm_widgets = ARRAY_SIZE(mt2701_cs42448_asoc_card_dapm_widgets),
2991f458d53SGarlic Tseng };
3001f458d53SGarlic Tseng 
3011f458d53SGarlic Tseng static int mt2701_cs42448_machine_probe(struct platform_device *pdev)
3021f458d53SGarlic Tseng {
3031f458d53SGarlic Tseng 	struct snd_soc_card *card = &mt2701_cs42448_soc_card;
3041f458d53SGarlic Tseng 	int ret;
3051f458d53SGarlic Tseng 	int i;
3061f458d53SGarlic Tseng 	struct device_node *platform_node, *codec_node, *codec_node_bt_mrg;
3071f458d53SGarlic Tseng 	struct mt2701_cs42448_private *priv =
3081f458d53SGarlic Tseng 		devm_kzalloc(&pdev->dev, sizeof(struct mt2701_cs42448_private),
3091f458d53SGarlic Tseng 			     GFP_KERNEL);
3101f458d53SGarlic Tseng 	struct device *dev = &pdev->dev;
3111f458d53SGarlic Tseng 
3121f458d53SGarlic Tseng 	if (!priv)
3131f458d53SGarlic Tseng 		return -ENOMEM;
3141f458d53SGarlic Tseng 
3151f458d53SGarlic Tseng 	platform_node = of_parse_phandle(pdev->dev.of_node,
3161f458d53SGarlic Tseng 					 "mediatek,platform", 0);
3171f458d53SGarlic Tseng 	if (!platform_node) {
3181f458d53SGarlic Tseng 		dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
3191f458d53SGarlic Tseng 		return -EINVAL;
3201f458d53SGarlic Tseng 	}
3211f458d53SGarlic Tseng 	for (i = 0; i < card->num_links; i++) {
3221f458d53SGarlic Tseng 		if (mt2701_cs42448_dai_links[i].platform_name)
3231f458d53SGarlic Tseng 			continue;
3241f458d53SGarlic Tseng 		mt2701_cs42448_dai_links[i].platform_of_node = platform_node;
3251f458d53SGarlic Tseng 	}
3261f458d53SGarlic Tseng 
3271f458d53SGarlic Tseng 	card->dev = dev;
3281f458d53SGarlic Tseng 
3291f458d53SGarlic Tseng 	codec_node = of_parse_phandle(pdev->dev.of_node,
3301f458d53SGarlic Tseng 				      "mediatek,audio-codec", 0);
3311f458d53SGarlic Tseng 	if (!codec_node) {
3321f458d53SGarlic Tseng 		dev_err(&pdev->dev,
3331f458d53SGarlic Tseng 			"Property 'audio-codec' missing or invalid\n");
3341f458d53SGarlic Tseng 		return -EINVAL;
3351f458d53SGarlic Tseng 	}
3361f458d53SGarlic Tseng 	for (i = 0; i < card->num_links; i++) {
3371f458d53SGarlic Tseng 		if (mt2701_cs42448_dai_links[i].codec_name)
3381f458d53SGarlic Tseng 			continue;
3391f458d53SGarlic Tseng 		mt2701_cs42448_dai_links[i].codec_of_node = codec_node;
3401f458d53SGarlic Tseng 	}
3411f458d53SGarlic Tseng 
3421f458d53SGarlic Tseng 	codec_node_bt_mrg = of_parse_phandle(pdev->dev.of_node,
3431f458d53SGarlic Tseng 					     "mediatek,audio-codec-bt-mrg", 0);
3441f458d53SGarlic Tseng 	if (!codec_node_bt_mrg) {
3451f458d53SGarlic Tseng 		dev_err(&pdev->dev,
3461f458d53SGarlic Tseng 			"Property 'audio-codec-bt-mrg' missing or invalid\n");
3471f458d53SGarlic Tseng 		return -EINVAL;
3481f458d53SGarlic Tseng 	}
3491f458d53SGarlic Tseng 	mt2701_cs42448_dai_links[DAI_LINK_BE_MRG_BT].codec_of_node
3501f458d53SGarlic Tseng 							= codec_node_bt_mrg;
3511f458d53SGarlic Tseng 
3521f458d53SGarlic Tseng 	ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
3531f458d53SGarlic Tseng 	if (ret) {
3541f458d53SGarlic Tseng 		dev_err(&pdev->dev, "failed to parse audio-routing: %d\n", ret);
3551f458d53SGarlic Tseng 		return ret;
3561f458d53SGarlic Tseng 	}
3571f458d53SGarlic Tseng 
3581f458d53SGarlic Tseng 	priv->i2s1_in_mux_gpio_sel_1 =
3591f458d53SGarlic Tseng 		of_get_named_gpio(dev->of_node, "i2s1-in-sel-gpio1", 0);
3601f458d53SGarlic Tseng 	if (gpio_is_valid(priv->i2s1_in_mux_gpio_sel_1)) {
3611f458d53SGarlic Tseng 		ret = devm_gpio_request(dev, priv->i2s1_in_mux_gpio_sel_1,
3621f458d53SGarlic Tseng 					"i2s1_in_mux_gpio_sel_1");
3631f458d53SGarlic Tseng 		if (ret)
3641f458d53SGarlic Tseng 			dev_warn(&pdev->dev, "%s devm_gpio_request fail %d\n",
3651f458d53SGarlic Tseng 				 __func__, ret);
3661f458d53SGarlic Tseng 		gpio_direction_output(priv->i2s1_in_mux_gpio_sel_1, 0);
3671f458d53SGarlic Tseng 	}
3681f458d53SGarlic Tseng 
3691f458d53SGarlic Tseng 	priv->i2s1_in_mux_gpio_sel_2 =
3701f458d53SGarlic Tseng 		of_get_named_gpio(dev->of_node, "i2s1-in-sel-gpio2", 0);
3711f458d53SGarlic Tseng 	if (gpio_is_valid(priv->i2s1_in_mux_gpio_sel_2)) {
3721f458d53SGarlic Tseng 		ret = devm_gpio_request(dev, priv->i2s1_in_mux_gpio_sel_2,
3731f458d53SGarlic Tseng 					"i2s1_in_mux_gpio_sel_2");
3741f458d53SGarlic Tseng 		if (ret)
3751f458d53SGarlic Tseng 			dev_warn(&pdev->dev, "%s devm_gpio_request fail2 %d\n",
3761f458d53SGarlic Tseng 				 __func__, ret);
3771f458d53SGarlic Tseng 		gpio_direction_output(priv->i2s1_in_mux_gpio_sel_2, 0);
3781f458d53SGarlic Tseng 	}
3791f458d53SGarlic Tseng 	snd_soc_card_set_drvdata(card, priv);
3801f458d53SGarlic Tseng 
3811f458d53SGarlic Tseng 	ret = devm_snd_soc_register_card(&pdev->dev, card);
3821f458d53SGarlic Tseng 
3831f458d53SGarlic Tseng 	if (ret)
3841f458d53SGarlic Tseng 		dev_err(&pdev->dev, "%s snd_soc_register_card fail %d\n",
3851f458d53SGarlic Tseng 			__func__, ret);
3861f458d53SGarlic Tseng 	return ret;
3871f458d53SGarlic Tseng }
3881f458d53SGarlic Tseng 
3891f458d53SGarlic Tseng #ifdef CONFIG_OF
3901f458d53SGarlic Tseng static const struct of_device_id mt2701_cs42448_machine_dt_match[] = {
3911f458d53SGarlic Tseng 	{.compatible = "mediatek,mt2701-cs42448-machine",},
3921f458d53SGarlic Tseng 	{}
3931f458d53SGarlic Tseng };
3941f458d53SGarlic Tseng #endif
3951f458d53SGarlic Tseng 
3961f458d53SGarlic Tseng static struct platform_driver mt2701_cs42448_machine = {
3971f458d53SGarlic Tseng 	.driver = {
3981f458d53SGarlic Tseng 		.name = "mt2701-cs42448",
3991f458d53SGarlic Tseng 		   #ifdef CONFIG_OF
4001f458d53SGarlic Tseng 		   .of_match_table = mt2701_cs42448_machine_dt_match,
4011f458d53SGarlic Tseng 		   #endif
4021f458d53SGarlic Tseng 	},
4031f458d53SGarlic Tseng 	.probe = mt2701_cs42448_machine_probe,
4041f458d53SGarlic Tseng };
4051f458d53SGarlic Tseng 
4061f458d53SGarlic Tseng module_platform_driver(mt2701_cs42448_machine);
4071f458d53SGarlic Tseng 
4081f458d53SGarlic Tseng /* Module information */
4091f458d53SGarlic Tseng MODULE_DESCRIPTION("MT2701 CS42448 ALSA SoC machine driver");
4101f458d53SGarlic Tseng MODULE_AUTHOR("Ir Lian <ir.lian@mediatek.com>");
4111f458d53SGarlic Tseng MODULE_LICENSE("GPL v2");
4121f458d53SGarlic Tseng MODULE_ALIAS("mt2701 cs42448 soc card");
413