1 /* 2 * Mediatek ALSA SoC AFE platform driver for 2701 3 * 4 * Copyright (c) 2016 MediaTek Inc. 5 * Author: Garlic Tseng <garlic.tseng@mediatek.com> 6 * Ir Lian <ir.lian@mediatek.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 and 10 * only version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/delay.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/pm_runtime.h> 23 #include <sound/soc.h> 24 25 #include "mt2701-afe-common.h" 26 27 #include "mt2701-afe-clock-ctrl.h" 28 #include "../common/mtk-afe-platform-driver.h" 29 #include "../common/mtk-afe-fe-dai.h" 30 31 #define AFE_IRQ_STATUS_BITS 0xff 32 33 static const struct snd_pcm_hardware mt2701_afe_hardware = { 34 .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED 35 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID, 36 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE 37 | SNDRV_PCM_FMTBIT_S32_LE, 38 .period_bytes_min = 1024, 39 .period_bytes_max = 1024 * 256, 40 .periods_min = 4, 41 .periods_max = 1024, 42 .buffer_bytes_max = 1024 * 1024 * 16, 43 .fifo_size = 0, 44 }; 45 46 struct mt2701_afe_rate { 47 unsigned int rate; 48 unsigned int regvalue; 49 }; 50 51 static const struct mt2701_afe_rate mt2701_afe_i2s_rates[] = { 52 { .rate = 8000, .regvalue = 0 }, 53 { .rate = 12000, .regvalue = 1 }, 54 { .rate = 16000, .regvalue = 2 }, 55 { .rate = 24000, .regvalue = 3 }, 56 { .rate = 32000, .regvalue = 4 }, 57 { .rate = 48000, .regvalue = 5 }, 58 { .rate = 96000, .regvalue = 6 }, 59 { .rate = 192000, .regvalue = 7 }, 60 { .rate = 384000, .regvalue = 8 }, 61 { .rate = 7350, .regvalue = 16 }, 62 { .rate = 11025, .regvalue = 17 }, 63 { .rate = 14700, .regvalue = 18 }, 64 { .rate = 22050, .regvalue = 19 }, 65 { .rate = 29400, .regvalue = 20 }, 66 { .rate = 44100, .regvalue = 21 }, 67 { .rate = 88200, .regvalue = 22 }, 68 { .rate = 176400, .regvalue = 23 }, 69 { .rate = 352800, .regvalue = 24 }, 70 }; 71 72 static int mt2701_dai_num_to_i2s(struct mtk_base_afe *afe, int num) 73 { 74 int val = num - MT2701_IO_I2S; 75 76 if (val < 0 || val >= MT2701_I2S_NUM) { 77 dev_err(afe->dev, "%s, num not available, num %d, val %d\n", 78 __func__, num, val); 79 return -EINVAL; 80 } 81 return val; 82 } 83 84 static int mt2701_afe_i2s_fs(unsigned int sample_rate) 85 { 86 int i; 87 88 for (i = 0; i < ARRAY_SIZE(mt2701_afe_i2s_rates); i++) 89 if (mt2701_afe_i2s_rates[i].rate == sample_rate) 90 return mt2701_afe_i2s_rates[i].regvalue; 91 92 return -EINVAL; 93 } 94 95 static int mt2701_afe_i2s_startup(struct snd_pcm_substream *substream, 96 struct snd_soc_dai *dai) 97 { 98 struct snd_soc_pcm_runtime *rtd = substream->private_data; 99 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); 100 struct mt2701_afe_private *afe_priv = afe->platform_priv; 101 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id); 102 int clk_num = MT2701_AUD_AUD_I2S1_MCLK + i2s_num; 103 int ret = 0; 104 105 if (i2s_num < 0) 106 return i2s_num; 107 108 /* enable mclk */ 109 ret = clk_prepare_enable(afe_priv->clocks[clk_num]); 110 if (ret) 111 dev_err(afe->dev, "Failed to enable mclk for I2S: %d\n", 112 i2s_num); 113 114 return ret; 115 } 116 117 static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream, 118 struct snd_soc_dai *dai, 119 int dir_invert) 120 { 121 struct snd_soc_pcm_runtime *rtd = substream->private_data; 122 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); 123 struct mt2701_afe_private *afe_priv = afe->platform_priv; 124 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id); 125 struct mt2701_i2s_path *i2s_path; 126 const struct mt2701_i2s_data *i2s_data; 127 int stream_dir = substream->stream; 128 129 if (i2s_num < 0) 130 return i2s_num; 131 132 i2s_path = &afe_priv->i2s_path[i2s_num]; 133 134 if (dir_invert) { 135 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) 136 stream_dir = SNDRV_PCM_STREAM_CAPTURE; 137 else 138 stream_dir = SNDRV_PCM_STREAM_PLAYBACK; 139 } 140 i2s_data = i2s_path->i2s_data[stream_dir]; 141 142 i2s_path->on[stream_dir]--; 143 if (i2s_path->on[stream_dir] < 0) { 144 dev_warn(afe->dev, "i2s_path->on: %d, dir: %d\n", 145 i2s_path->on[stream_dir], stream_dir); 146 i2s_path->on[stream_dir] = 0; 147 } 148 if (i2s_path->on[stream_dir]) 149 return 0; 150 151 /* disable i2s */ 152 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, 153 ASYS_I2S_CON_I2S_EN, 0); 154 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 155 1 << i2s_data->i2s_pwn_shift, 156 1 << i2s_data->i2s_pwn_shift); 157 return 0; 158 } 159 160 static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream, 161 struct snd_soc_dai *dai) 162 { 163 struct snd_soc_pcm_runtime *rtd = substream->private_data; 164 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); 165 struct mt2701_afe_private *afe_priv = afe->platform_priv; 166 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id); 167 struct mt2701_i2s_path *i2s_path; 168 int clk_num = MT2701_AUD_AUD_I2S1_MCLK + i2s_num; 169 170 if (i2s_num < 0) 171 return; 172 173 i2s_path = &afe_priv->i2s_path[i2s_num]; 174 175 if (i2s_path->occupied[substream->stream]) 176 i2s_path->occupied[substream->stream] = 0; 177 else 178 goto I2S_UNSTART; 179 180 mt2701_afe_i2s_path_shutdown(substream, dai, 0); 181 182 /* need to disable i2s-out path when disable i2s-in */ 183 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 184 mt2701_afe_i2s_path_shutdown(substream, dai, 1); 185 186 I2S_UNSTART: 187 /* disable mclk */ 188 clk_disable_unprepare(afe_priv->clocks[clk_num]); 189 } 190 191 static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream, 192 struct snd_soc_dai *dai, 193 int dir_invert) 194 { 195 struct snd_soc_pcm_runtime *rtd = substream->private_data; 196 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); 197 struct mt2701_afe_private *afe_priv = afe->platform_priv; 198 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id); 199 struct mt2701_i2s_path *i2s_path; 200 const struct mt2701_i2s_data *i2s_data; 201 struct snd_pcm_runtime * const runtime = substream->runtime; 202 int reg, fs, w_len = 1; /* now we support bck 64bits only */ 203 int stream_dir = substream->stream; 204 unsigned int mask = 0, val = 0; 205 206 if (i2s_num < 0) 207 return i2s_num; 208 209 i2s_path = &afe_priv->i2s_path[i2s_num]; 210 211 if (dir_invert) { 212 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) 213 stream_dir = SNDRV_PCM_STREAM_CAPTURE; 214 else 215 stream_dir = SNDRV_PCM_STREAM_PLAYBACK; 216 } 217 i2s_data = i2s_path->i2s_data[stream_dir]; 218 219 /* no need to enable if already done */ 220 i2s_path->on[stream_dir]++; 221 222 if (i2s_path->on[stream_dir] != 1) 223 return 0; 224 225 fs = mt2701_afe_i2s_fs(runtime->rate); 226 227 mask = ASYS_I2S_CON_FS | 228 ASYS_I2S_CON_I2S_COUPLE_MODE | /* 0 */ 229 ASYS_I2S_CON_I2S_MODE | 230 ASYS_I2S_CON_WIDE_MODE; 231 232 val = ASYS_I2S_CON_FS_SET(fs) | 233 ASYS_I2S_CON_I2S_MODE | 234 ASYS_I2S_CON_WIDE_MODE_SET(w_len); 235 236 if (stream_dir == SNDRV_PCM_STREAM_CAPTURE) { 237 mask |= ASYS_I2S_IN_PHASE_FIX; 238 val |= ASYS_I2S_IN_PHASE_FIX; 239 } 240 241 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, mask, val); 242 243 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) 244 reg = ASMO_TIMING_CON1; 245 else 246 reg = ASMI_TIMING_CON1; 247 248 regmap_update_bits(afe->regmap, reg, 249 i2s_data->i2s_asrc_fs_mask 250 << i2s_data->i2s_asrc_fs_shift, 251 fs << i2s_data->i2s_asrc_fs_shift); 252 253 /* enable i2s */ 254 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 255 1 << i2s_data->i2s_pwn_shift, 256 0 << i2s_data->i2s_pwn_shift); 257 258 /* reset i2s hw status before enable */ 259 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, 260 ASYS_I2S_CON_RESET, ASYS_I2S_CON_RESET); 261 udelay(1); 262 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, 263 ASYS_I2S_CON_RESET, 0); 264 udelay(1); 265 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, 266 ASYS_I2S_CON_I2S_EN, ASYS_I2S_CON_I2S_EN); 267 return 0; 268 } 269 270 static int mt2701_afe_i2s_prepare(struct snd_pcm_substream *substream, 271 struct snd_soc_dai *dai) 272 { 273 int clk_domain; 274 struct snd_soc_pcm_runtime *rtd = substream->private_data; 275 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); 276 struct mt2701_afe_private *afe_priv = afe->platform_priv; 277 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id); 278 struct mt2701_i2s_path *i2s_path; 279 int mclk_rate; 280 281 if (i2s_num < 0) 282 return i2s_num; 283 284 i2s_path = &afe_priv->i2s_path[i2s_num]; 285 mclk_rate = i2s_path->mclk_rate; 286 287 if (i2s_path->occupied[substream->stream]) 288 return -EBUSY; 289 i2s_path->occupied[substream->stream] = 1; 290 291 if (MT2701_PLL_DOMAIN_0_RATE % mclk_rate == 0) { 292 clk_domain = 0; 293 } else if (MT2701_PLL_DOMAIN_1_RATE % mclk_rate == 0) { 294 clk_domain = 1; 295 } else { 296 dev_err(dai->dev, "%s() bad mclk rate %d\n", 297 __func__, mclk_rate); 298 return -EINVAL; 299 } 300 mt2701_mclk_configuration(afe, i2s_num, clk_domain, mclk_rate); 301 302 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 303 mt2701_i2s_path_prepare_enable(substream, dai, 0); 304 } else { 305 /* need to enable i2s-out path when enable i2s-in */ 306 /* prepare for another direction "out" */ 307 mt2701_i2s_path_prepare_enable(substream, dai, 1); 308 /* prepare for "in" */ 309 mt2701_i2s_path_prepare_enable(substream, dai, 0); 310 } 311 312 return 0; 313 } 314 315 static int mt2701_afe_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, 316 unsigned int freq, int dir) 317 { 318 struct mtk_base_afe *afe = dev_get_drvdata(dai->dev); 319 struct mt2701_afe_private *afe_priv = afe->platform_priv; 320 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id); 321 322 if (i2s_num < 0) 323 return i2s_num; 324 325 /* mclk */ 326 if (dir == SND_SOC_CLOCK_IN) { 327 dev_warn(dai->dev, 328 "%s() warning: mt2701 doesn't support mclk input\n", 329 __func__); 330 return -EINVAL; 331 } 332 afe_priv->i2s_path[i2s_num].mclk_rate = freq; 333 return 0; 334 } 335 336 static int mt2701_btmrg_startup(struct snd_pcm_substream *substream, 337 struct snd_soc_dai *dai) 338 { 339 struct snd_soc_pcm_runtime *rtd = substream->private_data; 340 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); 341 struct mt2701_afe_private *afe_priv = afe->platform_priv; 342 343 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 344 AUDIO_TOP_CON4_PDN_MRGIF, 0); 345 346 afe_priv->mrg_enable[substream->stream] = 1; 347 return 0; 348 } 349 350 static int mt2701_btmrg_hw_params(struct snd_pcm_substream *substream, 351 struct snd_pcm_hw_params *params, 352 struct snd_soc_dai *dai) 353 { 354 struct snd_soc_pcm_runtime *rtd = substream->private_data; 355 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); 356 int stream_fs; 357 u32 val, msk; 358 359 stream_fs = params_rate(params); 360 361 if ((stream_fs != 8000) && (stream_fs != 16000)) { 362 dev_err(afe->dev, "%s() btmgr not supprt this stream_fs %d\n", 363 __func__, stream_fs); 364 return -EINVAL; 365 } 366 367 regmap_update_bits(afe->regmap, AFE_MRGIF_CON, 368 AFE_MRGIF_CON_I2S_MODE_MASK, 369 AFE_MRGIF_CON_I2S_MODE_32K); 370 371 val = AFE_DAIBT_CON0_BT_FUNC_EN | AFE_DAIBT_CON0_BT_FUNC_RDY 372 | AFE_DAIBT_CON0_MRG_USE; 373 msk = val; 374 375 if (stream_fs == 16000) 376 val |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN; 377 378 msk |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN; 379 380 regmap_update_bits(afe->regmap, AFE_DAIBT_CON0, msk, val); 381 382 regmap_update_bits(afe->regmap, AFE_DAIBT_CON0, 383 AFE_DAIBT_CON0_DAIBT_EN, 384 AFE_DAIBT_CON0_DAIBT_EN); 385 regmap_update_bits(afe->regmap, AFE_MRGIF_CON, 386 AFE_MRGIF_CON_MRG_I2S_EN, 387 AFE_MRGIF_CON_MRG_I2S_EN); 388 regmap_update_bits(afe->regmap, AFE_MRGIF_CON, 389 AFE_MRGIF_CON_MRG_EN, 390 AFE_MRGIF_CON_MRG_EN); 391 return 0; 392 } 393 394 static void mt2701_btmrg_shutdown(struct snd_pcm_substream *substream, 395 struct snd_soc_dai *dai) 396 { 397 struct snd_soc_pcm_runtime *rtd = substream->private_data; 398 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); 399 struct mt2701_afe_private *afe_priv = afe->platform_priv; 400 401 /* if the other direction stream is not occupied */ 402 if (!afe_priv->mrg_enable[!substream->stream]) { 403 regmap_update_bits(afe->regmap, AFE_DAIBT_CON0, 404 AFE_DAIBT_CON0_DAIBT_EN, 0); 405 regmap_update_bits(afe->regmap, AFE_MRGIF_CON, 406 AFE_MRGIF_CON_MRG_EN, 0); 407 regmap_update_bits(afe->regmap, AFE_MRGIF_CON, 408 AFE_MRGIF_CON_MRG_I2S_EN, 0); 409 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 410 AUDIO_TOP_CON4_PDN_MRGIF, 411 AUDIO_TOP_CON4_PDN_MRGIF); 412 } 413 afe_priv->mrg_enable[substream->stream] = 0; 414 } 415 416 static int mt2701_simple_fe_startup(struct snd_pcm_substream *substream, 417 struct snd_soc_dai *dai) 418 { 419 struct snd_soc_pcm_runtime *rtd = substream->private_data; 420 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); 421 int stream_dir = substream->stream; 422 int memif_num = rtd->cpu_dai->id; 423 struct mtk_base_afe_memif *memif_tmp; 424 425 /* can't run single DL & DLM at the same time */ 426 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) { 427 memif_tmp = &afe->memif[MT2701_MEMIF_DLM]; 428 if (memif_tmp->substream) { 429 dev_warn(afe->dev, "%s memif is not available, stream_dir %d, memif_num %d\n", 430 __func__, stream_dir, memif_num); 431 return -EBUSY; 432 } 433 } 434 return mtk_afe_fe_startup(substream, dai); 435 } 436 437 static int mt2701_simple_fe_hw_params(struct snd_pcm_substream *substream, 438 struct snd_pcm_hw_params *params, 439 struct snd_soc_dai *dai) 440 { 441 struct snd_soc_pcm_runtime *rtd = substream->private_data; 442 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); 443 int stream_dir = substream->stream; 444 445 /* single DL use PAIR_INTERLEAVE */ 446 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) { 447 regmap_update_bits(afe->regmap, 448 AFE_MEMIF_PBUF_SIZE, 449 AFE_MEMIF_PBUF_SIZE_DLM_MASK, 450 AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE); 451 } 452 return mtk_afe_fe_hw_params(substream, params, dai); 453 } 454 455 static int mt2701_dlm_fe_startup(struct snd_pcm_substream *substream, 456 struct snd_soc_dai *dai) 457 { 458 struct snd_soc_pcm_runtime *rtd = substream->private_data; 459 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); 460 struct mtk_base_afe_memif *memif_tmp; 461 const struct mtk_base_memif_data *memif_data; 462 int i; 463 464 for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) { 465 memif_tmp = &afe->memif[i]; 466 if (memif_tmp->substream) 467 return -EBUSY; 468 } 469 470 /* enable agent for all signal DL (due to hw design) */ 471 for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) { 472 memif_data = afe->memif[i].data; 473 regmap_update_bits(afe->regmap, 474 memif_data->agent_disable_reg, 475 1 << memif_data->agent_disable_shift, 476 0 << memif_data->agent_disable_shift); 477 } 478 479 return mtk_afe_fe_startup(substream, dai); 480 } 481 482 static void mt2701_dlm_fe_shutdown(struct snd_pcm_substream *substream, 483 struct snd_soc_dai *dai) 484 { 485 struct snd_soc_pcm_runtime *rtd = substream->private_data; 486 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); 487 const struct mtk_base_memif_data *memif_data; 488 int i; 489 490 for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) { 491 memif_data = afe->memif[i].data; 492 regmap_update_bits(afe->regmap, 493 memif_data->agent_disable_reg, 494 1 << memif_data->agent_disable_shift, 495 1 << memif_data->agent_disable_shift); 496 } 497 return mtk_afe_fe_shutdown(substream, dai); 498 } 499 500 static int mt2701_dlm_fe_hw_params(struct snd_pcm_substream *substream, 501 struct snd_pcm_hw_params *params, 502 struct snd_soc_dai *dai) 503 { 504 struct snd_soc_pcm_runtime *rtd = substream->private_data; 505 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); 506 int channels = params_channels(params); 507 508 regmap_update_bits(afe->regmap, 509 AFE_MEMIF_PBUF_SIZE, 510 AFE_MEMIF_PBUF_SIZE_DLM_MASK, 511 AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE); 512 regmap_update_bits(afe->regmap, 513 AFE_MEMIF_PBUF_SIZE, 514 AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK, 515 AFE_MEMIF_PBUF_SIZE_DLM_32BYTES); 516 regmap_update_bits(afe->regmap, 517 AFE_MEMIF_PBUF_SIZE, 518 AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK, 519 AFE_MEMIF_PBUF_SIZE_DLM_CH(channels)); 520 521 return mtk_afe_fe_hw_params(substream, params, dai); 522 } 523 524 static int mt2701_dlm_fe_trigger(struct snd_pcm_substream *substream, 525 int cmd, struct snd_soc_dai *dai) 526 { 527 struct snd_soc_pcm_runtime *rtd = substream->private_data; 528 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); 529 struct mtk_base_afe_memif *memif_tmp = &afe->memif[MT2701_MEMIF_DL1]; 530 531 switch (cmd) { 532 case SNDRV_PCM_TRIGGER_START: 533 case SNDRV_PCM_TRIGGER_RESUME: 534 regmap_update_bits(afe->regmap, memif_tmp->data->enable_reg, 535 1 << memif_tmp->data->enable_shift, 536 1 << memif_tmp->data->enable_shift); 537 mtk_afe_fe_trigger(substream, cmd, dai); 538 return 0; 539 case SNDRV_PCM_TRIGGER_STOP: 540 case SNDRV_PCM_TRIGGER_SUSPEND: 541 mtk_afe_fe_trigger(substream, cmd, dai); 542 regmap_update_bits(afe->regmap, memif_tmp->data->enable_reg, 543 1 << memif_tmp->data->enable_shift, 0); 544 545 return 0; 546 default: 547 return -EINVAL; 548 } 549 } 550 551 static int mt2701_memif_fs(struct snd_pcm_substream *substream, 552 unsigned int rate) 553 { 554 struct snd_soc_pcm_runtime *rtd = substream->private_data; 555 int fs; 556 557 if (rtd->cpu_dai->id != MT2701_MEMIF_ULBT) 558 fs = mt2701_afe_i2s_fs(rate); 559 else 560 fs = (rate == 16000 ? 1 : 0); 561 return fs; 562 } 563 564 static int mt2701_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) 565 { 566 return mt2701_afe_i2s_fs(rate); 567 } 568 569 /* FE DAIs */ 570 static const struct snd_soc_dai_ops mt2701_single_memif_dai_ops = { 571 .startup = mt2701_simple_fe_startup, 572 .shutdown = mtk_afe_fe_shutdown, 573 .hw_params = mt2701_simple_fe_hw_params, 574 .hw_free = mtk_afe_fe_hw_free, 575 .prepare = mtk_afe_fe_prepare, 576 .trigger = mtk_afe_fe_trigger, 577 578 }; 579 580 static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops = { 581 .startup = mt2701_dlm_fe_startup, 582 .shutdown = mt2701_dlm_fe_shutdown, 583 .hw_params = mt2701_dlm_fe_hw_params, 584 .hw_free = mtk_afe_fe_hw_free, 585 .prepare = mtk_afe_fe_prepare, 586 .trigger = mt2701_dlm_fe_trigger, 587 }; 588 589 /* I2S BE DAIs */ 590 static const struct snd_soc_dai_ops mt2701_afe_i2s_ops = { 591 .startup = mt2701_afe_i2s_startup, 592 .shutdown = mt2701_afe_i2s_shutdown, 593 .prepare = mt2701_afe_i2s_prepare, 594 .set_sysclk = mt2701_afe_i2s_set_sysclk, 595 }; 596 597 /* MRG BE DAIs */ 598 static struct snd_soc_dai_ops mt2701_btmrg_ops = { 599 .startup = mt2701_btmrg_startup, 600 .shutdown = mt2701_btmrg_shutdown, 601 .hw_params = mt2701_btmrg_hw_params, 602 }; 603 604 static struct snd_soc_dai_driver mt2701_afe_pcm_dais[] = { 605 /* FE DAIs: memory intefaces to CPU */ 606 { 607 .name = "PCM_multi", 608 .id = MT2701_MEMIF_DLM, 609 .suspend = mtk_afe_dai_suspend, 610 .resume = mtk_afe_dai_resume, 611 .playback = { 612 .stream_name = "DLM", 613 .channels_min = 1, 614 .channels_max = 8, 615 .rates = SNDRV_PCM_RATE_8000_192000, 616 .formats = (SNDRV_PCM_FMTBIT_S16_LE 617 | SNDRV_PCM_FMTBIT_S24_LE 618 | SNDRV_PCM_FMTBIT_S32_LE) 619 620 }, 621 .ops = &mt2701_dlm_memif_dai_ops, 622 }, 623 { 624 .name = "PCM0", 625 .id = MT2701_MEMIF_UL1, 626 .suspend = mtk_afe_dai_suspend, 627 .resume = mtk_afe_dai_resume, 628 .capture = { 629 .stream_name = "UL1", 630 .channels_min = 1, 631 .channels_max = 2, 632 .rates = SNDRV_PCM_RATE_8000_48000, 633 .formats = (SNDRV_PCM_FMTBIT_S16_LE 634 | SNDRV_PCM_FMTBIT_S24_LE 635 | SNDRV_PCM_FMTBIT_S32_LE) 636 }, 637 .ops = &mt2701_single_memif_dai_ops, 638 }, 639 { 640 .name = "PCM1", 641 .id = MT2701_MEMIF_UL2, 642 .suspend = mtk_afe_dai_suspend, 643 .resume = mtk_afe_dai_resume, 644 .capture = { 645 .stream_name = "UL2", 646 .channels_min = 1, 647 .channels_max = 2, 648 .rates = SNDRV_PCM_RATE_8000_192000, 649 .formats = (SNDRV_PCM_FMTBIT_S16_LE 650 | SNDRV_PCM_FMTBIT_S24_LE 651 | SNDRV_PCM_FMTBIT_S32_LE) 652 653 }, 654 .ops = &mt2701_single_memif_dai_ops, 655 }, 656 { 657 .name = "PCM_BT_DL", 658 .id = MT2701_MEMIF_DLBT, 659 .suspend = mtk_afe_dai_suspend, 660 .resume = mtk_afe_dai_resume, 661 .playback = { 662 .stream_name = "DLBT", 663 .channels_min = 1, 664 .channels_max = 1, 665 .rates = (SNDRV_PCM_RATE_8000 666 | SNDRV_PCM_RATE_16000), 667 .formats = SNDRV_PCM_FMTBIT_S16_LE, 668 }, 669 .ops = &mt2701_single_memif_dai_ops, 670 }, 671 { 672 .name = "PCM_BT_UL", 673 .id = MT2701_MEMIF_ULBT, 674 .suspend = mtk_afe_dai_suspend, 675 .resume = mtk_afe_dai_resume, 676 .capture = { 677 .stream_name = "ULBT", 678 .channels_min = 1, 679 .channels_max = 1, 680 .rates = (SNDRV_PCM_RATE_8000 681 | SNDRV_PCM_RATE_16000), 682 .formats = SNDRV_PCM_FMTBIT_S16_LE, 683 }, 684 .ops = &mt2701_single_memif_dai_ops, 685 }, 686 /* BE DAIs */ 687 { 688 .name = "I2S0", 689 .id = MT2701_IO_I2S, 690 .playback = { 691 .stream_name = "I2S0 Playback", 692 .channels_min = 1, 693 .channels_max = 2, 694 .rates = SNDRV_PCM_RATE_8000_192000, 695 .formats = (SNDRV_PCM_FMTBIT_S16_LE 696 | SNDRV_PCM_FMTBIT_S24_LE 697 | SNDRV_PCM_FMTBIT_S32_LE) 698 699 }, 700 .capture = { 701 .stream_name = "I2S0 Capture", 702 .channels_min = 1, 703 .channels_max = 2, 704 .rates = SNDRV_PCM_RATE_8000_192000, 705 .formats = (SNDRV_PCM_FMTBIT_S16_LE 706 | SNDRV_PCM_FMTBIT_S24_LE 707 | SNDRV_PCM_FMTBIT_S32_LE) 708 709 }, 710 .ops = &mt2701_afe_i2s_ops, 711 .symmetric_rates = 1, 712 }, 713 { 714 .name = "I2S1", 715 .id = MT2701_IO_2ND_I2S, 716 .playback = { 717 .stream_name = "I2S1 Playback", 718 .channels_min = 1, 719 .channels_max = 2, 720 .rates = SNDRV_PCM_RATE_8000_192000, 721 .formats = (SNDRV_PCM_FMTBIT_S16_LE 722 | SNDRV_PCM_FMTBIT_S24_LE 723 | SNDRV_PCM_FMTBIT_S32_LE) 724 }, 725 .capture = { 726 .stream_name = "I2S1 Capture", 727 .channels_min = 1, 728 .channels_max = 2, 729 .rates = SNDRV_PCM_RATE_8000_192000, 730 .formats = (SNDRV_PCM_FMTBIT_S16_LE 731 | SNDRV_PCM_FMTBIT_S24_LE 732 | SNDRV_PCM_FMTBIT_S32_LE) 733 }, 734 .ops = &mt2701_afe_i2s_ops, 735 .symmetric_rates = 1, 736 }, 737 { 738 .name = "I2S2", 739 .id = MT2701_IO_3RD_I2S, 740 .playback = { 741 .stream_name = "I2S2 Playback", 742 .channels_min = 1, 743 .channels_max = 2, 744 .rates = SNDRV_PCM_RATE_8000_192000, 745 .formats = (SNDRV_PCM_FMTBIT_S16_LE 746 | SNDRV_PCM_FMTBIT_S24_LE 747 | SNDRV_PCM_FMTBIT_S32_LE) 748 }, 749 .capture = { 750 .stream_name = "I2S2 Capture", 751 .channels_min = 1, 752 .channels_max = 2, 753 .rates = SNDRV_PCM_RATE_8000_192000, 754 .formats = (SNDRV_PCM_FMTBIT_S16_LE 755 | SNDRV_PCM_FMTBIT_S24_LE 756 | SNDRV_PCM_FMTBIT_S32_LE) 757 }, 758 .ops = &mt2701_afe_i2s_ops, 759 .symmetric_rates = 1, 760 }, 761 { 762 .name = "I2S3", 763 .id = MT2701_IO_4TH_I2S, 764 .playback = { 765 .stream_name = "I2S3 Playback", 766 .channels_min = 1, 767 .channels_max = 2, 768 .rates = SNDRV_PCM_RATE_8000_192000, 769 .formats = (SNDRV_PCM_FMTBIT_S16_LE 770 | SNDRV_PCM_FMTBIT_S24_LE 771 | SNDRV_PCM_FMTBIT_S32_LE) 772 }, 773 .capture = { 774 .stream_name = "I2S3 Capture", 775 .channels_min = 1, 776 .channels_max = 2, 777 .rates = SNDRV_PCM_RATE_8000_192000, 778 .formats = (SNDRV_PCM_FMTBIT_S16_LE 779 | SNDRV_PCM_FMTBIT_S24_LE 780 | SNDRV_PCM_FMTBIT_S32_LE) 781 }, 782 .ops = &mt2701_afe_i2s_ops, 783 .symmetric_rates = 1, 784 }, 785 { 786 .name = "MRG BT", 787 .id = MT2701_IO_MRG, 788 .playback = { 789 .stream_name = "BT Playback", 790 .channels_min = 1, 791 .channels_max = 1, 792 .rates = (SNDRV_PCM_RATE_8000 793 | SNDRV_PCM_RATE_16000), 794 .formats = SNDRV_PCM_FMTBIT_S16_LE, 795 }, 796 .capture = { 797 .stream_name = "BT Capture", 798 .channels_min = 1, 799 .channels_max = 1, 800 .rates = (SNDRV_PCM_RATE_8000 801 | SNDRV_PCM_RATE_16000), 802 .formats = SNDRV_PCM_FMTBIT_S16_LE, 803 }, 804 .ops = &mt2701_btmrg_ops, 805 .symmetric_rates = 1, 806 } 807 }; 808 809 static const struct snd_kcontrol_new mt2701_afe_o00_mix[] = { 810 SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN0, 0, 1, 0), 811 }; 812 813 static const struct snd_kcontrol_new mt2701_afe_o01_mix[] = { 814 SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN1, 1, 1, 0), 815 }; 816 817 static const struct snd_kcontrol_new mt2701_afe_o02_mix[] = { 818 SOC_DAPM_SINGLE_AUTODISABLE("I02 Switch", AFE_CONN2, 2, 1, 0), 819 }; 820 821 static const struct snd_kcontrol_new mt2701_afe_o03_mix[] = { 822 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 3, 1, 0), 823 }; 824 825 static const struct snd_kcontrol_new mt2701_afe_o14_mix[] = { 826 SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN14, 26, 1, 0), 827 }; 828 829 static const struct snd_kcontrol_new mt2701_afe_o15_mix[] = { 830 SOC_DAPM_SINGLE_AUTODISABLE("I12 Switch", AFE_CONN15, 12, 1, 0), 831 }; 832 833 static const struct snd_kcontrol_new mt2701_afe_o16_mix[] = { 834 SOC_DAPM_SINGLE_AUTODISABLE("I13 Switch", AFE_CONN16, 13, 1, 0), 835 }; 836 837 static const struct snd_kcontrol_new mt2701_afe_o17_mix[] = { 838 SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN17, 14, 1, 0), 839 }; 840 841 static const struct snd_kcontrol_new mt2701_afe_o18_mix[] = { 842 SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN18, 15, 1, 0), 843 }; 844 845 static const struct snd_kcontrol_new mt2701_afe_o19_mix[] = { 846 SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN19, 16, 1, 0), 847 }; 848 849 static const struct snd_kcontrol_new mt2701_afe_o20_mix[] = { 850 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN20, 17, 1, 0), 851 }; 852 853 static const struct snd_kcontrol_new mt2701_afe_o21_mix[] = { 854 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN21, 18, 1, 0), 855 }; 856 857 static const struct snd_kcontrol_new mt2701_afe_o22_mix[] = { 858 SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN22, 19, 1, 0), 859 }; 860 861 static const struct snd_kcontrol_new mt2701_afe_o23_mix[] = { 862 SOC_DAPM_SINGLE_AUTODISABLE("I20 Switch", AFE_CONN23, 20, 1, 0), 863 }; 864 865 static const struct snd_kcontrol_new mt2701_afe_o24_mix[] = { 866 SOC_DAPM_SINGLE_AUTODISABLE("I21 Switch", AFE_CONN24, 21, 1, 0), 867 }; 868 869 static const struct snd_kcontrol_new mt2701_afe_o31_mix[] = { 870 SOC_DAPM_SINGLE_AUTODISABLE("I35 Switch", AFE_CONN41, 9, 1, 0), 871 }; 872 873 static const struct snd_kcontrol_new mt2701_afe_i02_mix[] = { 874 SOC_DAPM_SINGLE("I2S0 Switch", SND_SOC_NOPM, 0, 1, 0), 875 }; 876 877 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s0[] = { 878 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S0 Out Switch", 879 ASYS_I2SO1_CON, 26, 1, 0), 880 }; 881 882 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s1[] = { 883 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S1 Out Switch", 884 ASYS_I2SO2_CON, 26, 1, 0), 885 }; 886 887 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s2[] = { 888 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S2 Out Switch", 889 PWR2_TOP_CON, 17, 1, 0), 890 }; 891 892 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s3[] = { 893 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S3 Out Switch", 894 PWR2_TOP_CON, 18, 1, 0), 895 }; 896 897 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s4[] = { 898 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S4 Out Switch", 899 PWR2_TOP_CON, 19, 1, 0), 900 }; 901 902 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc0[] = { 903 SOC_DAPM_SINGLE_AUTODISABLE("Asrc0 out Switch", AUDIO_TOP_CON4, 14, 1, 904 1), 905 }; 906 907 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc1[] = { 908 SOC_DAPM_SINGLE_AUTODISABLE("Asrc1 out Switch", AUDIO_TOP_CON4, 15, 1, 909 1), 910 }; 911 912 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc2[] = { 913 SOC_DAPM_SINGLE_AUTODISABLE("Asrc2 out Switch", PWR2_TOP_CON, 6, 1, 914 1), 915 }; 916 917 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc3[] = { 918 SOC_DAPM_SINGLE_AUTODISABLE("Asrc3 out Switch", PWR2_TOP_CON, 7, 1, 919 1), 920 }; 921 922 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc4[] = { 923 SOC_DAPM_SINGLE_AUTODISABLE("Asrc4 out Switch", PWR2_TOP_CON, 8, 1, 924 1), 925 }; 926 927 static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = { 928 /* inter-connections */ 929 SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0), 930 SND_SOC_DAPM_MIXER("I01", SND_SOC_NOPM, 0, 0, NULL, 0), 931 SND_SOC_DAPM_MIXER("I02", SND_SOC_NOPM, 0, 0, mt2701_afe_i02_mix, 932 ARRAY_SIZE(mt2701_afe_i02_mix)), 933 SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0), 934 SND_SOC_DAPM_MIXER("I12", SND_SOC_NOPM, 0, 0, NULL, 0), 935 SND_SOC_DAPM_MIXER("I13", SND_SOC_NOPM, 0, 0, NULL, 0), 936 SND_SOC_DAPM_MIXER("I14", SND_SOC_NOPM, 0, 0, NULL, 0), 937 SND_SOC_DAPM_MIXER("I15", SND_SOC_NOPM, 0, 0, NULL, 0), 938 SND_SOC_DAPM_MIXER("I16", SND_SOC_NOPM, 0, 0, NULL, 0), 939 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0), 940 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0), 941 SND_SOC_DAPM_MIXER("I19", SND_SOC_NOPM, 0, 0, NULL, 0), 942 SND_SOC_DAPM_MIXER("I26", SND_SOC_NOPM, 0, 0, NULL, 0), 943 SND_SOC_DAPM_MIXER("I35", SND_SOC_NOPM, 0, 0, NULL, 0), 944 945 SND_SOC_DAPM_MIXER("O00", SND_SOC_NOPM, 0, 0, mt2701_afe_o00_mix, 946 ARRAY_SIZE(mt2701_afe_o00_mix)), 947 SND_SOC_DAPM_MIXER("O01", SND_SOC_NOPM, 0, 0, mt2701_afe_o01_mix, 948 ARRAY_SIZE(mt2701_afe_o01_mix)), 949 SND_SOC_DAPM_MIXER("O02", SND_SOC_NOPM, 0, 0, mt2701_afe_o02_mix, 950 ARRAY_SIZE(mt2701_afe_o02_mix)), 951 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0, mt2701_afe_o03_mix, 952 ARRAY_SIZE(mt2701_afe_o03_mix)), 953 SND_SOC_DAPM_MIXER("O14", SND_SOC_NOPM, 0, 0, mt2701_afe_o14_mix, 954 ARRAY_SIZE(mt2701_afe_o14_mix)), 955 SND_SOC_DAPM_MIXER("O15", SND_SOC_NOPM, 0, 0, mt2701_afe_o15_mix, 956 ARRAY_SIZE(mt2701_afe_o15_mix)), 957 SND_SOC_DAPM_MIXER("O16", SND_SOC_NOPM, 0, 0, mt2701_afe_o16_mix, 958 ARRAY_SIZE(mt2701_afe_o16_mix)), 959 SND_SOC_DAPM_MIXER("O17", SND_SOC_NOPM, 0, 0, mt2701_afe_o17_mix, 960 ARRAY_SIZE(mt2701_afe_o17_mix)), 961 SND_SOC_DAPM_MIXER("O18", SND_SOC_NOPM, 0, 0, mt2701_afe_o18_mix, 962 ARRAY_SIZE(mt2701_afe_o18_mix)), 963 SND_SOC_DAPM_MIXER("O19", SND_SOC_NOPM, 0, 0, mt2701_afe_o19_mix, 964 ARRAY_SIZE(mt2701_afe_o19_mix)), 965 SND_SOC_DAPM_MIXER("O20", SND_SOC_NOPM, 0, 0, mt2701_afe_o20_mix, 966 ARRAY_SIZE(mt2701_afe_o20_mix)), 967 SND_SOC_DAPM_MIXER("O21", SND_SOC_NOPM, 0, 0, mt2701_afe_o21_mix, 968 ARRAY_SIZE(mt2701_afe_o21_mix)), 969 SND_SOC_DAPM_MIXER("O22", SND_SOC_NOPM, 0, 0, mt2701_afe_o22_mix, 970 ARRAY_SIZE(mt2701_afe_o22_mix)), 971 SND_SOC_DAPM_MIXER("O31", SND_SOC_NOPM, 0, 0, mt2701_afe_o31_mix, 972 ARRAY_SIZE(mt2701_afe_o31_mix)), 973 974 SND_SOC_DAPM_MIXER("I12I13", SND_SOC_NOPM, 0, 0, 975 mt2701_afe_multi_ch_out_i2s0, 976 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s0)), 977 SND_SOC_DAPM_MIXER("I14I15", SND_SOC_NOPM, 0, 0, 978 mt2701_afe_multi_ch_out_i2s1, 979 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s1)), 980 SND_SOC_DAPM_MIXER("I16I17", SND_SOC_NOPM, 0, 0, 981 mt2701_afe_multi_ch_out_i2s2, 982 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s2)), 983 SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM, 0, 0, 984 mt2701_afe_multi_ch_out_i2s3, 985 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3)), 986 987 SND_SOC_DAPM_MIXER("ASRC_O0", SND_SOC_NOPM, 0, 0, 988 mt2701_afe_multi_ch_out_asrc0, 989 ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc0)), 990 SND_SOC_DAPM_MIXER("ASRC_O1", SND_SOC_NOPM, 0, 0, 991 mt2701_afe_multi_ch_out_asrc1, 992 ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc1)), 993 SND_SOC_DAPM_MIXER("ASRC_O2", SND_SOC_NOPM, 0, 0, 994 mt2701_afe_multi_ch_out_asrc2, 995 ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc2)), 996 SND_SOC_DAPM_MIXER("ASRC_O3", SND_SOC_NOPM, 0, 0, 997 mt2701_afe_multi_ch_out_asrc3, 998 ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc3)), 999 }; 1000 1001 static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = { 1002 {"I12", NULL, "DL1"}, 1003 {"I13", NULL, "DL1"}, 1004 {"I35", NULL, "DLBT"}, 1005 1006 {"I2S0 Playback", NULL, "O15"}, 1007 {"I2S0 Playback", NULL, "O16"}, 1008 1009 {"I2S1 Playback", NULL, "O17"}, 1010 {"I2S1 Playback", NULL, "O18"}, 1011 {"I2S2 Playback", NULL, "O19"}, 1012 {"I2S2 Playback", NULL, "O20"}, 1013 {"I2S3 Playback", NULL, "O21"}, 1014 {"I2S3 Playback", NULL, "O22"}, 1015 {"BT Playback", NULL, "O31"}, 1016 1017 {"UL1", NULL, "O00"}, 1018 {"UL1", NULL, "O01"}, 1019 {"UL2", NULL, "O02"}, 1020 {"UL2", NULL, "O03"}, 1021 {"ULBT", NULL, "O14"}, 1022 1023 {"I00", NULL, "I2S0 Capture"}, 1024 {"I01", NULL, "I2S0 Capture"}, 1025 1026 {"I02", NULL, "I2S1 Capture"}, 1027 {"I03", NULL, "I2S1 Capture"}, 1028 /* I02,03 link to UL2, also need to open I2S0 */ 1029 {"I02", "I2S0 Switch", "I2S0 Capture"}, 1030 1031 {"I26", NULL, "BT Capture"}, 1032 1033 {"ASRC_O0", "Asrc0 out Switch", "DLM"}, 1034 {"ASRC_O1", "Asrc1 out Switch", "DLM"}, 1035 {"ASRC_O2", "Asrc2 out Switch", "DLM"}, 1036 {"ASRC_O3", "Asrc3 out Switch", "DLM"}, 1037 1038 {"I12I13", "Multich I2S0 Out Switch", "ASRC_O0"}, 1039 {"I14I15", "Multich I2S1 Out Switch", "ASRC_O1"}, 1040 {"I16I17", "Multich I2S2 Out Switch", "ASRC_O2"}, 1041 {"I18I19", "Multich I2S3 Out Switch", "ASRC_O3"}, 1042 1043 { "I12", NULL, "I12I13" }, 1044 { "I13", NULL, "I12I13" }, 1045 { "I14", NULL, "I14I15" }, 1046 { "I15", NULL, "I14I15" }, 1047 { "I16", NULL, "I16I17" }, 1048 { "I17", NULL, "I16I17" }, 1049 { "I18", NULL, "I18I19" }, 1050 { "I19", NULL, "I18I19" }, 1051 1052 { "O00", "I00 Switch", "I00" }, 1053 { "O01", "I01 Switch", "I01" }, 1054 { "O02", "I02 Switch", "I02" }, 1055 { "O03", "I03 Switch", "I03" }, 1056 { "O14", "I26 Switch", "I26" }, 1057 { "O15", "I12 Switch", "I12" }, 1058 { "O16", "I13 Switch", "I13" }, 1059 { "O17", "I14 Switch", "I14" }, 1060 { "O18", "I15 Switch", "I15" }, 1061 { "O19", "I16 Switch", "I16" }, 1062 { "O20", "I17 Switch", "I17" }, 1063 { "O21", "I18 Switch", "I18" }, 1064 { "O22", "I19 Switch", "I19" }, 1065 { "O31", "I35 Switch", "I35" }, 1066 1067 }; 1068 1069 static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component = { 1070 .name = "mt2701-afe-pcm-dai", 1071 .dapm_widgets = mt2701_afe_pcm_widgets, 1072 .num_dapm_widgets = ARRAY_SIZE(mt2701_afe_pcm_widgets), 1073 .dapm_routes = mt2701_afe_pcm_routes, 1074 .num_dapm_routes = ARRAY_SIZE(mt2701_afe_pcm_routes), 1075 }; 1076 1077 static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = { 1078 { 1079 .name = "DL1", 1080 .id = MT2701_MEMIF_DL1, 1081 .reg_ofs_base = AFE_DL1_BASE, 1082 .reg_ofs_cur = AFE_DL1_CUR, 1083 .fs_reg = AFE_DAC_CON1, 1084 .fs_shift = 0, 1085 .fs_maskbit = 0x1f, 1086 .mono_reg = AFE_DAC_CON3, 1087 .mono_shift = 16, 1088 .enable_reg = AFE_DAC_CON0, 1089 .enable_shift = 1, 1090 .hd_reg = AFE_MEMIF_HD_CON0, 1091 .hd_shift = 0, 1092 .agent_disable_reg = AUDIO_TOP_CON5, 1093 .agent_disable_shift = 6, 1094 .msb_reg = -1, 1095 .msb_shift = -1, 1096 }, 1097 { 1098 .name = "DL2", 1099 .id = MT2701_MEMIF_DL2, 1100 .reg_ofs_base = AFE_DL2_BASE, 1101 .reg_ofs_cur = AFE_DL2_CUR, 1102 .fs_reg = AFE_DAC_CON1, 1103 .fs_shift = 5, 1104 .fs_maskbit = 0x1f, 1105 .mono_reg = AFE_DAC_CON3, 1106 .mono_shift = 17, 1107 .enable_reg = AFE_DAC_CON0, 1108 .enable_shift = 2, 1109 .hd_reg = AFE_MEMIF_HD_CON0, 1110 .hd_shift = 2, 1111 .agent_disable_reg = AUDIO_TOP_CON5, 1112 .agent_disable_shift = 7, 1113 .msb_reg = -1, 1114 .msb_shift = -1, 1115 }, 1116 { 1117 .name = "DL3", 1118 .id = MT2701_MEMIF_DL3, 1119 .reg_ofs_base = AFE_DL3_BASE, 1120 .reg_ofs_cur = AFE_DL3_CUR, 1121 .fs_reg = AFE_DAC_CON1, 1122 .fs_shift = 10, 1123 .fs_maskbit = 0x1f, 1124 .mono_reg = AFE_DAC_CON3, 1125 .mono_shift = 18, 1126 .enable_reg = AFE_DAC_CON0, 1127 .enable_shift = 3, 1128 .hd_reg = AFE_MEMIF_HD_CON0, 1129 .hd_shift = 4, 1130 .agent_disable_reg = AUDIO_TOP_CON5, 1131 .agent_disable_shift = 8, 1132 .msb_reg = -1, 1133 .msb_shift = -1, 1134 }, 1135 { 1136 .name = "DL4", 1137 .id = MT2701_MEMIF_DL4, 1138 .reg_ofs_base = AFE_DL4_BASE, 1139 .reg_ofs_cur = AFE_DL4_CUR, 1140 .fs_reg = AFE_DAC_CON1, 1141 .fs_shift = 15, 1142 .fs_maskbit = 0x1f, 1143 .mono_reg = AFE_DAC_CON3, 1144 .mono_shift = 19, 1145 .enable_reg = AFE_DAC_CON0, 1146 .enable_shift = 4, 1147 .hd_reg = AFE_MEMIF_HD_CON0, 1148 .hd_shift = 6, 1149 .agent_disable_reg = AUDIO_TOP_CON5, 1150 .agent_disable_shift = 9, 1151 .msb_reg = -1, 1152 .msb_shift = -1, 1153 }, 1154 { 1155 .name = "DL5", 1156 .id = MT2701_MEMIF_DL5, 1157 .reg_ofs_base = AFE_DL5_BASE, 1158 .reg_ofs_cur = AFE_DL5_CUR, 1159 .fs_reg = AFE_DAC_CON1, 1160 .fs_shift = 20, 1161 .fs_maskbit = 0x1f, 1162 .mono_reg = AFE_DAC_CON3, 1163 .mono_shift = 20, 1164 .enable_reg = AFE_DAC_CON0, 1165 .enable_shift = 5, 1166 .hd_reg = AFE_MEMIF_HD_CON0, 1167 .hd_shift = 8, 1168 .agent_disable_reg = AUDIO_TOP_CON5, 1169 .agent_disable_shift = 10, 1170 .msb_reg = -1, 1171 .msb_shift = -1, 1172 }, 1173 { 1174 .name = "DLM", 1175 .id = MT2701_MEMIF_DLM, 1176 .reg_ofs_base = AFE_DLMCH_BASE, 1177 .reg_ofs_cur = AFE_DLMCH_CUR, 1178 .fs_reg = AFE_DAC_CON1, 1179 .fs_shift = 0, 1180 .fs_maskbit = 0x1f, 1181 .mono_reg = -1, 1182 .mono_shift = -1, 1183 .enable_reg = AFE_DAC_CON0, 1184 .enable_shift = 7, 1185 .hd_reg = AFE_MEMIF_PBUF_SIZE, 1186 .hd_shift = 28, 1187 .agent_disable_reg = AUDIO_TOP_CON5, 1188 .agent_disable_shift = 12, 1189 .msb_reg = -1, 1190 .msb_shift = -1, 1191 }, 1192 { 1193 .name = "UL1", 1194 .id = MT2701_MEMIF_UL1, 1195 .reg_ofs_base = AFE_VUL_BASE, 1196 .reg_ofs_cur = AFE_VUL_CUR, 1197 .fs_reg = AFE_DAC_CON2, 1198 .fs_shift = 0, 1199 .fs_maskbit = 0x1f, 1200 .mono_reg = AFE_DAC_CON4, 1201 .mono_shift = 0, 1202 .enable_reg = AFE_DAC_CON0, 1203 .enable_shift = 10, 1204 .hd_reg = AFE_MEMIF_HD_CON1, 1205 .hd_shift = 0, 1206 .agent_disable_reg = AUDIO_TOP_CON5, 1207 .agent_disable_shift = 0, 1208 .msb_reg = -1, 1209 .msb_shift = -1, 1210 }, 1211 { 1212 .name = "UL2", 1213 .id = MT2701_MEMIF_UL2, 1214 .reg_ofs_base = AFE_UL2_BASE, 1215 .reg_ofs_cur = AFE_UL2_CUR, 1216 .fs_reg = AFE_DAC_CON2, 1217 .fs_shift = 5, 1218 .fs_maskbit = 0x1f, 1219 .mono_reg = AFE_DAC_CON4, 1220 .mono_shift = 2, 1221 .enable_reg = AFE_DAC_CON0, 1222 .enable_shift = 11, 1223 .hd_reg = AFE_MEMIF_HD_CON1, 1224 .hd_shift = 2, 1225 .agent_disable_reg = AUDIO_TOP_CON5, 1226 .agent_disable_shift = 1, 1227 .msb_reg = -1, 1228 .msb_shift = -1, 1229 }, 1230 { 1231 .name = "UL3", 1232 .id = MT2701_MEMIF_UL3, 1233 .reg_ofs_base = AFE_UL3_BASE, 1234 .reg_ofs_cur = AFE_UL3_CUR, 1235 .fs_reg = AFE_DAC_CON2, 1236 .fs_shift = 10, 1237 .fs_maskbit = 0x1f, 1238 .mono_reg = AFE_DAC_CON4, 1239 .mono_shift = 4, 1240 .enable_reg = AFE_DAC_CON0, 1241 .enable_shift = 12, 1242 .hd_reg = AFE_MEMIF_HD_CON0, 1243 .hd_shift = 0, 1244 .agent_disable_reg = AUDIO_TOP_CON5, 1245 .agent_disable_shift = 2, 1246 .msb_reg = -1, 1247 .msb_shift = -1, 1248 }, 1249 { 1250 .name = "UL4", 1251 .id = MT2701_MEMIF_UL4, 1252 .reg_ofs_base = AFE_UL4_BASE, 1253 .reg_ofs_cur = AFE_UL4_CUR, 1254 .fs_reg = AFE_DAC_CON2, 1255 .fs_shift = 15, 1256 .fs_maskbit = 0x1f, 1257 .mono_reg = AFE_DAC_CON4, 1258 .mono_shift = 6, 1259 .enable_reg = AFE_DAC_CON0, 1260 .enable_shift = 13, 1261 .hd_reg = AFE_MEMIF_HD_CON0, 1262 .hd_shift = 6, 1263 .agent_disable_reg = AUDIO_TOP_CON5, 1264 .agent_disable_shift = 3, 1265 .msb_reg = -1, 1266 .msb_shift = -1, 1267 }, 1268 { 1269 .name = "UL5", 1270 .id = MT2701_MEMIF_UL5, 1271 .reg_ofs_base = AFE_UL5_BASE, 1272 .reg_ofs_cur = AFE_UL5_CUR, 1273 .fs_reg = AFE_DAC_CON2, 1274 .fs_shift = 20, 1275 .mono_reg = AFE_DAC_CON4, 1276 .mono_shift = 8, 1277 .fs_maskbit = 0x1f, 1278 .enable_reg = AFE_DAC_CON0, 1279 .enable_shift = 14, 1280 .hd_reg = AFE_MEMIF_HD_CON0, 1281 .hd_shift = 8, 1282 .agent_disable_reg = AUDIO_TOP_CON5, 1283 .agent_disable_shift = 4, 1284 .msb_reg = -1, 1285 .msb_shift = -1, 1286 }, 1287 { 1288 .name = "DLBT", 1289 .id = MT2701_MEMIF_DLBT, 1290 .reg_ofs_base = AFE_ARB1_BASE, 1291 .reg_ofs_cur = AFE_ARB1_CUR, 1292 .fs_reg = AFE_DAC_CON3, 1293 .fs_shift = 10, 1294 .fs_maskbit = 0x1f, 1295 .mono_reg = AFE_DAC_CON3, 1296 .mono_shift = 22, 1297 .enable_reg = AFE_DAC_CON0, 1298 .enable_shift = 8, 1299 .hd_reg = AFE_MEMIF_HD_CON0, 1300 .hd_shift = 14, 1301 .agent_disable_reg = AUDIO_TOP_CON5, 1302 .agent_disable_shift = 13, 1303 .msb_reg = -1, 1304 .msb_shift = -1, 1305 }, 1306 { 1307 .name = "ULBT", 1308 .id = MT2701_MEMIF_ULBT, 1309 .reg_ofs_base = AFE_DAI_BASE, 1310 .reg_ofs_cur = AFE_DAI_CUR, 1311 .fs_reg = AFE_DAC_CON2, 1312 .fs_shift = 30, 1313 .fs_maskbit = 0x1, 1314 .mono_reg = -1, 1315 .mono_shift = -1, 1316 .enable_reg = AFE_DAC_CON0, 1317 .enable_shift = 17, 1318 .hd_reg = AFE_MEMIF_HD_CON1, 1319 .hd_shift = 20, 1320 .agent_disable_reg = AUDIO_TOP_CON5, 1321 .agent_disable_shift = 16, 1322 .msb_reg = -1, 1323 .msb_shift = -1, 1324 }, 1325 }; 1326 1327 static const struct mtk_base_irq_data irq_data[MT2701_IRQ_ASYS_END] = { 1328 { 1329 .id = MT2701_IRQ_ASYS_IRQ1, 1330 .irq_cnt_reg = ASYS_IRQ1_CON, 1331 .irq_cnt_shift = 0, 1332 .irq_cnt_maskbit = 0xffffff, 1333 .irq_fs_reg = ASYS_IRQ1_CON, 1334 .irq_fs_shift = 24, 1335 .irq_fs_maskbit = 0x1f, 1336 .irq_en_reg = ASYS_IRQ1_CON, 1337 .irq_en_shift = 31, 1338 .irq_clr_reg = ASYS_IRQ_CLR, 1339 .irq_clr_shift = 0, 1340 }, 1341 { 1342 .id = MT2701_IRQ_ASYS_IRQ2, 1343 .irq_cnt_reg = ASYS_IRQ2_CON, 1344 .irq_cnt_shift = 0, 1345 .irq_cnt_maskbit = 0xffffff, 1346 .irq_fs_reg = ASYS_IRQ2_CON, 1347 .irq_fs_shift = 24, 1348 .irq_fs_maskbit = 0x1f, 1349 .irq_en_reg = ASYS_IRQ2_CON, 1350 .irq_en_shift = 31, 1351 .irq_clr_reg = ASYS_IRQ_CLR, 1352 .irq_clr_shift = 1, 1353 }, 1354 { 1355 .id = MT2701_IRQ_ASYS_IRQ3, 1356 .irq_cnt_reg = ASYS_IRQ3_CON, 1357 .irq_cnt_shift = 0, 1358 .irq_cnt_maskbit = 0xffffff, 1359 .irq_fs_reg = ASYS_IRQ3_CON, 1360 .irq_fs_shift = 24, 1361 .irq_fs_maskbit = 0x1f, 1362 .irq_en_reg = ASYS_IRQ3_CON, 1363 .irq_en_shift = 31, 1364 .irq_clr_reg = ASYS_IRQ_CLR, 1365 .irq_clr_shift = 2, 1366 } 1367 }; 1368 1369 static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = { 1370 { 1371 { 1372 .i2s_ctrl_reg = ASYS_I2SO1_CON, 1373 .i2s_pwn_shift = 6, 1374 .i2s_asrc_fs_shift = 0, 1375 .i2s_asrc_fs_mask = 0x1f, 1376 1377 }, 1378 { 1379 .i2s_ctrl_reg = ASYS_I2SIN1_CON, 1380 .i2s_pwn_shift = 0, 1381 .i2s_asrc_fs_shift = 0, 1382 .i2s_asrc_fs_mask = 0x1f, 1383 1384 }, 1385 }, 1386 { 1387 { 1388 .i2s_ctrl_reg = ASYS_I2SO2_CON, 1389 .i2s_pwn_shift = 7, 1390 .i2s_asrc_fs_shift = 5, 1391 .i2s_asrc_fs_mask = 0x1f, 1392 1393 }, 1394 { 1395 .i2s_ctrl_reg = ASYS_I2SIN2_CON, 1396 .i2s_pwn_shift = 1, 1397 .i2s_asrc_fs_shift = 5, 1398 .i2s_asrc_fs_mask = 0x1f, 1399 1400 }, 1401 }, 1402 { 1403 { 1404 .i2s_ctrl_reg = ASYS_I2SO3_CON, 1405 .i2s_pwn_shift = 8, 1406 .i2s_asrc_fs_shift = 10, 1407 .i2s_asrc_fs_mask = 0x1f, 1408 1409 }, 1410 { 1411 .i2s_ctrl_reg = ASYS_I2SIN3_CON, 1412 .i2s_pwn_shift = 2, 1413 .i2s_asrc_fs_shift = 10, 1414 .i2s_asrc_fs_mask = 0x1f, 1415 1416 }, 1417 }, 1418 { 1419 { 1420 .i2s_ctrl_reg = ASYS_I2SO4_CON, 1421 .i2s_pwn_shift = 9, 1422 .i2s_asrc_fs_shift = 15, 1423 .i2s_asrc_fs_mask = 0x1f, 1424 1425 }, 1426 { 1427 .i2s_ctrl_reg = ASYS_I2SIN4_CON, 1428 .i2s_pwn_shift = 3, 1429 .i2s_asrc_fs_shift = 15, 1430 .i2s_asrc_fs_mask = 0x1f, 1431 1432 }, 1433 }, 1434 }; 1435 1436 static const struct regmap_config mt2701_afe_regmap_config = { 1437 .reg_bits = 32, 1438 .reg_stride = 4, 1439 .val_bits = 32, 1440 .max_register = AFE_END_ADDR, 1441 .cache_type = REGCACHE_NONE, 1442 }; 1443 1444 static irqreturn_t mt2701_asys_isr(int irq_id, void *dev) 1445 { 1446 int id; 1447 struct mtk_base_afe *afe = dev; 1448 struct mtk_base_afe_memif *memif; 1449 struct mtk_base_afe_irq *irq; 1450 u32 status; 1451 1452 regmap_read(afe->regmap, ASYS_IRQ_STATUS, &status); 1453 regmap_write(afe->regmap, ASYS_IRQ_CLR, status); 1454 1455 for (id = 0; id < MT2701_MEMIF_NUM; ++id) { 1456 memif = &afe->memif[id]; 1457 if (memif->irq_usage < 0) 1458 continue; 1459 irq = &afe->irqs[memif->irq_usage]; 1460 if (status & 1 << (irq->irq_data->irq_clr_shift)) 1461 snd_pcm_period_elapsed(memif->substream); 1462 } 1463 return IRQ_HANDLED; 1464 } 1465 1466 static int mt2701_afe_runtime_suspend(struct device *dev) 1467 { 1468 struct mtk_base_afe *afe = dev_get_drvdata(dev); 1469 1470 mt2701_afe_disable_clock(afe); 1471 return 0; 1472 } 1473 1474 static int mt2701_afe_runtime_resume(struct device *dev) 1475 { 1476 struct mtk_base_afe *afe = dev_get_drvdata(dev); 1477 1478 return mt2701_afe_enable_clock(afe); 1479 } 1480 1481 static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev) 1482 { 1483 int ret, i; 1484 unsigned int irq_id; 1485 struct mtk_base_afe *afe; 1486 struct mt2701_afe_private *afe_priv; 1487 struct resource *res; 1488 struct device *dev; 1489 1490 ret = 0; 1491 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); 1492 if (!afe) 1493 return -ENOMEM; 1494 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv), 1495 GFP_KERNEL); 1496 if (!afe->platform_priv) 1497 return -ENOMEM; 1498 afe_priv = afe->platform_priv; 1499 1500 afe->dev = &pdev->dev; 1501 dev = afe->dev; 1502 1503 irq_id = platform_get_irq(pdev, 0); 1504 if (!irq_id) { 1505 dev_err(dev, "%s no irq found\n", dev->of_node->name); 1506 return -ENXIO; 1507 } 1508 ret = devm_request_irq(dev, irq_id, mt2701_asys_isr, 1509 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe); 1510 if (ret) { 1511 dev_err(dev, "could not request_irq for asys-isr\n"); 1512 return ret; 1513 } 1514 1515 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1516 1517 afe->base_addr = devm_ioremap_resource(&pdev->dev, res); 1518 1519 if (IS_ERR(afe->base_addr)) 1520 return PTR_ERR(afe->base_addr); 1521 1522 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr, 1523 &mt2701_afe_regmap_config); 1524 if (IS_ERR(afe->regmap)) 1525 return PTR_ERR(afe->regmap); 1526 1527 mutex_init(&afe->irq_alloc_lock); 1528 1529 /* memif initialize */ 1530 afe->memif_size = MT2701_MEMIF_NUM; 1531 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), 1532 GFP_KERNEL); 1533 1534 if (!afe->memif) 1535 return -ENOMEM; 1536 1537 for (i = 0; i < afe->memif_size; i++) { 1538 afe->memif[i].data = &memif_data[i]; 1539 afe->memif[i].irq_usage = -1; 1540 } 1541 1542 /* irq initialize */ 1543 afe->irqs_size = MT2701_IRQ_ASYS_END; 1544 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), 1545 GFP_KERNEL); 1546 1547 if (!afe->irqs) 1548 return -ENOMEM; 1549 1550 for (i = 0; i < afe->irqs_size; i++) 1551 afe->irqs[i].irq_data = &irq_data[i]; 1552 1553 /* I2S initialize */ 1554 for (i = 0; i < MT2701_I2S_NUM; i++) { 1555 afe_priv->i2s_path[i].i2s_data[I2S_OUT] 1556 = &mt2701_i2s_data[i][I2S_OUT]; 1557 afe_priv->i2s_path[i].i2s_data[I2S_IN] 1558 = &mt2701_i2s_data[i][I2S_IN]; 1559 } 1560 1561 afe->mtk_afe_hardware = &mt2701_afe_hardware; 1562 afe->memif_fs = mt2701_memif_fs; 1563 afe->irq_fs = mt2701_irq_fs; 1564 1565 afe->reg_back_up_list = mt2701_afe_backup_list; 1566 afe->reg_back_up_list_num = ARRAY_SIZE(mt2701_afe_backup_list); 1567 afe->runtime_resume = mt2701_afe_runtime_resume; 1568 afe->runtime_suspend = mt2701_afe_runtime_suspend; 1569 1570 /* initial audio related clock */ 1571 ret = mt2701_init_clock(afe); 1572 if (ret) { 1573 dev_err(dev, "init clock error\n"); 1574 return ret; 1575 } 1576 1577 platform_set_drvdata(pdev, afe); 1578 pm_runtime_enable(&pdev->dev); 1579 if (!pm_runtime_enabled(&pdev->dev)) 1580 goto err_pm_disable; 1581 1582 ret = snd_soc_register_platform(&pdev->dev, &mtk_afe_pcm_platform); 1583 if (ret) { 1584 dev_warn(dev, "err_platform\n"); 1585 goto err_platform; 1586 } 1587 1588 ret = snd_soc_register_component(&pdev->dev, 1589 &mt2701_afe_pcm_dai_component, 1590 mt2701_afe_pcm_dais, 1591 ARRAY_SIZE(mt2701_afe_pcm_dais)); 1592 if (ret) { 1593 dev_warn(dev, "err_dai_component\n"); 1594 goto err_dai_component; 1595 } 1596 1597 mt2701_afe_runtime_resume(&pdev->dev); 1598 1599 return 0; 1600 1601 err_dai_component: 1602 snd_soc_unregister_component(&pdev->dev); 1603 1604 err_platform: 1605 snd_soc_unregister_platform(&pdev->dev); 1606 1607 err_pm_disable: 1608 pm_runtime_disable(&pdev->dev); 1609 1610 return ret; 1611 } 1612 1613 static int mt2701_afe_pcm_dev_remove(struct platform_device *pdev) 1614 { 1615 struct mtk_base_afe *afe = platform_get_drvdata(pdev); 1616 1617 pm_runtime_disable(&pdev->dev); 1618 if (!pm_runtime_status_suspended(&pdev->dev)) 1619 mt2701_afe_runtime_suspend(&pdev->dev); 1620 1621 snd_soc_unregister_component(&pdev->dev); 1622 snd_soc_unregister_platform(&pdev->dev); 1623 /* disable afe clock */ 1624 mt2701_afe_disable_clock(afe); 1625 return 0; 1626 } 1627 1628 static const struct of_device_id mt2701_afe_pcm_dt_match[] = { 1629 { .compatible = "mediatek,mt2701-audio", }, 1630 {}, 1631 }; 1632 MODULE_DEVICE_TABLE(of, mt2701_afe_pcm_dt_match); 1633 1634 static const struct dev_pm_ops mt2701_afe_pm_ops = { 1635 SET_RUNTIME_PM_OPS(mt2701_afe_runtime_suspend, 1636 mt2701_afe_runtime_resume, NULL) 1637 }; 1638 1639 static struct platform_driver mt2701_afe_pcm_driver = { 1640 .driver = { 1641 .name = "mt2701-audio", 1642 .of_match_table = mt2701_afe_pcm_dt_match, 1643 #ifdef CONFIG_PM 1644 .pm = &mt2701_afe_pm_ops, 1645 #endif 1646 }, 1647 .probe = mt2701_afe_pcm_dev_probe, 1648 .remove = mt2701_afe_pcm_dev_remove, 1649 }; 1650 1651 module_platform_driver(mt2701_afe_pcm_driver); 1652 1653 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701"); 1654 MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>"); 1655 MODULE_LICENSE("GPL v2"); 1656 1657