1 /* 2 * mt2701-afe-common.h -- Mediatek 2701 audio driver definitions 3 * 4 * Copyright (c) 2016 MediaTek Inc. 5 * Author: Garlic Tseng <garlic.tseng@mediatek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 and 9 * only version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #ifndef _MT_2701_AFE_COMMON_H_ 18 #define _MT_2701_AFE_COMMON_H_ 19 20 #include <sound/soc.h> 21 #include <linux/clk.h> 22 #include <linux/regmap.h> 23 #include "mt2701-reg.h" 24 #include "../common/mtk-base-afe.h" 25 26 #define MT2701_STREAM_DIR_NUM (SNDRV_PCM_STREAM_LAST + 1) 27 #define MT2701_PLL_DOMAIN_0_RATE 98304000 28 #define MT2701_PLL_DOMAIN_1_RATE 90316800 29 #define MT2701_I2S_NUM 4 30 31 enum { 32 MT2701_MEMIF_DL1, 33 MT2701_MEMIF_DL2, 34 MT2701_MEMIF_DL3, 35 MT2701_MEMIF_DL4, 36 MT2701_MEMIF_DL5, 37 MT2701_MEMIF_DL_SINGLE_NUM, 38 MT2701_MEMIF_DLM = MT2701_MEMIF_DL_SINGLE_NUM, 39 MT2701_MEMIF_UL1, 40 MT2701_MEMIF_UL2, 41 MT2701_MEMIF_UL3, 42 MT2701_MEMIF_UL4, 43 MT2701_MEMIF_UL5, 44 MT2701_MEMIF_DLBT, 45 MT2701_MEMIF_ULBT, 46 MT2701_MEMIF_NUM, 47 MT2701_IO_I2S = MT2701_MEMIF_NUM, 48 MT2701_IO_2ND_I2S, 49 MT2701_IO_3RD_I2S, 50 MT2701_IO_4TH_I2S, 51 MT2701_IO_5TH_I2S, 52 MT2701_IO_6TH_I2S, 53 MT2701_IO_MRG, 54 }; 55 56 enum { 57 MT2701_IRQ_ASYS_IRQ1, 58 MT2701_IRQ_ASYS_IRQ2, 59 MT2701_IRQ_ASYS_IRQ3, 60 MT2701_IRQ_ASYS_END, 61 }; 62 63 enum audio_base_clock { 64 MT2701_INFRA_SYS_AUDIO, 65 MT2701_TOP_AUD_MCLK_SRC0, 66 MT2701_TOP_AUD_MCLK_SRC1, 67 MT2701_TOP_AUD_A1SYS, 68 MT2701_TOP_AUD_A2SYS, 69 MT2701_AUDSYS_AFE, 70 MT2701_AUDSYS_AFE_CONN, 71 MT2701_AUDSYS_A1SYS, 72 MT2701_AUDSYS_A2SYS, 73 MT2701_BASE_CLK_NUM, 74 }; 75 76 static const unsigned int mt2701_afe_backup_list[] = { 77 AUDIO_TOP_CON0, 78 AUDIO_TOP_CON4, 79 AUDIO_TOP_CON5, 80 ASYS_TOP_CON, 81 AFE_CONN0, 82 AFE_CONN1, 83 AFE_CONN2, 84 AFE_CONN3, 85 AFE_CONN15, 86 AFE_CONN16, 87 AFE_CONN17, 88 AFE_CONN18, 89 AFE_CONN19, 90 AFE_CONN20, 91 AFE_CONN21, 92 AFE_CONN22, 93 AFE_DAC_CON0, 94 AFE_MEMIF_PBUF_SIZE, 95 }; 96 97 struct mt2701_i2s_data { 98 int i2s_ctrl_reg; 99 int i2s_asrc_fs_shift; 100 int i2s_asrc_fs_mask; 101 }; 102 103 enum mt2701_i2s_dir { 104 I2S_OUT, 105 I2S_IN, 106 I2S_DIR_NUM, 107 }; 108 109 struct mt2701_i2s_path { 110 int dai_id; 111 int mclk_rate; 112 int on[I2S_DIR_NUM]; 113 int occupied[I2S_DIR_NUM]; 114 const struct mt2701_i2s_data *i2s_data[I2S_DIR_NUM]; 115 struct clk *hop_ck[I2S_DIR_NUM]; 116 struct clk *sel_ck; 117 struct clk *div_ck; 118 struct clk *mclk_ck; 119 struct clk *asrco_ck; 120 }; 121 122 struct mt2701_afe_private { 123 struct mt2701_i2s_path i2s_path[MT2701_I2S_NUM]; 124 struct clk *base_ck[MT2701_BASE_CLK_NUM]; 125 struct clk *mrgif_ck; 126 bool mrg_enable[MT2701_STREAM_DIR_NUM]; 127 }; 128 129 #endif 130