1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * mt2701-afe-common.h  --  Mediatek 2701 audio driver definitions
4  *
5  * Copyright (c) 2016 MediaTek Inc.
6  * Author: Garlic Tseng <garlic.tseng@mediatek.com>
7  */
8 
9 #ifndef _MT_2701_AFE_COMMON_H_
10 #define _MT_2701_AFE_COMMON_H_
11 
12 #include <sound/soc.h>
13 #include <linux/clk.h>
14 #include <linux/regmap.h>
15 #include "mt2701-reg.h"
16 #include "../common/mtk-base-afe.h"
17 
18 #define MT2701_PLL_DOMAIN_0_RATE	98304000
19 #define MT2701_PLL_DOMAIN_1_RATE	90316800
20 
21 enum {
22 	MT2701_MEMIF_DL1,
23 	MT2701_MEMIF_DL2,
24 	MT2701_MEMIF_DL3,
25 	MT2701_MEMIF_DL4,
26 	MT2701_MEMIF_DL5,
27 	MT2701_MEMIF_DL_SINGLE_NUM,
28 	MT2701_MEMIF_DLM = MT2701_MEMIF_DL_SINGLE_NUM,
29 	MT2701_MEMIF_UL1,
30 	MT2701_MEMIF_UL2,
31 	MT2701_MEMIF_UL3,
32 	MT2701_MEMIF_UL4,
33 	MT2701_MEMIF_UL5,
34 	MT2701_MEMIF_DLBT,
35 	MT2701_MEMIF_ULBT,
36 	MT2701_MEMIF_NUM,
37 	MT2701_IO_I2S = MT2701_MEMIF_NUM,
38 	MT2701_IO_2ND_I2S,
39 	MT2701_IO_3RD_I2S,
40 	MT2701_IO_4TH_I2S,
41 	MT2701_IO_5TH_I2S,
42 	MT2701_IO_6TH_I2S,
43 	MT2701_IO_MRG,
44 };
45 
46 enum {
47 	MT2701_IRQ_ASYS_IRQ1,
48 	MT2701_IRQ_ASYS_IRQ2,
49 	MT2701_IRQ_ASYS_IRQ3,
50 	MT2701_IRQ_ASYS_END,
51 };
52 
53 enum audio_base_clock {
54 	MT2701_INFRA_SYS_AUDIO,
55 	MT2701_TOP_AUD_MCLK_SRC0,
56 	MT2701_TOP_AUD_MCLK_SRC1,
57 	MT2701_TOP_AUD_A1SYS,
58 	MT2701_TOP_AUD_A2SYS,
59 	MT2701_AUDSYS_AFE,
60 	MT2701_AUDSYS_AFE_CONN,
61 	MT2701_AUDSYS_A1SYS,
62 	MT2701_AUDSYS_A2SYS,
63 	MT2701_BASE_CLK_NUM,
64 };
65 
66 static const unsigned int mt2701_afe_backup_list[] = {
67 	AUDIO_TOP_CON0,
68 	AUDIO_TOP_CON4,
69 	AUDIO_TOP_CON5,
70 	ASYS_TOP_CON,
71 	AFE_CONN0,
72 	AFE_CONN1,
73 	AFE_CONN2,
74 	AFE_CONN3,
75 	AFE_CONN15,
76 	AFE_CONN16,
77 	AFE_CONN17,
78 	AFE_CONN18,
79 	AFE_CONN19,
80 	AFE_CONN20,
81 	AFE_CONN21,
82 	AFE_CONN22,
83 	AFE_DAC_CON0,
84 	AFE_MEMIF_PBUF_SIZE,
85 };
86 
87 struct mt2701_i2s_data {
88 	int i2s_ctrl_reg;
89 	int i2s_asrc_fs_shift;
90 	int i2s_asrc_fs_mask;
91 };
92 
93 struct mt2701_i2s_path {
94 	int mclk_rate;
95 	int on[MTK_STREAM_NUM];
96 	int occupied[MTK_STREAM_NUM];
97 	const struct mt2701_i2s_data *i2s_data[MTK_STREAM_NUM];
98 	struct clk *hop_ck[MTK_STREAM_NUM];
99 	struct clk *sel_ck;
100 	struct clk *div_ck;
101 	struct clk *mclk_ck;
102 	struct clk *asrco_ck;
103 };
104 
105 struct mt2701_soc_variants {
106 	bool has_one_heart_mode;
107 	int i2s_num;
108 };
109 
110 struct mt2701_afe_private {
111 	struct mt2701_i2s_path *i2s_path;
112 	struct clk *base_ck[MT2701_BASE_CLK_NUM];
113 	struct clk *mrgif_ck;
114 	bool mrg_enable[MTK_STREAM_NUM];
115 
116 	const struct mt2701_soc_variants *soc;
117 };
118 
119 #endif
120