1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * mtk-afe-fe-dais.c  --  Mediatek afe fe dai operator
4  *
5  * Copyright (c) 2016 MediaTek Inc.
6  * Author: Garlic Tseng <garlic.tseng@mediatek.com>
7  */
8 
9 #include <linux/io.h>
10 #include <linux/module.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/regmap.h>
13 #include <sound/soc.h>
14 #include "mtk-afe-platform-driver.h"
15 #include <sound/pcm_params.h>
16 #include "mtk-afe-fe-dai.h"
17 #include "mtk-base-afe.h"
18 
19 #define AFE_BASE_END_OFFSET 8
20 
21 static int mtk_regmap_update_bits(struct regmap *map, int reg,
22 			   unsigned int mask,
23 			   unsigned int val, int shift)
24 {
25 	if (reg < 0 || WARN_ON_ONCE(shift < 0))
26 		return 0;
27 	return regmap_update_bits(map, reg, mask << shift, val << shift);
28 }
29 
30 static int mtk_regmap_write(struct regmap *map, int reg, unsigned int val)
31 {
32 	if (reg < 0)
33 		return 0;
34 	return regmap_write(map, reg, val);
35 }
36 
37 int mtk_afe_fe_startup(struct snd_pcm_substream *substream,
38 		       struct snd_soc_dai *dai)
39 {
40 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
41 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
42 	struct snd_pcm_runtime *runtime = substream->runtime;
43 	int memif_num = rtd->cpu_dai->id;
44 	struct mtk_base_afe_memif *memif = &afe->memif[memif_num];
45 	const struct snd_pcm_hardware *mtk_afe_hardware = afe->mtk_afe_hardware;
46 	int ret;
47 
48 	memif->substream = substream;
49 
50 	snd_pcm_hw_constraint_step(substream->runtime, 0,
51 				   SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 16);
52 	/* enable agent */
53 	mtk_regmap_update_bits(afe->regmap, memif->data->agent_disable_reg,
54 			       1, 0, memif->data->agent_disable_shift);
55 
56 	snd_soc_set_runtime_hwparams(substream, mtk_afe_hardware);
57 
58 	/*
59 	 * Capture cannot use ping-pong buffer since hw_ptr at IRQ may be
60 	 * smaller than period_size due to AFE's internal buffer.
61 	 * This easily leads to overrun when avail_min is period_size.
62 	 * One more period can hold the possible unread buffer.
63 	 */
64 	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
65 		int periods_max = mtk_afe_hardware->periods_max;
66 
67 		ret = snd_pcm_hw_constraint_minmax(runtime,
68 						   SNDRV_PCM_HW_PARAM_PERIODS,
69 						   3, periods_max);
70 		if (ret < 0) {
71 			dev_err(afe->dev, "hw_constraint_minmax failed\n");
72 			return ret;
73 		}
74 	}
75 
76 	ret = snd_pcm_hw_constraint_integer(runtime,
77 					    SNDRV_PCM_HW_PARAM_PERIODS);
78 	if (ret < 0)
79 		dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
80 
81 	/* dynamic allocate irq to memif */
82 	if (memif->irq_usage < 0) {
83 		int irq_id = mtk_dynamic_irq_acquire(afe);
84 
85 		if (irq_id != afe->irqs_size) {
86 			/* link */
87 			memif->irq_usage = irq_id;
88 		} else {
89 			dev_err(afe->dev, "%s() error: no more asys irq\n",
90 				__func__);
91 			ret = -EBUSY;
92 		}
93 	}
94 	return ret;
95 }
96 EXPORT_SYMBOL_GPL(mtk_afe_fe_startup);
97 
98 void mtk_afe_fe_shutdown(struct snd_pcm_substream *substream,
99 			 struct snd_soc_dai *dai)
100 {
101 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
102 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
103 	struct mtk_base_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
104 	int irq_id;
105 
106 	irq_id = memif->irq_usage;
107 
108 	mtk_regmap_update_bits(afe->regmap, memif->data->agent_disable_reg,
109 			       1, 1, memif->data->agent_disable_shift);
110 
111 	if (!memif->const_irq) {
112 		mtk_dynamic_irq_release(afe, irq_id);
113 		memif->irq_usage = -1;
114 		memif->substream = NULL;
115 	}
116 }
117 EXPORT_SYMBOL_GPL(mtk_afe_fe_shutdown);
118 
119 int mtk_afe_fe_hw_params(struct snd_pcm_substream *substream,
120 			 struct snd_pcm_hw_params *params,
121 			 struct snd_soc_dai *dai)
122 {
123 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
124 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
125 	int id = rtd->cpu_dai->id;
126 	struct mtk_base_afe_memif *memif = &afe->memif[id];
127 	int ret;
128 	unsigned int channels = params_channels(params);
129 	unsigned int rate = params_rate(params);
130 	snd_pcm_format_t format = params_format(params);
131 
132 	if (afe->request_dram_resource)
133 		afe->request_dram_resource(afe->dev);
134 
135 	dev_dbg(afe->dev, "%s(), %s, ch %d, rate %d, fmt %d, dma_addr %pad, dma_area %p, dma_bytes 0x%zx\n",
136 		__func__, memif->data->name,
137 		channels, rate, format,
138 		&substream->runtime->dma_addr,
139 		substream->runtime->dma_area,
140 		substream->runtime->dma_bytes);
141 
142 	memset_io(substream->runtime->dma_area, 0,
143 		  substream->runtime->dma_bytes);
144 
145 	/* set addr */
146 	ret = mtk_memif_set_addr(afe, id,
147 				 substream->runtime->dma_area,
148 				 substream->runtime->dma_addr,
149 				 substream->runtime->dma_bytes);
150 	if (ret) {
151 		dev_err(afe->dev, "%s(), error, id %d, set addr, ret %d\n",
152 			__func__, id, ret);
153 		return ret;
154 	}
155 
156 	/* set channel */
157 	ret = mtk_memif_set_channel(afe, id, channels);
158 	if (ret) {
159 		dev_err(afe->dev, "%s(), error, id %d, set channel %d, ret %d\n",
160 			__func__, id, channels, ret);
161 		return ret;
162 	}
163 
164 	/* set rate */
165 	ret = mtk_memif_set_rate_substream(substream, id, rate);
166 	if (ret) {
167 		dev_err(afe->dev, "%s(), error, id %d, set rate %d, ret %d\n",
168 			__func__, id, rate, ret);
169 		return ret;
170 	}
171 
172 	/* set format */
173 	ret = mtk_memif_set_format(afe, id, format);
174 	if (ret) {
175 		dev_err(afe->dev, "%s(), error, id %d, set format %d, ret %d\n",
176 			__func__, id, format, ret);
177 		return ret;
178 	}
179 
180 	return 0;
181 }
182 EXPORT_SYMBOL_GPL(mtk_afe_fe_hw_params);
183 
184 int mtk_afe_fe_hw_free(struct snd_pcm_substream *substream,
185 		       struct snd_soc_dai *dai)
186 {
187 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
188 
189 	if (afe->release_dram_resource)
190 		afe->release_dram_resource(afe->dev);
191 
192 	return 0;
193 }
194 EXPORT_SYMBOL_GPL(mtk_afe_fe_hw_free);
195 
196 int mtk_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd,
197 		       struct snd_soc_dai *dai)
198 {
199 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
200 	struct snd_pcm_runtime * const runtime = substream->runtime;
201 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
202 	int id = rtd->cpu_dai->id;
203 	struct mtk_base_afe_memif *memif = &afe->memif[id];
204 	struct mtk_base_afe_irq *irqs = &afe->irqs[memif->irq_usage];
205 	const struct mtk_base_irq_data *irq_data = irqs->irq_data;
206 	unsigned int counter = runtime->period_size;
207 	int fs;
208 	int ret;
209 
210 	dev_dbg(afe->dev, "%s %s cmd=%d\n", __func__, memif->data->name, cmd);
211 
212 	switch (cmd) {
213 	case SNDRV_PCM_TRIGGER_START:
214 	case SNDRV_PCM_TRIGGER_RESUME:
215 		ret = mtk_memif_set_enable(afe, id);
216 		if (ret) {
217 			dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n",
218 				__func__, id, ret);
219 			return ret;
220 		}
221 
222 		/* set irq counter */
223 		mtk_regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,
224 				       irq_data->irq_cnt_maskbit, counter,
225 				       irq_data->irq_cnt_shift);
226 
227 		/* set irq fs */
228 		fs = afe->irq_fs(substream, runtime->rate);
229 
230 		if (fs < 0)
231 			return -EINVAL;
232 
233 		mtk_regmap_update_bits(afe->regmap, irq_data->irq_fs_reg,
234 				       irq_data->irq_fs_maskbit, fs,
235 				       irq_data->irq_fs_shift);
236 
237 		/* enable interrupt */
238 		mtk_regmap_update_bits(afe->regmap, irq_data->irq_en_reg,
239 				       1, 1, irq_data->irq_en_shift);
240 
241 		return 0;
242 	case SNDRV_PCM_TRIGGER_STOP:
243 	case SNDRV_PCM_TRIGGER_SUSPEND:
244 		ret = mtk_memif_set_disable(afe, id);
245 		if (ret) {
246 			dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n",
247 				__func__, id, ret);
248 		}
249 
250 		/* disable interrupt */
251 		mtk_regmap_update_bits(afe->regmap, irq_data->irq_en_reg,
252 				       1, 0, irq_data->irq_en_shift);
253 		/* and clear pending IRQ */
254 		mtk_regmap_write(afe->regmap, irq_data->irq_clr_reg,
255 				 1 << irq_data->irq_clr_shift);
256 		return ret;
257 	default:
258 		return -EINVAL;
259 	}
260 }
261 EXPORT_SYMBOL_GPL(mtk_afe_fe_trigger);
262 
263 int mtk_afe_fe_prepare(struct snd_pcm_substream *substream,
264 		       struct snd_soc_dai *dai)
265 {
266 	struct snd_soc_pcm_runtime *rtd  = substream->private_data;
267 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
268 	int id = rtd->cpu_dai->id;
269 	int pbuf_size;
270 
271 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
272 		if (afe->get_memif_pbuf_size) {
273 			pbuf_size = afe->get_memif_pbuf_size(substream);
274 			mtk_memif_set_pbuf_size(afe, id, pbuf_size);
275 		}
276 	}
277 	return 0;
278 }
279 EXPORT_SYMBOL_GPL(mtk_afe_fe_prepare);
280 
281 const struct snd_soc_dai_ops mtk_afe_fe_ops = {
282 	.startup	= mtk_afe_fe_startup,
283 	.shutdown	= mtk_afe_fe_shutdown,
284 	.hw_params	= mtk_afe_fe_hw_params,
285 	.hw_free	= mtk_afe_fe_hw_free,
286 	.prepare	= mtk_afe_fe_prepare,
287 	.trigger	= mtk_afe_fe_trigger,
288 };
289 EXPORT_SYMBOL_GPL(mtk_afe_fe_ops);
290 
291 static DEFINE_MUTEX(irqs_lock);
292 int mtk_dynamic_irq_acquire(struct mtk_base_afe *afe)
293 {
294 	int i;
295 
296 	mutex_lock(&afe->irq_alloc_lock);
297 	for (i = 0; i < afe->irqs_size; ++i) {
298 		if (afe->irqs[i].irq_occupyed == 0) {
299 			afe->irqs[i].irq_occupyed = 1;
300 			mutex_unlock(&afe->irq_alloc_lock);
301 			return i;
302 		}
303 	}
304 	mutex_unlock(&afe->irq_alloc_lock);
305 	return afe->irqs_size;
306 }
307 EXPORT_SYMBOL_GPL(mtk_dynamic_irq_acquire);
308 
309 int mtk_dynamic_irq_release(struct mtk_base_afe *afe, int irq_id)
310 {
311 	mutex_lock(&afe->irq_alloc_lock);
312 	if (irq_id >= 0 && irq_id < afe->irqs_size) {
313 		afe->irqs[irq_id].irq_occupyed = 0;
314 		mutex_unlock(&afe->irq_alloc_lock);
315 		return 0;
316 	}
317 	mutex_unlock(&afe->irq_alloc_lock);
318 	return -EINVAL;
319 }
320 EXPORT_SYMBOL_GPL(mtk_dynamic_irq_release);
321 
322 int mtk_afe_suspend(struct snd_soc_component *component)
323 {
324 	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
325 	struct device *dev = afe->dev;
326 	struct regmap *regmap = afe->regmap;
327 	int i;
328 
329 	if (pm_runtime_status_suspended(dev) || afe->suspended)
330 		return 0;
331 
332 	if (!afe->reg_back_up)
333 		afe->reg_back_up =
334 			devm_kcalloc(dev, afe->reg_back_up_list_num,
335 				     sizeof(unsigned int), GFP_KERNEL);
336 
337 	for (i = 0; i < afe->reg_back_up_list_num; i++)
338 		regmap_read(regmap, afe->reg_back_up_list[i],
339 			    &afe->reg_back_up[i]);
340 
341 	afe->suspended = true;
342 	afe->runtime_suspend(dev);
343 	return 0;
344 }
345 EXPORT_SYMBOL_GPL(mtk_afe_suspend);
346 
347 int mtk_afe_resume(struct snd_soc_component *component)
348 {
349 	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
350 	struct device *dev = afe->dev;
351 	struct regmap *regmap = afe->regmap;
352 	int i = 0;
353 
354 	if (pm_runtime_status_suspended(dev) || !afe->suspended)
355 		return 0;
356 
357 	afe->runtime_resume(dev);
358 
359 	if (!afe->reg_back_up)
360 		dev_dbg(dev, "%s no reg_backup\n", __func__);
361 
362 	for (i = 0; i < afe->reg_back_up_list_num; i++)
363 		mtk_regmap_write(regmap, afe->reg_back_up_list[i],
364 				 afe->reg_back_up[i]);
365 
366 	afe->suspended = false;
367 	return 0;
368 }
369 EXPORT_SYMBOL_GPL(mtk_afe_resume);
370 
371 int mtk_memif_set_enable(struct mtk_base_afe *afe, int id)
372 {
373 	struct mtk_base_afe_memif *memif = &afe->memif[id];
374 
375 	if (memif->data->enable_shift < 0) {
376 		dev_warn(afe->dev, "%s(), error, id %d, enable_shift < 0\n",
377 			 __func__, id);
378 		return 0;
379 	}
380 	return mtk_regmap_update_bits(afe->regmap, memif->data->enable_reg,
381 				      1, 1, memif->data->enable_shift);
382 }
383 EXPORT_SYMBOL_GPL(mtk_memif_set_enable);
384 
385 int mtk_memif_set_disable(struct mtk_base_afe *afe, int id)
386 {
387 	struct mtk_base_afe_memif *memif = &afe->memif[id];
388 
389 	if (memif->data->enable_shift < 0) {
390 		dev_warn(afe->dev, "%s(), error, id %d, enable_shift < 0\n",
391 			 __func__, id);
392 		return 0;
393 	}
394 	return mtk_regmap_update_bits(afe->regmap, memif->data->enable_reg,
395 				      1, 0, memif->data->enable_shift);
396 }
397 EXPORT_SYMBOL_GPL(mtk_memif_set_disable);
398 
399 int mtk_memif_set_addr(struct mtk_base_afe *afe, int id,
400 		       unsigned char *dma_area,
401 		       dma_addr_t dma_addr,
402 		       size_t dma_bytes)
403 {
404 	struct mtk_base_afe_memif *memif = &afe->memif[id];
405 	int msb_at_bit33 = upper_32_bits(dma_addr) ? 1 : 0;
406 	unsigned int phys_buf_addr = lower_32_bits(dma_addr);
407 	unsigned int phys_buf_addr_upper_32 = upper_32_bits(dma_addr);
408 
409 	memif->dma_area = dma_area;
410 	memif->dma_addr = dma_addr;
411 	memif->dma_bytes = dma_bytes;
412 
413 	/* start */
414 	mtk_regmap_write(afe->regmap, memif->data->reg_ofs_base,
415 			 phys_buf_addr);
416 	/* end */
417 	if (memif->data->reg_ofs_end)
418 		mtk_regmap_write(afe->regmap,
419 				 memif->data->reg_ofs_end,
420 				 phys_buf_addr + dma_bytes - 1);
421 	else
422 		mtk_regmap_write(afe->regmap,
423 				 memif->data->reg_ofs_base +
424 				 AFE_BASE_END_OFFSET,
425 				 phys_buf_addr + dma_bytes - 1);
426 
427 	/* set start, end, upper 32 bits */
428 	if (memif->data->reg_ofs_base_msb) {
429 		mtk_regmap_write(afe->regmap, memif->data->reg_ofs_base_msb,
430 				 phys_buf_addr_upper_32);
431 		mtk_regmap_write(afe->regmap,
432 				 memif->data->reg_ofs_end_msb,
433 				 phys_buf_addr_upper_32);
434 	}
435 
436 	/* set MSB to 33-bit */
437 	if (memif->data->msb_reg >= 0)
438 		mtk_regmap_update_bits(afe->regmap, memif->data->msb_reg,
439 				       1, msb_at_bit33, memif->data->msb_shift);
440 
441 	return 0;
442 }
443 EXPORT_SYMBOL_GPL(mtk_memif_set_addr);
444 
445 int mtk_memif_set_channel(struct mtk_base_afe *afe,
446 			  int id, unsigned int channel)
447 {
448 	struct mtk_base_afe_memif *memif = &afe->memif[id];
449 	unsigned int mono;
450 
451 	if (memif->data->mono_shift < 0)
452 		return 0;
453 
454 	if (memif->data->quad_ch_mask) {
455 		unsigned int quad_ch = (channel == 4) ? 1 : 0;
456 
457 		mtk_regmap_update_bits(afe->regmap, memif->data->quad_ch_reg,
458 				       memif->data->quad_ch_mask,
459 				       quad_ch, memif->data->quad_ch_shift);
460 	}
461 
462 	if (memif->data->mono_invert)
463 		mono = (channel == 1) ? 0 : 1;
464 	else
465 		mono = (channel == 1) ? 1 : 0;
466 
467 	return mtk_regmap_update_bits(afe->regmap, memif->data->mono_reg,
468 				      1, mono, memif->data->mono_shift);
469 }
470 EXPORT_SYMBOL_GPL(mtk_memif_set_channel);
471 
472 static int mtk_memif_set_rate_fs(struct mtk_base_afe *afe,
473 				 int id, int fs)
474 {
475 	struct mtk_base_afe_memif *memif = &afe->memif[id];
476 
477 	if (memif->data->fs_shift >= 0)
478 		mtk_regmap_update_bits(afe->regmap, memif->data->fs_reg,
479 				       memif->data->fs_maskbit,
480 				       fs, memif->data->fs_shift);
481 
482 	return 0;
483 }
484 
485 int mtk_memif_set_rate(struct mtk_base_afe *afe,
486 		       int id, unsigned int rate)
487 {
488 	int fs = 0;
489 
490 	if (!afe->get_dai_fs) {
491 		dev_err(afe->dev, "%s(), error, afe->get_dai_fs == NULL\n",
492 			__func__);
493 		return -EINVAL;
494 	}
495 
496 	fs = afe->get_dai_fs(afe, id, rate);
497 
498 	if (fs < 0)
499 		return -EINVAL;
500 
501 	return mtk_memif_set_rate_fs(afe, id, fs);
502 }
503 EXPORT_SYMBOL_GPL(mtk_memif_set_rate);
504 
505 int mtk_memif_set_rate_substream(struct snd_pcm_substream *substream,
506 				 int id, unsigned int rate)
507 {
508 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
509 	struct snd_soc_component *component =
510 		snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
511 	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
512 
513 	int fs = 0;
514 
515 	if (!afe->memif_fs) {
516 		dev_err(afe->dev, "%s(), error, afe->memif_fs == NULL\n",
517 			__func__);
518 		return -EINVAL;
519 	}
520 
521 	fs = afe->memif_fs(substream, rate);
522 
523 	if (fs < 0)
524 		return -EINVAL;
525 
526 	return mtk_memif_set_rate_fs(afe, id, fs);
527 }
528 EXPORT_SYMBOL_GPL(mtk_memif_set_rate_substream);
529 
530 int mtk_memif_set_format(struct mtk_base_afe *afe,
531 			 int id, snd_pcm_format_t format)
532 {
533 	struct mtk_base_afe_memif *memif = &afe->memif[id];
534 	int hd_audio = 0;
535 	int hd_align = 0;
536 
537 	/* set hd mode */
538 	switch (format) {
539 	case SNDRV_PCM_FORMAT_S16_LE:
540 	case SNDRV_PCM_FORMAT_U16_LE:
541 		hd_audio = 0;
542 		break;
543 	case SNDRV_PCM_FORMAT_S32_LE:
544 	case SNDRV_PCM_FORMAT_U32_LE:
545 		hd_audio = 1;
546 		hd_align = 1;
547 		break;
548 	case SNDRV_PCM_FORMAT_S24_LE:
549 	case SNDRV_PCM_FORMAT_U24_LE:
550 		hd_audio = 1;
551 		break;
552 	default:
553 		dev_err(afe->dev, "%s() error: unsupported format %d\n",
554 			__func__, format);
555 		break;
556 	}
557 
558 	mtk_regmap_update_bits(afe->regmap, memif->data->hd_reg,
559 			       1, hd_audio, memif->data->hd_shift);
560 
561 	mtk_regmap_update_bits(afe->regmap, memif->data->hd_align_reg,
562 			       1, hd_align, memif->data->hd_align_mshift);
563 
564 	return 0;
565 }
566 EXPORT_SYMBOL_GPL(mtk_memif_set_format);
567 
568 int mtk_memif_set_pbuf_size(struct mtk_base_afe *afe,
569 			    int id, int pbuf_size)
570 {
571 	const struct mtk_base_memif_data *memif_data = afe->memif[id].data;
572 
573 	if (memif_data->pbuf_mask == 0 || memif_data->minlen_mask == 0)
574 		return 0;
575 
576 	mtk_regmap_update_bits(afe->regmap, memif_data->pbuf_reg,
577 			       memif_data->pbuf_mask,
578 			       pbuf_size, memif_data->pbuf_shift);
579 
580 	mtk_regmap_update_bits(afe->regmap, memif_data->minlen_reg,
581 			       memif_data->minlen_mask,
582 			       pbuf_size, memif_data->minlen_shift);
583 	return 0;
584 }
585 EXPORT_SYMBOL_GPL(mtk_memif_set_pbuf_size);
586 
587 MODULE_DESCRIPTION("Mediatek simple fe dai operator");
588 MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
589 MODULE_LICENSE("GPL v2");
590