13a280ed1SRyder Lee // SPDX-License-Identifier: GPL-2.0 2283b6124SGarlic Tseng /* 3283b6124SGarlic Tseng * mtk-afe-fe-dais.c -- Mediatek afe fe dai operator 4283b6124SGarlic Tseng * 5283b6124SGarlic Tseng * Copyright (c) 2016 MediaTek Inc. 6283b6124SGarlic Tseng * Author: Garlic Tseng <garlic.tseng@mediatek.com> 7283b6124SGarlic Tseng */ 8283b6124SGarlic Tseng 9283b6124SGarlic Tseng #include <linux/module.h> 10283b6124SGarlic Tseng #include <linux/pm_runtime.h> 11283b6124SGarlic Tseng #include <linux/regmap.h> 12283b6124SGarlic Tseng #include <sound/soc.h> 13f1b5bf07SKuninori Morimoto #include "mtk-afe-platform-driver.h" 14283b6124SGarlic Tseng #include "mtk-afe-fe-dai.h" 15283b6124SGarlic Tseng #include "mtk-base-afe.h" 16283b6124SGarlic Tseng 17283b6124SGarlic Tseng #define AFE_BASE_END_OFFSET 8 18283b6124SGarlic Tseng 1922e76614SBaoyou Xie static int mtk_regmap_update_bits(struct regmap *map, int reg, 2022e76614SBaoyou Xie unsigned int mask, 21c6839641SPi-Hsun Shih unsigned int val, int shift) 22283b6124SGarlic Tseng { 23c6839641SPi-Hsun Shih if (reg < 0 || WARN_ON_ONCE(shift < 0)) 24283b6124SGarlic Tseng return 0; 25c6839641SPi-Hsun Shih return regmap_update_bits(map, reg, mask << shift, val << shift); 26283b6124SGarlic Tseng } 27283b6124SGarlic Tseng 2822e76614SBaoyou Xie static int mtk_regmap_write(struct regmap *map, int reg, unsigned int val) 29283b6124SGarlic Tseng { 30283b6124SGarlic Tseng if (reg < 0) 31283b6124SGarlic Tseng return 0; 32283b6124SGarlic Tseng return regmap_write(map, reg, val); 33283b6124SGarlic Tseng } 34283b6124SGarlic Tseng 35283b6124SGarlic Tseng int mtk_afe_fe_startup(struct snd_pcm_substream *substream, 36283b6124SGarlic Tseng struct snd_soc_dai *dai) 37283b6124SGarlic Tseng { 38283b6124SGarlic Tseng struct snd_soc_pcm_runtime *rtd = substream->private_data; 39e4b31b81SRyder Lee struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 40283b6124SGarlic Tseng struct snd_pcm_runtime *runtime = substream->runtime; 41283b6124SGarlic Tseng int memif_num = rtd->cpu_dai->id; 42283b6124SGarlic Tseng struct mtk_base_afe_memif *memif = &afe->memif[memif_num]; 43283b6124SGarlic Tseng const struct snd_pcm_hardware *mtk_afe_hardware = afe->mtk_afe_hardware; 44283b6124SGarlic Tseng int ret; 45283b6124SGarlic Tseng 46283b6124SGarlic Tseng memif->substream = substream; 47283b6124SGarlic Tseng 48283b6124SGarlic Tseng snd_pcm_hw_constraint_step(substream->runtime, 0, 49283b6124SGarlic Tseng SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 16); 50283b6124SGarlic Tseng /* enable agent */ 51283b6124SGarlic Tseng mtk_regmap_update_bits(afe->regmap, memif->data->agent_disable_reg, 52c6839641SPi-Hsun Shih 1, 0, memif->data->agent_disable_shift); 53283b6124SGarlic Tseng 54283b6124SGarlic Tseng snd_soc_set_runtime_hwparams(substream, mtk_afe_hardware); 55283b6124SGarlic Tseng 56283b6124SGarlic Tseng /* 57283b6124SGarlic Tseng * Capture cannot use ping-pong buffer since hw_ptr at IRQ may be 58283b6124SGarlic Tseng * smaller than period_size due to AFE's internal buffer. 59283b6124SGarlic Tseng * This easily leads to overrun when avail_min is period_size. 60283b6124SGarlic Tseng * One more period can hold the possible unread buffer. 61283b6124SGarlic Tseng */ 62283b6124SGarlic Tseng if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 63283b6124SGarlic Tseng int periods_max = mtk_afe_hardware->periods_max; 64283b6124SGarlic Tseng 65283b6124SGarlic Tseng ret = snd_pcm_hw_constraint_minmax(runtime, 66283b6124SGarlic Tseng SNDRV_PCM_HW_PARAM_PERIODS, 67283b6124SGarlic Tseng 3, periods_max); 68283b6124SGarlic Tseng if (ret < 0) { 69283b6124SGarlic Tseng dev_err(afe->dev, "hw_constraint_minmax failed\n"); 70283b6124SGarlic Tseng return ret; 71283b6124SGarlic Tseng } 72283b6124SGarlic Tseng } 73283b6124SGarlic Tseng 74283b6124SGarlic Tseng ret = snd_pcm_hw_constraint_integer(runtime, 75283b6124SGarlic Tseng SNDRV_PCM_HW_PARAM_PERIODS); 76283b6124SGarlic Tseng if (ret < 0) 77283b6124SGarlic Tseng dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n"); 78283b6124SGarlic Tseng 79283b6124SGarlic Tseng /* dynamic allocate irq to memif */ 80283b6124SGarlic Tseng if (memif->irq_usage < 0) { 81283b6124SGarlic Tseng int irq_id = mtk_dynamic_irq_acquire(afe); 82283b6124SGarlic Tseng 83283b6124SGarlic Tseng if (irq_id != afe->irqs_size) { 84283b6124SGarlic Tseng /* link */ 85283b6124SGarlic Tseng memif->irq_usage = irq_id; 86283b6124SGarlic Tseng } else { 87283b6124SGarlic Tseng dev_err(afe->dev, "%s() error: no more asys irq\n", 88283b6124SGarlic Tseng __func__); 89283b6124SGarlic Tseng ret = -EBUSY; 90283b6124SGarlic Tseng } 91283b6124SGarlic Tseng } 92283b6124SGarlic Tseng return ret; 93283b6124SGarlic Tseng } 94283b6124SGarlic Tseng EXPORT_SYMBOL_GPL(mtk_afe_fe_startup); 95283b6124SGarlic Tseng 96283b6124SGarlic Tseng void mtk_afe_fe_shutdown(struct snd_pcm_substream *substream, 97283b6124SGarlic Tseng struct snd_soc_dai *dai) 98283b6124SGarlic Tseng { 99283b6124SGarlic Tseng struct snd_soc_pcm_runtime *rtd = substream->private_data; 100e4b31b81SRyder Lee struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 101283b6124SGarlic Tseng struct mtk_base_afe_memif *memif = &afe->memif[rtd->cpu_dai->id]; 102283b6124SGarlic Tseng int irq_id; 103283b6124SGarlic Tseng 104283b6124SGarlic Tseng irq_id = memif->irq_usage; 105283b6124SGarlic Tseng 106283b6124SGarlic Tseng mtk_regmap_update_bits(afe->regmap, memif->data->agent_disable_reg, 107c6839641SPi-Hsun Shih 1, 1, memif->data->agent_disable_shift); 108283b6124SGarlic Tseng 109283b6124SGarlic Tseng if (!memif->const_irq) { 110283b6124SGarlic Tseng mtk_dynamic_irq_release(afe, irq_id); 111283b6124SGarlic Tseng memif->irq_usage = -1; 112283b6124SGarlic Tseng memif->substream = NULL; 113283b6124SGarlic Tseng } 114283b6124SGarlic Tseng } 115283b6124SGarlic Tseng EXPORT_SYMBOL_GPL(mtk_afe_fe_shutdown); 116283b6124SGarlic Tseng 117283b6124SGarlic Tseng int mtk_afe_fe_hw_params(struct snd_pcm_substream *substream, 118283b6124SGarlic Tseng struct snd_pcm_hw_params *params, 119283b6124SGarlic Tseng struct snd_soc_dai *dai) 120283b6124SGarlic Tseng { 121283b6124SGarlic Tseng struct snd_soc_pcm_runtime *rtd = substream->private_data; 122e4b31b81SRyder Lee struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 123283b6124SGarlic Tseng struct mtk_base_afe_memif *memif = &afe->memif[rtd->cpu_dai->id]; 124283b6124SGarlic Tseng int msb_at_bit33 = 0; 125283b6124SGarlic Tseng int ret, fs = 0; 126283b6124SGarlic Tseng 127283b6124SGarlic Tseng ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params)); 128283b6124SGarlic Tseng if (ret < 0) 129283b6124SGarlic Tseng return ret; 130283b6124SGarlic Tseng 131283b6124SGarlic Tseng msb_at_bit33 = upper_32_bits(substream->runtime->dma_addr) ? 1 : 0; 132283b6124SGarlic Tseng memif->phys_buf_addr = lower_32_bits(substream->runtime->dma_addr); 133283b6124SGarlic Tseng memif->buffer_size = substream->runtime->dma_bytes; 134283b6124SGarlic Tseng 135283b6124SGarlic Tseng /* start */ 136283b6124SGarlic Tseng mtk_regmap_write(afe->regmap, memif->data->reg_ofs_base, 137283b6124SGarlic Tseng memif->phys_buf_addr); 138283b6124SGarlic Tseng /* end */ 139283b6124SGarlic Tseng mtk_regmap_write(afe->regmap, 140283b6124SGarlic Tseng memif->data->reg_ofs_base + AFE_BASE_END_OFFSET, 141283b6124SGarlic Tseng memif->phys_buf_addr + memif->buffer_size - 1); 142283b6124SGarlic Tseng 143283b6124SGarlic Tseng /* set MSB to 33-bit */ 144283b6124SGarlic Tseng mtk_regmap_update_bits(afe->regmap, memif->data->msb_reg, 145c6839641SPi-Hsun Shih 1, msb_at_bit33, memif->data->msb_shift); 146283b6124SGarlic Tseng 147283b6124SGarlic Tseng /* set channel */ 148283b6124SGarlic Tseng if (memif->data->mono_shift >= 0) { 149283b6124SGarlic Tseng unsigned int mono = (params_channels(params) == 1) ? 1 : 0; 150283b6124SGarlic Tseng 151283b6124SGarlic Tseng mtk_regmap_update_bits(afe->regmap, memif->data->mono_reg, 152c6839641SPi-Hsun Shih 1, mono, memif->data->mono_shift); 153283b6124SGarlic Tseng } 154283b6124SGarlic Tseng 155283b6124SGarlic Tseng /* set rate */ 156283b6124SGarlic Tseng if (memif->data->fs_shift < 0) 157283b6124SGarlic Tseng return 0; 158283b6124SGarlic Tseng 159283b6124SGarlic Tseng fs = afe->memif_fs(substream, params_rate(params)); 160283b6124SGarlic Tseng 161283b6124SGarlic Tseng if (fs < 0) 162283b6124SGarlic Tseng return -EINVAL; 163283b6124SGarlic Tseng 164283b6124SGarlic Tseng mtk_regmap_update_bits(afe->regmap, memif->data->fs_reg, 165c6839641SPi-Hsun Shih memif->data->fs_maskbit, fs, 166c6839641SPi-Hsun Shih memif->data->fs_shift); 167283b6124SGarlic Tseng 168283b6124SGarlic Tseng return 0; 169283b6124SGarlic Tseng } 170283b6124SGarlic Tseng EXPORT_SYMBOL_GPL(mtk_afe_fe_hw_params); 171283b6124SGarlic Tseng 172283b6124SGarlic Tseng int mtk_afe_fe_hw_free(struct snd_pcm_substream *substream, 173283b6124SGarlic Tseng struct snd_soc_dai *dai) 174283b6124SGarlic Tseng { 175283b6124SGarlic Tseng return snd_pcm_lib_free_pages(substream); 176283b6124SGarlic Tseng } 177283b6124SGarlic Tseng EXPORT_SYMBOL_GPL(mtk_afe_fe_hw_free); 178283b6124SGarlic Tseng 179283b6124SGarlic Tseng int mtk_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd, 180283b6124SGarlic Tseng struct snd_soc_dai *dai) 181283b6124SGarlic Tseng { 182283b6124SGarlic Tseng struct snd_soc_pcm_runtime *rtd = substream->private_data; 183283b6124SGarlic Tseng struct snd_pcm_runtime * const runtime = substream->runtime; 184e4b31b81SRyder Lee struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 185283b6124SGarlic Tseng struct mtk_base_afe_memif *memif = &afe->memif[rtd->cpu_dai->id]; 186283b6124SGarlic Tseng struct mtk_base_afe_irq *irqs = &afe->irqs[memif->irq_usage]; 187283b6124SGarlic Tseng const struct mtk_base_irq_data *irq_data = irqs->irq_data; 188283b6124SGarlic Tseng unsigned int counter = runtime->period_size; 189283b6124SGarlic Tseng int fs; 190283b6124SGarlic Tseng 191283b6124SGarlic Tseng dev_dbg(afe->dev, "%s %s cmd=%d\n", __func__, memif->data->name, cmd); 192283b6124SGarlic Tseng 193283b6124SGarlic Tseng switch (cmd) { 194283b6124SGarlic Tseng case SNDRV_PCM_TRIGGER_START: 195283b6124SGarlic Tseng case SNDRV_PCM_TRIGGER_RESUME: 196283b6124SGarlic Tseng mtk_regmap_update_bits(afe->regmap, 197283b6124SGarlic Tseng memif->data->enable_reg, 198c6839641SPi-Hsun Shih 1, 1, memif->data->enable_shift); 199283b6124SGarlic Tseng 200283b6124SGarlic Tseng /* set irq counter */ 201283b6124SGarlic Tseng mtk_regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg, 202c6839641SPi-Hsun Shih irq_data->irq_cnt_maskbit, counter, 203c6839641SPi-Hsun Shih irq_data->irq_cnt_shift); 204283b6124SGarlic Tseng 205283b6124SGarlic Tseng /* set irq fs */ 206283b6124SGarlic Tseng fs = afe->irq_fs(substream, runtime->rate); 207283b6124SGarlic Tseng 208283b6124SGarlic Tseng if (fs < 0) 209283b6124SGarlic Tseng return -EINVAL; 210283b6124SGarlic Tseng 211283b6124SGarlic Tseng mtk_regmap_update_bits(afe->regmap, irq_data->irq_fs_reg, 212c6839641SPi-Hsun Shih irq_data->irq_fs_maskbit, fs, 213c6839641SPi-Hsun Shih irq_data->irq_fs_shift); 214283b6124SGarlic Tseng 215283b6124SGarlic Tseng /* enable interrupt */ 216283b6124SGarlic Tseng mtk_regmap_update_bits(afe->regmap, irq_data->irq_en_reg, 217c6839641SPi-Hsun Shih 1, 1, irq_data->irq_en_shift); 218283b6124SGarlic Tseng 219283b6124SGarlic Tseng return 0; 220283b6124SGarlic Tseng case SNDRV_PCM_TRIGGER_STOP: 221283b6124SGarlic Tseng case SNDRV_PCM_TRIGGER_SUSPEND: 222283b6124SGarlic Tseng mtk_regmap_update_bits(afe->regmap, memif->data->enable_reg, 223c6839641SPi-Hsun Shih 1, 0, memif->data->enable_shift); 224283b6124SGarlic Tseng /* disable interrupt */ 225283b6124SGarlic Tseng mtk_regmap_update_bits(afe->regmap, irq_data->irq_en_reg, 226c6839641SPi-Hsun Shih 1, 0, irq_data->irq_en_shift); 227283b6124SGarlic Tseng /* and clear pending IRQ */ 228283b6124SGarlic Tseng mtk_regmap_write(afe->regmap, irq_data->irq_clr_reg, 229283b6124SGarlic Tseng 1 << irq_data->irq_clr_shift); 230283b6124SGarlic Tseng return 0; 231283b6124SGarlic Tseng default: 232283b6124SGarlic Tseng return -EINVAL; 233283b6124SGarlic Tseng } 234283b6124SGarlic Tseng } 235283b6124SGarlic Tseng EXPORT_SYMBOL_GPL(mtk_afe_fe_trigger); 236283b6124SGarlic Tseng 237283b6124SGarlic Tseng int mtk_afe_fe_prepare(struct snd_pcm_substream *substream, 238283b6124SGarlic Tseng struct snd_soc_dai *dai) 239283b6124SGarlic Tseng { 240283b6124SGarlic Tseng struct snd_soc_pcm_runtime *rtd = substream->private_data; 241e4b31b81SRyder Lee struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 242283b6124SGarlic Tseng struct mtk_base_afe_memif *memif = &afe->memif[rtd->cpu_dai->id]; 243283b6124SGarlic Tseng int hd_audio = 0; 244d2ac1fe0SJiaxin Yu int hd_align = 0; 245283b6124SGarlic Tseng 246283b6124SGarlic Tseng /* set hd mode */ 247283b6124SGarlic Tseng switch (substream->runtime->format) { 248283b6124SGarlic Tseng case SNDRV_PCM_FORMAT_S16_LE: 249283b6124SGarlic Tseng hd_audio = 0; 250283b6124SGarlic Tseng break; 251283b6124SGarlic Tseng case SNDRV_PCM_FORMAT_S32_LE: 252283b6124SGarlic Tseng hd_audio = 1; 2531628fc3fSShunli Wang hd_align = 1; 254283b6124SGarlic Tseng break; 255283b6124SGarlic Tseng case SNDRV_PCM_FORMAT_S24_LE: 256283b6124SGarlic Tseng hd_audio = 1; 257283b6124SGarlic Tseng break; 258283b6124SGarlic Tseng default: 259283b6124SGarlic Tseng dev_err(afe->dev, "%s() error: unsupported format %d\n", 260283b6124SGarlic Tseng __func__, substream->runtime->format); 261283b6124SGarlic Tseng break; 262283b6124SGarlic Tseng } 263283b6124SGarlic Tseng 264283b6124SGarlic Tseng mtk_regmap_update_bits(afe->regmap, memif->data->hd_reg, 265c6839641SPi-Hsun Shih 1, hd_audio, memif->data->hd_shift); 266283b6124SGarlic Tseng 2671628fc3fSShunli Wang mtk_regmap_update_bits(afe->regmap, memif->data->hd_align_reg, 268e355d3deSJiaxin Yu 1, hd_align, memif->data->hd_align_mshift); 2691628fc3fSShunli Wang 270283b6124SGarlic Tseng return 0; 271283b6124SGarlic Tseng } 272283b6124SGarlic Tseng EXPORT_SYMBOL_GPL(mtk_afe_fe_prepare); 273283b6124SGarlic Tseng 274283b6124SGarlic Tseng const struct snd_soc_dai_ops mtk_afe_fe_ops = { 275283b6124SGarlic Tseng .startup = mtk_afe_fe_startup, 276283b6124SGarlic Tseng .shutdown = mtk_afe_fe_shutdown, 277283b6124SGarlic Tseng .hw_params = mtk_afe_fe_hw_params, 278283b6124SGarlic Tseng .hw_free = mtk_afe_fe_hw_free, 279283b6124SGarlic Tseng .prepare = mtk_afe_fe_prepare, 280283b6124SGarlic Tseng .trigger = mtk_afe_fe_trigger, 281283b6124SGarlic Tseng }; 282283b6124SGarlic Tseng EXPORT_SYMBOL_GPL(mtk_afe_fe_ops); 283283b6124SGarlic Tseng 284283b6124SGarlic Tseng static DEFINE_MUTEX(irqs_lock); 285283b6124SGarlic Tseng int mtk_dynamic_irq_acquire(struct mtk_base_afe *afe) 286283b6124SGarlic Tseng { 287283b6124SGarlic Tseng int i; 288283b6124SGarlic Tseng 289283b6124SGarlic Tseng mutex_lock(&afe->irq_alloc_lock); 290283b6124SGarlic Tseng for (i = 0; i < afe->irqs_size; ++i) { 291283b6124SGarlic Tseng if (afe->irqs[i].irq_occupyed == 0) { 292283b6124SGarlic Tseng afe->irqs[i].irq_occupyed = 1; 293283b6124SGarlic Tseng mutex_unlock(&afe->irq_alloc_lock); 294283b6124SGarlic Tseng return i; 295283b6124SGarlic Tseng } 296283b6124SGarlic Tseng } 297283b6124SGarlic Tseng mutex_unlock(&afe->irq_alloc_lock); 298283b6124SGarlic Tseng return afe->irqs_size; 299283b6124SGarlic Tseng } 300283b6124SGarlic Tseng EXPORT_SYMBOL_GPL(mtk_dynamic_irq_acquire); 301283b6124SGarlic Tseng 302283b6124SGarlic Tseng int mtk_dynamic_irq_release(struct mtk_base_afe *afe, int irq_id) 303283b6124SGarlic Tseng { 304283b6124SGarlic Tseng mutex_lock(&afe->irq_alloc_lock); 305283b6124SGarlic Tseng if (irq_id >= 0 && irq_id < afe->irqs_size) { 306283b6124SGarlic Tseng afe->irqs[irq_id].irq_occupyed = 0; 307283b6124SGarlic Tseng mutex_unlock(&afe->irq_alloc_lock); 308283b6124SGarlic Tseng return 0; 309283b6124SGarlic Tseng } 310283b6124SGarlic Tseng mutex_unlock(&afe->irq_alloc_lock); 311283b6124SGarlic Tseng return -EINVAL; 312283b6124SGarlic Tseng } 313283b6124SGarlic Tseng EXPORT_SYMBOL_GPL(mtk_dynamic_irq_release); 314283b6124SGarlic Tseng 315283b6124SGarlic Tseng int mtk_afe_dai_suspend(struct snd_soc_dai *dai) 316283b6124SGarlic Tseng { 317e4b31b81SRyder Lee struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 318283b6124SGarlic Tseng struct device *dev = afe->dev; 319283b6124SGarlic Tseng struct regmap *regmap = afe->regmap; 320283b6124SGarlic Tseng int i; 321283b6124SGarlic Tseng 322283b6124SGarlic Tseng if (pm_runtime_status_suspended(dev) || afe->suspended) 323283b6124SGarlic Tseng return 0; 324283b6124SGarlic Tseng 325283b6124SGarlic Tseng if (!afe->reg_back_up) 326283b6124SGarlic Tseng afe->reg_back_up = 327283b6124SGarlic Tseng devm_kcalloc(dev, afe->reg_back_up_list_num, 328283b6124SGarlic Tseng sizeof(unsigned int), GFP_KERNEL); 329283b6124SGarlic Tseng 330283b6124SGarlic Tseng for (i = 0; i < afe->reg_back_up_list_num; i++) 331283b6124SGarlic Tseng regmap_read(regmap, afe->reg_back_up_list[i], 332283b6124SGarlic Tseng &afe->reg_back_up[i]); 333283b6124SGarlic Tseng 334283b6124SGarlic Tseng afe->suspended = true; 335283b6124SGarlic Tseng afe->runtime_suspend(dev); 336283b6124SGarlic Tseng return 0; 337283b6124SGarlic Tseng } 338283b6124SGarlic Tseng EXPORT_SYMBOL_GPL(mtk_afe_dai_suspend); 339283b6124SGarlic Tseng 340283b6124SGarlic Tseng int mtk_afe_dai_resume(struct snd_soc_dai *dai) 341283b6124SGarlic Tseng { 342e4b31b81SRyder Lee struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 343283b6124SGarlic Tseng struct device *dev = afe->dev; 344283b6124SGarlic Tseng struct regmap *regmap = afe->regmap; 345283b6124SGarlic Tseng int i = 0; 346283b6124SGarlic Tseng 347283b6124SGarlic Tseng if (pm_runtime_status_suspended(dev) || !afe->suspended) 348283b6124SGarlic Tseng return 0; 349283b6124SGarlic Tseng 350283b6124SGarlic Tseng afe->runtime_resume(dev); 351283b6124SGarlic Tseng 352283b6124SGarlic Tseng if (!afe->reg_back_up) 353283b6124SGarlic Tseng dev_dbg(dev, "%s no reg_backup\n", __func__); 354283b6124SGarlic Tseng 355283b6124SGarlic Tseng for (i = 0; i < afe->reg_back_up_list_num; i++) 356283b6124SGarlic Tseng mtk_regmap_write(regmap, afe->reg_back_up_list[i], 357283b6124SGarlic Tseng afe->reg_back_up[i]); 358283b6124SGarlic Tseng 359283b6124SGarlic Tseng afe->suspended = false; 360283b6124SGarlic Tseng return 0; 361283b6124SGarlic Tseng } 362283b6124SGarlic Tseng EXPORT_SYMBOL_GPL(mtk_afe_dai_resume); 363283b6124SGarlic Tseng 3649cdf85a1SEason Yen int mtk_memif_set_enable(struct mtk_base_afe *afe, int id) 3659cdf85a1SEason Yen { 3669cdf85a1SEason Yen struct mtk_base_afe_memif *memif = &afe->memif[id]; 3679cdf85a1SEason Yen 3689cdf85a1SEason Yen if (memif->data->enable_shift < 0) { 3699cdf85a1SEason Yen dev_warn(afe->dev, "%s(), error, id %d, enable_shift < 0\n", 3709cdf85a1SEason Yen __func__, id); 3719cdf85a1SEason Yen return 0; 3729cdf85a1SEason Yen } 3739cdf85a1SEason Yen return mtk_regmap_update_bits(afe->regmap, memif->data->enable_reg, 3749cdf85a1SEason Yen 1, 1, memif->data->enable_shift); 3759cdf85a1SEason Yen } 3769cdf85a1SEason Yen EXPORT_SYMBOL_GPL(mtk_memif_set_enable); 3779cdf85a1SEason Yen 3789cdf85a1SEason Yen int mtk_memif_set_disable(struct mtk_base_afe *afe, int id) 3799cdf85a1SEason Yen { 3809cdf85a1SEason Yen struct mtk_base_afe_memif *memif = &afe->memif[id]; 3819cdf85a1SEason Yen 3829cdf85a1SEason Yen if (memif->data->enable_shift < 0) { 3839cdf85a1SEason Yen dev_warn(afe->dev, "%s(), error, id %d, enable_shift < 0\n", 3849cdf85a1SEason Yen __func__, id); 3859cdf85a1SEason Yen return 0; 3869cdf85a1SEason Yen } 3879cdf85a1SEason Yen return mtk_regmap_update_bits(afe->regmap, memif->data->enable_reg, 3889cdf85a1SEason Yen 1, 0, memif->data->enable_shift); 3899cdf85a1SEason Yen } 3909cdf85a1SEason Yen EXPORT_SYMBOL_GPL(mtk_memif_set_disable); 3919cdf85a1SEason Yen 3929cdf85a1SEason Yen int mtk_memif_set_addr(struct mtk_base_afe *afe, int id, 3939cdf85a1SEason Yen unsigned char *dma_area, 3949cdf85a1SEason Yen dma_addr_t dma_addr, 3959cdf85a1SEason Yen size_t dma_bytes) 3969cdf85a1SEason Yen { 3979cdf85a1SEason Yen struct mtk_base_afe_memif *memif = &afe->memif[id]; 3989cdf85a1SEason Yen int msb_at_bit33 = upper_32_bits(dma_addr) ? 1 : 0; 3999cdf85a1SEason Yen unsigned int phys_buf_addr = lower_32_bits(dma_addr); 4009cdf85a1SEason Yen unsigned int phys_buf_addr_upper_32 = upper_32_bits(dma_addr); 4019cdf85a1SEason Yen 4029cdf85a1SEason Yen memif->dma_area = dma_area; 4039cdf85a1SEason Yen memif->dma_addr = dma_addr; 4049cdf85a1SEason Yen memif->dma_bytes = dma_bytes; 4059cdf85a1SEason Yen 4069cdf85a1SEason Yen /* start */ 4079cdf85a1SEason Yen mtk_regmap_write(afe->regmap, memif->data->reg_ofs_base, 4089cdf85a1SEason Yen phys_buf_addr); 4099cdf85a1SEason Yen /* end */ 4109cdf85a1SEason Yen if (memif->data->reg_ofs_end) 4119cdf85a1SEason Yen mtk_regmap_write(afe->regmap, 4129cdf85a1SEason Yen memif->data->reg_ofs_end, 4139cdf85a1SEason Yen phys_buf_addr + dma_bytes - 1); 4149cdf85a1SEason Yen else 4159cdf85a1SEason Yen mtk_regmap_write(afe->regmap, 4169cdf85a1SEason Yen memif->data->reg_ofs_base + 4179cdf85a1SEason Yen AFE_BASE_END_OFFSET, 4189cdf85a1SEason Yen phys_buf_addr + dma_bytes - 1); 4199cdf85a1SEason Yen 4209cdf85a1SEason Yen /* set start, end, upper 32 bits */ 4219cdf85a1SEason Yen if (memif->data->reg_ofs_base_msb) { 4229cdf85a1SEason Yen mtk_regmap_write(afe->regmap, memif->data->reg_ofs_base_msb, 4239cdf85a1SEason Yen phys_buf_addr_upper_32); 4249cdf85a1SEason Yen mtk_regmap_write(afe->regmap, 4259cdf85a1SEason Yen memif->data->reg_ofs_end_msb, 4269cdf85a1SEason Yen phys_buf_addr_upper_32); 4279cdf85a1SEason Yen } 4289cdf85a1SEason Yen 4299cdf85a1SEason Yen /* set MSB to 33-bit */ 4309cdf85a1SEason Yen if (memif->data->msb_reg >= 0) 4319cdf85a1SEason Yen mtk_regmap_update_bits(afe->regmap, memif->data->msb_reg, 4329cdf85a1SEason Yen 1, msb_at_bit33, memif->data->msb_shift); 4339cdf85a1SEason Yen 4349cdf85a1SEason Yen return 0; 4359cdf85a1SEason Yen } 4369cdf85a1SEason Yen EXPORT_SYMBOL_GPL(mtk_memif_set_addr); 4379cdf85a1SEason Yen 4389cdf85a1SEason Yen int mtk_memif_set_channel(struct mtk_base_afe *afe, 4399cdf85a1SEason Yen int id, unsigned int channel) 4409cdf85a1SEason Yen { 4419cdf85a1SEason Yen struct mtk_base_afe_memif *memif = &afe->memif[id]; 4429cdf85a1SEason Yen unsigned int mono; 4439cdf85a1SEason Yen 4449cdf85a1SEason Yen if (memif->data->mono_shift < 0) 4459cdf85a1SEason Yen return 0; 4469cdf85a1SEason Yen 4479cdf85a1SEason Yen if (memif->data->quad_ch_mask) { 4489cdf85a1SEason Yen unsigned int quad_ch = (channel == 4) ? 1 : 0; 4499cdf85a1SEason Yen 4509cdf85a1SEason Yen mtk_regmap_update_bits(afe->regmap, memif->data->quad_ch_reg, 4519cdf85a1SEason Yen memif->data->quad_ch_mask, 4529cdf85a1SEason Yen quad_ch, memif->data->quad_ch_shift); 4539cdf85a1SEason Yen } 4549cdf85a1SEason Yen 4559cdf85a1SEason Yen if (memif->data->mono_invert) 4569cdf85a1SEason Yen mono = (channel == 1) ? 0 : 1; 4579cdf85a1SEason Yen else 4589cdf85a1SEason Yen mono = (channel == 1) ? 1 : 0; 4599cdf85a1SEason Yen 4609cdf85a1SEason Yen return mtk_regmap_update_bits(afe->regmap, memif->data->mono_reg, 4619cdf85a1SEason Yen 1, mono, memif->data->mono_shift); 4629cdf85a1SEason Yen } 4639cdf85a1SEason Yen EXPORT_SYMBOL_GPL(mtk_memif_set_channel); 4649cdf85a1SEason Yen 4659cdf85a1SEason Yen static int mtk_memif_set_rate_fs(struct mtk_base_afe *afe, 4669cdf85a1SEason Yen int id, int fs) 4679cdf85a1SEason Yen { 4689cdf85a1SEason Yen struct mtk_base_afe_memif *memif = &afe->memif[id]; 4699cdf85a1SEason Yen 4709cdf85a1SEason Yen if (memif->data->fs_shift >= 0) 4719cdf85a1SEason Yen mtk_regmap_update_bits(afe->regmap, memif->data->fs_reg, 4729cdf85a1SEason Yen memif->data->fs_maskbit, 4739cdf85a1SEason Yen fs, memif->data->fs_shift); 4749cdf85a1SEason Yen 4759cdf85a1SEason Yen return 0; 4769cdf85a1SEason Yen } 4779cdf85a1SEason Yen 4789cdf85a1SEason Yen int mtk_memif_set_rate(struct mtk_base_afe *afe, 4799cdf85a1SEason Yen int id, unsigned int rate) 4809cdf85a1SEason Yen { 4819cdf85a1SEason Yen int fs = 0; 4829cdf85a1SEason Yen 4839cdf85a1SEason Yen if (!afe->get_dai_fs) { 4849cdf85a1SEason Yen dev_err(afe->dev, "%s(), error, afe->get_dai_fs == NULL\n", 4859cdf85a1SEason Yen __func__); 4869cdf85a1SEason Yen return -EINVAL; 4879cdf85a1SEason Yen } 4889cdf85a1SEason Yen 4899cdf85a1SEason Yen fs = afe->get_dai_fs(afe, id, rate); 4909cdf85a1SEason Yen 4919cdf85a1SEason Yen if (fs < 0) 4929cdf85a1SEason Yen return -EINVAL; 4939cdf85a1SEason Yen 4949cdf85a1SEason Yen return mtk_memif_set_rate_fs(afe, id, fs); 4959cdf85a1SEason Yen } 4969cdf85a1SEason Yen EXPORT_SYMBOL_GPL(mtk_memif_set_rate); 4979cdf85a1SEason Yen 4989cdf85a1SEason Yen int mtk_memif_set_rate_substream(struct snd_pcm_substream *substream, 4999cdf85a1SEason Yen int id, unsigned int rate) 5009cdf85a1SEason Yen { 5019cdf85a1SEason Yen struct snd_soc_pcm_runtime *rtd = substream->private_data; 5029cdf85a1SEason Yen struct snd_soc_component *component = 5039cdf85a1SEason Yen snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 5049cdf85a1SEason Yen struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 5059cdf85a1SEason Yen 5069cdf85a1SEason Yen int fs = 0; 5079cdf85a1SEason Yen 5089cdf85a1SEason Yen if (!afe->memif_fs) { 5099cdf85a1SEason Yen dev_err(afe->dev, "%s(), error, afe->memif_fs == NULL\n", 5109cdf85a1SEason Yen __func__); 5119cdf85a1SEason Yen return -EINVAL; 5129cdf85a1SEason Yen } 5139cdf85a1SEason Yen 5149cdf85a1SEason Yen fs = afe->memif_fs(substream, rate); 5159cdf85a1SEason Yen 5169cdf85a1SEason Yen if (fs < 0) 5179cdf85a1SEason Yen return -EINVAL; 5189cdf85a1SEason Yen 5199cdf85a1SEason Yen return mtk_memif_set_rate_fs(afe, id, fs); 5209cdf85a1SEason Yen } 5219cdf85a1SEason Yen EXPORT_SYMBOL_GPL(mtk_memif_set_rate_substream); 5229cdf85a1SEason Yen 5239cdf85a1SEason Yen int mtk_memif_set_format(struct mtk_base_afe *afe, 5249cdf85a1SEason Yen int id, snd_pcm_format_t format) 5259cdf85a1SEason Yen { 5269cdf85a1SEason Yen struct mtk_base_afe_memif *memif = &afe->memif[id]; 5279cdf85a1SEason Yen int hd_audio = 0; 5289cdf85a1SEason Yen int hd_align = 0; 5299cdf85a1SEason Yen 5309cdf85a1SEason Yen /* set hd mode */ 5319cdf85a1SEason Yen switch (format) { 5329cdf85a1SEason Yen case SNDRV_PCM_FORMAT_S16_LE: 5339cdf85a1SEason Yen case SNDRV_PCM_FORMAT_U16_LE: 5349cdf85a1SEason Yen hd_audio = 0; 5359cdf85a1SEason Yen break; 5369cdf85a1SEason Yen case SNDRV_PCM_FORMAT_S32_LE: 5379cdf85a1SEason Yen case SNDRV_PCM_FORMAT_U32_LE: 5389cdf85a1SEason Yen hd_audio = 1; 5399cdf85a1SEason Yen hd_align = 1; 5409cdf85a1SEason Yen break; 5419cdf85a1SEason Yen case SNDRV_PCM_FORMAT_S24_LE: 5429cdf85a1SEason Yen case SNDRV_PCM_FORMAT_U24_LE: 5439cdf85a1SEason Yen hd_audio = 1; 5449cdf85a1SEason Yen break; 5459cdf85a1SEason Yen default: 5469cdf85a1SEason Yen dev_err(afe->dev, "%s() error: unsupported format %d\n", 5479cdf85a1SEason Yen __func__, format); 5489cdf85a1SEason Yen break; 5499cdf85a1SEason Yen } 5509cdf85a1SEason Yen 5519cdf85a1SEason Yen mtk_regmap_update_bits(afe->regmap, memif->data->hd_reg, 5529cdf85a1SEason Yen 1, hd_audio, memif->data->hd_shift); 5539cdf85a1SEason Yen 5549cdf85a1SEason Yen mtk_regmap_update_bits(afe->regmap, memif->data->hd_align_reg, 5559cdf85a1SEason Yen 1, hd_align, memif->data->hd_align_mshift); 5569cdf85a1SEason Yen 5579cdf85a1SEason Yen return 0; 5589cdf85a1SEason Yen } 5599cdf85a1SEason Yen EXPORT_SYMBOL_GPL(mtk_memif_set_format); 5609cdf85a1SEason Yen 5619cdf85a1SEason Yen int mtk_memif_set_pbuf_size(struct mtk_base_afe *afe, 5629cdf85a1SEason Yen int id, int pbuf_size) 5639cdf85a1SEason Yen { 5649cdf85a1SEason Yen const struct mtk_base_memif_data *memif_data = afe->memif[id].data; 5659cdf85a1SEason Yen 5669cdf85a1SEason Yen if (memif_data->pbuf_mask == 0 || memif_data->minlen_mask == 0) 5679cdf85a1SEason Yen return 0; 5689cdf85a1SEason Yen 5699cdf85a1SEason Yen mtk_regmap_update_bits(afe->regmap, memif_data->pbuf_reg, 5709cdf85a1SEason Yen memif_data->pbuf_mask, 5719cdf85a1SEason Yen pbuf_size, memif_data->pbuf_shift); 5729cdf85a1SEason Yen 5739cdf85a1SEason Yen mtk_regmap_update_bits(afe->regmap, memif_data->minlen_reg, 5749cdf85a1SEason Yen memif_data->minlen_mask, 5759cdf85a1SEason Yen pbuf_size, memif_data->minlen_shift); 5769cdf85a1SEason Yen return 0; 5779cdf85a1SEason Yen } 5789cdf85a1SEason Yen EXPORT_SYMBOL_GPL(mtk_memif_set_pbuf_size); 5799cdf85a1SEason Yen 580283b6124SGarlic Tseng MODULE_DESCRIPTION("Mediatek simple fe dai operator"); 581283b6124SGarlic Tseng MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>"); 582283b6124SGarlic Tseng MODULE_LICENSE("GPL v2"); 583