1 /* 2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * You should have received a copy of the GNU General Public License along 10 * with this program; if not, write to the Free Software Foundation, Inc., 11 * 675 Mass Ave, Cambridge, MA 02139, USA. 12 * 13 */ 14 15 #include <linux/init.h> 16 #include <linux/io.h> 17 #include <linux/of.h> 18 #include <linux/of_device.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/platform_device.h> 22 #include <linux/slab.h> 23 24 #include <linux/clk.h> 25 #include <linux/delay.h> 26 27 #include <linux/dma-mapping.h> 28 29 #include <sound/core.h> 30 #include <sound/pcm.h> 31 #include <sound/pcm_params.h> 32 #include <sound/soc.h> 33 #include <sound/initval.h> 34 #include <sound/dmaengine_pcm.h> 35 36 #include "jz4740-i2s.h" 37 38 #define JZ4740_DMA_TYPE_AIC_TRANSMIT 24 39 #define JZ4740_DMA_TYPE_AIC_RECEIVE 25 40 41 #define JZ_REG_AIC_CONF 0x00 42 #define JZ_REG_AIC_CTRL 0x04 43 #define JZ_REG_AIC_I2S_FMT 0x10 44 #define JZ_REG_AIC_FIFO_STATUS 0x14 45 #define JZ_REG_AIC_I2S_STATUS 0x1c 46 #define JZ_REG_AIC_CLK_DIV 0x30 47 #define JZ_REG_AIC_FIFO 0x34 48 49 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12) 50 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8) 51 #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) 52 #define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) 53 #define JZ_AIC_CONF_I2S BIT(4) 54 #define JZ_AIC_CONF_RESET BIT(3) 55 #define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) 56 #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) 57 #define JZ_AIC_CONF_ENABLE BIT(0) 58 59 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12 60 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8 61 #define JZ4780_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 24 62 #define JZ4780_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 16 63 #define JZ4780_AIC_CONF_FIFO_RX_THRESHOLD_MASK \ 64 (0xf << JZ4780_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) 65 #define JZ4780_AIC_CONF_FIFO_TX_THRESHOLD_MASK \ 66 (0x1f << JZ4780_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) 67 68 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19) 69 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16) 70 #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) 71 #define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) 72 #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) 73 #define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) 74 #define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) 75 #define JZ_AIC_CTRL_FLUSH BIT(8) 76 #define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) 77 #define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) 78 #define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) 79 #define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) 80 #define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) 81 #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) 82 #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) 83 84 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19 85 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16 86 87 #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) 88 #define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) 89 #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) 90 #define JZ_AIC_I2S_FMT_MSB BIT(0) 91 92 #define JZ_AIC_I2S_STATUS_BUSY BIT(2) 93 94 #define JZ_AIC_CLK_DIV_MASK 0xf 95 #define I2SDIV_DV_SHIFT 8 96 #define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT) 97 #define I2SDIV_IDV_SHIFT 8 98 #define I2SDIV_IDV_MASK (0xf << I2SDIV_IDV_SHIFT) 99 100 enum jz47xx_i2s_version { 101 JZ_I2S_JZ4740, 102 JZ_I2S_JZ4780, 103 }; 104 105 struct jz4740_i2s { 106 struct resource *mem; 107 void __iomem *base; 108 dma_addr_t phys_base; 109 110 struct clk *clk_aic; 111 struct clk *clk_i2s; 112 113 struct snd_dmaengine_dai_dma_data playback_dma_data; 114 struct snd_dmaengine_dai_dma_data capture_dma_data; 115 116 enum jz47xx_i2s_version version; 117 }; 118 119 static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s, 120 unsigned int reg) 121 { 122 return readl(i2s->base + reg); 123 } 124 125 static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s, 126 unsigned int reg, uint32_t value) 127 { 128 writel(value, i2s->base + reg); 129 } 130 131 static int jz4740_i2s_startup(struct snd_pcm_substream *substream, 132 struct snd_soc_dai *dai) 133 { 134 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 135 uint32_t conf, ctrl; 136 int ret; 137 138 if (dai->active) 139 return 0; 140 141 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); 142 ctrl |= JZ_AIC_CTRL_FLUSH; 143 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); 144 145 ret = clk_prepare_enable(i2s->clk_i2s); 146 if (ret) 147 return ret; 148 149 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); 150 conf |= JZ_AIC_CONF_ENABLE; 151 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); 152 153 return 0; 154 } 155 156 static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream, 157 struct snd_soc_dai *dai) 158 { 159 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 160 uint32_t conf; 161 162 if (dai->active) 163 return; 164 165 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); 166 conf &= ~JZ_AIC_CONF_ENABLE; 167 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); 168 169 clk_disable_unprepare(i2s->clk_i2s); 170 } 171 172 static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 173 struct snd_soc_dai *dai) 174 { 175 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 176 177 uint32_t ctrl; 178 uint32_t mask; 179 180 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 181 mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA; 182 else 183 mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA; 184 185 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); 186 187 switch (cmd) { 188 case SNDRV_PCM_TRIGGER_START: 189 case SNDRV_PCM_TRIGGER_RESUME: 190 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 191 ctrl |= mask; 192 break; 193 case SNDRV_PCM_TRIGGER_STOP: 194 case SNDRV_PCM_TRIGGER_SUSPEND: 195 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 196 ctrl &= ~mask; 197 break; 198 default: 199 return -EINVAL; 200 } 201 202 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); 203 204 return 0; 205 } 206 207 static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 208 { 209 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 210 211 uint32_t format = 0; 212 uint32_t conf; 213 214 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); 215 216 conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER); 217 218 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 219 case SND_SOC_DAIFMT_CBS_CFS: 220 conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER; 221 format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK; 222 break; 223 case SND_SOC_DAIFMT_CBM_CFS: 224 conf |= JZ_AIC_CONF_SYNC_CLK_MASTER; 225 break; 226 case SND_SOC_DAIFMT_CBS_CFM: 227 conf |= JZ_AIC_CONF_BIT_CLK_MASTER; 228 break; 229 case SND_SOC_DAIFMT_CBM_CFM: 230 break; 231 default: 232 return -EINVAL; 233 } 234 235 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 236 case SND_SOC_DAIFMT_MSB: 237 format |= JZ_AIC_I2S_FMT_MSB; 238 break; 239 case SND_SOC_DAIFMT_I2S: 240 break; 241 default: 242 return -EINVAL; 243 } 244 245 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 246 case SND_SOC_DAIFMT_NB_NF: 247 break; 248 default: 249 return -EINVAL; 250 } 251 252 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); 253 jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format); 254 255 return 0; 256 } 257 258 static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, 259 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 260 { 261 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 262 unsigned int sample_size; 263 uint32_t ctrl, div_reg; 264 int div; 265 266 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); 267 268 div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV); 269 div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params)); 270 271 switch (params_format(params)) { 272 case SNDRV_PCM_FORMAT_S8: 273 sample_size = 0; 274 break; 275 case SNDRV_PCM_FORMAT_S16: 276 sample_size = 1; 277 break; 278 default: 279 return -EINVAL; 280 } 281 282 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 283 ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK; 284 ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET; 285 if (params_channels(params) == 1) 286 ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO; 287 else 288 ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO; 289 290 div_reg &= ~I2SDIV_DV_MASK; 291 div_reg |= (div - 1) << I2SDIV_DV_SHIFT; 292 } else { 293 ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK; 294 ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET; 295 296 if (i2s->version >= JZ_I2S_JZ4780) { 297 div_reg &= ~I2SDIV_IDV_MASK; 298 div_reg |= (div - 1) << I2SDIV_IDV_SHIFT; 299 } else { 300 div_reg &= ~I2SDIV_DV_MASK; 301 div_reg |= (div - 1) << I2SDIV_DV_SHIFT; 302 } 303 } 304 305 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); 306 jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg); 307 308 return 0; 309 } 310 311 static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, 312 unsigned int freq, int dir) 313 { 314 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 315 struct clk *parent; 316 int ret = 0; 317 318 switch (clk_id) { 319 case JZ4740_I2S_CLKSRC_EXT: 320 parent = clk_get(NULL, "ext"); 321 clk_set_parent(i2s->clk_i2s, parent); 322 break; 323 case JZ4740_I2S_CLKSRC_PLL: 324 parent = clk_get(NULL, "pll half"); 325 clk_set_parent(i2s->clk_i2s, parent); 326 ret = clk_set_rate(i2s->clk_i2s, freq); 327 break; 328 default: 329 return -EINVAL; 330 } 331 clk_put(parent); 332 333 return ret; 334 } 335 336 static int jz4740_i2s_suspend(struct snd_soc_dai *dai) 337 { 338 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 339 uint32_t conf; 340 341 if (dai->active) { 342 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); 343 conf &= ~JZ_AIC_CONF_ENABLE; 344 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); 345 346 clk_disable_unprepare(i2s->clk_i2s); 347 } 348 349 clk_disable_unprepare(i2s->clk_aic); 350 351 return 0; 352 } 353 354 static int jz4740_i2s_resume(struct snd_soc_dai *dai) 355 { 356 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 357 uint32_t conf; 358 int ret; 359 360 ret = clk_prepare_enable(i2s->clk_aic); 361 if (ret) 362 return ret; 363 364 if (dai->active) { 365 ret = clk_prepare_enable(i2s->clk_i2s); 366 if (ret) { 367 clk_disable_unprepare(i2s->clk_aic); 368 return ret; 369 } 370 371 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); 372 conf |= JZ_AIC_CONF_ENABLE; 373 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); 374 } 375 376 return 0; 377 } 378 379 static void jz4740_i2c_init_pcm_config(struct jz4740_i2s *i2s) 380 { 381 struct snd_dmaengine_dai_dma_data *dma_data; 382 383 /* Playback */ 384 dma_data = &i2s->playback_dma_data; 385 dma_data->maxburst = 16; 386 dma_data->slave_id = JZ4740_DMA_TYPE_AIC_TRANSMIT; 387 dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO; 388 389 /* Capture */ 390 dma_data = &i2s->capture_dma_data; 391 dma_data->maxburst = 16; 392 dma_data->slave_id = JZ4740_DMA_TYPE_AIC_RECEIVE; 393 dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO; 394 } 395 396 static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) 397 { 398 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 399 uint32_t conf; 400 int ret; 401 402 ret = clk_prepare_enable(i2s->clk_aic); 403 if (ret) 404 return ret; 405 406 jz4740_i2c_init_pcm_config(i2s); 407 snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data, 408 &i2s->capture_dma_data); 409 410 if (i2s->version >= JZ_I2S_JZ4780) { 411 conf = (7 << JZ4780_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) | 412 (8 << JZ4780_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) | 413 JZ_AIC_CONF_OVERFLOW_PLAY_LAST | 414 JZ_AIC_CONF_I2S | 415 JZ_AIC_CONF_INTERNAL_CODEC; 416 } else { 417 conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) | 418 (8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) | 419 JZ_AIC_CONF_OVERFLOW_PLAY_LAST | 420 JZ_AIC_CONF_I2S | 421 JZ_AIC_CONF_INTERNAL_CODEC; 422 } 423 424 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); 425 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); 426 427 return 0; 428 } 429 430 static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai) 431 { 432 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 433 434 clk_disable_unprepare(i2s->clk_aic); 435 return 0; 436 } 437 438 static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = { 439 .startup = jz4740_i2s_startup, 440 .shutdown = jz4740_i2s_shutdown, 441 .trigger = jz4740_i2s_trigger, 442 .hw_params = jz4740_i2s_hw_params, 443 .set_fmt = jz4740_i2s_set_fmt, 444 .set_sysclk = jz4740_i2s_set_sysclk, 445 }; 446 447 #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 448 SNDRV_PCM_FMTBIT_S16_LE) 449 450 static struct snd_soc_dai_driver jz4740_i2s_dai = { 451 .probe = jz4740_i2s_dai_probe, 452 .remove = jz4740_i2s_dai_remove, 453 .playback = { 454 .channels_min = 1, 455 .channels_max = 2, 456 .rates = SNDRV_PCM_RATE_8000_48000, 457 .formats = JZ4740_I2S_FMTS, 458 }, 459 .capture = { 460 .channels_min = 2, 461 .channels_max = 2, 462 .rates = SNDRV_PCM_RATE_8000_48000, 463 .formats = JZ4740_I2S_FMTS, 464 }, 465 .symmetric_rates = 1, 466 .ops = &jz4740_i2s_dai_ops, 467 .suspend = jz4740_i2s_suspend, 468 .resume = jz4740_i2s_resume, 469 }; 470 471 static struct snd_soc_dai_driver jz4780_i2s_dai = { 472 .probe = jz4740_i2s_dai_probe, 473 .remove = jz4740_i2s_dai_remove, 474 .playback = { 475 .channels_min = 1, 476 .channels_max = 2, 477 .rates = SNDRV_PCM_RATE_8000_48000, 478 .formats = JZ4740_I2S_FMTS, 479 }, 480 .capture = { 481 .channels_min = 2, 482 .channels_max = 2, 483 .rates = SNDRV_PCM_RATE_8000_48000, 484 .formats = JZ4740_I2S_FMTS, 485 }, 486 .ops = &jz4740_i2s_dai_ops, 487 .suspend = jz4740_i2s_suspend, 488 .resume = jz4740_i2s_resume, 489 }; 490 491 static const struct snd_soc_component_driver jz4740_i2s_component = { 492 .name = "jz4740-i2s", 493 }; 494 495 #ifdef CONFIG_OF 496 static const struct of_device_id jz4740_of_matches[] = { 497 { .compatible = "ingenic,jz4740-i2s", .data = (void *)JZ_I2S_JZ4740 }, 498 { .compatible = "ingenic,jz4780-i2s", .data = (void *)JZ_I2S_JZ4780 }, 499 { /* sentinel */ } 500 }; 501 MODULE_DEVICE_TABLE(of, jz4740_of_matches); 502 #endif 503 504 static int jz4740_i2s_dev_probe(struct platform_device *pdev) 505 { 506 struct jz4740_i2s *i2s; 507 struct resource *mem; 508 int ret; 509 const struct of_device_id *match; 510 511 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); 512 if (!i2s) 513 return -ENOMEM; 514 515 match = of_match_device(jz4740_of_matches, &pdev->dev); 516 if (match) 517 i2s->version = (enum jz47xx_i2s_version)match->data; 518 519 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 520 i2s->base = devm_ioremap_resource(&pdev->dev, mem); 521 if (IS_ERR(i2s->base)) 522 return PTR_ERR(i2s->base); 523 524 i2s->phys_base = mem->start; 525 526 i2s->clk_aic = devm_clk_get(&pdev->dev, "aic"); 527 if (IS_ERR(i2s->clk_aic)) 528 return PTR_ERR(i2s->clk_aic); 529 530 i2s->clk_i2s = devm_clk_get(&pdev->dev, "i2s"); 531 if (IS_ERR(i2s->clk_i2s)) 532 return PTR_ERR(i2s->clk_i2s); 533 534 platform_set_drvdata(pdev, i2s); 535 536 if (i2s->version == JZ_I2S_JZ4780) 537 ret = devm_snd_soc_register_component(&pdev->dev, 538 &jz4740_i2s_component, &jz4780_i2s_dai, 1); 539 else 540 ret = devm_snd_soc_register_component(&pdev->dev, 541 &jz4740_i2s_component, &jz4740_i2s_dai, 1); 542 543 if (ret) 544 return ret; 545 546 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 547 SND_DMAENGINE_PCM_FLAG_COMPAT); 548 } 549 550 static struct platform_driver jz4740_i2s_driver = { 551 .probe = jz4740_i2s_dev_probe, 552 .driver = { 553 .name = "jz4740-i2s", 554 .of_match_table = of_match_ptr(jz4740_of_matches) 555 }, 556 }; 557 558 module_platform_driver(jz4740_i2s_driver); 559 560 MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>"); 561 MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver"); 562 MODULE_LICENSE("GPL"); 563 MODULE_ALIAS("platform:jz4740-i2s"); 564