1 /* 2 * skl.c - Implementation of ASoC Intel SKL HD Audio driver 3 * 4 * Copyright (C) 2014-2015 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * 7 * Derived mostly from Intel HDA driver with following copyrights: 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; version 2 of the License. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 22 */ 23 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/platform_device.h> 28 #include <linux/firmware.h> 29 #include <linux/delay.h> 30 #include <sound/pcm.h> 31 #include <sound/soc-acpi.h> 32 #include <sound/hda_register.h> 33 #include <sound/hdaudio.h> 34 #include <sound/hda_i915.h> 35 #include "skl.h" 36 #include "skl-sst-dsp.h" 37 #include "skl-sst-ipc.h" 38 39 static struct skl_machine_pdata skl_dmic_data; 40 41 /* 42 * initialize the PCI registers 43 */ 44 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, 45 unsigned char mask, unsigned char val) 46 { 47 unsigned char data; 48 49 pci_read_config_byte(pci, reg, &data); 50 data &= ~mask; 51 data |= (val & mask); 52 pci_write_config_byte(pci, reg, data); 53 } 54 55 static void skl_init_pci(struct skl *skl) 56 { 57 struct hdac_ext_bus *ebus = &skl->ebus; 58 59 /* 60 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 61 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 62 * Ensuring these bits are 0 clears playback static on some HD Audio 63 * codecs. 64 * The PCI register TCSEL is defined in the Intel manuals. 65 */ 66 dev_dbg(ebus_to_hbus(ebus)->dev, "Clearing TCSEL\n"); 67 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); 68 } 69 70 static void update_pci_dword(struct pci_dev *pci, 71 unsigned int reg, u32 mask, u32 val) 72 { 73 u32 data = 0; 74 75 pci_read_config_dword(pci, reg, &data); 76 data &= ~mask; 77 data |= (val & mask); 78 pci_write_config_dword(pci, reg, data); 79 } 80 81 /* 82 * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits 83 * 84 * @dev: device pointer 85 * @enable: enable/disable flag 86 */ 87 static void skl_enable_miscbdcge(struct device *dev, bool enable) 88 { 89 struct pci_dev *pci = to_pci_dev(dev); 90 u32 val; 91 92 val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; 93 94 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); 95 } 96 97 /** 98 * skl_clock_power_gating: Enable/Disable clock and power gating 99 * 100 * @dev: Device pointer 101 * @enable: Enable/Disable flag 102 */ 103 static void skl_clock_power_gating(struct device *dev, bool enable) 104 { 105 struct pci_dev *pci = to_pci_dev(dev); 106 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 107 struct hdac_bus *bus = ebus_to_hbus(ebus); 108 u32 val; 109 110 /* Update PDCGE bit of CGCTL register */ 111 val = enable ? AZX_CGCTL_ADSPDCGE : 0; 112 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); 113 114 /* Update L1SEN bit of EM2 register */ 115 val = enable ? AZX_REG_VS_EM2_L1SEN : 0; 116 snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val); 117 118 /* Update ADSPPGD bit of PGCTL register */ 119 val = enable ? 0 : AZX_PGCTL_ADSPPGD; 120 update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val); 121 } 122 123 /* 124 * While performing reset, controller may not come back properly causing 125 * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset 126 * (init chip) and then again set CGCTL.MISCBDCGE to 1 127 */ 128 static int skl_init_chip(struct hdac_bus *bus, bool full_reset) 129 { 130 struct hdac_ext_bus *ebus = hbus_to_ebus(bus); 131 struct hdac_ext_link *hlink; 132 int ret; 133 134 skl_enable_miscbdcge(bus->dev, false); 135 ret = snd_hdac_bus_init_chip(bus, full_reset); 136 137 /* Reset stream-to-link mapping */ 138 list_for_each_entry(hlink, &ebus->hlink_list, list) 139 bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV); 140 141 skl_enable_miscbdcge(bus->dev, true); 142 143 return ret; 144 } 145 146 void skl_update_d0i3c(struct device *dev, bool enable) 147 { 148 struct pci_dev *pci = to_pci_dev(dev); 149 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 150 struct hdac_bus *bus = ebus_to_hbus(ebus); 151 u8 reg; 152 int timeout = 50; 153 154 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 155 /* Do not write to D0I3C until command in progress bit is cleared */ 156 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 157 udelay(10); 158 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 159 } 160 161 /* Highly unlikely. But if it happens, flag error explicitly */ 162 if (!timeout) { 163 dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n"); 164 return; 165 } 166 167 if (enable) 168 reg = reg | AZX_REG_VS_D0I3C_I3; 169 else 170 reg = reg & (~AZX_REG_VS_D0I3C_I3); 171 172 snd_hdac_chip_writeb(bus, VS_D0I3C, reg); 173 174 timeout = 50; 175 /* Wait for cmd in progress to be cleared before exiting the function */ 176 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 177 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 178 udelay(10); 179 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 180 } 181 182 /* Highly unlikely. But if it happens, flag error explicitly */ 183 if (!timeout) { 184 dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n"); 185 return; 186 } 187 188 dev_dbg(bus->dev, "D0I3C register = 0x%x\n", 189 snd_hdac_chip_readb(bus, VS_D0I3C)); 190 } 191 192 /* called from IRQ */ 193 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) 194 { 195 snd_pcm_period_elapsed(hstr->substream); 196 } 197 198 static irqreturn_t skl_interrupt(int irq, void *dev_id) 199 { 200 struct hdac_ext_bus *ebus = dev_id; 201 struct hdac_bus *bus = ebus_to_hbus(ebus); 202 u32 status; 203 204 if (!pm_runtime_active(bus->dev)) 205 return IRQ_NONE; 206 207 spin_lock(&bus->reg_lock); 208 209 status = snd_hdac_chip_readl(bus, INTSTS); 210 if (status == 0 || status == 0xffffffff) { 211 spin_unlock(&bus->reg_lock); 212 return IRQ_NONE; 213 } 214 215 /* clear rirb int */ 216 status = snd_hdac_chip_readb(bus, RIRBSTS); 217 if (status & RIRB_INT_MASK) { 218 if (status & RIRB_INT_RESPONSE) 219 snd_hdac_bus_update_rirb(bus); 220 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 221 } 222 223 spin_unlock(&bus->reg_lock); 224 225 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; 226 } 227 228 static irqreturn_t skl_threaded_handler(int irq, void *dev_id) 229 { 230 struct hdac_ext_bus *ebus = dev_id; 231 struct hdac_bus *bus = ebus_to_hbus(ebus); 232 u32 status; 233 234 status = snd_hdac_chip_readl(bus, INTSTS); 235 236 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); 237 238 return IRQ_HANDLED; 239 } 240 241 static int skl_acquire_irq(struct hdac_ext_bus *ebus, int do_disconnect) 242 { 243 struct skl *skl = ebus_to_skl(ebus); 244 struct hdac_bus *bus = ebus_to_hbus(ebus); 245 int ret; 246 247 ret = request_threaded_irq(skl->pci->irq, skl_interrupt, 248 skl_threaded_handler, 249 IRQF_SHARED, 250 KBUILD_MODNAME, ebus); 251 if (ret) { 252 dev_err(bus->dev, 253 "unable to grab IRQ %d, disabling device\n", 254 skl->pci->irq); 255 return ret; 256 } 257 258 bus->irq = skl->pci->irq; 259 pci_intx(skl->pci, 1); 260 261 return 0; 262 } 263 264 static int skl_suspend_late(struct device *dev) 265 { 266 struct pci_dev *pci = to_pci_dev(dev); 267 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 268 struct skl *skl = ebus_to_skl(ebus); 269 270 return skl_suspend_late_dsp(skl); 271 } 272 273 #ifdef CONFIG_PM 274 static int _skl_suspend(struct hdac_ext_bus *ebus) 275 { 276 struct skl *skl = ebus_to_skl(ebus); 277 struct hdac_bus *bus = ebus_to_hbus(ebus); 278 struct pci_dev *pci = to_pci_dev(bus->dev); 279 int ret; 280 281 snd_hdac_ext_bus_link_power_down_all(ebus); 282 283 ret = skl_suspend_dsp(skl); 284 if (ret < 0) 285 return ret; 286 287 snd_hdac_bus_stop_chip(bus); 288 update_pci_dword(pci, AZX_PCIREG_PGCTL, 289 AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK); 290 skl_enable_miscbdcge(bus->dev, false); 291 snd_hdac_bus_enter_link_reset(bus); 292 skl_enable_miscbdcge(bus->dev, true); 293 skl_cleanup_resources(skl); 294 295 return 0; 296 } 297 298 static int _skl_resume(struct hdac_ext_bus *ebus) 299 { 300 struct skl *skl = ebus_to_skl(ebus); 301 struct hdac_bus *bus = ebus_to_hbus(ebus); 302 303 skl_init_pci(skl); 304 skl_init_chip(bus, true); 305 306 return skl_resume_dsp(skl); 307 } 308 #endif 309 310 #ifdef CONFIG_PM_SLEEP 311 /* 312 * power management 313 */ 314 static int skl_suspend(struct device *dev) 315 { 316 struct pci_dev *pci = to_pci_dev(dev); 317 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 318 struct skl *skl = ebus_to_skl(ebus); 319 struct hdac_bus *bus = ebus_to_hbus(ebus); 320 int ret = 0; 321 322 /* 323 * Do not suspend if streams which are marked ignore suspend are 324 * running, we need to save the state for these and continue 325 */ 326 if (skl->supend_active) { 327 /* turn off the links and stop the CORB/RIRB DMA if it is On */ 328 snd_hdac_ext_bus_link_power_down_all(ebus); 329 330 if (ebus->cmd_dma_state) 331 snd_hdac_bus_stop_cmd_io(&ebus->bus); 332 333 enable_irq_wake(bus->irq); 334 pci_save_state(pci); 335 } else { 336 ret = _skl_suspend(ebus); 337 if (ret < 0) 338 return ret; 339 skl->skl_sst->fw_loaded = false; 340 } 341 342 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 343 ret = snd_hdac_display_power(bus, false); 344 if (ret < 0) 345 dev_err(bus->dev, 346 "Cannot turn OFF display power on i915\n"); 347 } 348 349 return ret; 350 } 351 352 static int skl_resume(struct device *dev) 353 { 354 struct pci_dev *pci = to_pci_dev(dev); 355 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 356 struct skl *skl = ebus_to_skl(ebus); 357 struct hdac_bus *bus = ebus_to_hbus(ebus); 358 struct hdac_ext_link *hlink = NULL; 359 int ret; 360 361 /* Turned OFF in HDMI codec driver after codec reconfiguration */ 362 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 363 ret = snd_hdac_display_power(bus, true); 364 if (ret < 0) { 365 dev_err(bus->dev, 366 "Cannot turn on display power on i915\n"); 367 return ret; 368 } 369 } 370 371 /* 372 * resume only when we are not in suspend active, otherwise need to 373 * restore the device 374 */ 375 if (skl->supend_active) { 376 pci_restore_state(pci); 377 snd_hdac_ext_bus_link_power_up_all(ebus); 378 disable_irq_wake(bus->irq); 379 /* 380 * turn On the links which are On before active suspend 381 * and start the CORB/RIRB DMA if On before 382 * active suspend. 383 */ 384 list_for_each_entry(hlink, &ebus->hlink_list, list) { 385 if (hlink->ref_count) 386 snd_hdac_ext_bus_link_power_up(hlink); 387 } 388 389 if (ebus->cmd_dma_state) 390 snd_hdac_bus_init_cmd_io(&ebus->bus); 391 ret = 0; 392 } else { 393 ret = _skl_resume(ebus); 394 395 /* turn off the links which are off before suspend */ 396 list_for_each_entry(hlink, &ebus->hlink_list, list) { 397 if (!hlink->ref_count) 398 snd_hdac_ext_bus_link_power_down(hlink); 399 } 400 401 if (!ebus->cmd_dma_state) 402 snd_hdac_bus_stop_cmd_io(&ebus->bus); 403 } 404 405 return ret; 406 } 407 #endif /* CONFIG_PM_SLEEP */ 408 409 #ifdef CONFIG_PM 410 static int skl_runtime_suspend(struct device *dev) 411 { 412 struct pci_dev *pci = to_pci_dev(dev); 413 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 414 struct hdac_bus *bus = ebus_to_hbus(ebus); 415 416 dev_dbg(bus->dev, "in %s\n", __func__); 417 418 return _skl_suspend(ebus); 419 } 420 421 static int skl_runtime_resume(struct device *dev) 422 { 423 struct pci_dev *pci = to_pci_dev(dev); 424 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 425 struct hdac_bus *bus = ebus_to_hbus(ebus); 426 427 dev_dbg(bus->dev, "in %s\n", __func__); 428 429 return _skl_resume(ebus); 430 } 431 #endif /* CONFIG_PM */ 432 433 static const struct dev_pm_ops skl_pm = { 434 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) 435 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) 436 .suspend_late = skl_suspend_late, 437 }; 438 439 /* 440 * destructor 441 */ 442 static int skl_free(struct hdac_ext_bus *ebus) 443 { 444 struct skl *skl = ebus_to_skl(ebus); 445 struct hdac_bus *bus = ebus_to_hbus(ebus); 446 447 skl->init_done = 0; /* to be sure */ 448 449 snd_hdac_ext_stop_streams(ebus); 450 451 if (bus->irq >= 0) 452 free_irq(bus->irq, (void *)ebus); 453 snd_hdac_bus_free_stream_pages(bus); 454 snd_hdac_stream_free_all(ebus); 455 snd_hdac_link_free_all(ebus); 456 457 if (bus->remap_addr) 458 iounmap(bus->remap_addr); 459 460 pci_release_regions(skl->pci); 461 pci_disable_device(skl->pci); 462 463 snd_hdac_ext_bus_exit(ebus); 464 465 cancel_work_sync(&skl->probe_work); 466 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 467 snd_hdac_i915_exit(&ebus->bus); 468 469 return 0; 470 } 471 472 /* 473 * For each ssp there are 3 clocks (mclk/sclk/sclkfs). 474 * e.g. for ssp0, clocks will be named as 475 * "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs" 476 * So for skl+, there are 6 ssps, so 18 clocks will be created. 477 */ 478 static struct skl_ssp_clk skl_ssp_clks[] = { 479 {.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"}, 480 {.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"}, 481 {.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"}, 482 {.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"}, 483 {.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"}, 484 {.name = "ssp2_sclkfs"}, 485 {.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"}, 486 {.name = "ssp5_sclkfs"}, 487 }; 488 489 static int skl_find_machine(struct skl *skl, void *driver_data) 490 { 491 struct snd_soc_acpi_mach *mach = driver_data; 492 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); 493 struct skl_machine_pdata *pdata; 494 495 mach = snd_soc_acpi_find_machine(mach); 496 if (mach == NULL) { 497 dev_err(bus->dev, "No matching machine driver found\n"); 498 return -ENODEV; 499 } 500 501 skl->mach = mach; 502 skl->fw_name = mach->fw_filename; 503 pdata = skl->mach->pdata; 504 505 if (mach->pdata) 506 skl->use_tplg_pcm = pdata->use_tplg_pcm; 507 508 return 0; 509 } 510 511 static int skl_machine_device_register(struct skl *skl) 512 { 513 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); 514 struct snd_soc_acpi_mach *mach = skl->mach; 515 struct platform_device *pdev; 516 int ret; 517 518 pdev = platform_device_alloc(mach->drv_name, -1); 519 if (pdev == NULL) { 520 dev_err(bus->dev, "platform device alloc failed\n"); 521 return -EIO; 522 } 523 524 ret = platform_device_add(pdev); 525 if (ret) { 526 dev_err(bus->dev, "failed to add machine device\n"); 527 platform_device_put(pdev); 528 return -EIO; 529 } 530 531 if (mach->pdata) 532 dev_set_drvdata(&pdev->dev, mach->pdata); 533 534 skl->i2s_dev = pdev; 535 536 return 0; 537 } 538 539 static void skl_machine_device_unregister(struct skl *skl) 540 { 541 if (skl->i2s_dev) 542 platform_device_unregister(skl->i2s_dev); 543 } 544 545 static int skl_dmic_device_register(struct skl *skl) 546 { 547 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); 548 struct platform_device *pdev; 549 int ret; 550 551 /* SKL has one dmic port, so allocate dmic device for this */ 552 pdev = platform_device_alloc("dmic-codec", -1); 553 if (!pdev) { 554 dev_err(bus->dev, "failed to allocate dmic device\n"); 555 return -ENOMEM; 556 } 557 558 ret = platform_device_add(pdev); 559 if (ret) { 560 dev_err(bus->dev, "failed to add dmic device: %d\n", ret); 561 platform_device_put(pdev); 562 return ret; 563 } 564 skl->dmic_dev = pdev; 565 566 return 0; 567 } 568 569 static void skl_dmic_device_unregister(struct skl *skl) 570 { 571 if (skl->dmic_dev) 572 platform_device_unregister(skl->dmic_dev); 573 } 574 575 static struct skl_clk_parent_src skl_clk_src[] = { 576 { .clk_id = SKL_XTAL, .name = "xtal" }, 577 { .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 }, 578 { .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 }, 579 }; 580 581 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id) 582 { 583 unsigned int i; 584 585 for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) { 586 if (skl_clk_src[i].clk_id == clk_id) 587 return &skl_clk_src[i]; 588 } 589 590 return NULL; 591 } 592 593 static void init_skl_xtal_rate(int pci_id) 594 { 595 switch (pci_id) { 596 case 0x9d70: 597 case 0x9d71: 598 skl_clk_src[0].rate = 24000000; 599 return; 600 601 default: 602 skl_clk_src[0].rate = 19200000; 603 return; 604 } 605 } 606 607 static int skl_clock_device_register(struct skl *skl) 608 { 609 struct platform_device_info pdevinfo = {NULL}; 610 struct skl_clk_pdata *clk_pdata; 611 612 clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata), 613 GFP_KERNEL); 614 if (!clk_pdata) 615 return -ENOMEM; 616 617 init_skl_xtal_rate(skl->pci->device); 618 619 clk_pdata->parent_clks = skl_clk_src; 620 clk_pdata->ssp_clks = skl_ssp_clks; 621 clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks); 622 623 /* Query NHLT to fill the rates and parent */ 624 skl_get_clks(skl, clk_pdata->ssp_clks); 625 clk_pdata->pvt_data = skl; 626 627 /* Register Platform device */ 628 pdevinfo.parent = &skl->pci->dev; 629 pdevinfo.id = -1; 630 pdevinfo.name = "skl-ssp-clk"; 631 pdevinfo.data = clk_pdata; 632 pdevinfo.size_data = sizeof(*clk_pdata); 633 skl->clk_dev = platform_device_register_full(&pdevinfo); 634 return PTR_ERR_OR_ZERO(skl->clk_dev); 635 } 636 637 static void skl_clock_device_unregister(struct skl *skl) 638 { 639 if (skl->clk_dev) 640 platform_device_unregister(skl->clk_dev); 641 } 642 643 /* 644 * Probe the given codec address 645 */ 646 static int probe_codec(struct hdac_ext_bus *ebus, int addr) 647 { 648 struct hdac_bus *bus = ebus_to_hbus(ebus); 649 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 650 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 651 unsigned int res = -1; 652 653 mutex_lock(&bus->cmd_mutex); 654 snd_hdac_bus_send_cmd(bus, cmd); 655 snd_hdac_bus_get_response(bus, addr, &res); 656 mutex_unlock(&bus->cmd_mutex); 657 if (res == -1) 658 return -EIO; 659 dev_dbg(bus->dev, "codec #%d probed OK\n", addr); 660 661 return snd_hdac_ext_bus_device_init(ebus, addr); 662 } 663 664 /* Codec initialization */ 665 static void skl_codec_create(struct hdac_ext_bus *ebus) 666 { 667 struct hdac_bus *bus = ebus_to_hbus(ebus); 668 int c, max_slots; 669 670 max_slots = HDA_MAX_CODECS; 671 672 /* First try to probe all given codec slots */ 673 for (c = 0; c < max_slots; c++) { 674 if ((bus->codec_mask & (1 << c))) { 675 if (probe_codec(ebus, c) < 0) { 676 /* 677 * Some BIOSen give you wrong codec addresses 678 * that don't exist 679 */ 680 dev_warn(bus->dev, 681 "Codec #%d probe error; disabling it...\n", c); 682 bus->codec_mask &= ~(1 << c); 683 /* 684 * More badly, accessing to a non-existing 685 * codec often screws up the controller bus, 686 * and disturbs the further communications. 687 * Thus if an error occurs during probing, 688 * better to reset the controller bus to get 689 * back to the sanity state. 690 */ 691 snd_hdac_bus_stop_chip(bus); 692 skl_init_chip(bus, true); 693 } 694 } 695 } 696 } 697 698 static const struct hdac_bus_ops bus_core_ops = { 699 .command = snd_hdac_bus_send_cmd, 700 .get_response = snd_hdac_bus_get_response, 701 }; 702 703 static int skl_i915_init(struct hdac_bus *bus) 704 { 705 int err; 706 707 /* 708 * The HDMI codec is in GPU so we need to ensure that it is powered 709 * up and ready for probe 710 */ 711 err = snd_hdac_i915_init(bus); 712 if (err < 0) 713 return err; 714 715 err = snd_hdac_display_power(bus, true); 716 if (err < 0) 717 dev_err(bus->dev, "Cannot turn on display power on i915\n"); 718 719 return err; 720 } 721 722 static void skl_probe_work(struct work_struct *work) 723 { 724 struct skl *skl = container_of(work, struct skl, probe_work); 725 struct hdac_ext_bus *ebus = &skl->ebus; 726 struct hdac_bus *bus = ebus_to_hbus(ebus); 727 struct hdac_ext_link *hlink = NULL; 728 int err; 729 730 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 731 err = skl_i915_init(bus); 732 if (err < 0) 733 return; 734 } 735 736 err = skl_init_chip(bus, true); 737 if (err < 0) { 738 dev_err(bus->dev, "Init chip failed with err: %d\n", err); 739 goto out_err; 740 } 741 742 /* codec detection */ 743 if (!bus->codec_mask) 744 dev_info(bus->dev, "no hda codecs found!\n"); 745 746 /* create codec instances */ 747 skl_codec_create(ebus); 748 749 /* register platform dai and controls */ 750 err = skl_platform_register(bus->dev); 751 if (err < 0) { 752 dev_err(bus->dev, "platform register failed: %d\n", err); 753 return; 754 } 755 756 if (bus->ppcap) { 757 err = skl_machine_device_register(skl); 758 if (err < 0) { 759 dev_err(bus->dev, "machine register failed: %d\n", err); 760 goto out_err; 761 } 762 } 763 764 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 765 err = snd_hdac_display_power(bus, false); 766 if (err < 0) { 767 dev_err(bus->dev, "Cannot turn off display power on i915\n"); 768 skl_machine_device_unregister(skl); 769 return; 770 } 771 } 772 773 /* 774 * we are done probing so decrement link counts 775 */ 776 list_for_each_entry(hlink, &ebus->hlink_list, list) 777 snd_hdac_ext_bus_link_put(ebus, hlink); 778 779 /* configure PM */ 780 pm_runtime_put_noidle(bus->dev); 781 pm_runtime_allow(bus->dev); 782 skl->init_done = 1; 783 784 return; 785 786 out_err: 787 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 788 err = snd_hdac_display_power(bus, false); 789 } 790 791 /* 792 * constructor 793 */ 794 static int skl_create(struct pci_dev *pci, 795 const struct hdac_io_ops *io_ops, 796 struct skl **rskl) 797 { 798 struct skl *skl; 799 struct hdac_ext_bus *ebus; 800 801 int err; 802 803 *rskl = NULL; 804 805 err = pci_enable_device(pci); 806 if (err < 0) 807 return err; 808 809 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); 810 if (!skl) { 811 pci_disable_device(pci); 812 return -ENOMEM; 813 } 814 ebus = &skl->ebus; 815 snd_hdac_ext_bus_init(ebus, &pci->dev, &bus_core_ops, io_ops); 816 ebus->bus.use_posbuf = 1; 817 skl->pci = pci; 818 INIT_WORK(&skl->probe_work, skl_probe_work); 819 820 ebus->bus.bdl_pos_adj = 0; 821 822 *rskl = skl; 823 824 return 0; 825 } 826 827 static int skl_first_init(struct hdac_ext_bus *ebus) 828 { 829 struct skl *skl = ebus_to_skl(ebus); 830 struct hdac_bus *bus = ebus_to_hbus(ebus); 831 struct pci_dev *pci = skl->pci; 832 int err; 833 unsigned short gcap; 834 int cp_streams, pb_streams, start_idx; 835 836 err = pci_request_regions(pci, "Skylake HD audio"); 837 if (err < 0) 838 return err; 839 840 bus->addr = pci_resource_start(pci, 0); 841 bus->remap_addr = pci_ioremap_bar(pci, 0); 842 if (bus->remap_addr == NULL) { 843 dev_err(bus->dev, "ioremap error\n"); 844 return -ENXIO; 845 } 846 847 skl_init_chip(bus, true); 848 849 snd_hdac_bus_parse_capabilities(bus); 850 851 if (skl_acquire_irq(ebus, 0) < 0) 852 return -EBUSY; 853 854 pci_set_master(pci); 855 synchronize_irq(bus->irq); 856 857 gcap = snd_hdac_chip_readw(bus, GCAP); 858 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); 859 860 /* allow 64bit DMA address if supported by H/W */ 861 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) { 862 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64)); 863 } else { 864 dma_set_mask(bus->dev, DMA_BIT_MASK(32)); 865 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32)); 866 } 867 868 /* read number of streams from GCAP register */ 869 cp_streams = (gcap >> 8) & 0x0f; 870 pb_streams = (gcap >> 12) & 0x0f; 871 872 if (!pb_streams && !cp_streams) 873 return -EIO; 874 875 ebus->num_streams = cp_streams + pb_streams; 876 877 /* initialize streams */ 878 snd_hdac_ext_stream_init_all 879 (ebus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); 880 start_idx = cp_streams; 881 snd_hdac_ext_stream_init_all 882 (ebus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); 883 884 err = snd_hdac_bus_alloc_stream_pages(bus); 885 if (err < 0) 886 return err; 887 888 /* initialize chip */ 889 skl_init_pci(skl); 890 891 return skl_init_chip(bus, true); 892 } 893 894 static int skl_probe(struct pci_dev *pci, 895 const struct pci_device_id *pci_id) 896 { 897 struct skl *skl; 898 struct hdac_ext_bus *ebus = NULL; 899 struct hdac_bus *bus = NULL; 900 int err; 901 902 /* we use ext core ops, so provide NULL for ops here */ 903 err = skl_create(pci, NULL, &skl); 904 if (err < 0) 905 return err; 906 907 ebus = &skl->ebus; 908 bus = ebus_to_hbus(ebus); 909 910 err = skl_first_init(ebus); 911 if (err < 0) 912 goto out_free; 913 914 skl->pci_id = pci->device; 915 916 device_disable_async_suspend(bus->dev); 917 918 skl->nhlt = skl_nhlt_init(bus->dev); 919 920 if (skl->nhlt == NULL) { 921 err = -ENODEV; 922 goto out_free; 923 } 924 925 err = skl_nhlt_create_sysfs(skl); 926 if (err < 0) 927 goto out_nhlt_free; 928 929 skl_nhlt_update_topology_bin(skl); 930 931 pci_set_drvdata(skl->pci, ebus); 932 933 skl_dmic_data.dmic_num = skl_get_dmic_geo(skl); 934 935 /* check if dsp is there */ 936 if (bus->ppcap) { 937 /* create device for dsp clk */ 938 err = skl_clock_device_register(skl); 939 if (err < 0) 940 goto out_clk_free; 941 942 err = skl_find_machine(skl, (void *)pci_id->driver_data); 943 if (err < 0) 944 goto out_nhlt_free; 945 946 err = skl_init_dsp(skl); 947 if (err < 0) { 948 dev_dbg(bus->dev, "error failed to register dsp\n"); 949 goto out_nhlt_free; 950 } 951 skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge; 952 skl->skl_sst->clock_power_gating = skl_clock_power_gating; 953 } 954 if (bus->mlcap) 955 snd_hdac_ext_bus_get_ml_capabilities(ebus); 956 957 snd_hdac_bus_stop_chip(bus); 958 959 /* create device for soc dmic */ 960 err = skl_dmic_device_register(skl); 961 if (err < 0) 962 goto out_dsp_free; 963 964 schedule_work(&skl->probe_work); 965 966 return 0; 967 968 out_dsp_free: 969 skl_free_dsp(skl); 970 out_clk_free: 971 skl_clock_device_unregister(skl); 972 out_nhlt_free: 973 skl_nhlt_free(skl->nhlt); 974 out_free: 975 skl_free(ebus); 976 977 return err; 978 } 979 980 static void skl_shutdown(struct pci_dev *pci) 981 { 982 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 983 struct hdac_bus *bus = ebus_to_hbus(ebus); 984 struct hdac_stream *s; 985 struct hdac_ext_stream *stream; 986 struct skl *skl; 987 988 if (ebus == NULL) 989 return; 990 991 skl = ebus_to_skl(ebus); 992 993 if (!skl->init_done) 994 return; 995 996 snd_hdac_ext_stop_streams(ebus); 997 list_for_each_entry(s, &bus->stream_list, list) { 998 stream = stream_to_hdac_ext_stream(s); 999 snd_hdac_ext_stream_decouple(ebus, stream, false); 1000 } 1001 1002 snd_hdac_bus_stop_chip(bus); 1003 } 1004 1005 static void skl_remove(struct pci_dev *pci) 1006 { 1007 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 1008 struct skl *skl = ebus_to_skl(ebus); 1009 1010 release_firmware(skl->tplg); 1011 1012 pm_runtime_get_noresume(&pci->dev); 1013 1014 /* codec removal, invoke bus_device_remove */ 1015 snd_hdac_ext_bus_device_remove(ebus); 1016 1017 skl->debugfs = NULL; 1018 skl_platform_unregister(&pci->dev); 1019 skl_free_dsp(skl); 1020 skl_machine_device_unregister(skl); 1021 skl_dmic_device_unregister(skl); 1022 skl_clock_device_unregister(skl); 1023 skl_nhlt_remove_sysfs(skl); 1024 skl_nhlt_free(skl->nhlt); 1025 skl_free(ebus); 1026 dev_set_drvdata(&pci->dev, NULL); 1027 } 1028 1029 static struct snd_soc_acpi_codecs skl_codecs = { 1030 .num_codecs = 1, 1031 .codecs = {"10508825"} 1032 }; 1033 1034 static struct snd_soc_acpi_codecs kbl_codecs = { 1035 .num_codecs = 1, 1036 .codecs = {"10508825"} 1037 }; 1038 1039 static struct snd_soc_acpi_codecs bxt_codecs = { 1040 .num_codecs = 1, 1041 .codecs = {"MX98357A"} 1042 }; 1043 1044 static struct snd_soc_acpi_codecs kbl_poppy_codecs = { 1045 .num_codecs = 1, 1046 .codecs = {"10EC5663"} 1047 }; 1048 1049 static struct snd_soc_acpi_codecs kbl_5663_5514_codecs = { 1050 .num_codecs = 2, 1051 .codecs = {"10EC5663", "10EC5514"} 1052 }; 1053 1054 static struct snd_soc_acpi_codecs kbl_7219_98357_codecs = { 1055 .num_codecs = 1, 1056 .codecs = {"MX98357A"} 1057 }; 1058 1059 static struct skl_machine_pdata cnl_pdata = { 1060 .use_tplg_pcm = true, 1061 }; 1062 1063 static struct snd_soc_acpi_mach sst_skl_devdata[] = { 1064 { 1065 .id = "INT343A", 1066 .drv_name = "skl_alc286s_i2s", 1067 .fw_filename = "intel/dsp_fw_release.bin", 1068 }, 1069 { 1070 .id = "INT343B", 1071 .drv_name = "skl_n88l25_s4567", 1072 .fw_filename = "intel/dsp_fw_release.bin", 1073 .machine_quirk = snd_soc_acpi_codec_list, 1074 .quirk_data = &skl_codecs, 1075 .pdata = &skl_dmic_data 1076 }, 1077 { 1078 .id = "MX98357A", 1079 .drv_name = "skl_n88l25_m98357a", 1080 .fw_filename = "intel/dsp_fw_release.bin", 1081 .machine_quirk = snd_soc_acpi_codec_list, 1082 .quirk_data = &skl_codecs, 1083 .pdata = &skl_dmic_data 1084 }, 1085 {} 1086 }; 1087 1088 static struct snd_soc_acpi_mach sst_bxtp_devdata[] = { 1089 { 1090 .id = "INT343A", 1091 .drv_name = "bxt_alc298s_i2s", 1092 .fw_filename = "intel/dsp_fw_bxtn.bin", 1093 }, 1094 { 1095 .id = "DLGS7219", 1096 .drv_name = "bxt_da7219_max98357a_i2s", 1097 .fw_filename = "intel/dsp_fw_bxtn.bin", 1098 .machine_quirk = snd_soc_acpi_codec_list, 1099 .quirk_data = &bxt_codecs, 1100 }, 1101 {} 1102 }; 1103 1104 static struct snd_soc_acpi_mach sst_kbl_devdata[] = { 1105 { 1106 .id = "INT343A", 1107 .drv_name = "kbl_alc286s_i2s", 1108 .fw_filename = "intel/dsp_fw_kbl.bin", 1109 }, 1110 { 1111 .id = "INT343B", 1112 .drv_name = "kbl_n88l25_s4567", 1113 .fw_filename = "intel/dsp_fw_kbl.bin", 1114 .machine_quirk = snd_soc_acpi_codec_list, 1115 .quirk_data = &kbl_codecs, 1116 .pdata = &skl_dmic_data 1117 }, 1118 { 1119 .id = "MX98357A", 1120 .drv_name = "kbl_n88l25_m98357a", 1121 .fw_filename = "intel/dsp_fw_kbl.bin", 1122 .machine_quirk = snd_soc_acpi_codec_list, 1123 .quirk_data = &kbl_codecs, 1124 .pdata = &skl_dmic_data 1125 }, 1126 { 1127 .id = "MX98927", 1128 .drv_name = "kbl_r5514_5663_max", 1129 .fw_filename = "intel/dsp_fw_kbl.bin", 1130 .machine_quirk = snd_soc_acpi_codec_list, 1131 .quirk_data = &kbl_5663_5514_codecs, 1132 .pdata = &skl_dmic_data 1133 }, 1134 { 1135 .id = "MX98927", 1136 .drv_name = "kbl_rt5663_m98927", 1137 .fw_filename = "intel/dsp_fw_kbl.bin", 1138 .machine_quirk = snd_soc_acpi_codec_list, 1139 .quirk_data = &kbl_poppy_codecs, 1140 .pdata = &skl_dmic_data 1141 }, 1142 { 1143 .id = "10EC5663", 1144 .drv_name = "kbl_rt5663", 1145 .fw_filename = "intel/dsp_fw_kbl.bin", 1146 }, 1147 { 1148 .id = "DLGS7219", 1149 .drv_name = "kbl_da7219_max98357a", 1150 .fw_filename = "intel/dsp_fw_kbl.bin", 1151 .machine_quirk = snd_soc_acpi_codec_list, 1152 .quirk_data = &kbl_7219_98357_codecs, 1153 .pdata = &skl_dmic_data 1154 }, 1155 1156 {} 1157 }; 1158 1159 static struct snd_soc_acpi_mach sst_glk_devdata[] = { 1160 { 1161 .id = "INT343A", 1162 .drv_name = "glk_alc298s_i2s", 1163 .fw_filename = "intel/dsp_fw_glk.bin", 1164 }, 1165 {} 1166 }; 1167 1168 static const struct snd_soc_acpi_mach sst_cnl_devdata[] = { 1169 { 1170 .id = "INT34C2", 1171 .drv_name = "cnl_rt274", 1172 .fw_filename = "intel/dsp_fw_cnl.bin", 1173 .pdata = &cnl_pdata, 1174 }, 1175 {} 1176 }; 1177 1178 /* PCI IDs */ 1179 static const struct pci_device_id skl_ids[] = { 1180 /* Sunrise Point-LP */ 1181 { PCI_DEVICE(0x8086, 0x9d70), 1182 .driver_data = (unsigned long)&sst_skl_devdata}, 1183 /* BXT-P */ 1184 { PCI_DEVICE(0x8086, 0x5a98), 1185 .driver_data = (unsigned long)&sst_bxtp_devdata}, 1186 /* KBL */ 1187 { PCI_DEVICE(0x8086, 0x9D71), 1188 .driver_data = (unsigned long)&sst_kbl_devdata}, 1189 /* GLK */ 1190 { PCI_DEVICE(0x8086, 0x3198), 1191 .driver_data = (unsigned long)&sst_glk_devdata}, 1192 /* CNL */ 1193 { PCI_DEVICE(0x8086, 0x9dc8), 1194 .driver_data = (unsigned long)&sst_cnl_devdata}, 1195 { 0, } 1196 }; 1197 MODULE_DEVICE_TABLE(pci, skl_ids); 1198 1199 /* pci_driver definition */ 1200 static struct pci_driver skl_driver = { 1201 .name = KBUILD_MODNAME, 1202 .id_table = skl_ids, 1203 .probe = skl_probe, 1204 .remove = skl_remove, 1205 .shutdown = skl_shutdown, 1206 .driver = { 1207 .pm = &skl_pm, 1208 }, 1209 }; 1210 module_pci_driver(skl_driver); 1211 1212 MODULE_LICENSE("GPL v2"); 1213 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver"); 1214