1 /* 2 * skl.c - Implementation of ASoC Intel SKL HD Audio driver 3 * 4 * Copyright (C) 2014-2015 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * 7 * Derived mostly from Intel HDA driver with following copyrights: 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; version 2 of the License. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 22 */ 23 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/platform_device.h> 28 #include <linux/firmware.h> 29 #include <linux/delay.h> 30 #include <sound/pcm.h> 31 #include <sound/soc-acpi.h> 32 #include <sound/hda_register.h> 33 #include <sound/hdaudio.h> 34 #include <sound/hda_i915.h> 35 #include "skl.h" 36 #include "skl-sst-dsp.h" 37 #include "skl-sst-ipc.h" 38 39 static struct skl_machine_pdata skl_dmic_data; 40 41 /* 42 * initialize the PCI registers 43 */ 44 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, 45 unsigned char mask, unsigned char val) 46 { 47 unsigned char data; 48 49 pci_read_config_byte(pci, reg, &data); 50 data &= ~mask; 51 data |= (val & mask); 52 pci_write_config_byte(pci, reg, data); 53 } 54 55 static void skl_init_pci(struct skl *skl) 56 { 57 struct hdac_ext_bus *ebus = &skl->ebus; 58 59 /* 60 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 61 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 62 * Ensuring these bits are 0 clears playback static on some HD Audio 63 * codecs. 64 * The PCI register TCSEL is defined in the Intel manuals. 65 */ 66 dev_dbg(ebus_to_hbus(ebus)->dev, "Clearing TCSEL\n"); 67 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); 68 } 69 70 static void update_pci_dword(struct pci_dev *pci, 71 unsigned int reg, u32 mask, u32 val) 72 { 73 u32 data = 0; 74 75 pci_read_config_dword(pci, reg, &data); 76 data &= ~mask; 77 data |= (val & mask); 78 pci_write_config_dword(pci, reg, data); 79 } 80 81 /* 82 * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits 83 * 84 * @dev: device pointer 85 * @enable: enable/disable flag 86 */ 87 static void skl_enable_miscbdcge(struct device *dev, bool enable) 88 { 89 struct pci_dev *pci = to_pci_dev(dev); 90 u32 val; 91 92 val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; 93 94 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); 95 } 96 97 /* 98 * While performing reset, controller may not come back properly causing 99 * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset 100 * (init chip) and then again set CGCTL.MISCBDCGE to 1 101 */ 102 static int skl_init_chip(struct hdac_bus *bus, bool full_reset) 103 { 104 int ret; 105 106 skl_enable_miscbdcge(bus->dev, false); 107 ret = snd_hdac_bus_init_chip(bus, full_reset); 108 skl_enable_miscbdcge(bus->dev, true); 109 110 return ret; 111 } 112 113 void skl_update_d0i3c(struct device *dev, bool enable) 114 { 115 struct pci_dev *pci = to_pci_dev(dev); 116 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 117 struct hdac_bus *bus = ebus_to_hbus(ebus); 118 u8 reg; 119 int timeout = 50; 120 121 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 122 /* Do not write to D0I3C until command in progress bit is cleared */ 123 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 124 udelay(10); 125 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 126 } 127 128 /* Highly unlikely. But if it happens, flag error explicitly */ 129 if (!timeout) { 130 dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n"); 131 return; 132 } 133 134 if (enable) 135 reg = reg | AZX_REG_VS_D0I3C_I3; 136 else 137 reg = reg & (~AZX_REG_VS_D0I3C_I3); 138 139 snd_hdac_chip_writeb(bus, VS_D0I3C, reg); 140 141 timeout = 50; 142 /* Wait for cmd in progress to be cleared before exiting the function */ 143 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 144 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 145 udelay(10); 146 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 147 } 148 149 /* Highly unlikely. But if it happens, flag error explicitly */ 150 if (!timeout) { 151 dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n"); 152 return; 153 } 154 155 dev_dbg(bus->dev, "D0I3C register = 0x%x\n", 156 snd_hdac_chip_readb(bus, VS_D0I3C)); 157 } 158 159 /* called from IRQ */ 160 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) 161 { 162 snd_pcm_period_elapsed(hstr->substream); 163 } 164 165 static irqreturn_t skl_interrupt(int irq, void *dev_id) 166 { 167 struct hdac_ext_bus *ebus = dev_id; 168 struct hdac_bus *bus = ebus_to_hbus(ebus); 169 u32 status; 170 171 if (!pm_runtime_active(bus->dev)) 172 return IRQ_NONE; 173 174 spin_lock(&bus->reg_lock); 175 176 status = snd_hdac_chip_readl(bus, INTSTS); 177 if (status == 0 || status == 0xffffffff) { 178 spin_unlock(&bus->reg_lock); 179 return IRQ_NONE; 180 } 181 182 /* clear rirb int */ 183 status = snd_hdac_chip_readb(bus, RIRBSTS); 184 if (status & RIRB_INT_MASK) { 185 if (status & RIRB_INT_RESPONSE) 186 snd_hdac_bus_update_rirb(bus); 187 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 188 } 189 190 spin_unlock(&bus->reg_lock); 191 192 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; 193 } 194 195 static irqreturn_t skl_threaded_handler(int irq, void *dev_id) 196 { 197 struct hdac_ext_bus *ebus = dev_id; 198 struct hdac_bus *bus = ebus_to_hbus(ebus); 199 u32 status; 200 201 status = snd_hdac_chip_readl(bus, INTSTS); 202 203 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); 204 205 return IRQ_HANDLED; 206 } 207 208 static int skl_acquire_irq(struct hdac_ext_bus *ebus, int do_disconnect) 209 { 210 struct skl *skl = ebus_to_skl(ebus); 211 struct hdac_bus *bus = ebus_to_hbus(ebus); 212 int ret; 213 214 ret = request_threaded_irq(skl->pci->irq, skl_interrupt, 215 skl_threaded_handler, 216 IRQF_SHARED, 217 KBUILD_MODNAME, ebus); 218 if (ret) { 219 dev_err(bus->dev, 220 "unable to grab IRQ %d, disabling device\n", 221 skl->pci->irq); 222 return ret; 223 } 224 225 bus->irq = skl->pci->irq; 226 pci_intx(skl->pci, 1); 227 228 return 0; 229 } 230 231 static int skl_suspend_late(struct device *dev) 232 { 233 struct pci_dev *pci = to_pci_dev(dev); 234 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 235 struct skl *skl = ebus_to_skl(ebus); 236 237 return skl_suspend_late_dsp(skl); 238 } 239 240 #ifdef CONFIG_PM 241 static int _skl_suspend(struct hdac_ext_bus *ebus) 242 { 243 struct skl *skl = ebus_to_skl(ebus); 244 struct hdac_bus *bus = ebus_to_hbus(ebus); 245 struct pci_dev *pci = to_pci_dev(bus->dev); 246 int ret; 247 248 snd_hdac_ext_bus_link_power_down_all(ebus); 249 250 ret = skl_suspend_dsp(skl); 251 if (ret < 0) 252 return ret; 253 254 snd_hdac_bus_stop_chip(bus); 255 update_pci_dword(pci, AZX_PCIREG_PGCTL, 256 AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK); 257 skl_enable_miscbdcge(bus->dev, false); 258 snd_hdac_bus_enter_link_reset(bus); 259 skl_enable_miscbdcge(bus->dev, true); 260 skl_cleanup_resources(skl); 261 262 return 0; 263 } 264 265 static int _skl_resume(struct hdac_ext_bus *ebus) 266 { 267 struct skl *skl = ebus_to_skl(ebus); 268 struct hdac_bus *bus = ebus_to_hbus(ebus); 269 270 skl_init_pci(skl); 271 skl_init_chip(bus, true); 272 273 return skl_resume_dsp(skl); 274 } 275 #endif 276 277 #ifdef CONFIG_PM_SLEEP 278 /* 279 * power management 280 */ 281 static int skl_suspend(struct device *dev) 282 { 283 struct pci_dev *pci = to_pci_dev(dev); 284 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 285 struct skl *skl = ebus_to_skl(ebus); 286 struct hdac_bus *bus = ebus_to_hbus(ebus); 287 int ret = 0; 288 289 /* 290 * Do not suspend if streams which are marked ignore suspend are 291 * running, we need to save the state for these and continue 292 */ 293 if (skl->supend_active) { 294 /* turn off the links and stop the CORB/RIRB DMA if it is On */ 295 snd_hdac_ext_bus_link_power_down_all(ebus); 296 297 if (ebus->cmd_dma_state) 298 snd_hdac_bus_stop_cmd_io(&ebus->bus); 299 300 enable_irq_wake(bus->irq); 301 pci_save_state(pci); 302 } else { 303 ret = _skl_suspend(ebus); 304 if (ret < 0) 305 return ret; 306 skl->skl_sst->fw_loaded = false; 307 } 308 309 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 310 ret = snd_hdac_display_power(bus, false); 311 if (ret < 0) 312 dev_err(bus->dev, 313 "Cannot turn OFF display power on i915\n"); 314 } 315 316 return ret; 317 } 318 319 static int skl_resume(struct device *dev) 320 { 321 struct pci_dev *pci = to_pci_dev(dev); 322 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 323 struct skl *skl = ebus_to_skl(ebus); 324 struct hdac_bus *bus = ebus_to_hbus(ebus); 325 struct hdac_ext_link *hlink = NULL; 326 int ret; 327 328 /* Turned OFF in HDMI codec driver after codec reconfiguration */ 329 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 330 ret = snd_hdac_display_power(bus, true); 331 if (ret < 0) { 332 dev_err(bus->dev, 333 "Cannot turn on display power on i915\n"); 334 return ret; 335 } 336 } 337 338 /* 339 * resume only when we are not in suspend active, otherwise need to 340 * restore the device 341 */ 342 if (skl->supend_active) { 343 pci_restore_state(pci); 344 snd_hdac_ext_bus_link_power_up_all(ebus); 345 disable_irq_wake(bus->irq); 346 /* 347 * turn On the links which are On before active suspend 348 * and start the CORB/RIRB DMA if On before 349 * active suspend. 350 */ 351 list_for_each_entry(hlink, &ebus->hlink_list, list) { 352 if (hlink->ref_count) 353 snd_hdac_ext_bus_link_power_up(hlink); 354 } 355 356 if (ebus->cmd_dma_state) 357 snd_hdac_bus_init_cmd_io(&ebus->bus); 358 ret = 0; 359 } else { 360 ret = _skl_resume(ebus); 361 362 /* turn off the links which are off before suspend */ 363 list_for_each_entry(hlink, &ebus->hlink_list, list) { 364 if (!hlink->ref_count) 365 snd_hdac_ext_bus_link_power_down(hlink); 366 } 367 368 if (!ebus->cmd_dma_state) 369 snd_hdac_bus_stop_cmd_io(&ebus->bus); 370 } 371 372 return ret; 373 } 374 #endif /* CONFIG_PM_SLEEP */ 375 376 #ifdef CONFIG_PM 377 static int skl_runtime_suspend(struct device *dev) 378 { 379 struct pci_dev *pci = to_pci_dev(dev); 380 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 381 struct hdac_bus *bus = ebus_to_hbus(ebus); 382 383 dev_dbg(bus->dev, "in %s\n", __func__); 384 385 return _skl_suspend(ebus); 386 } 387 388 static int skl_runtime_resume(struct device *dev) 389 { 390 struct pci_dev *pci = to_pci_dev(dev); 391 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 392 struct hdac_bus *bus = ebus_to_hbus(ebus); 393 394 dev_dbg(bus->dev, "in %s\n", __func__); 395 396 return _skl_resume(ebus); 397 } 398 #endif /* CONFIG_PM */ 399 400 static const struct dev_pm_ops skl_pm = { 401 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) 402 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) 403 .suspend_late = skl_suspend_late, 404 }; 405 406 /* 407 * destructor 408 */ 409 static int skl_free(struct hdac_ext_bus *ebus) 410 { 411 struct skl *skl = ebus_to_skl(ebus); 412 struct hdac_bus *bus = ebus_to_hbus(ebus); 413 414 skl->init_done = 0; /* to be sure */ 415 416 snd_hdac_ext_stop_streams(ebus); 417 418 if (bus->irq >= 0) 419 free_irq(bus->irq, (void *)ebus); 420 snd_hdac_bus_free_stream_pages(bus); 421 snd_hdac_stream_free_all(ebus); 422 snd_hdac_link_free_all(ebus); 423 424 if (bus->remap_addr) 425 iounmap(bus->remap_addr); 426 427 pci_release_regions(skl->pci); 428 pci_disable_device(skl->pci); 429 430 snd_hdac_ext_bus_exit(ebus); 431 432 cancel_work_sync(&skl->probe_work); 433 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 434 snd_hdac_i915_exit(&ebus->bus); 435 436 return 0; 437 } 438 439 /* 440 * For each ssp there are 3 clocks (mclk/sclk/sclkfs). 441 * e.g. for ssp0, clocks will be named as 442 * "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs" 443 * So for skl+, there are 6 ssps, so 18 clocks will be created. 444 */ 445 static struct skl_ssp_clk skl_ssp_clks[] = { 446 {.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"}, 447 {.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"}, 448 {.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"}, 449 {.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"}, 450 {.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"}, 451 {.name = "ssp2_sclkfs"}, 452 {.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"}, 453 {.name = "ssp5_sclkfs"}, 454 }; 455 456 static int skl_find_machine(struct skl *skl, void *driver_data) 457 { 458 struct snd_soc_acpi_mach *mach = driver_data; 459 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); 460 struct skl_machine_pdata *pdata; 461 462 mach = snd_soc_acpi_find_machine(mach); 463 if (mach == NULL) { 464 dev_err(bus->dev, "No matching machine driver found\n"); 465 return -ENODEV; 466 } 467 468 skl->mach = mach; 469 skl->fw_name = mach->fw_filename; 470 pdata = skl->mach->pdata; 471 472 if (mach->pdata) 473 skl->use_tplg_pcm = pdata->use_tplg_pcm; 474 475 return 0; 476 } 477 478 static int skl_machine_device_register(struct skl *skl) 479 { 480 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); 481 struct snd_soc_acpi_mach *mach = skl->mach; 482 struct platform_device *pdev; 483 int ret; 484 485 pdev = platform_device_alloc(mach->drv_name, -1); 486 if (pdev == NULL) { 487 dev_err(bus->dev, "platform device alloc failed\n"); 488 return -EIO; 489 } 490 491 ret = platform_device_add(pdev); 492 if (ret) { 493 dev_err(bus->dev, "failed to add machine device\n"); 494 platform_device_put(pdev); 495 return -EIO; 496 } 497 498 if (mach->pdata) 499 dev_set_drvdata(&pdev->dev, mach->pdata); 500 501 skl->i2s_dev = pdev; 502 503 return 0; 504 } 505 506 static void skl_machine_device_unregister(struct skl *skl) 507 { 508 if (skl->i2s_dev) 509 platform_device_unregister(skl->i2s_dev); 510 } 511 512 static int skl_dmic_device_register(struct skl *skl) 513 { 514 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); 515 struct platform_device *pdev; 516 int ret; 517 518 /* SKL has one dmic port, so allocate dmic device for this */ 519 pdev = platform_device_alloc("dmic-codec", -1); 520 if (!pdev) { 521 dev_err(bus->dev, "failed to allocate dmic device\n"); 522 return -ENOMEM; 523 } 524 525 ret = platform_device_add(pdev); 526 if (ret) { 527 dev_err(bus->dev, "failed to add dmic device: %d\n", ret); 528 platform_device_put(pdev); 529 return ret; 530 } 531 skl->dmic_dev = pdev; 532 533 return 0; 534 } 535 536 static void skl_dmic_device_unregister(struct skl *skl) 537 { 538 if (skl->dmic_dev) 539 platform_device_unregister(skl->dmic_dev); 540 } 541 542 static struct skl_clk_parent_src skl_clk_src[] = { 543 { .clk_id = SKL_XTAL, .name = "xtal" }, 544 { .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 }, 545 { .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 }, 546 }; 547 548 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id) 549 { 550 unsigned int i; 551 552 for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) { 553 if (skl_clk_src[i].clk_id == clk_id) 554 return &skl_clk_src[i]; 555 } 556 557 return NULL; 558 } 559 560 static void init_skl_xtal_rate(int pci_id) 561 { 562 switch (pci_id) { 563 case 0x9d70: 564 case 0x9d71: 565 skl_clk_src[0].rate = 24000000; 566 return; 567 568 default: 569 skl_clk_src[0].rate = 19200000; 570 return; 571 } 572 } 573 574 static int skl_clock_device_register(struct skl *skl) 575 { 576 struct platform_device_info pdevinfo = {NULL}; 577 struct skl_clk_pdata *clk_pdata; 578 579 clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata), 580 GFP_KERNEL); 581 if (!clk_pdata) 582 return -ENOMEM; 583 584 init_skl_xtal_rate(skl->pci->device); 585 586 clk_pdata->parent_clks = skl_clk_src; 587 clk_pdata->ssp_clks = skl_ssp_clks; 588 clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks); 589 590 /* Query NHLT to fill the rates and parent */ 591 skl_get_clks(skl, clk_pdata->ssp_clks); 592 clk_pdata->pvt_data = skl; 593 594 /* Register Platform device */ 595 pdevinfo.parent = &skl->pci->dev; 596 pdevinfo.id = -1; 597 pdevinfo.name = "skl-ssp-clk"; 598 pdevinfo.data = clk_pdata; 599 pdevinfo.size_data = sizeof(*clk_pdata); 600 skl->clk_dev = platform_device_register_full(&pdevinfo); 601 return PTR_ERR_OR_ZERO(skl->clk_dev); 602 } 603 604 static void skl_clock_device_unregister(struct skl *skl) 605 { 606 if (skl->clk_dev) 607 platform_device_unregister(skl->clk_dev); 608 } 609 610 /* 611 * Probe the given codec address 612 */ 613 static int probe_codec(struct hdac_ext_bus *ebus, int addr) 614 { 615 struct hdac_bus *bus = ebus_to_hbus(ebus); 616 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 617 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 618 unsigned int res = -1; 619 620 mutex_lock(&bus->cmd_mutex); 621 snd_hdac_bus_send_cmd(bus, cmd); 622 snd_hdac_bus_get_response(bus, addr, &res); 623 mutex_unlock(&bus->cmd_mutex); 624 if (res == -1) 625 return -EIO; 626 dev_dbg(bus->dev, "codec #%d probed OK\n", addr); 627 628 return snd_hdac_ext_bus_device_init(ebus, addr); 629 } 630 631 /* Codec initialization */ 632 static void skl_codec_create(struct hdac_ext_bus *ebus) 633 { 634 struct hdac_bus *bus = ebus_to_hbus(ebus); 635 int c, max_slots; 636 637 max_slots = HDA_MAX_CODECS; 638 639 /* First try to probe all given codec slots */ 640 for (c = 0; c < max_slots; c++) { 641 if ((bus->codec_mask & (1 << c))) { 642 if (probe_codec(ebus, c) < 0) { 643 /* 644 * Some BIOSen give you wrong codec addresses 645 * that don't exist 646 */ 647 dev_warn(bus->dev, 648 "Codec #%d probe error; disabling it...\n", c); 649 bus->codec_mask &= ~(1 << c); 650 /* 651 * More badly, accessing to a non-existing 652 * codec often screws up the controller bus, 653 * and disturbs the further communications. 654 * Thus if an error occurs during probing, 655 * better to reset the controller bus to get 656 * back to the sanity state. 657 */ 658 snd_hdac_bus_stop_chip(bus); 659 skl_init_chip(bus, true); 660 } 661 } 662 } 663 } 664 665 static const struct hdac_bus_ops bus_core_ops = { 666 .command = snd_hdac_bus_send_cmd, 667 .get_response = snd_hdac_bus_get_response, 668 }; 669 670 static int skl_i915_init(struct hdac_bus *bus) 671 { 672 int err; 673 674 /* 675 * The HDMI codec is in GPU so we need to ensure that it is powered 676 * up and ready for probe 677 */ 678 err = snd_hdac_i915_init(bus); 679 if (err < 0) 680 return err; 681 682 err = snd_hdac_display_power(bus, true); 683 if (err < 0) 684 dev_err(bus->dev, "Cannot turn on display power on i915\n"); 685 686 return err; 687 } 688 689 static void skl_probe_work(struct work_struct *work) 690 { 691 struct skl *skl = container_of(work, struct skl, probe_work); 692 struct hdac_ext_bus *ebus = &skl->ebus; 693 struct hdac_bus *bus = ebus_to_hbus(ebus); 694 struct hdac_ext_link *hlink = NULL; 695 int err; 696 697 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 698 err = skl_i915_init(bus); 699 if (err < 0) 700 return; 701 } 702 703 err = skl_init_chip(bus, true); 704 if (err < 0) { 705 dev_err(bus->dev, "Init chip failed with err: %d\n", err); 706 goto out_err; 707 } 708 709 /* codec detection */ 710 if (!bus->codec_mask) 711 dev_info(bus->dev, "no hda codecs found!\n"); 712 713 /* create codec instances */ 714 skl_codec_create(ebus); 715 716 /* register platform dai and controls */ 717 err = skl_platform_register(bus->dev); 718 if (err < 0) { 719 dev_err(bus->dev, "platform register failed: %d\n", err); 720 return; 721 } 722 723 if (bus->ppcap) { 724 err = skl_machine_device_register(skl); 725 if (err < 0) { 726 dev_err(bus->dev, "machine register failed: %d\n", err); 727 goto out_err; 728 } 729 } 730 731 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 732 err = snd_hdac_display_power(bus, false); 733 if (err < 0) { 734 dev_err(bus->dev, "Cannot turn off display power on i915\n"); 735 skl_machine_device_unregister(skl); 736 return; 737 } 738 } 739 740 /* 741 * we are done probing so decrement link counts 742 */ 743 list_for_each_entry(hlink, &ebus->hlink_list, list) 744 snd_hdac_ext_bus_link_put(ebus, hlink); 745 746 /* configure PM */ 747 pm_runtime_put_noidle(bus->dev); 748 pm_runtime_allow(bus->dev); 749 skl->init_done = 1; 750 751 return; 752 753 out_err: 754 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 755 err = snd_hdac_display_power(bus, false); 756 } 757 758 /* 759 * constructor 760 */ 761 static int skl_create(struct pci_dev *pci, 762 const struct hdac_io_ops *io_ops, 763 struct skl **rskl) 764 { 765 struct skl *skl; 766 struct hdac_ext_bus *ebus; 767 768 int err; 769 770 *rskl = NULL; 771 772 err = pci_enable_device(pci); 773 if (err < 0) 774 return err; 775 776 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); 777 if (!skl) { 778 pci_disable_device(pci); 779 return -ENOMEM; 780 } 781 ebus = &skl->ebus; 782 snd_hdac_ext_bus_init(ebus, &pci->dev, &bus_core_ops, io_ops); 783 ebus->bus.use_posbuf = 1; 784 skl->pci = pci; 785 INIT_WORK(&skl->probe_work, skl_probe_work); 786 787 ebus->bus.bdl_pos_adj = 0; 788 789 *rskl = skl; 790 791 return 0; 792 } 793 794 static int skl_first_init(struct hdac_ext_bus *ebus) 795 { 796 struct skl *skl = ebus_to_skl(ebus); 797 struct hdac_bus *bus = ebus_to_hbus(ebus); 798 struct pci_dev *pci = skl->pci; 799 int err; 800 unsigned short gcap; 801 int cp_streams, pb_streams, start_idx; 802 803 err = pci_request_regions(pci, "Skylake HD audio"); 804 if (err < 0) 805 return err; 806 807 bus->addr = pci_resource_start(pci, 0); 808 bus->remap_addr = pci_ioremap_bar(pci, 0); 809 if (bus->remap_addr == NULL) { 810 dev_err(bus->dev, "ioremap error\n"); 811 return -ENXIO; 812 } 813 814 skl_init_chip(bus, true); 815 816 snd_hdac_bus_parse_capabilities(bus); 817 818 if (skl_acquire_irq(ebus, 0) < 0) 819 return -EBUSY; 820 821 pci_set_master(pci); 822 synchronize_irq(bus->irq); 823 824 gcap = snd_hdac_chip_readw(bus, GCAP); 825 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); 826 827 /* allow 64bit DMA address if supported by H/W */ 828 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) { 829 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64)); 830 } else { 831 dma_set_mask(bus->dev, DMA_BIT_MASK(32)); 832 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32)); 833 } 834 835 /* read number of streams from GCAP register */ 836 cp_streams = (gcap >> 8) & 0x0f; 837 pb_streams = (gcap >> 12) & 0x0f; 838 839 if (!pb_streams && !cp_streams) 840 return -EIO; 841 842 ebus->num_streams = cp_streams + pb_streams; 843 844 /* initialize streams */ 845 snd_hdac_ext_stream_init_all 846 (ebus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); 847 start_idx = cp_streams; 848 snd_hdac_ext_stream_init_all 849 (ebus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); 850 851 err = snd_hdac_bus_alloc_stream_pages(bus); 852 if (err < 0) 853 return err; 854 855 /* initialize chip */ 856 skl_init_pci(skl); 857 858 return skl_init_chip(bus, true); 859 } 860 861 static int skl_probe(struct pci_dev *pci, 862 const struct pci_device_id *pci_id) 863 { 864 struct skl *skl; 865 struct hdac_ext_bus *ebus = NULL; 866 struct hdac_bus *bus = NULL; 867 int err; 868 869 /* we use ext core ops, so provide NULL for ops here */ 870 err = skl_create(pci, NULL, &skl); 871 if (err < 0) 872 return err; 873 874 ebus = &skl->ebus; 875 bus = ebus_to_hbus(ebus); 876 877 err = skl_first_init(ebus); 878 if (err < 0) 879 goto out_free; 880 881 skl->pci_id = pci->device; 882 883 device_disable_async_suspend(bus->dev); 884 885 skl->nhlt = skl_nhlt_init(bus->dev); 886 887 if (skl->nhlt == NULL) { 888 err = -ENODEV; 889 goto out_free; 890 } 891 892 err = skl_nhlt_create_sysfs(skl); 893 if (err < 0) 894 goto out_nhlt_free; 895 896 skl_nhlt_update_topology_bin(skl); 897 898 pci_set_drvdata(skl->pci, ebus); 899 900 skl_dmic_data.dmic_num = skl_get_dmic_geo(skl); 901 902 /* check if dsp is there */ 903 if (bus->ppcap) { 904 /* create device for dsp clk */ 905 err = skl_clock_device_register(skl); 906 if (err < 0) 907 goto out_clk_free; 908 909 err = skl_find_machine(skl, (void *)pci_id->driver_data); 910 if (err < 0) 911 goto out_nhlt_free; 912 913 err = skl_init_dsp(skl); 914 if (err < 0) { 915 dev_dbg(bus->dev, "error failed to register dsp\n"); 916 goto out_nhlt_free; 917 } 918 skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge; 919 } 920 if (bus->mlcap) 921 snd_hdac_ext_bus_get_ml_capabilities(ebus); 922 923 snd_hdac_bus_stop_chip(bus); 924 925 /* create device for soc dmic */ 926 err = skl_dmic_device_register(skl); 927 if (err < 0) 928 goto out_dsp_free; 929 930 schedule_work(&skl->probe_work); 931 932 return 0; 933 934 out_dsp_free: 935 skl_free_dsp(skl); 936 out_clk_free: 937 skl_clock_device_unregister(skl); 938 out_nhlt_free: 939 skl_nhlt_free(skl->nhlt); 940 out_free: 941 skl_free(ebus); 942 943 return err; 944 } 945 946 static void skl_shutdown(struct pci_dev *pci) 947 { 948 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 949 struct hdac_bus *bus = ebus_to_hbus(ebus); 950 struct hdac_stream *s; 951 struct hdac_ext_stream *stream; 952 struct skl *skl; 953 954 if (ebus == NULL) 955 return; 956 957 skl = ebus_to_skl(ebus); 958 959 if (!skl->init_done) 960 return; 961 962 snd_hdac_ext_stop_streams(ebus); 963 list_for_each_entry(s, &bus->stream_list, list) { 964 stream = stream_to_hdac_ext_stream(s); 965 snd_hdac_ext_stream_decouple(ebus, stream, false); 966 } 967 968 snd_hdac_bus_stop_chip(bus); 969 } 970 971 static void skl_remove(struct pci_dev *pci) 972 { 973 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 974 struct skl *skl = ebus_to_skl(ebus); 975 976 release_firmware(skl->tplg); 977 978 pm_runtime_get_noresume(&pci->dev); 979 980 /* codec removal, invoke bus_device_remove */ 981 snd_hdac_ext_bus_device_remove(ebus); 982 983 skl->debugfs = NULL; 984 skl_platform_unregister(&pci->dev); 985 skl_free_dsp(skl); 986 skl_machine_device_unregister(skl); 987 skl_dmic_device_unregister(skl); 988 skl_clock_device_unregister(skl); 989 skl_nhlt_remove_sysfs(skl); 990 skl_nhlt_free(skl->nhlt); 991 skl_free(ebus); 992 dev_set_drvdata(&pci->dev, NULL); 993 } 994 995 static struct snd_soc_acpi_codecs skl_codecs = { 996 .num_codecs = 1, 997 .codecs = {"10508825"} 998 }; 999 1000 static struct snd_soc_acpi_codecs kbl_codecs = { 1001 .num_codecs = 1, 1002 .codecs = {"10508825"} 1003 }; 1004 1005 static struct snd_soc_acpi_codecs bxt_codecs = { 1006 .num_codecs = 1, 1007 .codecs = {"MX98357A"} 1008 }; 1009 1010 static struct snd_soc_acpi_codecs kbl_poppy_codecs = { 1011 .num_codecs = 1, 1012 .codecs = {"10EC5663"} 1013 }; 1014 1015 static struct snd_soc_acpi_codecs kbl_5663_5514_codecs = { 1016 .num_codecs = 2, 1017 .codecs = {"10EC5663", "10EC5514"} 1018 }; 1019 1020 static struct skl_machine_pdata cnl_pdata = { 1021 .use_tplg_pcm = true, 1022 }; 1023 1024 static struct snd_soc_acpi_mach sst_skl_devdata[] = { 1025 { 1026 .id = "INT343A", 1027 .drv_name = "skl_alc286s_i2s", 1028 .fw_filename = "intel/dsp_fw_release.bin", 1029 }, 1030 { 1031 .id = "INT343B", 1032 .drv_name = "skl_n88l25_s4567", 1033 .fw_filename = "intel/dsp_fw_release.bin", 1034 .machine_quirk = snd_soc_acpi_codec_list, 1035 .quirk_data = &skl_codecs, 1036 .pdata = &skl_dmic_data 1037 }, 1038 { 1039 .id = "MX98357A", 1040 .drv_name = "skl_n88l25_m98357a", 1041 .fw_filename = "intel/dsp_fw_release.bin", 1042 .machine_quirk = snd_soc_acpi_codec_list, 1043 .quirk_data = &skl_codecs, 1044 .pdata = &skl_dmic_data 1045 }, 1046 {} 1047 }; 1048 1049 static struct snd_soc_acpi_mach sst_bxtp_devdata[] = { 1050 { 1051 .id = "INT343A", 1052 .drv_name = "bxt_alc298s_i2s", 1053 .fw_filename = "intel/dsp_fw_bxtn.bin", 1054 }, 1055 { 1056 .id = "DLGS7219", 1057 .drv_name = "bxt_da7219_max98357a_i2s", 1058 .fw_filename = "intel/dsp_fw_bxtn.bin", 1059 .machine_quirk = snd_soc_acpi_codec_list, 1060 .quirk_data = &bxt_codecs, 1061 }, 1062 {} 1063 }; 1064 1065 static struct snd_soc_acpi_mach sst_kbl_devdata[] = { 1066 { 1067 .id = "INT343A", 1068 .drv_name = "kbl_alc286s_i2s", 1069 .fw_filename = "intel/dsp_fw_kbl.bin", 1070 }, 1071 { 1072 .id = "INT343B", 1073 .drv_name = "kbl_n88l25_s4567", 1074 .fw_filename = "intel/dsp_fw_kbl.bin", 1075 .machine_quirk = snd_soc_acpi_codec_list, 1076 .quirk_data = &kbl_codecs, 1077 .pdata = &skl_dmic_data 1078 }, 1079 { 1080 .id = "MX98357A", 1081 .drv_name = "kbl_n88l25_m98357a", 1082 .fw_filename = "intel/dsp_fw_kbl.bin", 1083 .machine_quirk = snd_soc_acpi_codec_list, 1084 .quirk_data = &kbl_codecs, 1085 .pdata = &skl_dmic_data 1086 }, 1087 { 1088 .id = "MX98927", 1089 .drv_name = "kbl_r5514_5663_max", 1090 .fw_filename = "intel/dsp_fw_kbl.bin", 1091 .machine_quirk = snd_soc_acpi_codec_list, 1092 .quirk_data = &kbl_5663_5514_codecs, 1093 .pdata = &skl_dmic_data 1094 }, 1095 { 1096 .id = "MX98927", 1097 .drv_name = "kbl_rt5663_m98927", 1098 .fw_filename = "intel/dsp_fw_kbl.bin", 1099 .machine_quirk = snd_soc_acpi_codec_list, 1100 .quirk_data = &kbl_poppy_codecs, 1101 .pdata = &skl_dmic_data 1102 }, 1103 { 1104 .id = "10EC5663", 1105 .drv_name = "kbl_rt5663", 1106 .fw_filename = "intel/dsp_fw_kbl.bin", 1107 }, 1108 1109 {} 1110 }; 1111 1112 static struct snd_soc_acpi_mach sst_glk_devdata[] = { 1113 { 1114 .id = "INT343A", 1115 .drv_name = "glk_alc298s_i2s", 1116 .fw_filename = "intel/dsp_fw_glk.bin", 1117 }, 1118 {} 1119 }; 1120 1121 static const struct snd_soc_acpi_mach sst_cnl_devdata[] = { 1122 { 1123 .id = "INT34C2", 1124 .drv_name = "cnl_rt274", 1125 .fw_filename = "intel/dsp_fw_cnl.bin", 1126 .pdata = &cnl_pdata, 1127 }, 1128 {} 1129 }; 1130 1131 /* PCI IDs */ 1132 static const struct pci_device_id skl_ids[] = { 1133 /* Sunrise Point-LP */ 1134 { PCI_DEVICE(0x8086, 0x9d70), 1135 .driver_data = (unsigned long)&sst_skl_devdata}, 1136 /* BXT-P */ 1137 { PCI_DEVICE(0x8086, 0x5a98), 1138 .driver_data = (unsigned long)&sst_bxtp_devdata}, 1139 /* KBL */ 1140 { PCI_DEVICE(0x8086, 0x9D71), 1141 .driver_data = (unsigned long)&sst_kbl_devdata}, 1142 /* GLK */ 1143 { PCI_DEVICE(0x8086, 0x3198), 1144 .driver_data = (unsigned long)&sst_glk_devdata}, 1145 /* CNL */ 1146 { PCI_DEVICE(0x8086, 0x9dc8), 1147 .driver_data = (unsigned long)&sst_cnl_devdata}, 1148 { 0, } 1149 }; 1150 MODULE_DEVICE_TABLE(pci, skl_ids); 1151 1152 /* pci_driver definition */ 1153 static struct pci_driver skl_driver = { 1154 .name = KBUILD_MODNAME, 1155 .id_table = skl_ids, 1156 .probe = skl_probe, 1157 .remove = skl_remove, 1158 .shutdown = skl_shutdown, 1159 .driver = { 1160 .pm = &skl_pm, 1161 }, 1162 }; 1163 module_pci_driver(skl_driver); 1164 1165 MODULE_LICENSE("GPL v2"); 1166 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver"); 1167