1 /* 2 * skl.c - Implementation of ASoC Intel SKL HD Audio driver 3 * 4 * Copyright (C) 2014-2015 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * 7 * Derived mostly from Intel HDA driver with following copyrights: 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; version 2 of the License. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 22 */ 23 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/platform_device.h> 28 #include <linux/firmware.h> 29 #include <linux/delay.h> 30 #include <sound/pcm.h> 31 #include <sound/soc-acpi.h> 32 #include <sound/soc-acpi-intel-match.h> 33 #include <sound/hda_register.h> 34 #include <sound/hdaudio.h> 35 #include <sound/hda_i915.h> 36 #include "skl.h" 37 #include "skl-sst-dsp.h" 38 #include "skl-sst-ipc.h" 39 40 /* 41 * initialize the PCI registers 42 */ 43 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, 44 unsigned char mask, unsigned char val) 45 { 46 unsigned char data; 47 48 pci_read_config_byte(pci, reg, &data); 49 data &= ~mask; 50 data |= (val & mask); 51 pci_write_config_byte(pci, reg, data); 52 } 53 54 static void skl_init_pci(struct skl *skl) 55 { 56 struct hdac_ext_bus *ebus = &skl->ebus; 57 58 /* 59 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 60 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 61 * Ensuring these bits are 0 clears playback static on some HD Audio 62 * codecs. 63 * The PCI register TCSEL is defined in the Intel manuals. 64 */ 65 dev_dbg(ebus_to_hbus(ebus)->dev, "Clearing TCSEL\n"); 66 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); 67 } 68 69 static void update_pci_dword(struct pci_dev *pci, 70 unsigned int reg, u32 mask, u32 val) 71 { 72 u32 data = 0; 73 74 pci_read_config_dword(pci, reg, &data); 75 data &= ~mask; 76 data |= (val & mask); 77 pci_write_config_dword(pci, reg, data); 78 } 79 80 /* 81 * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits 82 * 83 * @dev: device pointer 84 * @enable: enable/disable flag 85 */ 86 static void skl_enable_miscbdcge(struct device *dev, bool enable) 87 { 88 struct pci_dev *pci = to_pci_dev(dev); 89 u32 val; 90 91 val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; 92 93 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); 94 } 95 96 /** 97 * skl_clock_power_gating: Enable/Disable clock and power gating 98 * 99 * @dev: Device pointer 100 * @enable: Enable/Disable flag 101 */ 102 static void skl_clock_power_gating(struct device *dev, bool enable) 103 { 104 struct pci_dev *pci = to_pci_dev(dev); 105 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 106 struct hdac_bus *bus = ebus_to_hbus(ebus); 107 u32 val; 108 109 /* Update PDCGE bit of CGCTL register */ 110 val = enable ? AZX_CGCTL_ADSPDCGE : 0; 111 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); 112 113 /* Update L1SEN bit of EM2 register */ 114 val = enable ? AZX_REG_VS_EM2_L1SEN : 0; 115 snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val); 116 117 /* Update ADSPPGD bit of PGCTL register */ 118 val = enable ? 0 : AZX_PGCTL_ADSPPGD; 119 update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val); 120 } 121 122 /* 123 * While performing reset, controller may not come back properly causing 124 * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset 125 * (init chip) and then again set CGCTL.MISCBDCGE to 1 126 */ 127 static int skl_init_chip(struct hdac_bus *bus, bool full_reset) 128 { 129 struct hdac_ext_bus *ebus = hbus_to_ebus(bus); 130 struct hdac_ext_link *hlink; 131 int ret; 132 133 skl_enable_miscbdcge(bus->dev, false); 134 ret = snd_hdac_bus_init_chip(bus, full_reset); 135 136 /* Reset stream-to-link mapping */ 137 list_for_each_entry(hlink, &ebus->hlink_list, list) 138 bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV); 139 140 skl_enable_miscbdcge(bus->dev, true); 141 142 return ret; 143 } 144 145 void skl_update_d0i3c(struct device *dev, bool enable) 146 { 147 struct pci_dev *pci = to_pci_dev(dev); 148 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 149 struct hdac_bus *bus = ebus_to_hbus(ebus); 150 u8 reg; 151 int timeout = 50; 152 153 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 154 /* Do not write to D0I3C until command in progress bit is cleared */ 155 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 156 udelay(10); 157 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 158 } 159 160 /* Highly unlikely. But if it happens, flag error explicitly */ 161 if (!timeout) { 162 dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n"); 163 return; 164 } 165 166 if (enable) 167 reg = reg | AZX_REG_VS_D0I3C_I3; 168 else 169 reg = reg & (~AZX_REG_VS_D0I3C_I3); 170 171 snd_hdac_chip_writeb(bus, VS_D0I3C, reg); 172 173 timeout = 50; 174 /* Wait for cmd in progress to be cleared before exiting the function */ 175 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 176 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 177 udelay(10); 178 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 179 } 180 181 /* Highly unlikely. But if it happens, flag error explicitly */ 182 if (!timeout) { 183 dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n"); 184 return; 185 } 186 187 dev_dbg(bus->dev, "D0I3C register = 0x%x\n", 188 snd_hdac_chip_readb(bus, VS_D0I3C)); 189 } 190 191 /* called from IRQ */ 192 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) 193 { 194 snd_pcm_period_elapsed(hstr->substream); 195 } 196 197 static irqreturn_t skl_interrupt(int irq, void *dev_id) 198 { 199 struct hdac_ext_bus *ebus = dev_id; 200 struct hdac_bus *bus = ebus_to_hbus(ebus); 201 u32 status; 202 203 if (!pm_runtime_active(bus->dev)) 204 return IRQ_NONE; 205 206 spin_lock(&bus->reg_lock); 207 208 status = snd_hdac_chip_readl(bus, INTSTS); 209 if (status == 0 || status == 0xffffffff) { 210 spin_unlock(&bus->reg_lock); 211 return IRQ_NONE; 212 } 213 214 /* clear rirb int */ 215 status = snd_hdac_chip_readb(bus, RIRBSTS); 216 if (status & RIRB_INT_MASK) { 217 if (status & RIRB_INT_RESPONSE) 218 snd_hdac_bus_update_rirb(bus); 219 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 220 } 221 222 spin_unlock(&bus->reg_lock); 223 224 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; 225 } 226 227 static irqreturn_t skl_threaded_handler(int irq, void *dev_id) 228 { 229 struct hdac_ext_bus *ebus = dev_id; 230 struct hdac_bus *bus = ebus_to_hbus(ebus); 231 u32 status; 232 233 status = snd_hdac_chip_readl(bus, INTSTS); 234 235 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); 236 237 return IRQ_HANDLED; 238 } 239 240 static int skl_acquire_irq(struct hdac_ext_bus *ebus, int do_disconnect) 241 { 242 struct skl *skl = ebus_to_skl(ebus); 243 struct hdac_bus *bus = ebus_to_hbus(ebus); 244 int ret; 245 246 ret = request_threaded_irq(skl->pci->irq, skl_interrupt, 247 skl_threaded_handler, 248 IRQF_SHARED, 249 KBUILD_MODNAME, ebus); 250 if (ret) { 251 dev_err(bus->dev, 252 "unable to grab IRQ %d, disabling device\n", 253 skl->pci->irq); 254 return ret; 255 } 256 257 bus->irq = skl->pci->irq; 258 pci_intx(skl->pci, 1); 259 260 return 0; 261 } 262 263 static int skl_suspend_late(struct device *dev) 264 { 265 struct pci_dev *pci = to_pci_dev(dev); 266 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 267 struct skl *skl = ebus_to_skl(ebus); 268 269 return skl_suspend_late_dsp(skl); 270 } 271 272 #ifdef CONFIG_PM 273 static int _skl_suspend(struct hdac_ext_bus *ebus) 274 { 275 struct skl *skl = ebus_to_skl(ebus); 276 struct hdac_bus *bus = ebus_to_hbus(ebus); 277 struct pci_dev *pci = to_pci_dev(bus->dev); 278 int ret; 279 280 snd_hdac_ext_bus_link_power_down_all(ebus); 281 282 ret = skl_suspend_dsp(skl); 283 if (ret < 0) 284 return ret; 285 286 snd_hdac_bus_stop_chip(bus); 287 update_pci_dword(pci, AZX_PCIREG_PGCTL, 288 AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK); 289 skl_enable_miscbdcge(bus->dev, false); 290 snd_hdac_bus_enter_link_reset(bus); 291 skl_enable_miscbdcge(bus->dev, true); 292 skl_cleanup_resources(skl); 293 294 return 0; 295 } 296 297 static int _skl_resume(struct hdac_ext_bus *ebus) 298 { 299 struct skl *skl = ebus_to_skl(ebus); 300 struct hdac_bus *bus = ebus_to_hbus(ebus); 301 302 skl_init_pci(skl); 303 skl_init_chip(bus, true); 304 305 return skl_resume_dsp(skl); 306 } 307 #endif 308 309 #ifdef CONFIG_PM_SLEEP 310 /* 311 * power management 312 */ 313 static int skl_suspend(struct device *dev) 314 { 315 struct pci_dev *pci = to_pci_dev(dev); 316 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 317 struct skl *skl = ebus_to_skl(ebus); 318 struct hdac_bus *bus = ebus_to_hbus(ebus); 319 int ret = 0; 320 321 /* 322 * Do not suspend if streams which are marked ignore suspend are 323 * running, we need to save the state for these and continue 324 */ 325 if (skl->supend_active) { 326 /* turn off the links and stop the CORB/RIRB DMA if it is On */ 327 snd_hdac_ext_bus_link_power_down_all(ebus); 328 329 if (ebus->cmd_dma_state) 330 snd_hdac_bus_stop_cmd_io(&ebus->bus); 331 332 enable_irq_wake(bus->irq); 333 pci_save_state(pci); 334 } else { 335 ret = _skl_suspend(ebus); 336 if (ret < 0) 337 return ret; 338 skl->skl_sst->fw_loaded = false; 339 } 340 341 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 342 ret = snd_hdac_display_power(bus, false); 343 if (ret < 0) 344 dev_err(bus->dev, 345 "Cannot turn OFF display power on i915\n"); 346 } 347 348 return ret; 349 } 350 351 static int skl_resume(struct device *dev) 352 { 353 struct pci_dev *pci = to_pci_dev(dev); 354 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 355 struct skl *skl = ebus_to_skl(ebus); 356 struct hdac_bus *bus = ebus_to_hbus(ebus); 357 struct hdac_ext_link *hlink = NULL; 358 int ret; 359 360 /* Turned OFF in HDMI codec driver after codec reconfiguration */ 361 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 362 ret = snd_hdac_display_power(bus, true); 363 if (ret < 0) { 364 dev_err(bus->dev, 365 "Cannot turn on display power on i915\n"); 366 return ret; 367 } 368 } 369 370 /* 371 * resume only when we are not in suspend active, otherwise need to 372 * restore the device 373 */ 374 if (skl->supend_active) { 375 pci_restore_state(pci); 376 snd_hdac_ext_bus_link_power_up_all(ebus); 377 disable_irq_wake(bus->irq); 378 /* 379 * turn On the links which are On before active suspend 380 * and start the CORB/RIRB DMA if On before 381 * active suspend. 382 */ 383 list_for_each_entry(hlink, &ebus->hlink_list, list) { 384 if (hlink->ref_count) 385 snd_hdac_ext_bus_link_power_up(hlink); 386 } 387 388 if (ebus->cmd_dma_state) 389 snd_hdac_bus_init_cmd_io(&ebus->bus); 390 ret = 0; 391 } else { 392 ret = _skl_resume(ebus); 393 394 /* turn off the links which are off before suspend */ 395 list_for_each_entry(hlink, &ebus->hlink_list, list) { 396 if (!hlink->ref_count) 397 snd_hdac_ext_bus_link_power_down(hlink); 398 } 399 400 if (!ebus->cmd_dma_state) 401 snd_hdac_bus_stop_cmd_io(&ebus->bus); 402 } 403 404 return ret; 405 } 406 #endif /* CONFIG_PM_SLEEP */ 407 408 #ifdef CONFIG_PM 409 static int skl_runtime_suspend(struct device *dev) 410 { 411 struct pci_dev *pci = to_pci_dev(dev); 412 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 413 struct hdac_bus *bus = ebus_to_hbus(ebus); 414 415 dev_dbg(bus->dev, "in %s\n", __func__); 416 417 return _skl_suspend(ebus); 418 } 419 420 static int skl_runtime_resume(struct device *dev) 421 { 422 struct pci_dev *pci = to_pci_dev(dev); 423 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 424 struct hdac_bus *bus = ebus_to_hbus(ebus); 425 426 dev_dbg(bus->dev, "in %s\n", __func__); 427 428 return _skl_resume(ebus); 429 } 430 #endif /* CONFIG_PM */ 431 432 static const struct dev_pm_ops skl_pm = { 433 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) 434 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) 435 .suspend_late = skl_suspend_late, 436 }; 437 438 /* 439 * destructor 440 */ 441 static int skl_free(struct hdac_ext_bus *ebus) 442 { 443 struct skl *skl = ebus_to_skl(ebus); 444 struct hdac_bus *bus = ebus_to_hbus(ebus); 445 446 skl->init_done = 0; /* to be sure */ 447 448 snd_hdac_ext_stop_streams(ebus); 449 450 if (bus->irq >= 0) 451 free_irq(bus->irq, (void *)ebus); 452 snd_hdac_bus_free_stream_pages(bus); 453 snd_hdac_stream_free_all(ebus); 454 snd_hdac_link_free_all(ebus); 455 456 if (bus->remap_addr) 457 iounmap(bus->remap_addr); 458 459 pci_release_regions(skl->pci); 460 pci_disable_device(skl->pci); 461 462 snd_hdac_ext_bus_exit(ebus); 463 464 cancel_work_sync(&skl->probe_work); 465 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 466 snd_hdac_i915_exit(&ebus->bus); 467 468 return 0; 469 } 470 471 /* 472 * For each ssp there are 3 clocks (mclk/sclk/sclkfs). 473 * e.g. for ssp0, clocks will be named as 474 * "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs" 475 * So for skl+, there are 6 ssps, so 18 clocks will be created. 476 */ 477 static struct skl_ssp_clk skl_ssp_clks[] = { 478 {.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"}, 479 {.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"}, 480 {.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"}, 481 {.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"}, 482 {.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"}, 483 {.name = "ssp2_sclkfs"}, 484 {.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"}, 485 {.name = "ssp5_sclkfs"}, 486 }; 487 488 static int skl_find_machine(struct skl *skl, void *driver_data) 489 { 490 struct snd_soc_acpi_mach *mach = driver_data; 491 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); 492 struct skl_machine_pdata *pdata; 493 494 mach = snd_soc_acpi_find_machine(mach); 495 if (mach == NULL) { 496 dev_err(bus->dev, "No matching machine driver found\n"); 497 return -ENODEV; 498 } 499 500 skl->mach = mach; 501 skl->fw_name = mach->fw_filename; 502 pdata = mach->pdata; 503 504 if (pdata) { 505 skl->use_tplg_pcm = pdata->use_tplg_pcm; 506 pdata->dmic_num = skl_get_dmic_geo(skl); 507 } 508 509 return 0; 510 } 511 512 static int skl_machine_device_register(struct skl *skl) 513 { 514 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); 515 struct snd_soc_acpi_mach *mach = skl->mach; 516 struct platform_device *pdev; 517 int ret; 518 519 pdev = platform_device_alloc(mach->drv_name, -1); 520 if (pdev == NULL) { 521 dev_err(bus->dev, "platform device alloc failed\n"); 522 return -EIO; 523 } 524 525 ret = platform_device_add(pdev); 526 if (ret) { 527 dev_err(bus->dev, "failed to add machine device\n"); 528 platform_device_put(pdev); 529 return -EIO; 530 } 531 532 if (mach->pdata) 533 dev_set_drvdata(&pdev->dev, mach->pdata); 534 535 skl->i2s_dev = pdev; 536 537 return 0; 538 } 539 540 static void skl_machine_device_unregister(struct skl *skl) 541 { 542 if (skl->i2s_dev) 543 platform_device_unregister(skl->i2s_dev); 544 } 545 546 static int skl_dmic_device_register(struct skl *skl) 547 { 548 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); 549 struct platform_device *pdev; 550 int ret; 551 552 /* SKL has one dmic port, so allocate dmic device for this */ 553 pdev = platform_device_alloc("dmic-codec", -1); 554 if (!pdev) { 555 dev_err(bus->dev, "failed to allocate dmic device\n"); 556 return -ENOMEM; 557 } 558 559 ret = platform_device_add(pdev); 560 if (ret) { 561 dev_err(bus->dev, "failed to add dmic device: %d\n", ret); 562 platform_device_put(pdev); 563 return ret; 564 } 565 skl->dmic_dev = pdev; 566 567 return 0; 568 } 569 570 static void skl_dmic_device_unregister(struct skl *skl) 571 { 572 if (skl->dmic_dev) 573 platform_device_unregister(skl->dmic_dev); 574 } 575 576 static struct skl_clk_parent_src skl_clk_src[] = { 577 { .clk_id = SKL_XTAL, .name = "xtal" }, 578 { .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 }, 579 { .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 }, 580 }; 581 582 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id) 583 { 584 unsigned int i; 585 586 for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) { 587 if (skl_clk_src[i].clk_id == clk_id) 588 return &skl_clk_src[i]; 589 } 590 591 return NULL; 592 } 593 594 static void init_skl_xtal_rate(int pci_id) 595 { 596 switch (pci_id) { 597 case 0x9d70: 598 case 0x9d71: 599 skl_clk_src[0].rate = 24000000; 600 return; 601 602 default: 603 skl_clk_src[0].rate = 19200000; 604 return; 605 } 606 } 607 608 static int skl_clock_device_register(struct skl *skl) 609 { 610 struct platform_device_info pdevinfo = {NULL}; 611 struct skl_clk_pdata *clk_pdata; 612 613 clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata), 614 GFP_KERNEL); 615 if (!clk_pdata) 616 return -ENOMEM; 617 618 init_skl_xtal_rate(skl->pci->device); 619 620 clk_pdata->parent_clks = skl_clk_src; 621 clk_pdata->ssp_clks = skl_ssp_clks; 622 clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks); 623 624 /* Query NHLT to fill the rates and parent */ 625 skl_get_clks(skl, clk_pdata->ssp_clks); 626 clk_pdata->pvt_data = skl; 627 628 /* Register Platform device */ 629 pdevinfo.parent = &skl->pci->dev; 630 pdevinfo.id = -1; 631 pdevinfo.name = "skl-ssp-clk"; 632 pdevinfo.data = clk_pdata; 633 pdevinfo.size_data = sizeof(*clk_pdata); 634 skl->clk_dev = platform_device_register_full(&pdevinfo); 635 return PTR_ERR_OR_ZERO(skl->clk_dev); 636 } 637 638 static void skl_clock_device_unregister(struct skl *skl) 639 { 640 if (skl->clk_dev) 641 platform_device_unregister(skl->clk_dev); 642 } 643 644 /* 645 * Probe the given codec address 646 */ 647 static int probe_codec(struct hdac_ext_bus *ebus, int addr) 648 { 649 struct hdac_bus *bus = ebus_to_hbus(ebus); 650 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 651 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 652 unsigned int res = -1; 653 654 mutex_lock(&bus->cmd_mutex); 655 snd_hdac_bus_send_cmd(bus, cmd); 656 snd_hdac_bus_get_response(bus, addr, &res); 657 mutex_unlock(&bus->cmd_mutex); 658 if (res == -1) 659 return -EIO; 660 dev_dbg(bus->dev, "codec #%d probed OK\n", addr); 661 662 return snd_hdac_ext_bus_device_init(ebus, addr); 663 } 664 665 /* Codec initialization */ 666 static void skl_codec_create(struct hdac_ext_bus *ebus) 667 { 668 struct hdac_bus *bus = ebus_to_hbus(ebus); 669 int c, max_slots; 670 671 max_slots = HDA_MAX_CODECS; 672 673 /* First try to probe all given codec slots */ 674 for (c = 0; c < max_slots; c++) { 675 if ((bus->codec_mask & (1 << c))) { 676 if (probe_codec(ebus, c) < 0) { 677 /* 678 * Some BIOSen give you wrong codec addresses 679 * that don't exist 680 */ 681 dev_warn(bus->dev, 682 "Codec #%d probe error; disabling it...\n", c); 683 bus->codec_mask &= ~(1 << c); 684 /* 685 * More badly, accessing to a non-existing 686 * codec often screws up the controller bus, 687 * and disturbs the further communications. 688 * Thus if an error occurs during probing, 689 * better to reset the controller bus to get 690 * back to the sanity state. 691 */ 692 snd_hdac_bus_stop_chip(bus); 693 skl_init_chip(bus, true); 694 } 695 } 696 } 697 } 698 699 static const struct hdac_bus_ops bus_core_ops = { 700 .command = snd_hdac_bus_send_cmd, 701 .get_response = snd_hdac_bus_get_response, 702 }; 703 704 static int skl_i915_init(struct hdac_bus *bus) 705 { 706 int err; 707 708 /* 709 * The HDMI codec is in GPU so we need to ensure that it is powered 710 * up and ready for probe 711 */ 712 err = snd_hdac_i915_init(bus); 713 if (err < 0) 714 return err; 715 716 err = snd_hdac_display_power(bus, true); 717 if (err < 0) 718 dev_err(bus->dev, "Cannot turn on display power on i915\n"); 719 720 return err; 721 } 722 723 static void skl_probe_work(struct work_struct *work) 724 { 725 struct skl *skl = container_of(work, struct skl, probe_work); 726 struct hdac_ext_bus *ebus = &skl->ebus; 727 struct hdac_bus *bus = ebus_to_hbus(ebus); 728 struct hdac_ext_link *hlink = NULL; 729 int err; 730 731 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 732 err = skl_i915_init(bus); 733 if (err < 0) 734 return; 735 } 736 737 err = skl_init_chip(bus, true); 738 if (err < 0) { 739 dev_err(bus->dev, "Init chip failed with err: %d\n", err); 740 goto out_err; 741 } 742 743 /* codec detection */ 744 if (!bus->codec_mask) 745 dev_info(bus->dev, "no hda codecs found!\n"); 746 747 /* create codec instances */ 748 skl_codec_create(ebus); 749 750 /* register platform dai and controls */ 751 err = skl_platform_register(bus->dev); 752 if (err < 0) { 753 dev_err(bus->dev, "platform register failed: %d\n", err); 754 return; 755 } 756 757 if (bus->ppcap) { 758 err = skl_machine_device_register(skl); 759 if (err < 0) { 760 dev_err(bus->dev, "machine register failed: %d\n", err); 761 goto out_err; 762 } 763 } 764 765 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 766 err = snd_hdac_display_power(bus, false); 767 if (err < 0) { 768 dev_err(bus->dev, "Cannot turn off display power on i915\n"); 769 skl_machine_device_unregister(skl); 770 return; 771 } 772 } 773 774 /* 775 * we are done probing so decrement link counts 776 */ 777 list_for_each_entry(hlink, &ebus->hlink_list, list) 778 snd_hdac_ext_bus_link_put(ebus, hlink); 779 780 /* configure PM */ 781 pm_runtime_put_noidle(bus->dev); 782 pm_runtime_allow(bus->dev); 783 skl->init_done = 1; 784 785 return; 786 787 out_err: 788 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 789 err = snd_hdac_display_power(bus, false); 790 } 791 792 /* 793 * constructor 794 */ 795 static int skl_create(struct pci_dev *pci, 796 const struct hdac_io_ops *io_ops, 797 struct skl **rskl) 798 { 799 struct skl *skl; 800 struct hdac_ext_bus *ebus; 801 802 int err; 803 804 *rskl = NULL; 805 806 err = pci_enable_device(pci); 807 if (err < 0) 808 return err; 809 810 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); 811 if (!skl) { 812 pci_disable_device(pci); 813 return -ENOMEM; 814 } 815 ebus = &skl->ebus; 816 snd_hdac_ext_bus_init(ebus, &pci->dev, &bus_core_ops, io_ops); 817 ebus->bus.use_posbuf = 1; 818 skl->pci = pci; 819 INIT_WORK(&skl->probe_work, skl_probe_work); 820 821 ebus->bus.bdl_pos_adj = 0; 822 823 *rskl = skl; 824 825 return 0; 826 } 827 828 static int skl_first_init(struct hdac_ext_bus *ebus) 829 { 830 struct skl *skl = ebus_to_skl(ebus); 831 struct hdac_bus *bus = ebus_to_hbus(ebus); 832 struct pci_dev *pci = skl->pci; 833 int err; 834 unsigned short gcap; 835 int cp_streams, pb_streams, start_idx; 836 837 err = pci_request_regions(pci, "Skylake HD audio"); 838 if (err < 0) 839 return err; 840 841 bus->addr = pci_resource_start(pci, 0); 842 bus->remap_addr = pci_ioremap_bar(pci, 0); 843 if (bus->remap_addr == NULL) { 844 dev_err(bus->dev, "ioremap error\n"); 845 return -ENXIO; 846 } 847 848 skl_init_chip(bus, true); 849 850 snd_hdac_bus_parse_capabilities(bus); 851 852 if (skl_acquire_irq(ebus, 0) < 0) 853 return -EBUSY; 854 855 pci_set_master(pci); 856 synchronize_irq(bus->irq); 857 858 gcap = snd_hdac_chip_readw(bus, GCAP); 859 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); 860 861 /* allow 64bit DMA address if supported by H/W */ 862 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) { 863 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64)); 864 } else { 865 dma_set_mask(bus->dev, DMA_BIT_MASK(32)); 866 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32)); 867 } 868 869 /* read number of streams from GCAP register */ 870 cp_streams = (gcap >> 8) & 0x0f; 871 pb_streams = (gcap >> 12) & 0x0f; 872 873 if (!pb_streams && !cp_streams) 874 return -EIO; 875 876 ebus->num_streams = cp_streams + pb_streams; 877 878 /* initialize streams */ 879 snd_hdac_ext_stream_init_all 880 (ebus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); 881 start_idx = cp_streams; 882 snd_hdac_ext_stream_init_all 883 (ebus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); 884 885 err = snd_hdac_bus_alloc_stream_pages(bus); 886 if (err < 0) 887 return err; 888 889 /* initialize chip */ 890 skl_init_pci(skl); 891 892 return skl_init_chip(bus, true); 893 } 894 895 static int skl_probe(struct pci_dev *pci, 896 const struct pci_device_id *pci_id) 897 { 898 struct skl *skl; 899 struct hdac_ext_bus *ebus = NULL; 900 struct hdac_bus *bus = NULL; 901 int err; 902 903 /* we use ext core ops, so provide NULL for ops here */ 904 err = skl_create(pci, NULL, &skl); 905 if (err < 0) 906 return err; 907 908 ebus = &skl->ebus; 909 bus = ebus_to_hbus(ebus); 910 911 err = skl_first_init(ebus); 912 if (err < 0) 913 goto out_free; 914 915 skl->pci_id = pci->device; 916 917 device_disable_async_suspend(bus->dev); 918 919 skl->nhlt = skl_nhlt_init(bus->dev); 920 921 if (skl->nhlt == NULL) { 922 err = -ENODEV; 923 goto out_free; 924 } 925 926 err = skl_nhlt_create_sysfs(skl); 927 if (err < 0) 928 goto out_nhlt_free; 929 930 skl_nhlt_update_topology_bin(skl); 931 932 pci_set_drvdata(skl->pci, ebus); 933 934 /* check if dsp is there */ 935 if (bus->ppcap) { 936 /* create device for dsp clk */ 937 err = skl_clock_device_register(skl); 938 if (err < 0) 939 goto out_clk_free; 940 941 err = skl_find_machine(skl, (void *)pci_id->driver_data); 942 if (err < 0) 943 goto out_nhlt_free; 944 945 err = skl_init_dsp(skl); 946 if (err < 0) { 947 dev_dbg(bus->dev, "error failed to register dsp\n"); 948 goto out_nhlt_free; 949 } 950 skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge; 951 skl->skl_sst->clock_power_gating = skl_clock_power_gating; 952 } 953 if (bus->mlcap) 954 snd_hdac_ext_bus_get_ml_capabilities(ebus); 955 956 snd_hdac_bus_stop_chip(bus); 957 958 /* create device for soc dmic */ 959 err = skl_dmic_device_register(skl); 960 if (err < 0) 961 goto out_dsp_free; 962 963 schedule_work(&skl->probe_work); 964 965 return 0; 966 967 out_dsp_free: 968 skl_free_dsp(skl); 969 out_clk_free: 970 skl_clock_device_unregister(skl); 971 out_nhlt_free: 972 skl_nhlt_free(skl->nhlt); 973 out_free: 974 skl_free(ebus); 975 976 return err; 977 } 978 979 static void skl_shutdown(struct pci_dev *pci) 980 { 981 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 982 struct hdac_bus *bus = ebus_to_hbus(ebus); 983 struct hdac_stream *s; 984 struct hdac_ext_stream *stream; 985 struct skl *skl; 986 987 if (ebus == NULL) 988 return; 989 990 skl = ebus_to_skl(ebus); 991 992 if (!skl->init_done) 993 return; 994 995 snd_hdac_ext_stop_streams(ebus); 996 list_for_each_entry(s, &bus->stream_list, list) { 997 stream = stream_to_hdac_ext_stream(s); 998 snd_hdac_ext_stream_decouple(ebus, stream, false); 999 } 1000 1001 snd_hdac_bus_stop_chip(bus); 1002 } 1003 1004 static void skl_remove(struct pci_dev *pci) 1005 { 1006 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 1007 struct skl *skl = ebus_to_skl(ebus); 1008 1009 release_firmware(skl->tplg); 1010 1011 pm_runtime_get_noresume(&pci->dev); 1012 1013 /* codec removal, invoke bus_device_remove */ 1014 snd_hdac_ext_bus_device_remove(ebus); 1015 1016 skl->debugfs = NULL; 1017 skl_platform_unregister(&pci->dev); 1018 skl_free_dsp(skl); 1019 skl_machine_device_unregister(skl); 1020 skl_dmic_device_unregister(skl); 1021 skl_clock_device_unregister(skl); 1022 skl_nhlt_remove_sysfs(skl); 1023 skl_nhlt_free(skl->nhlt); 1024 skl_free(ebus); 1025 dev_set_drvdata(&pci->dev, NULL); 1026 } 1027 1028 /* PCI IDs */ 1029 static const struct pci_device_id skl_ids[] = { 1030 /* Sunrise Point-LP */ 1031 { PCI_DEVICE(0x8086, 0x9d70), 1032 .driver_data = (unsigned long)&snd_soc_acpi_intel_skl_machines}, 1033 /* BXT-P */ 1034 { PCI_DEVICE(0x8086, 0x5a98), 1035 .driver_data = (unsigned long)&snd_soc_acpi_intel_bxt_machines}, 1036 /* KBL */ 1037 { PCI_DEVICE(0x8086, 0x9D71), 1038 .driver_data = (unsigned long)&snd_soc_acpi_intel_kbl_machines}, 1039 /* GLK */ 1040 { PCI_DEVICE(0x8086, 0x3198), 1041 .driver_data = (unsigned long)&snd_soc_acpi_intel_glk_machines}, 1042 /* CNL */ 1043 { PCI_DEVICE(0x8086, 0x9dc8), 1044 .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, 1045 { 0, } 1046 }; 1047 MODULE_DEVICE_TABLE(pci, skl_ids); 1048 1049 /* pci_driver definition */ 1050 static struct pci_driver skl_driver = { 1051 .name = KBUILD_MODNAME, 1052 .id_table = skl_ids, 1053 .probe = skl_probe, 1054 .remove = skl_remove, 1055 .shutdown = skl_shutdown, 1056 .driver = { 1057 .pm = &skl_pm, 1058 }, 1059 }; 1060 module_pci_driver(skl_driver); 1061 1062 MODULE_LICENSE("GPL v2"); 1063 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver"); 1064