1 /* 2 * skl.c - Implementation of ASoC Intel SKL HD Audio driver 3 * 4 * Copyright (C) 2014-2015 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * 7 * Derived mostly from Intel HDA driver with following copyrights: 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; version 2 of the License. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 22 */ 23 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/platform_device.h> 28 #include <linux/firmware.h> 29 #include <linux/delay.h> 30 #include <sound/pcm.h> 31 #include <sound/soc-acpi.h> 32 #include <sound/hda_register.h> 33 #include <sound/hdaudio.h> 34 #include <sound/hda_i915.h> 35 #include "skl.h" 36 #include "skl-sst-dsp.h" 37 #include "skl-sst-ipc.h" 38 39 static struct skl_machine_pdata skl_dmic_data; 40 41 /* 42 * initialize the PCI registers 43 */ 44 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, 45 unsigned char mask, unsigned char val) 46 { 47 unsigned char data; 48 49 pci_read_config_byte(pci, reg, &data); 50 data &= ~mask; 51 data |= (val & mask); 52 pci_write_config_byte(pci, reg, data); 53 } 54 55 static void skl_init_pci(struct skl *skl) 56 { 57 struct hdac_bus *bus = skl_to_bus(skl); 58 59 /* 60 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 61 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 62 * Ensuring these bits are 0 clears playback static on some HD Audio 63 * codecs. 64 * The PCI register TCSEL is defined in the Intel manuals. 65 */ 66 dev_dbg(bus->dev, "Clearing TCSEL\n"); 67 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); 68 } 69 70 static void update_pci_dword(struct pci_dev *pci, 71 unsigned int reg, u32 mask, u32 val) 72 { 73 u32 data = 0; 74 75 pci_read_config_dword(pci, reg, &data); 76 data &= ~mask; 77 data |= (val & mask); 78 pci_write_config_dword(pci, reg, data); 79 } 80 81 /* 82 * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits 83 * 84 * @dev: device pointer 85 * @enable: enable/disable flag 86 */ 87 static void skl_enable_miscbdcge(struct device *dev, bool enable) 88 { 89 struct pci_dev *pci = to_pci_dev(dev); 90 u32 val; 91 92 val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; 93 94 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); 95 } 96 97 /** 98 * skl_clock_power_gating: Enable/Disable clock and power gating 99 * 100 * @dev: Device pointer 101 * @enable: Enable/Disable flag 102 */ 103 static void skl_clock_power_gating(struct device *dev, bool enable) 104 { 105 struct pci_dev *pci = to_pci_dev(dev); 106 struct hdac_bus *bus = pci_get_drvdata(pci); 107 u32 val; 108 109 /* Update PDCGE bit of CGCTL register */ 110 val = enable ? AZX_CGCTL_ADSPDCGE : 0; 111 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); 112 113 /* Update L1SEN bit of EM2 register */ 114 val = enable ? AZX_REG_VS_EM2_L1SEN : 0; 115 snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val); 116 117 /* Update ADSPPGD bit of PGCTL register */ 118 val = enable ? 0 : AZX_PGCTL_ADSPPGD; 119 update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val); 120 } 121 122 /* 123 * While performing reset, controller may not come back properly causing 124 * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset 125 * (init chip) and then again set CGCTL.MISCBDCGE to 1 126 */ 127 static int skl_init_chip(struct hdac_bus *bus, bool full_reset) 128 { 129 struct hdac_ext_link *hlink; 130 int ret; 131 132 skl_enable_miscbdcge(bus->dev, false); 133 ret = snd_hdac_bus_init_chip(bus, full_reset); 134 135 /* Reset stream-to-link mapping */ 136 list_for_each_entry(hlink, &bus->hlink_list, list) 137 bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV); 138 139 skl_enable_miscbdcge(bus->dev, true); 140 141 return ret; 142 } 143 144 void skl_update_d0i3c(struct device *dev, bool enable) 145 { 146 struct pci_dev *pci = to_pci_dev(dev); 147 struct hdac_bus *bus = pci_get_drvdata(pci); 148 u8 reg; 149 int timeout = 50; 150 151 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 152 /* Do not write to D0I3C until command in progress bit is cleared */ 153 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 154 udelay(10); 155 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 156 } 157 158 /* Highly unlikely. But if it happens, flag error explicitly */ 159 if (!timeout) { 160 dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n"); 161 return; 162 } 163 164 if (enable) 165 reg = reg | AZX_REG_VS_D0I3C_I3; 166 else 167 reg = reg & (~AZX_REG_VS_D0I3C_I3); 168 169 snd_hdac_chip_writeb(bus, VS_D0I3C, reg); 170 171 timeout = 50; 172 /* Wait for cmd in progress to be cleared before exiting the function */ 173 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 174 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 175 udelay(10); 176 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 177 } 178 179 /* Highly unlikely. But if it happens, flag error explicitly */ 180 if (!timeout) { 181 dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n"); 182 return; 183 } 184 185 dev_dbg(bus->dev, "D0I3C register = 0x%x\n", 186 snd_hdac_chip_readb(bus, VS_D0I3C)); 187 } 188 189 /* called from IRQ */ 190 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) 191 { 192 snd_pcm_period_elapsed(hstr->substream); 193 } 194 195 static irqreturn_t skl_interrupt(int irq, void *dev_id) 196 { 197 struct hdac_bus *bus = dev_id; 198 u32 status; 199 200 if (!pm_runtime_active(bus->dev)) 201 return IRQ_NONE; 202 203 spin_lock(&bus->reg_lock); 204 205 status = snd_hdac_chip_readl(bus, INTSTS); 206 if (status == 0 || status == 0xffffffff) { 207 spin_unlock(&bus->reg_lock); 208 return IRQ_NONE; 209 } 210 211 /* clear rirb int */ 212 status = snd_hdac_chip_readb(bus, RIRBSTS); 213 if (status & RIRB_INT_MASK) { 214 if (status & RIRB_INT_RESPONSE) 215 snd_hdac_bus_update_rirb(bus); 216 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 217 } 218 219 spin_unlock(&bus->reg_lock); 220 221 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; 222 } 223 224 static irqreturn_t skl_threaded_handler(int irq, void *dev_id) 225 { 226 struct hdac_bus *bus = dev_id; 227 u32 status; 228 229 status = snd_hdac_chip_readl(bus, INTSTS); 230 231 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); 232 233 return IRQ_HANDLED; 234 } 235 236 static int skl_acquire_irq(struct hdac_bus *bus, int do_disconnect) 237 { 238 struct skl *skl = bus_to_skl(bus); 239 int ret; 240 241 ret = request_threaded_irq(skl->pci->irq, skl_interrupt, 242 skl_threaded_handler, 243 IRQF_SHARED, 244 KBUILD_MODNAME, bus); 245 if (ret) { 246 dev_err(bus->dev, 247 "unable to grab IRQ %d, disabling device\n", 248 skl->pci->irq); 249 return ret; 250 } 251 252 bus->irq = skl->pci->irq; 253 pci_intx(skl->pci, 1); 254 255 return 0; 256 } 257 258 static int skl_suspend_late(struct device *dev) 259 { 260 struct pci_dev *pci = to_pci_dev(dev); 261 struct hdac_bus *bus = pci_get_drvdata(pci); 262 struct skl *skl = bus_to_skl(bus); 263 264 return skl_suspend_late_dsp(skl); 265 } 266 267 #ifdef CONFIG_PM 268 static int _skl_suspend(struct hdac_bus *bus) 269 { 270 struct skl *skl = bus_to_skl(bus); 271 struct pci_dev *pci = to_pci_dev(bus->dev); 272 int ret; 273 274 snd_hdac_ext_bus_link_power_down_all(bus); 275 276 ret = skl_suspend_dsp(skl); 277 if (ret < 0) 278 return ret; 279 280 snd_hdac_bus_stop_chip(bus); 281 update_pci_dword(pci, AZX_PCIREG_PGCTL, 282 AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK); 283 skl_enable_miscbdcge(bus->dev, false); 284 snd_hdac_bus_enter_link_reset(bus); 285 skl_enable_miscbdcge(bus->dev, true); 286 skl_cleanup_resources(skl); 287 288 return 0; 289 } 290 291 static int _skl_resume(struct hdac_bus *bus) 292 { 293 struct skl *skl = bus_to_skl(bus); 294 295 skl_init_pci(skl); 296 skl_init_chip(bus, true); 297 298 return skl_resume_dsp(skl); 299 } 300 #endif 301 302 #ifdef CONFIG_PM_SLEEP 303 /* 304 * power management 305 */ 306 static int skl_suspend(struct device *dev) 307 { 308 struct pci_dev *pci = to_pci_dev(dev); 309 struct hdac_bus *bus = pci_get_drvdata(pci); 310 struct skl *skl = bus_to_skl(bus); 311 int ret = 0; 312 313 /* 314 * Do not suspend if streams which are marked ignore suspend are 315 * running, we need to save the state for these and continue 316 */ 317 if (skl->supend_active) { 318 /* turn off the links and stop the CORB/RIRB DMA if it is On */ 319 snd_hdac_ext_bus_link_power_down_all(bus); 320 321 if (bus->cmd_dma_state) 322 snd_hdac_bus_stop_cmd_io(bus); 323 324 enable_irq_wake(bus->irq); 325 pci_save_state(pci); 326 } else { 327 ret = _skl_suspend(bus); 328 if (ret < 0) 329 return ret; 330 skl->skl_sst->fw_loaded = false; 331 } 332 333 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 334 ret = snd_hdac_display_power(bus, false); 335 if (ret < 0) 336 dev_err(bus->dev, 337 "Cannot turn OFF display power on i915\n"); 338 } 339 340 return ret; 341 } 342 343 static int skl_resume(struct device *dev) 344 { 345 struct pci_dev *pci = to_pci_dev(dev); 346 struct hdac_bus *bus = pci_get_drvdata(pci); 347 struct skl *skl = bus_to_skl(bus); 348 struct hdac_ext_link *hlink = NULL; 349 int ret; 350 351 /* Turned OFF in HDMI codec driver after codec reconfiguration */ 352 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 353 ret = snd_hdac_display_power(bus, true); 354 if (ret < 0) { 355 dev_err(bus->dev, 356 "Cannot turn on display power on i915\n"); 357 return ret; 358 } 359 } 360 361 /* 362 * resume only when we are not in suspend active, otherwise need to 363 * restore the device 364 */ 365 if (skl->supend_active) { 366 pci_restore_state(pci); 367 snd_hdac_ext_bus_link_power_up_all(bus); 368 disable_irq_wake(bus->irq); 369 /* 370 * turn On the links which are On before active suspend 371 * and start the CORB/RIRB DMA if On before 372 * active suspend. 373 */ 374 list_for_each_entry(hlink, &bus->hlink_list, list) { 375 if (hlink->ref_count) 376 snd_hdac_ext_bus_link_power_up(hlink); 377 } 378 379 ret = 0; 380 if (bus->cmd_dma_state) 381 snd_hdac_bus_init_cmd_io(bus); 382 } else { 383 ret = _skl_resume(bus); 384 385 /* turn off the links which are off before suspend */ 386 list_for_each_entry(hlink, &bus->hlink_list, list) { 387 if (!hlink->ref_count) 388 snd_hdac_ext_bus_link_power_down(hlink); 389 } 390 391 if (!bus->cmd_dma_state) 392 snd_hdac_bus_stop_cmd_io(bus); 393 } 394 395 return ret; 396 } 397 #endif /* CONFIG_PM_SLEEP */ 398 399 #ifdef CONFIG_PM 400 static int skl_runtime_suspend(struct device *dev) 401 { 402 struct pci_dev *pci = to_pci_dev(dev); 403 struct hdac_bus *bus = pci_get_drvdata(pci); 404 405 dev_dbg(bus->dev, "in %s\n", __func__); 406 407 return _skl_suspend(bus); 408 } 409 410 static int skl_runtime_resume(struct device *dev) 411 { 412 struct pci_dev *pci = to_pci_dev(dev); 413 struct hdac_bus *bus = pci_get_drvdata(pci); 414 415 dev_dbg(bus->dev, "in %s\n", __func__); 416 417 return _skl_resume(bus); 418 } 419 #endif /* CONFIG_PM */ 420 421 static const struct dev_pm_ops skl_pm = { 422 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) 423 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) 424 .suspend_late = skl_suspend_late, 425 }; 426 427 /* 428 * destructor 429 */ 430 static int skl_free(struct hdac_bus *bus) 431 { 432 struct skl *skl = bus_to_skl(bus); 433 434 skl->init_done = 0; /* to be sure */ 435 436 snd_hdac_ext_stop_streams(bus); 437 438 if (bus->irq >= 0) 439 free_irq(bus->irq, (void *)bus); 440 snd_hdac_bus_free_stream_pages(bus); 441 snd_hdac_stream_free_all(bus); 442 snd_hdac_link_free_all(bus); 443 444 if (bus->remap_addr) 445 iounmap(bus->remap_addr); 446 447 pci_release_regions(skl->pci); 448 pci_disable_device(skl->pci); 449 450 snd_hdac_ext_bus_exit(bus); 451 452 cancel_work_sync(&skl->probe_work); 453 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 454 snd_hdac_i915_exit(bus); 455 456 return 0; 457 } 458 459 /* 460 * For each ssp there are 3 clocks (mclk/sclk/sclkfs). 461 * e.g. for ssp0, clocks will be named as 462 * "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs" 463 * So for skl+, there are 6 ssps, so 18 clocks will be created. 464 */ 465 static struct skl_ssp_clk skl_ssp_clks[] = { 466 {.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"}, 467 {.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"}, 468 {.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"}, 469 {.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"}, 470 {.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"}, 471 {.name = "ssp2_sclkfs"}, 472 {.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"}, 473 {.name = "ssp5_sclkfs"}, 474 }; 475 476 static int skl_find_machine(struct skl *skl, void *driver_data) 477 { 478 struct hdac_bus *bus = skl_to_bus(skl); 479 struct snd_soc_acpi_mach *mach = driver_data; 480 struct skl_machine_pdata *pdata; 481 482 mach = snd_soc_acpi_find_machine(mach); 483 if (mach == NULL) { 484 dev_err(bus->dev, "No matching machine driver found\n"); 485 return -ENODEV; 486 } 487 488 skl->mach = mach; 489 skl->fw_name = mach->fw_filename; 490 pdata = skl->mach->pdata; 491 492 if (mach->pdata) 493 skl->use_tplg_pcm = pdata->use_tplg_pcm; 494 495 return 0; 496 } 497 498 static int skl_machine_device_register(struct skl *skl) 499 { 500 struct hdac_bus *bus = skl_to_bus(skl); 501 struct snd_soc_acpi_mach *mach = skl->mach; 502 struct platform_device *pdev; 503 int ret; 504 505 pdev = platform_device_alloc(mach->drv_name, -1); 506 if (pdev == NULL) { 507 dev_err(bus->dev, "platform device alloc failed\n"); 508 return -EIO; 509 } 510 511 ret = platform_device_add(pdev); 512 if (ret) { 513 dev_err(bus->dev, "failed to add machine device\n"); 514 platform_device_put(pdev); 515 return -EIO; 516 } 517 518 if (mach->pdata) 519 dev_set_drvdata(&pdev->dev, mach->pdata); 520 521 skl->i2s_dev = pdev; 522 523 return 0; 524 } 525 526 static void skl_machine_device_unregister(struct skl *skl) 527 { 528 if (skl->i2s_dev) 529 platform_device_unregister(skl->i2s_dev); 530 } 531 532 static int skl_dmic_device_register(struct skl *skl) 533 { 534 struct hdac_bus *bus = skl_to_bus(skl); 535 struct platform_device *pdev; 536 int ret; 537 538 /* SKL has one dmic port, so allocate dmic device for this */ 539 pdev = platform_device_alloc("dmic-codec", -1); 540 if (!pdev) { 541 dev_err(bus->dev, "failed to allocate dmic device\n"); 542 return -ENOMEM; 543 } 544 545 ret = platform_device_add(pdev); 546 if (ret) { 547 dev_err(bus->dev, "failed to add dmic device: %d\n", ret); 548 platform_device_put(pdev); 549 return ret; 550 } 551 skl->dmic_dev = pdev; 552 553 return 0; 554 } 555 556 static void skl_dmic_device_unregister(struct skl *skl) 557 { 558 if (skl->dmic_dev) 559 platform_device_unregister(skl->dmic_dev); 560 } 561 562 static struct skl_clk_parent_src skl_clk_src[] = { 563 { .clk_id = SKL_XTAL, .name = "xtal" }, 564 { .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 }, 565 { .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 }, 566 }; 567 568 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id) 569 { 570 unsigned int i; 571 572 for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) { 573 if (skl_clk_src[i].clk_id == clk_id) 574 return &skl_clk_src[i]; 575 } 576 577 return NULL; 578 } 579 580 static void init_skl_xtal_rate(int pci_id) 581 { 582 switch (pci_id) { 583 case 0x9d70: 584 case 0x9d71: 585 skl_clk_src[0].rate = 24000000; 586 return; 587 588 default: 589 skl_clk_src[0].rate = 19200000; 590 return; 591 } 592 } 593 594 static int skl_clock_device_register(struct skl *skl) 595 { 596 struct platform_device_info pdevinfo = {NULL}; 597 struct skl_clk_pdata *clk_pdata; 598 599 clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata), 600 GFP_KERNEL); 601 if (!clk_pdata) 602 return -ENOMEM; 603 604 init_skl_xtal_rate(skl->pci->device); 605 606 clk_pdata->parent_clks = skl_clk_src; 607 clk_pdata->ssp_clks = skl_ssp_clks; 608 clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks); 609 610 /* Query NHLT to fill the rates and parent */ 611 skl_get_clks(skl, clk_pdata->ssp_clks); 612 clk_pdata->pvt_data = skl; 613 614 /* Register Platform device */ 615 pdevinfo.parent = &skl->pci->dev; 616 pdevinfo.id = -1; 617 pdevinfo.name = "skl-ssp-clk"; 618 pdevinfo.data = clk_pdata; 619 pdevinfo.size_data = sizeof(*clk_pdata); 620 skl->clk_dev = platform_device_register_full(&pdevinfo); 621 return PTR_ERR_OR_ZERO(skl->clk_dev); 622 } 623 624 static void skl_clock_device_unregister(struct skl *skl) 625 { 626 if (skl->clk_dev) 627 platform_device_unregister(skl->clk_dev); 628 } 629 630 /* 631 * Probe the given codec address 632 */ 633 static int probe_codec(struct hdac_bus *bus, int addr) 634 { 635 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 636 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 637 unsigned int res = -1; 638 struct skl *skl = bus_to_skl(bus); 639 struct hdac_device *hdev; 640 641 mutex_lock(&bus->cmd_mutex); 642 snd_hdac_bus_send_cmd(bus, cmd); 643 snd_hdac_bus_get_response(bus, addr, &res); 644 mutex_unlock(&bus->cmd_mutex); 645 if (res == -1) 646 return -EIO; 647 dev_dbg(bus->dev, "codec #%d probed OK\n", addr); 648 649 hdev = devm_kzalloc(&skl->pci->dev, sizeof(*hdev), GFP_KERNEL); 650 if (!hdev) 651 return -ENOMEM; 652 653 return snd_hdac_ext_bus_device_init(bus, addr, hdev); 654 } 655 656 /* Codec initialization */ 657 static void skl_codec_create(struct hdac_bus *bus) 658 { 659 int c, max_slots; 660 661 max_slots = HDA_MAX_CODECS; 662 663 /* First try to probe all given codec slots */ 664 for (c = 0; c < max_slots; c++) { 665 if ((bus->codec_mask & (1 << c))) { 666 if (probe_codec(bus, c) < 0) { 667 /* 668 * Some BIOSen give you wrong codec addresses 669 * that don't exist 670 */ 671 dev_warn(bus->dev, 672 "Codec #%d probe error; disabling it...\n", c); 673 bus->codec_mask &= ~(1 << c); 674 /* 675 * More badly, accessing to a non-existing 676 * codec often screws up the controller bus, 677 * and disturbs the further communications. 678 * Thus if an error occurs during probing, 679 * better to reset the controller bus to get 680 * back to the sanity state. 681 */ 682 snd_hdac_bus_stop_chip(bus); 683 skl_init_chip(bus, true); 684 } 685 } 686 } 687 } 688 689 static const struct hdac_bus_ops bus_core_ops = { 690 .command = snd_hdac_bus_send_cmd, 691 .get_response = snd_hdac_bus_get_response, 692 }; 693 694 static int skl_i915_init(struct hdac_bus *bus) 695 { 696 int err; 697 698 /* 699 * The HDMI codec is in GPU so we need to ensure that it is powered 700 * up and ready for probe 701 */ 702 err = snd_hdac_i915_init(bus); 703 if (err < 0) 704 return err; 705 706 err = snd_hdac_display_power(bus, true); 707 if (err < 0) 708 dev_err(bus->dev, "Cannot turn on display power on i915\n"); 709 710 return err; 711 } 712 713 static void skl_probe_work(struct work_struct *work) 714 { 715 struct skl *skl = container_of(work, struct skl, probe_work); 716 struct hdac_bus *bus = skl_to_bus(skl); 717 struct hdac_ext_link *hlink = NULL; 718 int err; 719 720 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 721 err = skl_i915_init(bus); 722 if (err < 0) 723 return; 724 } 725 726 err = skl_init_chip(bus, true); 727 if (err < 0) { 728 dev_err(bus->dev, "Init chip failed with err: %d\n", err); 729 goto out_err; 730 } 731 732 /* codec detection */ 733 if (!bus->codec_mask) 734 dev_info(bus->dev, "no hda codecs found!\n"); 735 736 /* create codec instances */ 737 skl_codec_create(bus); 738 739 /* register platform dai and controls */ 740 err = skl_platform_register(bus->dev); 741 if (err < 0) { 742 dev_err(bus->dev, "platform register failed: %d\n", err); 743 return; 744 } 745 746 if (bus->ppcap) { 747 err = skl_machine_device_register(skl); 748 if (err < 0) { 749 dev_err(bus->dev, "machine register failed: %d\n", err); 750 goto out_err; 751 } 752 } 753 754 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 755 err = snd_hdac_display_power(bus, false); 756 if (err < 0) { 757 dev_err(bus->dev, "Cannot turn off display power on i915\n"); 758 skl_machine_device_unregister(skl); 759 return; 760 } 761 } 762 763 /* 764 * we are done probing so decrement link counts 765 */ 766 list_for_each_entry(hlink, &bus->hlink_list, list) 767 snd_hdac_ext_bus_link_put(bus, hlink); 768 769 /* configure PM */ 770 pm_runtime_put_noidle(bus->dev); 771 pm_runtime_allow(bus->dev); 772 skl->init_done = 1; 773 774 return; 775 776 out_err: 777 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 778 err = snd_hdac_display_power(bus, false); 779 } 780 781 /* 782 * constructor 783 */ 784 static int skl_create(struct pci_dev *pci, 785 const struct hdac_io_ops *io_ops, 786 struct skl **rskl) 787 { 788 struct skl *skl; 789 struct hdac_bus *bus; 790 791 int err; 792 793 *rskl = NULL; 794 795 err = pci_enable_device(pci); 796 if (err < 0) 797 return err; 798 799 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); 800 if (!skl) { 801 pci_disable_device(pci); 802 return -ENOMEM; 803 } 804 805 bus = skl_to_bus(skl); 806 snd_hdac_ext_bus_init(bus, &pci->dev, &bus_core_ops, io_ops, NULL); 807 bus->use_posbuf = 1; 808 skl->pci = pci; 809 INIT_WORK(&skl->probe_work, skl_probe_work); 810 bus->bdl_pos_adj = 0; 811 812 *rskl = skl; 813 814 return 0; 815 } 816 817 static int skl_first_init(struct hdac_bus *bus) 818 { 819 struct skl *skl = bus_to_skl(bus); 820 struct pci_dev *pci = skl->pci; 821 int err; 822 unsigned short gcap; 823 int cp_streams, pb_streams, start_idx; 824 825 err = pci_request_regions(pci, "Skylake HD audio"); 826 if (err < 0) 827 return err; 828 829 bus->addr = pci_resource_start(pci, 0); 830 bus->remap_addr = pci_ioremap_bar(pci, 0); 831 if (bus->remap_addr == NULL) { 832 dev_err(bus->dev, "ioremap error\n"); 833 return -ENXIO; 834 } 835 836 skl_init_chip(bus, true); 837 838 snd_hdac_bus_parse_capabilities(bus); 839 840 if (skl_acquire_irq(bus, 0) < 0) 841 return -EBUSY; 842 843 pci_set_master(pci); 844 synchronize_irq(bus->irq); 845 846 gcap = snd_hdac_chip_readw(bus, GCAP); 847 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); 848 849 /* allow 64bit DMA address if supported by H/W */ 850 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) { 851 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64)); 852 } else { 853 dma_set_mask(bus->dev, DMA_BIT_MASK(32)); 854 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32)); 855 } 856 857 /* read number of streams from GCAP register */ 858 cp_streams = (gcap >> 8) & 0x0f; 859 pb_streams = (gcap >> 12) & 0x0f; 860 861 if (!pb_streams && !cp_streams) 862 return -EIO; 863 864 bus->num_streams = cp_streams + pb_streams; 865 866 /* initialize streams */ 867 snd_hdac_ext_stream_init_all 868 (bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); 869 start_idx = cp_streams; 870 snd_hdac_ext_stream_init_all 871 (bus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); 872 873 err = snd_hdac_bus_alloc_stream_pages(bus); 874 if (err < 0) 875 return err; 876 877 /* initialize chip */ 878 skl_init_pci(skl); 879 880 return skl_init_chip(bus, true); 881 } 882 883 static int skl_probe(struct pci_dev *pci, 884 const struct pci_device_id *pci_id) 885 { 886 struct skl *skl; 887 struct hdac_bus *bus = NULL; 888 int err; 889 890 /* we use ext core ops, so provide NULL for ops here */ 891 err = skl_create(pci, NULL, &skl); 892 if (err < 0) 893 return err; 894 895 bus = skl_to_bus(skl); 896 897 err = skl_first_init(bus); 898 if (err < 0) 899 goto out_free; 900 901 skl->pci_id = pci->device; 902 903 device_disable_async_suspend(bus->dev); 904 905 skl->nhlt = skl_nhlt_init(bus->dev); 906 907 if (skl->nhlt == NULL) { 908 err = -ENODEV; 909 goto out_free; 910 } 911 912 err = skl_nhlt_create_sysfs(skl); 913 if (err < 0) 914 goto out_nhlt_free; 915 916 skl_nhlt_update_topology_bin(skl); 917 918 pci_set_drvdata(skl->pci, bus); 919 920 skl_dmic_data.dmic_num = skl_get_dmic_geo(skl); 921 922 /* check if dsp is there */ 923 if (bus->ppcap) { 924 /* create device for dsp clk */ 925 err = skl_clock_device_register(skl); 926 if (err < 0) 927 goto out_clk_free; 928 929 err = skl_find_machine(skl, (void *)pci_id->driver_data); 930 if (err < 0) 931 goto out_nhlt_free; 932 933 err = skl_init_dsp(skl); 934 if (err < 0) { 935 dev_dbg(bus->dev, "error failed to register dsp\n"); 936 goto out_nhlt_free; 937 } 938 skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge; 939 skl->skl_sst->clock_power_gating = skl_clock_power_gating; 940 } 941 if (bus->mlcap) 942 snd_hdac_ext_bus_get_ml_capabilities(bus); 943 944 snd_hdac_bus_stop_chip(bus); 945 946 /* create device for soc dmic */ 947 err = skl_dmic_device_register(skl); 948 if (err < 0) 949 goto out_dsp_free; 950 951 schedule_work(&skl->probe_work); 952 953 return 0; 954 955 out_dsp_free: 956 skl_free_dsp(skl); 957 out_clk_free: 958 skl_clock_device_unregister(skl); 959 out_nhlt_free: 960 skl_nhlt_free(skl->nhlt); 961 out_free: 962 skl_free(bus); 963 964 return err; 965 } 966 967 static void skl_shutdown(struct pci_dev *pci) 968 { 969 struct hdac_bus *bus = pci_get_drvdata(pci); 970 struct hdac_stream *s; 971 struct hdac_ext_stream *stream; 972 struct skl *skl; 973 974 if (!bus) 975 return; 976 977 skl = bus_to_skl(bus); 978 979 if (!skl->init_done) 980 return; 981 982 snd_hdac_ext_stop_streams(bus); 983 list_for_each_entry(s, &bus->stream_list, list) { 984 stream = stream_to_hdac_ext_stream(s); 985 snd_hdac_ext_stream_decouple(bus, stream, false); 986 } 987 988 snd_hdac_bus_stop_chip(bus); 989 } 990 991 static void skl_remove(struct pci_dev *pci) 992 { 993 struct hdac_bus *bus = pci_get_drvdata(pci); 994 struct skl *skl = bus_to_skl(bus); 995 996 release_firmware(skl->tplg); 997 998 pm_runtime_get_noresume(&pci->dev); 999 1000 /* codec removal, invoke bus_device_remove */ 1001 snd_hdac_ext_bus_device_remove(bus); 1002 1003 skl->debugfs = NULL; 1004 skl_platform_unregister(&pci->dev); 1005 skl_free_dsp(skl); 1006 skl_machine_device_unregister(skl); 1007 skl_dmic_device_unregister(skl); 1008 skl_clock_device_unregister(skl); 1009 skl_nhlt_remove_sysfs(skl); 1010 skl_nhlt_free(skl->nhlt); 1011 skl_free(bus); 1012 dev_set_drvdata(&pci->dev, NULL); 1013 } 1014 1015 static struct snd_soc_acpi_codecs skl_codecs = { 1016 .num_codecs = 1, 1017 .codecs = {"10508825"} 1018 }; 1019 1020 static struct snd_soc_acpi_codecs kbl_codecs = { 1021 .num_codecs = 1, 1022 .codecs = {"10508825"} 1023 }; 1024 1025 static struct snd_soc_acpi_codecs bxt_codecs = { 1026 .num_codecs = 1, 1027 .codecs = {"MX98357A"} 1028 }; 1029 1030 static struct snd_soc_acpi_codecs kbl_poppy_codecs = { 1031 .num_codecs = 1, 1032 .codecs = {"10EC5663"} 1033 }; 1034 1035 static struct snd_soc_acpi_codecs kbl_5663_5514_codecs = { 1036 .num_codecs = 2, 1037 .codecs = {"10EC5663", "10EC5514"} 1038 }; 1039 1040 static struct snd_soc_acpi_codecs kbl_7219_98357_codecs = { 1041 .num_codecs = 1, 1042 .codecs = {"MX98357A"} 1043 }; 1044 1045 static struct skl_machine_pdata cnl_pdata = { 1046 .use_tplg_pcm = true, 1047 }; 1048 1049 static struct snd_soc_acpi_mach sst_skl_devdata[] = { 1050 { 1051 .id = "INT343A", 1052 .drv_name = "skl_alc286s_i2s", 1053 .fw_filename = "intel/dsp_fw_release.bin", 1054 }, 1055 { 1056 .id = "INT343B", 1057 .drv_name = "skl_n88l25_s4567", 1058 .fw_filename = "intel/dsp_fw_release.bin", 1059 .machine_quirk = snd_soc_acpi_codec_list, 1060 .quirk_data = &skl_codecs, 1061 .pdata = &skl_dmic_data 1062 }, 1063 { 1064 .id = "MX98357A", 1065 .drv_name = "skl_n88l25_m98357a", 1066 .fw_filename = "intel/dsp_fw_release.bin", 1067 .machine_quirk = snd_soc_acpi_codec_list, 1068 .quirk_data = &skl_codecs, 1069 .pdata = &skl_dmic_data 1070 }, 1071 {} 1072 }; 1073 1074 static struct snd_soc_acpi_mach sst_bxtp_devdata[] = { 1075 { 1076 .id = "INT343A", 1077 .drv_name = "bxt_alc298s_i2s", 1078 .fw_filename = "intel/dsp_fw_bxtn.bin", 1079 }, 1080 { 1081 .id = "DLGS7219", 1082 .drv_name = "bxt_da7219_max98357a_i2s", 1083 .fw_filename = "intel/dsp_fw_bxtn.bin", 1084 .machine_quirk = snd_soc_acpi_codec_list, 1085 .quirk_data = &bxt_codecs, 1086 }, 1087 {} 1088 }; 1089 1090 static struct snd_soc_acpi_mach sst_kbl_devdata[] = { 1091 { 1092 .id = "INT343A", 1093 .drv_name = "kbl_alc286s_i2s", 1094 .fw_filename = "intel/dsp_fw_kbl.bin", 1095 }, 1096 { 1097 .id = "INT343B", 1098 .drv_name = "kbl_n88l25_s4567", 1099 .fw_filename = "intel/dsp_fw_kbl.bin", 1100 .machine_quirk = snd_soc_acpi_codec_list, 1101 .quirk_data = &kbl_codecs, 1102 .pdata = &skl_dmic_data 1103 }, 1104 { 1105 .id = "MX98357A", 1106 .drv_name = "kbl_n88l25_m98357a", 1107 .fw_filename = "intel/dsp_fw_kbl.bin", 1108 .machine_quirk = snd_soc_acpi_codec_list, 1109 .quirk_data = &kbl_codecs, 1110 .pdata = &skl_dmic_data 1111 }, 1112 { 1113 .id = "MX98927", 1114 .drv_name = "kbl_r5514_5663_max", 1115 .fw_filename = "intel/dsp_fw_kbl.bin", 1116 .machine_quirk = snd_soc_acpi_codec_list, 1117 .quirk_data = &kbl_5663_5514_codecs, 1118 .pdata = &skl_dmic_data 1119 }, 1120 { 1121 .id = "MX98927", 1122 .drv_name = "kbl_rt5663_m98927", 1123 .fw_filename = "intel/dsp_fw_kbl.bin", 1124 .machine_quirk = snd_soc_acpi_codec_list, 1125 .quirk_data = &kbl_poppy_codecs, 1126 .pdata = &skl_dmic_data 1127 }, 1128 { 1129 .id = "10EC5663", 1130 .drv_name = "kbl_rt5663", 1131 .fw_filename = "intel/dsp_fw_kbl.bin", 1132 }, 1133 { 1134 .id = "DLGS7219", 1135 .drv_name = "kbl_da7219_max98357a", 1136 .fw_filename = "intel/dsp_fw_kbl.bin", 1137 .machine_quirk = snd_soc_acpi_codec_list, 1138 .quirk_data = &kbl_7219_98357_codecs, 1139 .pdata = &skl_dmic_data 1140 }, 1141 1142 {} 1143 }; 1144 1145 static struct snd_soc_acpi_mach sst_glk_devdata[] = { 1146 { 1147 .id = "INT343A", 1148 .drv_name = "glk_alc298s_i2s", 1149 .fw_filename = "intel/dsp_fw_glk.bin", 1150 }, 1151 {} 1152 }; 1153 1154 static const struct snd_soc_acpi_mach sst_cnl_devdata[] = { 1155 { 1156 .id = "INT34C2", 1157 .drv_name = "cnl_rt274", 1158 .fw_filename = "intel/dsp_fw_cnl.bin", 1159 .pdata = &cnl_pdata, 1160 }, 1161 {} 1162 }; 1163 1164 /* PCI IDs */ 1165 static const struct pci_device_id skl_ids[] = { 1166 /* Sunrise Point-LP */ 1167 { PCI_DEVICE(0x8086, 0x9d70), 1168 .driver_data = (unsigned long)&sst_skl_devdata}, 1169 /* BXT-P */ 1170 { PCI_DEVICE(0x8086, 0x5a98), 1171 .driver_data = (unsigned long)&sst_bxtp_devdata}, 1172 /* KBL */ 1173 { PCI_DEVICE(0x8086, 0x9D71), 1174 .driver_data = (unsigned long)&sst_kbl_devdata}, 1175 /* GLK */ 1176 { PCI_DEVICE(0x8086, 0x3198), 1177 .driver_data = (unsigned long)&sst_glk_devdata}, 1178 /* CNL */ 1179 { PCI_DEVICE(0x8086, 0x9dc8), 1180 .driver_data = (unsigned long)&sst_cnl_devdata}, 1181 { 0, } 1182 }; 1183 MODULE_DEVICE_TABLE(pci, skl_ids); 1184 1185 /* pci_driver definition */ 1186 static struct pci_driver skl_driver = { 1187 .name = KBUILD_MODNAME, 1188 .id_table = skl_ids, 1189 .probe = skl_probe, 1190 .remove = skl_remove, 1191 .shutdown = skl_shutdown, 1192 .driver = { 1193 .pm = &skl_pm, 1194 }, 1195 }; 1196 module_pci_driver(skl_driver); 1197 1198 MODULE_LICENSE("GPL v2"); 1199 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver"); 1200