1 /* 2 * skl.c - Implementation of ASoC Intel SKL HD Audio driver 3 * 4 * Copyright (C) 2014-2015 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * 7 * Derived mostly from Intel HDA driver with following copyrights: 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; version 2 of the License. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 22 */ 23 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/platform_device.h> 28 #include <sound/pcm.h> 29 #include "skl.h" 30 31 /* 32 * initialize the PCI registers 33 */ 34 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, 35 unsigned char mask, unsigned char val) 36 { 37 unsigned char data; 38 39 pci_read_config_byte(pci, reg, &data); 40 data &= ~mask; 41 data |= (val & mask); 42 pci_write_config_byte(pci, reg, data); 43 } 44 45 static void skl_init_pci(struct skl *skl) 46 { 47 struct hdac_ext_bus *ebus = &skl->ebus; 48 49 /* 50 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 51 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 52 * Ensuring these bits are 0 clears playback static on some HD Audio 53 * codecs. 54 * The PCI register TCSEL is defined in the Intel manuals. 55 */ 56 dev_dbg(ebus_to_hbus(ebus)->dev, "Clearing TCSEL\n"); 57 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); 58 } 59 60 /* called from IRQ */ 61 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) 62 { 63 snd_pcm_period_elapsed(hstr->substream); 64 } 65 66 static irqreturn_t skl_interrupt(int irq, void *dev_id) 67 { 68 struct hdac_ext_bus *ebus = dev_id; 69 struct hdac_bus *bus = ebus_to_hbus(ebus); 70 u32 status; 71 72 if (!pm_runtime_active(bus->dev)) 73 return IRQ_NONE; 74 75 spin_lock(&bus->reg_lock); 76 77 status = snd_hdac_chip_readl(bus, INTSTS); 78 if (status == 0 || status == 0xffffffff) { 79 spin_unlock(&bus->reg_lock); 80 return IRQ_NONE; 81 } 82 83 /* clear rirb int */ 84 status = snd_hdac_chip_readb(bus, RIRBSTS); 85 if (status & RIRB_INT_MASK) { 86 if (status & RIRB_INT_RESPONSE) 87 snd_hdac_bus_update_rirb(bus); 88 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 89 } 90 91 spin_unlock(&bus->reg_lock); 92 93 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; 94 } 95 96 static irqreturn_t skl_threaded_handler(int irq, void *dev_id) 97 { 98 struct hdac_ext_bus *ebus = dev_id; 99 struct hdac_bus *bus = ebus_to_hbus(ebus); 100 u32 status; 101 102 status = snd_hdac_chip_readl(bus, INTSTS); 103 104 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); 105 106 return IRQ_HANDLED; 107 } 108 109 static int skl_acquire_irq(struct hdac_ext_bus *ebus, int do_disconnect) 110 { 111 struct skl *skl = ebus_to_skl(ebus); 112 struct hdac_bus *bus = ebus_to_hbus(ebus); 113 int ret; 114 115 ret = request_threaded_irq(skl->pci->irq, skl_interrupt, 116 skl_threaded_handler, 117 IRQF_SHARED, 118 KBUILD_MODNAME, ebus); 119 if (ret) { 120 dev_err(bus->dev, 121 "unable to grab IRQ %d, disabling device\n", 122 skl->pci->irq); 123 return ret; 124 } 125 126 bus->irq = skl->pci->irq; 127 pci_intx(skl->pci, 1); 128 129 return 0; 130 } 131 132 #ifdef CONFIG_PM_SLEEP 133 /* 134 * power management 135 */ 136 static int skl_suspend(struct device *dev) 137 { 138 struct pci_dev *pci = to_pci_dev(dev); 139 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 140 struct hdac_bus *bus = ebus_to_hbus(ebus); 141 142 snd_hdac_bus_stop_chip(bus); 143 snd_hdac_bus_enter_link_reset(bus); 144 145 return 0; 146 } 147 148 static int skl_resume(struct device *dev) 149 { 150 struct pci_dev *pci = to_pci_dev(dev); 151 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 152 struct hdac_bus *bus = ebus_to_hbus(ebus); 153 struct skl *hda = ebus_to_skl(ebus); 154 155 skl_init_pci(hda); 156 157 snd_hdac_bus_init_chip(bus, 1); 158 159 return 0; 160 } 161 #endif /* CONFIG_PM_SLEEP */ 162 163 #ifdef CONFIG_PM 164 static int skl_runtime_suspend(struct device *dev) 165 { 166 struct pci_dev *pci = to_pci_dev(dev); 167 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 168 struct hdac_bus *bus = ebus_to_hbus(ebus); 169 struct skl *skl = ebus_to_skl(ebus); 170 int ret; 171 172 dev_dbg(bus->dev, "in %s\n", __func__); 173 174 /* enable controller wake up event */ 175 snd_hdac_chip_updatew(bus, WAKEEN, 0, STATESTS_INT_MASK); 176 177 snd_hdac_ext_bus_link_power_down_all(ebus); 178 179 ret = skl_suspend_dsp(skl); 180 if (ret < 0) 181 return ret; 182 183 snd_hdac_bus_stop_chip(bus); 184 snd_hdac_bus_enter_link_reset(bus); 185 186 return 0; 187 } 188 189 static int skl_runtime_resume(struct device *dev) 190 { 191 struct pci_dev *pci = to_pci_dev(dev); 192 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 193 struct hdac_bus *bus = ebus_to_hbus(ebus); 194 struct skl *skl = ebus_to_skl(ebus); 195 int status; 196 197 dev_dbg(bus->dev, "in %s\n", __func__); 198 199 /* Read STATESTS before controller reset */ 200 status = snd_hdac_chip_readw(bus, STATESTS); 201 202 skl_init_pci(skl); 203 snd_hdac_bus_init_chip(bus, true); 204 /* disable controller Wake Up event */ 205 snd_hdac_chip_updatew(bus, WAKEEN, STATESTS_INT_MASK, 0); 206 207 return skl_resume_dsp(skl); 208 } 209 #endif /* CONFIG_PM */ 210 211 static const struct dev_pm_ops skl_pm = { 212 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) 213 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) 214 }; 215 216 /* 217 * destructor 218 */ 219 static int skl_free(struct hdac_ext_bus *ebus) 220 { 221 struct skl *skl = ebus_to_skl(ebus); 222 struct hdac_bus *bus = ebus_to_hbus(ebus); 223 224 skl->init_failed = 1; /* to be sure */ 225 226 snd_hdac_ext_stop_streams(ebus); 227 228 if (bus->irq >= 0) 229 free_irq(bus->irq, (void *)bus); 230 if (bus->remap_addr) 231 iounmap(bus->remap_addr); 232 233 snd_hdac_bus_free_stream_pages(bus); 234 snd_hdac_stream_free_all(ebus); 235 snd_hdac_link_free_all(ebus); 236 pci_release_regions(skl->pci); 237 pci_disable_device(skl->pci); 238 239 snd_hdac_ext_bus_exit(ebus); 240 241 return 0; 242 } 243 244 static int skl_dmic_device_register(struct skl *skl) 245 { 246 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); 247 struct platform_device *pdev; 248 int ret; 249 250 /* SKL has one dmic port, so allocate dmic device for this */ 251 pdev = platform_device_alloc("dmic-codec", -1); 252 if (!pdev) { 253 dev_err(bus->dev, "failed to allocate dmic device\n"); 254 return -ENOMEM; 255 } 256 257 ret = platform_device_add(pdev); 258 if (ret) { 259 dev_err(bus->dev, "failed to add dmic device: %d\n", ret); 260 platform_device_put(pdev); 261 return ret; 262 } 263 skl->dmic_dev = pdev; 264 265 return 0; 266 } 267 268 static void skl_dmic_device_unregister(struct skl *skl) 269 { 270 if (skl->dmic_dev) 271 platform_device_unregister(skl->dmic_dev); 272 } 273 274 /* 275 * Probe the given codec address 276 */ 277 static int probe_codec(struct hdac_ext_bus *ebus, int addr) 278 { 279 struct hdac_bus *bus = ebus_to_hbus(ebus); 280 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 281 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 282 unsigned int res; 283 284 mutex_lock(&bus->cmd_mutex); 285 snd_hdac_bus_send_cmd(bus, cmd); 286 snd_hdac_bus_get_response(bus, addr, &res); 287 mutex_unlock(&bus->cmd_mutex); 288 if (res == -1) 289 return -EIO; 290 dev_dbg(bus->dev, "codec #%d probed OK\n", addr); 291 292 return snd_hdac_ext_bus_device_init(ebus, addr); 293 } 294 295 /* Codec initialization */ 296 static int skl_codec_create(struct hdac_ext_bus *ebus) 297 { 298 struct hdac_bus *bus = ebus_to_hbus(ebus); 299 int c, max_slots; 300 301 max_slots = HDA_MAX_CODECS; 302 303 /* First try to probe all given codec slots */ 304 for (c = 0; c < max_slots; c++) { 305 if ((bus->codec_mask & (1 << c))) { 306 if (probe_codec(ebus, c) < 0) { 307 /* 308 * Some BIOSen give you wrong codec addresses 309 * that don't exist 310 */ 311 dev_warn(bus->dev, 312 "Codec #%d probe error; disabling it...\n", c); 313 bus->codec_mask &= ~(1 << c); 314 /* 315 * More badly, accessing to a non-existing 316 * codec often screws up the controller bus, 317 * and disturbs the further communications. 318 * Thus if an error occurs during probing, 319 * better to reset the controller bus to get 320 * back to the sanity state. 321 */ 322 snd_hdac_bus_stop_chip(bus); 323 snd_hdac_bus_init_chip(bus, true); 324 } 325 } 326 } 327 328 return 0; 329 } 330 331 static const struct hdac_bus_ops bus_core_ops = { 332 .command = snd_hdac_bus_send_cmd, 333 .get_response = snd_hdac_bus_get_response, 334 }; 335 336 /* 337 * constructor 338 */ 339 static int skl_create(struct pci_dev *pci, 340 const struct hdac_io_ops *io_ops, 341 struct skl **rskl) 342 { 343 struct skl *skl; 344 struct hdac_ext_bus *ebus; 345 346 int err; 347 348 *rskl = NULL; 349 350 err = pci_enable_device(pci); 351 if (err < 0) 352 return err; 353 354 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); 355 if (!skl) { 356 pci_disable_device(pci); 357 return -ENOMEM; 358 } 359 ebus = &skl->ebus; 360 snd_hdac_ext_bus_init(ebus, &pci->dev, &bus_core_ops, io_ops); 361 ebus->bus.use_posbuf = 1; 362 skl->pci = pci; 363 364 ebus->bus.bdl_pos_adj = 0; 365 366 *rskl = skl; 367 368 return 0; 369 } 370 371 static int skl_first_init(struct hdac_ext_bus *ebus) 372 { 373 struct skl *skl = ebus_to_skl(ebus); 374 struct hdac_bus *bus = ebus_to_hbus(ebus); 375 struct pci_dev *pci = skl->pci; 376 int err; 377 unsigned short gcap; 378 int cp_streams, pb_streams, start_idx; 379 380 err = pci_request_regions(pci, "Skylake HD audio"); 381 if (err < 0) 382 return err; 383 384 bus->addr = pci_resource_start(pci, 0); 385 bus->remap_addr = pci_ioremap_bar(pci, 0); 386 if (bus->remap_addr == NULL) { 387 dev_err(bus->dev, "ioremap error\n"); 388 return -ENXIO; 389 } 390 391 snd_hdac_ext_bus_parse_capabilities(ebus); 392 393 if (skl_acquire_irq(ebus, 0) < 0) 394 return -EBUSY; 395 396 pci_set_master(pci); 397 synchronize_irq(bus->irq); 398 399 gcap = snd_hdac_chip_readw(bus, GCAP); 400 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); 401 402 /* allow 64bit DMA address if supported by H/W */ 403 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) { 404 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64)); 405 } else { 406 dma_set_mask(bus->dev, DMA_BIT_MASK(32)); 407 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32)); 408 } 409 410 /* read number of streams from GCAP register */ 411 cp_streams = (gcap >> 8) & 0x0f; 412 pb_streams = (gcap >> 12) & 0x0f; 413 414 if (!pb_streams && !cp_streams) 415 return -EIO; 416 417 ebus->num_streams = cp_streams + pb_streams; 418 419 /* initialize streams */ 420 snd_hdac_ext_stream_init_all 421 (ebus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); 422 start_idx = cp_streams; 423 snd_hdac_ext_stream_init_all 424 (ebus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); 425 426 err = snd_hdac_bus_alloc_stream_pages(bus); 427 if (err < 0) 428 return err; 429 430 /* initialize chip */ 431 skl_init_pci(skl); 432 433 snd_hdac_bus_init_chip(bus, true); 434 435 /* codec detection */ 436 if (!bus->codec_mask) { 437 dev_err(bus->dev, "no codecs found!\n"); 438 return -ENODEV; 439 } 440 441 return 0; 442 } 443 444 static int skl_probe(struct pci_dev *pci, 445 const struct pci_device_id *pci_id) 446 { 447 struct skl *skl; 448 struct hdac_ext_bus *ebus = NULL; 449 struct hdac_bus *bus = NULL; 450 int err; 451 452 /* we use ext core ops, so provide NULL for ops here */ 453 err = skl_create(pci, NULL, &skl); 454 if (err < 0) 455 return err; 456 457 ebus = &skl->ebus; 458 bus = ebus_to_hbus(ebus); 459 460 err = skl_first_init(ebus); 461 if (err < 0) 462 goto out_free; 463 464 skl->nhlt = skl_nhlt_init(bus->dev); 465 466 if (skl->nhlt == NULL) 467 goto out_free; 468 469 pci_set_drvdata(skl->pci, ebus); 470 471 /* check if dsp is there */ 472 if (ebus->ppcap) { 473 err = skl_init_dsp(skl); 474 if (err < 0) { 475 dev_dbg(bus->dev, "error failed to register dsp\n"); 476 goto out_free; 477 } 478 } 479 if (ebus->mlcap) 480 snd_hdac_ext_bus_get_ml_capabilities(ebus); 481 482 /* create device for soc dmic */ 483 err = skl_dmic_device_register(skl); 484 if (err < 0) 485 goto out_dsp_free; 486 487 /* register platform dai and controls */ 488 err = skl_platform_register(bus->dev); 489 if (err < 0) 490 goto out_dmic_free; 491 492 /* create codec instances */ 493 err = skl_codec_create(ebus); 494 if (err < 0) 495 goto out_unregister; 496 497 /*configure PM */ 498 pm_runtime_set_autosuspend_delay(bus->dev, SKL_SUSPEND_DELAY); 499 pm_runtime_use_autosuspend(bus->dev); 500 pm_runtime_put_noidle(bus->dev); 501 pm_runtime_allow(bus->dev); 502 503 return 0; 504 505 out_unregister: 506 skl_platform_unregister(bus->dev); 507 out_dmic_free: 508 skl_dmic_device_unregister(skl); 509 out_dsp_free: 510 skl_free_dsp(skl); 511 out_free: 512 skl->init_failed = 1; 513 skl_free(ebus); 514 515 return err; 516 } 517 518 static void skl_remove(struct pci_dev *pci) 519 { 520 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 521 struct skl *skl = ebus_to_skl(ebus); 522 523 if (pci_dev_run_wake(pci)) 524 pm_runtime_get_noresume(&pci->dev); 525 pci_dev_put(pci); 526 skl_platform_unregister(&pci->dev); 527 skl_free_dsp(skl); 528 skl_dmic_device_unregister(skl); 529 skl_free(ebus); 530 dev_set_drvdata(&pci->dev, NULL); 531 } 532 533 /* PCI IDs */ 534 static const struct pci_device_id skl_ids[] = { 535 /* Sunrise Point-LP */ 536 { PCI_DEVICE(0x8086, 0x9d70), 0}, 537 { 0, } 538 }; 539 MODULE_DEVICE_TABLE(pci, skl_ids); 540 541 /* pci_driver definition */ 542 static struct pci_driver skl_driver = { 543 .name = KBUILD_MODNAME, 544 .id_table = skl_ids, 545 .probe = skl_probe, 546 .remove = skl_remove, 547 .driver = { 548 .pm = &skl_pm, 549 }, 550 }; 551 module_pci_driver(skl_driver); 552 553 MODULE_LICENSE("GPL v2"); 554 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver"); 555