1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * skl.c - Implementation of ASoC Intel SKL HD Audio driver 4 * 5 * Copyright (C) 2014-2015 Intel Corp 6 * Author: Jeeja KP <jeeja.kp@intel.com> 7 * 8 * Derived mostly from Intel HDA driver with following copyrights: 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 12 * 13 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 14 */ 15 16 #include <linux/module.h> 17 #include <linux/pci.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/platform_device.h> 20 #include <linux/firmware.h> 21 #include <linux/delay.h> 22 #include <sound/pcm.h> 23 #include <sound/soc-acpi.h> 24 #include <sound/soc-acpi-intel-match.h> 25 #include <sound/hda_register.h> 26 #include <sound/hdaudio.h> 27 #include <sound/hda_i915.h> 28 #include <sound/hda_codec.h> 29 #include <sound/intel-nhlt.h> 30 #include <sound/intel-dsp-config.h> 31 #include "skl.h" 32 #include "skl-sst-dsp.h" 33 #include "skl-sst-ipc.h" 34 35 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 36 #include "../../../soc/codecs/hdac_hda.h" 37 #endif 38 static int skl_pci_binding; 39 module_param_named(pci_binding, skl_pci_binding, int, 0444); 40 MODULE_PARM_DESC(pci_binding, "PCI binding (0=auto, 1=only legacy, 2=only asoc"); 41 42 /* 43 * initialize the PCI registers 44 */ 45 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, 46 unsigned char mask, unsigned char val) 47 { 48 unsigned char data; 49 50 pci_read_config_byte(pci, reg, &data); 51 data &= ~mask; 52 data |= (val & mask); 53 pci_write_config_byte(pci, reg, data); 54 } 55 56 static void skl_init_pci(struct skl_dev *skl) 57 { 58 struct hdac_bus *bus = skl_to_bus(skl); 59 60 /* 61 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 62 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 63 * Ensuring these bits are 0 clears playback static on some HD Audio 64 * codecs. 65 * The PCI register TCSEL is defined in the Intel manuals. 66 */ 67 dev_dbg(bus->dev, "Clearing TCSEL\n"); 68 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); 69 } 70 71 static void update_pci_dword(struct pci_dev *pci, 72 unsigned int reg, u32 mask, u32 val) 73 { 74 u32 data = 0; 75 76 pci_read_config_dword(pci, reg, &data); 77 data &= ~mask; 78 data |= (val & mask); 79 pci_write_config_dword(pci, reg, data); 80 } 81 82 /* 83 * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits 84 * 85 * @dev: device pointer 86 * @enable: enable/disable flag 87 */ 88 static void skl_enable_miscbdcge(struct device *dev, bool enable) 89 { 90 struct pci_dev *pci = to_pci_dev(dev); 91 u32 val; 92 93 val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; 94 95 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); 96 } 97 98 /** 99 * skl_clock_power_gating: Enable/Disable clock and power gating 100 * 101 * @dev: Device pointer 102 * @enable: Enable/Disable flag 103 */ 104 static void skl_clock_power_gating(struct device *dev, bool enable) 105 { 106 struct pci_dev *pci = to_pci_dev(dev); 107 struct hdac_bus *bus = pci_get_drvdata(pci); 108 u32 val; 109 110 /* Update PDCGE bit of CGCTL register */ 111 val = enable ? AZX_CGCTL_ADSPDCGE : 0; 112 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); 113 114 /* Update L1SEN bit of EM2 register */ 115 val = enable ? AZX_REG_VS_EM2_L1SEN : 0; 116 snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val); 117 118 /* Update ADSPPGD bit of PGCTL register */ 119 val = enable ? 0 : AZX_PGCTL_ADSPPGD; 120 update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val); 121 } 122 123 /* 124 * While performing reset, controller may not come back properly causing 125 * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset 126 * (init chip) and then again set CGCTL.MISCBDCGE to 1 127 */ 128 static int skl_init_chip(struct hdac_bus *bus, bool full_reset) 129 { 130 struct hdac_ext_link *hlink; 131 int ret; 132 133 skl_enable_miscbdcge(bus->dev, false); 134 ret = snd_hdac_bus_init_chip(bus, full_reset); 135 136 /* Reset stream-to-link mapping */ 137 list_for_each_entry(hlink, &bus->hlink_list, list) 138 writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV); 139 140 skl_enable_miscbdcge(bus->dev, true); 141 142 return ret; 143 } 144 145 void skl_update_d0i3c(struct device *dev, bool enable) 146 { 147 struct pci_dev *pci = to_pci_dev(dev); 148 struct hdac_bus *bus = pci_get_drvdata(pci); 149 u8 reg; 150 int timeout = 50; 151 152 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 153 /* Do not write to D0I3C until command in progress bit is cleared */ 154 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 155 udelay(10); 156 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 157 } 158 159 /* Highly unlikely. But if it happens, flag error explicitly */ 160 if (!timeout) { 161 dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n"); 162 return; 163 } 164 165 if (enable) 166 reg = reg | AZX_REG_VS_D0I3C_I3; 167 else 168 reg = reg & (~AZX_REG_VS_D0I3C_I3); 169 170 snd_hdac_chip_writeb(bus, VS_D0I3C, reg); 171 172 timeout = 50; 173 /* Wait for cmd in progress to be cleared before exiting the function */ 174 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 175 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 176 udelay(10); 177 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 178 } 179 180 /* Highly unlikely. But if it happens, flag error explicitly */ 181 if (!timeout) { 182 dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n"); 183 return; 184 } 185 186 dev_dbg(bus->dev, "D0I3C register = 0x%x\n", 187 snd_hdac_chip_readb(bus, VS_D0I3C)); 188 } 189 190 /** 191 * skl_dum_set - set DUM bit in EM2 register 192 * @bus: HD-audio core bus 193 * 194 * Addresses incorrect position reporting for capture streams. 195 * Used on device power up. 196 */ 197 static void skl_dum_set(struct hdac_bus *bus) 198 { 199 /* For the DUM bit to be set, CRST needs to be out of reset state */ 200 if (!(snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)) { 201 skl_enable_miscbdcge(bus->dev, false); 202 snd_hdac_bus_exit_link_reset(bus); 203 skl_enable_miscbdcge(bus->dev, true); 204 } 205 206 snd_hdac_chip_updatel(bus, VS_EM2, AZX_VS_EM2_DUM, AZX_VS_EM2_DUM); 207 } 208 209 /* called from IRQ */ 210 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) 211 { 212 snd_pcm_period_elapsed(hstr->substream); 213 } 214 215 static irqreturn_t skl_interrupt(int irq, void *dev_id) 216 { 217 struct hdac_bus *bus = dev_id; 218 u32 status; 219 220 if (!pm_runtime_active(bus->dev)) 221 return IRQ_NONE; 222 223 spin_lock(&bus->reg_lock); 224 225 status = snd_hdac_chip_readl(bus, INTSTS); 226 if (status == 0 || status == 0xffffffff) { 227 spin_unlock(&bus->reg_lock); 228 return IRQ_NONE; 229 } 230 231 /* clear rirb int */ 232 status = snd_hdac_chip_readb(bus, RIRBSTS); 233 if (status & RIRB_INT_MASK) { 234 if (status & RIRB_INT_RESPONSE) 235 snd_hdac_bus_update_rirb(bus); 236 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 237 } 238 239 spin_unlock(&bus->reg_lock); 240 241 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; 242 } 243 244 static irqreturn_t skl_threaded_handler(int irq, void *dev_id) 245 { 246 struct hdac_bus *bus = dev_id; 247 u32 status; 248 249 status = snd_hdac_chip_readl(bus, INTSTS); 250 251 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); 252 253 return IRQ_HANDLED; 254 } 255 256 static int skl_acquire_irq(struct hdac_bus *bus, int do_disconnect) 257 { 258 struct skl_dev *skl = bus_to_skl(bus); 259 int ret; 260 261 ret = request_threaded_irq(skl->pci->irq, skl_interrupt, 262 skl_threaded_handler, 263 IRQF_SHARED, 264 KBUILD_MODNAME, bus); 265 if (ret) { 266 dev_err(bus->dev, 267 "unable to grab IRQ %d, disabling device\n", 268 skl->pci->irq); 269 return ret; 270 } 271 272 bus->irq = skl->pci->irq; 273 pci_intx(skl->pci, 1); 274 275 return 0; 276 } 277 278 static int skl_suspend_late(struct device *dev) 279 { 280 struct pci_dev *pci = to_pci_dev(dev); 281 struct hdac_bus *bus = pci_get_drvdata(pci); 282 struct skl_dev *skl = bus_to_skl(bus); 283 284 return skl_suspend_late_dsp(skl); 285 } 286 287 #ifdef CONFIG_PM 288 static int _skl_suspend(struct hdac_bus *bus) 289 { 290 struct skl_dev *skl = bus_to_skl(bus); 291 struct pci_dev *pci = to_pci_dev(bus->dev); 292 int ret; 293 294 snd_hdac_ext_bus_link_power_down_all(bus); 295 296 ret = skl_suspend_dsp(skl); 297 if (ret < 0) 298 return ret; 299 300 snd_hdac_bus_stop_chip(bus); 301 update_pci_dword(pci, AZX_PCIREG_PGCTL, 302 AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK); 303 skl_enable_miscbdcge(bus->dev, false); 304 snd_hdac_bus_enter_link_reset(bus); 305 skl_enable_miscbdcge(bus->dev, true); 306 skl_cleanup_resources(skl); 307 308 return 0; 309 } 310 311 static int _skl_resume(struct hdac_bus *bus) 312 { 313 struct skl_dev *skl = bus_to_skl(bus); 314 315 skl_init_pci(skl); 316 skl_dum_set(bus); 317 skl_init_chip(bus, true); 318 319 return skl_resume_dsp(skl); 320 } 321 #endif 322 323 #ifdef CONFIG_PM_SLEEP 324 /* 325 * power management 326 */ 327 static int skl_suspend(struct device *dev) 328 { 329 struct pci_dev *pci = to_pci_dev(dev); 330 struct hdac_bus *bus = pci_get_drvdata(pci); 331 struct skl_dev *skl = bus_to_skl(bus); 332 int ret; 333 334 /* 335 * Do not suspend if streams which are marked ignore suspend are 336 * running, we need to save the state for these and continue 337 */ 338 if (skl->supend_active) { 339 /* turn off the links and stop the CORB/RIRB DMA if it is On */ 340 snd_hdac_ext_bus_link_power_down_all(bus); 341 342 if (bus->cmd_dma_state) 343 snd_hdac_bus_stop_cmd_io(bus); 344 345 enable_irq_wake(bus->irq); 346 pci_save_state(pci); 347 } else { 348 ret = _skl_suspend(bus); 349 if (ret < 0) 350 return ret; 351 skl->fw_loaded = false; 352 } 353 354 return 0; 355 } 356 357 static int skl_resume(struct device *dev) 358 { 359 struct pci_dev *pci = to_pci_dev(dev); 360 struct hdac_bus *bus = pci_get_drvdata(pci); 361 struct skl_dev *skl = bus_to_skl(bus); 362 struct hdac_ext_link *hlink = NULL; 363 int ret; 364 365 /* 366 * resume only when we are not in suspend active, otherwise need to 367 * restore the device 368 */ 369 if (skl->supend_active) { 370 pci_restore_state(pci); 371 snd_hdac_ext_bus_link_power_up_all(bus); 372 disable_irq_wake(bus->irq); 373 /* 374 * turn On the links which are On before active suspend 375 * and start the CORB/RIRB DMA if On before 376 * active suspend. 377 */ 378 list_for_each_entry(hlink, &bus->hlink_list, list) { 379 if (hlink->ref_count) 380 snd_hdac_ext_bus_link_power_up(hlink); 381 } 382 383 ret = 0; 384 if (bus->cmd_dma_state) 385 snd_hdac_bus_init_cmd_io(bus); 386 } else { 387 ret = _skl_resume(bus); 388 389 /* turn off the links which are off before suspend */ 390 list_for_each_entry(hlink, &bus->hlink_list, list) { 391 if (!hlink->ref_count) 392 snd_hdac_ext_bus_link_power_down(hlink); 393 } 394 395 if (!bus->cmd_dma_state) 396 snd_hdac_bus_stop_cmd_io(bus); 397 } 398 399 return ret; 400 } 401 #endif /* CONFIG_PM_SLEEP */ 402 403 #ifdef CONFIG_PM 404 static int skl_runtime_suspend(struct device *dev) 405 { 406 struct pci_dev *pci = to_pci_dev(dev); 407 struct hdac_bus *bus = pci_get_drvdata(pci); 408 409 dev_dbg(bus->dev, "in %s\n", __func__); 410 411 return _skl_suspend(bus); 412 } 413 414 static int skl_runtime_resume(struct device *dev) 415 { 416 struct pci_dev *pci = to_pci_dev(dev); 417 struct hdac_bus *bus = pci_get_drvdata(pci); 418 419 dev_dbg(bus->dev, "in %s\n", __func__); 420 421 return _skl_resume(bus); 422 } 423 #endif /* CONFIG_PM */ 424 425 static const struct dev_pm_ops skl_pm = { 426 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) 427 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) 428 .suspend_late = skl_suspend_late, 429 }; 430 431 /* 432 * destructor 433 */ 434 static int skl_free(struct hdac_bus *bus) 435 { 436 struct skl_dev *skl = bus_to_skl(bus); 437 438 skl->init_done = 0; /* to be sure */ 439 440 snd_hdac_ext_stop_streams(bus); 441 442 if (bus->irq >= 0) 443 free_irq(bus->irq, (void *)bus); 444 snd_hdac_bus_free_stream_pages(bus); 445 snd_hdac_stream_free_all(bus); 446 snd_hdac_link_free_all(bus); 447 448 if (bus->remap_addr) 449 iounmap(bus->remap_addr); 450 451 pci_release_regions(skl->pci); 452 pci_disable_device(skl->pci); 453 454 snd_hdac_ext_bus_exit(bus); 455 456 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 457 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); 458 snd_hdac_i915_exit(bus); 459 } 460 461 return 0; 462 } 463 464 /* 465 * For each ssp there are 3 clocks (mclk/sclk/sclkfs). 466 * e.g. for ssp0, clocks will be named as 467 * "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs" 468 * So for skl+, there are 6 ssps, so 18 clocks will be created. 469 */ 470 static struct skl_ssp_clk skl_ssp_clks[] = { 471 {.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"}, 472 {.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"}, 473 {.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"}, 474 {.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"}, 475 {.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"}, 476 {.name = "ssp2_sclkfs"}, 477 {.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"}, 478 {.name = "ssp5_sclkfs"}, 479 }; 480 481 static struct snd_soc_acpi_mach *skl_find_hda_machine(struct skl_dev *skl, 482 struct snd_soc_acpi_mach *machines) 483 { 484 struct snd_soc_acpi_mach *mach; 485 486 /* point to common table */ 487 mach = snd_soc_acpi_intel_hda_machines; 488 489 /* all entries in the machine table use the same firmware */ 490 mach->fw_filename = machines->fw_filename; 491 492 return mach; 493 } 494 495 static int skl_find_machine(struct skl_dev *skl, void *driver_data) 496 { 497 struct hdac_bus *bus = skl_to_bus(skl); 498 struct snd_soc_acpi_mach *mach = driver_data; 499 struct skl_machine_pdata *pdata; 500 501 mach = snd_soc_acpi_find_machine(mach); 502 if (!mach) { 503 dev_dbg(bus->dev, "No matching I2S machine driver found\n"); 504 mach = skl_find_hda_machine(skl, driver_data); 505 if (!mach) { 506 dev_err(bus->dev, "No matching machine driver found\n"); 507 return -ENODEV; 508 } 509 } 510 511 skl->mach = mach; 512 skl->fw_name = mach->fw_filename; 513 pdata = mach->pdata; 514 515 if (pdata) { 516 skl->use_tplg_pcm = pdata->use_tplg_pcm; 517 mach->mach_params.dmic_num = 518 intel_nhlt_get_dmic_geo(&skl->pci->dev, 519 skl->nhlt); 520 } 521 522 return 0; 523 } 524 525 static int skl_machine_device_register(struct skl_dev *skl) 526 { 527 struct snd_soc_acpi_mach *mach = skl->mach; 528 struct hdac_bus *bus = skl_to_bus(skl); 529 struct platform_device *pdev; 530 int ret; 531 532 pdev = platform_device_alloc(mach->drv_name, -1); 533 if (pdev == NULL) { 534 dev_err(bus->dev, "platform device alloc failed\n"); 535 return -EIO; 536 } 537 538 mach->mach_params.platform = dev_name(bus->dev); 539 mach->mach_params.codec_mask = bus->codec_mask; 540 541 ret = platform_device_add_data(pdev, (const void *)mach, sizeof(*mach)); 542 if (ret) { 543 dev_err(bus->dev, "failed to add machine device platform data\n"); 544 platform_device_put(pdev); 545 return ret; 546 } 547 548 ret = platform_device_add(pdev); 549 if (ret) { 550 dev_err(bus->dev, "failed to add machine device\n"); 551 platform_device_put(pdev); 552 return -EIO; 553 } 554 555 556 skl->i2s_dev = pdev; 557 558 return 0; 559 } 560 561 static void skl_machine_device_unregister(struct skl_dev *skl) 562 { 563 if (skl->i2s_dev) 564 platform_device_unregister(skl->i2s_dev); 565 } 566 567 static int skl_dmic_device_register(struct skl_dev *skl) 568 { 569 struct hdac_bus *bus = skl_to_bus(skl); 570 struct platform_device *pdev; 571 int ret; 572 573 /* SKL has one dmic port, so allocate dmic device for this */ 574 pdev = platform_device_alloc("dmic-codec", -1); 575 if (!pdev) { 576 dev_err(bus->dev, "failed to allocate dmic device\n"); 577 return -ENOMEM; 578 } 579 580 ret = platform_device_add(pdev); 581 if (ret) { 582 dev_err(bus->dev, "failed to add dmic device: %d\n", ret); 583 platform_device_put(pdev); 584 return ret; 585 } 586 skl->dmic_dev = pdev; 587 588 return 0; 589 } 590 591 static void skl_dmic_device_unregister(struct skl_dev *skl) 592 { 593 if (skl->dmic_dev) 594 platform_device_unregister(skl->dmic_dev); 595 } 596 597 static struct skl_clk_parent_src skl_clk_src[] = { 598 { .clk_id = SKL_XTAL, .name = "xtal" }, 599 { .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 }, 600 { .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 }, 601 }; 602 603 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id) 604 { 605 unsigned int i; 606 607 for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) { 608 if (skl_clk_src[i].clk_id == clk_id) 609 return &skl_clk_src[i]; 610 } 611 612 return NULL; 613 } 614 615 static void init_skl_xtal_rate(int pci_id) 616 { 617 switch (pci_id) { 618 case 0x9d70: 619 case 0x9d71: 620 skl_clk_src[0].rate = 24000000; 621 return; 622 623 default: 624 skl_clk_src[0].rate = 19200000; 625 return; 626 } 627 } 628 629 static int skl_clock_device_register(struct skl_dev *skl) 630 { 631 struct platform_device_info pdevinfo = {NULL}; 632 struct skl_clk_pdata *clk_pdata; 633 634 clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata), 635 GFP_KERNEL); 636 if (!clk_pdata) 637 return -ENOMEM; 638 639 init_skl_xtal_rate(skl->pci->device); 640 641 clk_pdata->parent_clks = skl_clk_src; 642 clk_pdata->ssp_clks = skl_ssp_clks; 643 clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks); 644 645 /* Query NHLT to fill the rates and parent */ 646 skl_get_clks(skl, clk_pdata->ssp_clks); 647 clk_pdata->pvt_data = skl; 648 649 /* Register Platform device */ 650 pdevinfo.parent = &skl->pci->dev; 651 pdevinfo.id = -1; 652 pdevinfo.name = "skl-ssp-clk"; 653 pdevinfo.data = clk_pdata; 654 pdevinfo.size_data = sizeof(*clk_pdata); 655 skl->clk_dev = platform_device_register_full(&pdevinfo); 656 return PTR_ERR_OR_ZERO(skl->clk_dev); 657 } 658 659 static void skl_clock_device_unregister(struct skl_dev *skl) 660 { 661 if (skl->clk_dev) 662 platform_device_unregister(skl->clk_dev); 663 } 664 665 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 666 667 #define IDISP_INTEL_VENDOR_ID 0x80860000 668 669 /* 670 * load the legacy codec driver 671 */ 672 static void load_codec_module(struct hda_codec *codec) 673 { 674 #ifdef MODULE 675 char modalias[MODULE_NAME_LEN]; 676 const char *mod = NULL; 677 678 snd_hdac_codec_modalias(&codec->core, modalias, sizeof(modalias)); 679 mod = modalias; 680 dev_dbg(&codec->core.dev, "loading %s codec module\n", mod); 681 request_module(mod); 682 #endif 683 } 684 685 #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */ 686 687 /* 688 * Probe the given codec address 689 */ 690 static int probe_codec(struct hdac_bus *bus, int addr) 691 { 692 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 693 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 694 unsigned int res = -1; 695 struct skl_dev *skl = bus_to_skl(bus); 696 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 697 struct hdac_hda_priv *hda_codec; 698 int err; 699 #endif 700 struct hdac_device *hdev; 701 702 mutex_lock(&bus->cmd_mutex); 703 snd_hdac_bus_send_cmd(bus, cmd); 704 snd_hdac_bus_get_response(bus, addr, &res); 705 mutex_unlock(&bus->cmd_mutex); 706 if (res == -1) 707 return -EIO; 708 dev_dbg(bus->dev, "codec #%d probed OK: %x\n", addr, res); 709 710 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 711 hda_codec = devm_kzalloc(&skl->pci->dev, sizeof(*hda_codec), 712 GFP_KERNEL); 713 if (!hda_codec) 714 return -ENOMEM; 715 716 hda_codec->codec.bus = skl_to_hbus(skl); 717 hdev = &hda_codec->codec.core; 718 719 err = snd_hdac_ext_bus_device_init(bus, addr, hdev); 720 if (err < 0) 721 return err; 722 723 /* use legacy bus only for HDA codecs, idisp uses ext bus */ 724 if ((res & 0xFFFF0000) != IDISP_INTEL_VENDOR_ID) { 725 hdev->type = HDA_DEV_LEGACY; 726 load_codec_module(&hda_codec->codec); 727 } 728 return 0; 729 #else 730 hdev = devm_kzalloc(&skl->pci->dev, sizeof(*hdev), GFP_KERNEL); 731 if (!hdev) 732 return -ENOMEM; 733 734 return snd_hdac_ext_bus_device_init(bus, addr, hdev); 735 #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */ 736 } 737 738 /* Codec initialization */ 739 static void skl_codec_create(struct hdac_bus *bus) 740 { 741 int c, max_slots; 742 743 max_slots = HDA_MAX_CODECS; 744 745 /* First try to probe all given codec slots */ 746 for (c = 0; c < max_slots; c++) { 747 if ((bus->codec_mask & (1 << c))) { 748 if (probe_codec(bus, c) < 0) { 749 /* 750 * Some BIOSen give you wrong codec addresses 751 * that don't exist 752 */ 753 dev_warn(bus->dev, 754 "Codec #%d probe error; disabling it...\n", c); 755 bus->codec_mask &= ~(1 << c); 756 /* 757 * More badly, accessing to a non-existing 758 * codec often screws up the controller bus, 759 * and disturbs the further communications. 760 * Thus if an error occurs during probing, 761 * better to reset the controller bus to get 762 * back to the sanity state. 763 */ 764 snd_hdac_bus_stop_chip(bus); 765 skl_init_chip(bus, true); 766 } 767 } 768 } 769 } 770 771 static int skl_i915_init(struct hdac_bus *bus) 772 { 773 int err; 774 775 /* 776 * The HDMI codec is in GPU so we need to ensure that it is powered 777 * up and ready for probe 778 */ 779 err = snd_hdac_i915_init(bus); 780 if (err < 0) 781 return err; 782 783 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true); 784 785 return 0; 786 } 787 788 static void skl_probe_work(struct work_struct *work) 789 { 790 struct skl_dev *skl = container_of(work, struct skl_dev, probe_work); 791 struct hdac_bus *bus = skl_to_bus(skl); 792 struct hdac_ext_link *hlink = NULL; 793 int err; 794 795 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 796 err = skl_i915_init(bus); 797 if (err < 0) 798 return; 799 } 800 801 skl_init_pci(skl); 802 skl_dum_set(bus); 803 804 err = skl_init_chip(bus, true); 805 if (err < 0) { 806 dev_err(bus->dev, "Init chip failed with err: %d\n", err); 807 goto out_err; 808 } 809 810 /* codec detection */ 811 if (!bus->codec_mask) 812 dev_info(bus->dev, "no hda codecs found!\n"); 813 814 /* create codec instances */ 815 skl_codec_create(bus); 816 817 /* register platform dai and controls */ 818 err = skl_platform_register(bus->dev); 819 if (err < 0) { 820 dev_err(bus->dev, "platform register failed: %d\n", err); 821 goto out_err; 822 } 823 824 err = skl_machine_device_register(skl); 825 if (err < 0) { 826 dev_err(bus->dev, "machine register failed: %d\n", err); 827 goto out_err; 828 } 829 830 /* 831 * we are done probing so decrement link counts 832 */ 833 list_for_each_entry(hlink, &bus->hlink_list, list) 834 snd_hdac_ext_bus_link_put(bus, hlink); 835 836 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 837 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); 838 839 /* configure PM */ 840 pm_runtime_put_noidle(bus->dev); 841 pm_runtime_allow(bus->dev); 842 skl->init_done = 1; 843 844 return; 845 846 out_err: 847 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 848 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); 849 } 850 851 /* 852 * constructor 853 */ 854 static int skl_create(struct pci_dev *pci, 855 struct skl_dev **rskl) 856 { 857 struct hdac_ext_bus_ops *ext_ops = NULL; 858 struct skl_dev *skl; 859 struct hdac_bus *bus; 860 struct hda_bus *hbus; 861 int err; 862 863 *rskl = NULL; 864 865 err = pci_enable_device(pci); 866 if (err < 0) 867 return err; 868 869 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); 870 if (!skl) { 871 pci_disable_device(pci); 872 return -ENOMEM; 873 } 874 875 hbus = skl_to_hbus(skl); 876 bus = skl_to_bus(skl); 877 878 INIT_LIST_HEAD(&skl->ppl_list); 879 INIT_LIST_HEAD(&skl->bind_list); 880 881 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 882 ext_ops = snd_soc_hdac_hda_get_ops(); 883 #endif 884 snd_hdac_ext_bus_init(bus, &pci->dev, NULL, ext_ops); 885 bus->use_posbuf = 1; 886 skl->pci = pci; 887 INIT_WORK(&skl->probe_work, skl_probe_work); 888 bus->bdl_pos_adj = 0; 889 890 mutex_init(&hbus->prepare_mutex); 891 hbus->pci = pci; 892 hbus->mixer_assigned = -1; 893 hbus->modelname = "sklbus"; 894 895 *rskl = skl; 896 897 return 0; 898 } 899 900 static int skl_first_init(struct hdac_bus *bus) 901 { 902 struct skl_dev *skl = bus_to_skl(bus); 903 struct pci_dev *pci = skl->pci; 904 int err; 905 unsigned short gcap; 906 int cp_streams, pb_streams, start_idx; 907 908 err = pci_request_regions(pci, "Skylake HD audio"); 909 if (err < 0) 910 return err; 911 912 bus->addr = pci_resource_start(pci, 0); 913 bus->remap_addr = pci_ioremap_bar(pci, 0); 914 if (bus->remap_addr == NULL) { 915 dev_err(bus->dev, "ioremap error\n"); 916 return -ENXIO; 917 } 918 919 snd_hdac_bus_parse_capabilities(bus); 920 921 /* check if PPCAP exists */ 922 if (!bus->ppcap) { 923 dev_err(bus->dev, "bus ppcap not set, HDaudio or DSP not present?\n"); 924 return -ENODEV; 925 } 926 927 if (skl_acquire_irq(bus, 0) < 0) 928 return -EBUSY; 929 930 pci_set_master(pci); 931 synchronize_irq(bus->irq); 932 933 gcap = snd_hdac_chip_readw(bus, GCAP); 934 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); 935 936 /* read number of streams from GCAP register */ 937 cp_streams = (gcap >> 8) & 0x0f; 938 pb_streams = (gcap >> 12) & 0x0f; 939 940 if (!pb_streams && !cp_streams) { 941 dev_err(bus->dev, "no streams found in GCAP definitions?\n"); 942 return -EIO; 943 } 944 945 bus->num_streams = cp_streams + pb_streams; 946 947 /* allow 64bit DMA address if supported by H/W */ 948 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) { 949 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64)); 950 } else { 951 dma_set_mask(bus->dev, DMA_BIT_MASK(32)); 952 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32)); 953 } 954 955 /* initialize streams */ 956 snd_hdac_ext_stream_init_all 957 (bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); 958 start_idx = cp_streams; 959 snd_hdac_ext_stream_init_all 960 (bus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); 961 962 err = snd_hdac_bus_alloc_stream_pages(bus); 963 if (err < 0) 964 return err; 965 966 return 0; 967 } 968 969 static int skl_probe(struct pci_dev *pci, 970 const struct pci_device_id *pci_id) 971 { 972 struct skl_dev *skl; 973 struct hdac_bus *bus = NULL; 974 int err; 975 976 switch (skl_pci_binding) { 977 case SND_SKL_PCI_BIND_AUTO: 978 err = snd_intel_dsp_driver_probe(pci); 979 if (err != SND_INTEL_DSP_DRIVER_ANY && 980 err != SND_INTEL_DSP_DRIVER_SST) 981 return -ENODEV; 982 break; 983 case SND_SKL_PCI_BIND_LEGACY: 984 dev_info(&pci->dev, "Module parameter forced binding with HDaudio legacy, aborting probe\n"); 985 return -ENODEV; 986 case SND_SKL_PCI_BIND_ASOC: 987 dev_info(&pci->dev, "Module parameter forced binding with SKL driver, bypassed detection logic\n"); 988 break; 989 default: 990 dev_err(&pci->dev, "invalid value for skl_pci_binding module parameter, ignored\n"); 991 break; 992 } 993 994 /* we use ext core ops, so provide NULL for ops here */ 995 err = skl_create(pci, &skl); 996 if (err < 0) 997 return err; 998 999 bus = skl_to_bus(skl); 1000 1001 err = skl_first_init(bus); 1002 if (err < 0) { 1003 dev_err(bus->dev, "skl_first_init failed with err: %d\n", err); 1004 goto out_free; 1005 } 1006 1007 skl->pci_id = pci->device; 1008 1009 device_disable_async_suspend(bus->dev); 1010 1011 skl->nhlt = intel_nhlt_init(bus->dev); 1012 1013 if (skl->nhlt == NULL) { 1014 #if !IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 1015 dev_err(bus->dev, "no nhlt info found\n"); 1016 err = -ENODEV; 1017 goto out_free; 1018 #else 1019 dev_warn(bus->dev, "no nhlt info found, continuing to try to enable HDaudio codec\n"); 1020 #endif 1021 } else { 1022 1023 err = skl_nhlt_create_sysfs(skl); 1024 if (err < 0) { 1025 dev_err(bus->dev, "skl_nhlt_create_sysfs failed with err: %d\n", err); 1026 goto out_nhlt_free; 1027 } 1028 1029 skl_nhlt_update_topology_bin(skl); 1030 1031 /* create device for dsp clk */ 1032 err = skl_clock_device_register(skl); 1033 if (err < 0) { 1034 dev_err(bus->dev, "skl_clock_device_register failed with err: %d\n", err); 1035 goto out_clk_free; 1036 } 1037 } 1038 1039 pci_set_drvdata(skl->pci, bus); 1040 1041 1042 err = skl_find_machine(skl, (void *)pci_id->driver_data); 1043 if (err < 0) { 1044 dev_err(bus->dev, "skl_find_machine failed with err: %d\n", err); 1045 goto out_nhlt_free; 1046 } 1047 1048 err = skl_init_dsp(skl); 1049 if (err < 0) { 1050 dev_dbg(bus->dev, "error failed to register dsp\n"); 1051 goto out_nhlt_free; 1052 } 1053 skl->enable_miscbdcge = skl_enable_miscbdcge; 1054 skl->clock_power_gating = skl_clock_power_gating; 1055 1056 if (bus->mlcap) 1057 snd_hdac_ext_bus_get_ml_capabilities(bus); 1058 1059 /* create device for soc dmic */ 1060 err = skl_dmic_device_register(skl); 1061 if (err < 0) { 1062 dev_err(bus->dev, "skl_dmic_device_register failed with err: %d\n", err); 1063 goto out_dsp_free; 1064 } 1065 1066 schedule_work(&skl->probe_work); 1067 1068 return 0; 1069 1070 out_dsp_free: 1071 skl_free_dsp(skl); 1072 out_clk_free: 1073 skl_clock_device_unregister(skl); 1074 out_nhlt_free: 1075 intel_nhlt_free(skl->nhlt); 1076 out_free: 1077 skl_free(bus); 1078 1079 return err; 1080 } 1081 1082 static void skl_shutdown(struct pci_dev *pci) 1083 { 1084 struct hdac_bus *bus = pci_get_drvdata(pci); 1085 struct hdac_stream *s; 1086 struct hdac_ext_stream *stream; 1087 struct skl_dev *skl; 1088 1089 if (!bus) 1090 return; 1091 1092 skl = bus_to_skl(bus); 1093 1094 if (!skl->init_done) 1095 return; 1096 1097 snd_hdac_ext_stop_streams(bus); 1098 list_for_each_entry(s, &bus->stream_list, list) { 1099 stream = stream_to_hdac_ext_stream(s); 1100 snd_hdac_ext_stream_decouple(bus, stream, false); 1101 } 1102 1103 snd_hdac_bus_stop_chip(bus); 1104 } 1105 1106 static void skl_remove(struct pci_dev *pci) 1107 { 1108 struct hdac_bus *bus = pci_get_drvdata(pci); 1109 struct skl_dev *skl = bus_to_skl(bus); 1110 1111 cancel_work_sync(&skl->probe_work); 1112 1113 pm_runtime_get_noresume(&pci->dev); 1114 1115 /* codec removal, invoke bus_device_remove */ 1116 snd_hdac_ext_bus_device_remove(bus); 1117 1118 skl_platform_unregister(&pci->dev); 1119 skl_free_dsp(skl); 1120 skl_machine_device_unregister(skl); 1121 skl_dmic_device_unregister(skl); 1122 skl_clock_device_unregister(skl); 1123 skl_nhlt_remove_sysfs(skl); 1124 intel_nhlt_free(skl->nhlt); 1125 skl_free(bus); 1126 dev_set_drvdata(&pci->dev, NULL); 1127 } 1128 1129 /* PCI IDs */ 1130 static const struct pci_device_id skl_ids[] = { 1131 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKL) 1132 /* Sunrise Point-LP */ 1133 { PCI_DEVICE(0x8086, 0x9d70), 1134 .driver_data = (unsigned long)&snd_soc_acpi_intel_skl_machines}, 1135 #endif 1136 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_APL) 1137 /* BXT-P */ 1138 { PCI_DEVICE(0x8086, 0x5a98), 1139 .driver_data = (unsigned long)&snd_soc_acpi_intel_bxt_machines}, 1140 #endif 1141 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_KBL) 1142 /* KBL */ 1143 { PCI_DEVICE(0x8086, 0x9D71), 1144 .driver_data = (unsigned long)&snd_soc_acpi_intel_kbl_machines}, 1145 #endif 1146 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_GLK) 1147 /* GLK */ 1148 { PCI_DEVICE(0x8086, 0x3198), 1149 .driver_data = (unsigned long)&snd_soc_acpi_intel_glk_machines}, 1150 #endif 1151 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CNL) 1152 /* CNL */ 1153 { PCI_DEVICE(0x8086, 0x9dc8), 1154 .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, 1155 #endif 1156 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CFL) 1157 /* CFL */ 1158 { PCI_DEVICE(0x8086, 0xa348), 1159 .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, 1160 #endif 1161 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_LP) 1162 /* CML-LP */ 1163 { PCI_DEVICE(0x8086, 0x02c8), 1164 .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, 1165 #endif 1166 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_H) 1167 /* CML-H */ 1168 { PCI_DEVICE(0x8086, 0x06c8), 1169 .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, 1170 #endif 1171 { 0, } 1172 }; 1173 MODULE_DEVICE_TABLE(pci, skl_ids); 1174 1175 /* pci_driver definition */ 1176 static struct pci_driver skl_driver = { 1177 .name = KBUILD_MODNAME, 1178 .id_table = skl_ids, 1179 .probe = skl_probe, 1180 .remove = skl_remove, 1181 .shutdown = skl_shutdown, 1182 .driver = { 1183 .pm = &skl_pm, 1184 }, 1185 }; 1186 module_pci_driver(skl_driver); 1187 1188 MODULE_LICENSE("GPL v2"); 1189 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver"); 1190