1 /* 2 * skl.c - Implementation of ASoC Intel SKL HD Audio driver 3 * 4 * Copyright (C) 2014-2015 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * 7 * Derived mostly from Intel HDA driver with following copyrights: 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; version 2 of the License. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 22 */ 23 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/platform_device.h> 28 #include <linux/firmware.h> 29 #include <linux/delay.h> 30 #include <sound/pcm.h> 31 #include <sound/soc-acpi.h> 32 #include <sound/soc-acpi-intel-match.h> 33 #include <sound/hda_register.h> 34 #include <sound/hdaudio.h> 35 #include <sound/hda_i915.h> 36 #include <sound/hda_codec.h> 37 #include "skl.h" 38 #include "skl-sst-dsp.h" 39 #include "skl-sst-ipc.h" 40 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 41 #include "../../../soc/codecs/hdac_hda.h" 42 #endif 43 static int skl_pci_binding; 44 module_param_named(pci_binding, skl_pci_binding, int, 0444); 45 MODULE_PARM_DESC(pci_binding, "PCI binding (0=auto, 1=only legacy, 2=only asoc"); 46 47 /* 48 * initialize the PCI registers 49 */ 50 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, 51 unsigned char mask, unsigned char val) 52 { 53 unsigned char data; 54 55 pci_read_config_byte(pci, reg, &data); 56 data &= ~mask; 57 data |= (val & mask); 58 pci_write_config_byte(pci, reg, data); 59 } 60 61 static void skl_init_pci(struct skl *skl) 62 { 63 struct hdac_bus *bus = skl_to_bus(skl); 64 65 /* 66 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 67 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 68 * Ensuring these bits are 0 clears playback static on some HD Audio 69 * codecs. 70 * The PCI register TCSEL is defined in the Intel manuals. 71 */ 72 dev_dbg(bus->dev, "Clearing TCSEL\n"); 73 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); 74 } 75 76 static void update_pci_dword(struct pci_dev *pci, 77 unsigned int reg, u32 mask, u32 val) 78 { 79 u32 data = 0; 80 81 pci_read_config_dword(pci, reg, &data); 82 data &= ~mask; 83 data |= (val & mask); 84 pci_write_config_dword(pci, reg, data); 85 } 86 87 /* 88 * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits 89 * 90 * @dev: device pointer 91 * @enable: enable/disable flag 92 */ 93 static void skl_enable_miscbdcge(struct device *dev, bool enable) 94 { 95 struct pci_dev *pci = to_pci_dev(dev); 96 u32 val; 97 98 val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; 99 100 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); 101 } 102 103 /** 104 * skl_clock_power_gating: Enable/Disable clock and power gating 105 * 106 * @dev: Device pointer 107 * @enable: Enable/Disable flag 108 */ 109 static void skl_clock_power_gating(struct device *dev, bool enable) 110 { 111 struct pci_dev *pci = to_pci_dev(dev); 112 struct hdac_bus *bus = pci_get_drvdata(pci); 113 u32 val; 114 115 /* Update PDCGE bit of CGCTL register */ 116 val = enable ? AZX_CGCTL_ADSPDCGE : 0; 117 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); 118 119 /* Update L1SEN bit of EM2 register */ 120 val = enable ? AZX_REG_VS_EM2_L1SEN : 0; 121 snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val); 122 123 /* Update ADSPPGD bit of PGCTL register */ 124 val = enable ? 0 : AZX_PGCTL_ADSPPGD; 125 update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val); 126 } 127 128 /* 129 * While performing reset, controller may not come back properly causing 130 * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset 131 * (init chip) and then again set CGCTL.MISCBDCGE to 1 132 */ 133 static int skl_init_chip(struct hdac_bus *bus, bool full_reset) 134 { 135 struct hdac_ext_link *hlink; 136 int ret; 137 138 skl_enable_miscbdcge(bus->dev, false); 139 ret = snd_hdac_bus_init_chip(bus, full_reset); 140 141 /* Reset stream-to-link mapping */ 142 list_for_each_entry(hlink, &bus->hlink_list, list) 143 bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV); 144 145 skl_enable_miscbdcge(bus->dev, true); 146 147 return ret; 148 } 149 150 void skl_update_d0i3c(struct device *dev, bool enable) 151 { 152 struct pci_dev *pci = to_pci_dev(dev); 153 struct hdac_bus *bus = pci_get_drvdata(pci); 154 u8 reg; 155 int timeout = 50; 156 157 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 158 /* Do not write to D0I3C until command in progress bit is cleared */ 159 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 160 udelay(10); 161 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 162 } 163 164 /* Highly unlikely. But if it happens, flag error explicitly */ 165 if (!timeout) { 166 dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n"); 167 return; 168 } 169 170 if (enable) 171 reg = reg | AZX_REG_VS_D0I3C_I3; 172 else 173 reg = reg & (~AZX_REG_VS_D0I3C_I3); 174 175 snd_hdac_chip_writeb(bus, VS_D0I3C, reg); 176 177 timeout = 50; 178 /* Wait for cmd in progress to be cleared before exiting the function */ 179 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 180 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 181 udelay(10); 182 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 183 } 184 185 /* Highly unlikely. But if it happens, flag error explicitly */ 186 if (!timeout) { 187 dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n"); 188 return; 189 } 190 191 dev_dbg(bus->dev, "D0I3C register = 0x%x\n", 192 snd_hdac_chip_readb(bus, VS_D0I3C)); 193 } 194 195 /* called from IRQ */ 196 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) 197 { 198 snd_pcm_period_elapsed(hstr->substream); 199 } 200 201 static irqreturn_t skl_interrupt(int irq, void *dev_id) 202 { 203 struct hdac_bus *bus = dev_id; 204 u32 status; 205 206 if (!pm_runtime_active(bus->dev)) 207 return IRQ_NONE; 208 209 spin_lock(&bus->reg_lock); 210 211 status = snd_hdac_chip_readl(bus, INTSTS); 212 if (status == 0 || status == 0xffffffff) { 213 spin_unlock(&bus->reg_lock); 214 return IRQ_NONE; 215 } 216 217 /* clear rirb int */ 218 status = snd_hdac_chip_readb(bus, RIRBSTS); 219 if (status & RIRB_INT_MASK) { 220 if (status & RIRB_INT_RESPONSE) 221 snd_hdac_bus_update_rirb(bus); 222 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 223 } 224 225 spin_unlock(&bus->reg_lock); 226 227 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; 228 } 229 230 static irqreturn_t skl_threaded_handler(int irq, void *dev_id) 231 { 232 struct hdac_bus *bus = dev_id; 233 u32 status; 234 235 status = snd_hdac_chip_readl(bus, INTSTS); 236 237 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); 238 239 return IRQ_HANDLED; 240 } 241 242 static int skl_acquire_irq(struct hdac_bus *bus, int do_disconnect) 243 { 244 struct skl *skl = bus_to_skl(bus); 245 int ret; 246 247 ret = request_threaded_irq(skl->pci->irq, skl_interrupt, 248 skl_threaded_handler, 249 IRQF_SHARED, 250 KBUILD_MODNAME, bus); 251 if (ret) { 252 dev_err(bus->dev, 253 "unable to grab IRQ %d, disabling device\n", 254 skl->pci->irq); 255 return ret; 256 } 257 258 bus->irq = skl->pci->irq; 259 pci_intx(skl->pci, 1); 260 261 return 0; 262 } 263 264 static int skl_suspend_late(struct device *dev) 265 { 266 struct pci_dev *pci = to_pci_dev(dev); 267 struct hdac_bus *bus = pci_get_drvdata(pci); 268 struct skl *skl = bus_to_skl(bus); 269 270 return skl_suspend_late_dsp(skl); 271 } 272 273 #ifdef CONFIG_PM 274 static int _skl_suspend(struct hdac_bus *bus) 275 { 276 struct skl *skl = bus_to_skl(bus); 277 struct pci_dev *pci = to_pci_dev(bus->dev); 278 int ret; 279 280 snd_hdac_ext_bus_link_power_down_all(bus); 281 282 ret = skl_suspend_dsp(skl); 283 if (ret < 0) 284 return ret; 285 286 snd_hdac_bus_stop_chip(bus); 287 update_pci_dword(pci, AZX_PCIREG_PGCTL, 288 AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK); 289 skl_enable_miscbdcge(bus->dev, false); 290 snd_hdac_bus_enter_link_reset(bus); 291 skl_enable_miscbdcge(bus->dev, true); 292 skl_cleanup_resources(skl); 293 294 return 0; 295 } 296 297 static int _skl_resume(struct hdac_bus *bus) 298 { 299 struct skl *skl = bus_to_skl(bus); 300 301 skl_init_pci(skl); 302 skl_init_chip(bus, true); 303 304 return skl_resume_dsp(skl); 305 } 306 #endif 307 308 #ifdef CONFIG_PM_SLEEP 309 /* 310 * power management 311 */ 312 static int skl_suspend(struct device *dev) 313 { 314 struct pci_dev *pci = to_pci_dev(dev); 315 struct hdac_bus *bus = pci_get_drvdata(pci); 316 struct skl *skl = bus_to_skl(bus); 317 int ret; 318 319 /* 320 * Do not suspend if streams which are marked ignore suspend are 321 * running, we need to save the state for these and continue 322 */ 323 if (skl->supend_active) { 324 /* turn off the links and stop the CORB/RIRB DMA if it is On */ 325 snd_hdac_ext_bus_link_power_down_all(bus); 326 327 if (bus->cmd_dma_state) 328 snd_hdac_bus_stop_cmd_io(bus); 329 330 enable_irq_wake(bus->irq); 331 pci_save_state(pci); 332 } else { 333 ret = _skl_suspend(bus); 334 if (ret < 0) 335 return ret; 336 skl->skl_sst->fw_loaded = false; 337 } 338 339 return 0; 340 } 341 342 static int skl_resume(struct device *dev) 343 { 344 struct pci_dev *pci = to_pci_dev(dev); 345 struct hdac_bus *bus = pci_get_drvdata(pci); 346 struct skl *skl = bus_to_skl(bus); 347 struct hdac_ext_link *hlink = NULL; 348 int ret; 349 350 /* 351 * resume only when we are not in suspend active, otherwise need to 352 * restore the device 353 */ 354 if (skl->supend_active) { 355 pci_restore_state(pci); 356 snd_hdac_ext_bus_link_power_up_all(bus); 357 disable_irq_wake(bus->irq); 358 /* 359 * turn On the links which are On before active suspend 360 * and start the CORB/RIRB DMA if On before 361 * active suspend. 362 */ 363 list_for_each_entry(hlink, &bus->hlink_list, list) { 364 if (hlink->ref_count) 365 snd_hdac_ext_bus_link_power_up(hlink); 366 } 367 368 ret = 0; 369 if (bus->cmd_dma_state) 370 snd_hdac_bus_init_cmd_io(bus); 371 } else { 372 ret = _skl_resume(bus); 373 374 /* turn off the links which are off before suspend */ 375 list_for_each_entry(hlink, &bus->hlink_list, list) { 376 if (!hlink->ref_count) 377 snd_hdac_ext_bus_link_power_down(hlink); 378 } 379 380 if (!bus->cmd_dma_state) 381 snd_hdac_bus_stop_cmd_io(bus); 382 } 383 384 return ret; 385 } 386 #endif /* CONFIG_PM_SLEEP */ 387 388 #ifdef CONFIG_PM 389 static int skl_runtime_suspend(struct device *dev) 390 { 391 struct pci_dev *pci = to_pci_dev(dev); 392 struct hdac_bus *bus = pci_get_drvdata(pci); 393 394 dev_dbg(bus->dev, "in %s\n", __func__); 395 396 return _skl_suspend(bus); 397 } 398 399 static int skl_runtime_resume(struct device *dev) 400 { 401 struct pci_dev *pci = to_pci_dev(dev); 402 struct hdac_bus *bus = pci_get_drvdata(pci); 403 404 dev_dbg(bus->dev, "in %s\n", __func__); 405 406 return _skl_resume(bus); 407 } 408 #endif /* CONFIG_PM */ 409 410 static const struct dev_pm_ops skl_pm = { 411 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) 412 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) 413 .suspend_late = skl_suspend_late, 414 }; 415 416 /* 417 * destructor 418 */ 419 static int skl_free(struct hdac_bus *bus) 420 { 421 struct skl *skl = bus_to_skl(bus); 422 423 skl->init_done = 0; /* to be sure */ 424 425 snd_hdac_ext_stop_streams(bus); 426 427 if (bus->irq >= 0) 428 free_irq(bus->irq, (void *)bus); 429 snd_hdac_bus_free_stream_pages(bus); 430 snd_hdac_stream_free_all(bus); 431 snd_hdac_link_free_all(bus); 432 433 if (bus->remap_addr) 434 iounmap(bus->remap_addr); 435 436 pci_release_regions(skl->pci); 437 pci_disable_device(skl->pci); 438 439 snd_hdac_ext_bus_exit(bus); 440 441 cancel_work_sync(&skl->probe_work); 442 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 443 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); 444 snd_hdac_i915_exit(bus); 445 } 446 447 return 0; 448 } 449 450 /* 451 * For each ssp there are 3 clocks (mclk/sclk/sclkfs). 452 * e.g. for ssp0, clocks will be named as 453 * "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs" 454 * So for skl+, there are 6 ssps, so 18 clocks will be created. 455 */ 456 static struct skl_ssp_clk skl_ssp_clks[] = { 457 {.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"}, 458 {.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"}, 459 {.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"}, 460 {.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"}, 461 {.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"}, 462 {.name = "ssp2_sclkfs"}, 463 {.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"}, 464 {.name = "ssp5_sclkfs"}, 465 }; 466 467 static struct snd_soc_acpi_mach *skl_find_hda_machine(struct skl *skl, 468 struct snd_soc_acpi_mach *machines) 469 { 470 struct hdac_bus *bus = skl_to_bus(skl); 471 struct snd_soc_acpi_mach *mach; 472 473 /* check if we have any codecs detected on bus */ 474 if (bus->codec_mask == 0) 475 return NULL; 476 477 /* point to common table */ 478 mach = snd_soc_acpi_intel_hda_machines; 479 480 /* all entries in the machine table use the same firmware */ 481 mach->fw_filename = machines->fw_filename; 482 483 return mach; 484 } 485 486 static int skl_find_machine(struct skl *skl, void *driver_data) 487 { 488 struct hdac_bus *bus = skl_to_bus(skl); 489 struct snd_soc_acpi_mach *mach = driver_data; 490 struct skl_machine_pdata *pdata; 491 492 mach = snd_soc_acpi_find_machine(mach); 493 if (!mach) { 494 dev_dbg(bus->dev, "No matching I2S machine driver found\n"); 495 mach = skl_find_hda_machine(skl, driver_data); 496 if (!mach) { 497 dev_err(bus->dev, "No matching machine driver found\n"); 498 return -ENODEV; 499 } 500 } 501 502 skl->mach = mach; 503 skl->fw_name = mach->fw_filename; 504 pdata = mach->pdata; 505 506 if (pdata) { 507 skl->use_tplg_pcm = pdata->use_tplg_pcm; 508 mach->mach_params.dmic_num = skl_get_dmic_geo(skl); 509 } 510 511 return 0; 512 } 513 514 static int skl_machine_device_register(struct skl *skl) 515 { 516 struct snd_soc_acpi_mach *mach = skl->mach; 517 struct hdac_bus *bus = skl_to_bus(skl); 518 struct platform_device *pdev; 519 int ret; 520 521 pdev = platform_device_alloc(mach->drv_name, -1); 522 if (pdev == NULL) { 523 dev_err(bus->dev, "platform device alloc failed\n"); 524 return -EIO; 525 } 526 527 mach->mach_params.platform = dev_name(bus->dev); 528 mach->mach_params.codec_mask = bus->codec_mask; 529 530 ret = platform_device_add_data(pdev, (const void *)mach, sizeof(*mach)); 531 if (ret) { 532 dev_err(bus->dev, "failed to add machine device platform data\n"); 533 platform_device_put(pdev); 534 return ret; 535 } 536 537 ret = platform_device_add(pdev); 538 if (ret) { 539 dev_err(bus->dev, "failed to add machine device\n"); 540 platform_device_put(pdev); 541 return -EIO; 542 } 543 544 545 skl->i2s_dev = pdev; 546 547 return 0; 548 } 549 550 static void skl_machine_device_unregister(struct skl *skl) 551 { 552 if (skl->i2s_dev) 553 platform_device_unregister(skl->i2s_dev); 554 } 555 556 static int skl_dmic_device_register(struct skl *skl) 557 { 558 struct hdac_bus *bus = skl_to_bus(skl); 559 struct platform_device *pdev; 560 int ret; 561 562 /* SKL has one dmic port, so allocate dmic device for this */ 563 pdev = platform_device_alloc("dmic-codec", -1); 564 if (!pdev) { 565 dev_err(bus->dev, "failed to allocate dmic device\n"); 566 return -ENOMEM; 567 } 568 569 ret = platform_device_add(pdev); 570 if (ret) { 571 dev_err(bus->dev, "failed to add dmic device: %d\n", ret); 572 platform_device_put(pdev); 573 return ret; 574 } 575 skl->dmic_dev = pdev; 576 577 return 0; 578 } 579 580 static void skl_dmic_device_unregister(struct skl *skl) 581 { 582 if (skl->dmic_dev) 583 platform_device_unregister(skl->dmic_dev); 584 } 585 586 static struct skl_clk_parent_src skl_clk_src[] = { 587 { .clk_id = SKL_XTAL, .name = "xtal" }, 588 { .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 }, 589 { .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 }, 590 }; 591 592 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id) 593 { 594 unsigned int i; 595 596 for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) { 597 if (skl_clk_src[i].clk_id == clk_id) 598 return &skl_clk_src[i]; 599 } 600 601 return NULL; 602 } 603 604 static void init_skl_xtal_rate(int pci_id) 605 { 606 switch (pci_id) { 607 case 0x9d70: 608 case 0x9d71: 609 skl_clk_src[0].rate = 24000000; 610 return; 611 612 default: 613 skl_clk_src[0].rate = 19200000; 614 return; 615 } 616 } 617 618 static int skl_clock_device_register(struct skl *skl) 619 { 620 struct platform_device_info pdevinfo = {NULL}; 621 struct skl_clk_pdata *clk_pdata; 622 623 clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata), 624 GFP_KERNEL); 625 if (!clk_pdata) 626 return -ENOMEM; 627 628 init_skl_xtal_rate(skl->pci->device); 629 630 clk_pdata->parent_clks = skl_clk_src; 631 clk_pdata->ssp_clks = skl_ssp_clks; 632 clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks); 633 634 /* Query NHLT to fill the rates and parent */ 635 skl_get_clks(skl, clk_pdata->ssp_clks); 636 clk_pdata->pvt_data = skl; 637 638 /* Register Platform device */ 639 pdevinfo.parent = &skl->pci->dev; 640 pdevinfo.id = -1; 641 pdevinfo.name = "skl-ssp-clk"; 642 pdevinfo.data = clk_pdata; 643 pdevinfo.size_data = sizeof(*clk_pdata); 644 skl->clk_dev = platform_device_register_full(&pdevinfo); 645 return PTR_ERR_OR_ZERO(skl->clk_dev); 646 } 647 648 static void skl_clock_device_unregister(struct skl *skl) 649 { 650 if (skl->clk_dev) 651 platform_device_unregister(skl->clk_dev); 652 } 653 654 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 655 656 #define IDISP_INTEL_VENDOR_ID 0x80860000 657 658 /* 659 * load the legacy codec driver 660 */ 661 static void load_codec_module(struct hda_codec *codec) 662 { 663 #ifdef MODULE 664 char modalias[MODULE_NAME_LEN]; 665 const char *mod = NULL; 666 667 snd_hdac_codec_modalias(&codec->core, modalias, sizeof(modalias)); 668 mod = modalias; 669 dev_dbg(&codec->core.dev, "loading %s codec module\n", mod); 670 request_module(mod); 671 #endif 672 } 673 674 #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */ 675 676 /* 677 * Probe the given codec address 678 */ 679 static int probe_codec(struct hdac_bus *bus, int addr) 680 { 681 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 682 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 683 unsigned int res = -1; 684 struct skl *skl = bus_to_skl(bus); 685 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 686 struct hdac_hda_priv *hda_codec; 687 int err; 688 #endif 689 struct hdac_device *hdev; 690 691 mutex_lock(&bus->cmd_mutex); 692 snd_hdac_bus_send_cmd(bus, cmd); 693 snd_hdac_bus_get_response(bus, addr, &res); 694 mutex_unlock(&bus->cmd_mutex); 695 if (res == -1) 696 return -EIO; 697 dev_dbg(bus->dev, "codec #%d probed OK: %x\n", addr, res); 698 699 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 700 hda_codec = devm_kzalloc(&skl->pci->dev, sizeof(*hda_codec), 701 GFP_KERNEL); 702 if (!hda_codec) 703 return -ENOMEM; 704 705 hda_codec->codec.bus = skl_to_hbus(skl); 706 hdev = &hda_codec->codec.core; 707 708 err = snd_hdac_ext_bus_device_init(bus, addr, hdev); 709 if (err < 0) 710 return err; 711 712 /* use legacy bus only for HDA codecs, idisp uses ext bus */ 713 if ((res & 0xFFFF0000) != IDISP_INTEL_VENDOR_ID) { 714 hdev->type = HDA_DEV_LEGACY; 715 load_codec_module(&hda_codec->codec); 716 } 717 return 0; 718 #else 719 hdev = devm_kzalloc(&skl->pci->dev, sizeof(*hdev), GFP_KERNEL); 720 if (!hdev) 721 return -ENOMEM; 722 723 return snd_hdac_ext_bus_device_init(bus, addr, hdev); 724 #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */ 725 } 726 727 /* Codec initialization */ 728 static void skl_codec_create(struct hdac_bus *bus) 729 { 730 int c, max_slots; 731 732 max_slots = HDA_MAX_CODECS; 733 734 /* First try to probe all given codec slots */ 735 for (c = 0; c < max_slots; c++) { 736 if ((bus->codec_mask & (1 << c))) { 737 if (probe_codec(bus, c) < 0) { 738 /* 739 * Some BIOSen give you wrong codec addresses 740 * that don't exist 741 */ 742 dev_warn(bus->dev, 743 "Codec #%d probe error; disabling it...\n", c); 744 bus->codec_mask &= ~(1 << c); 745 /* 746 * More badly, accessing to a non-existing 747 * codec often screws up the controller bus, 748 * and disturbs the further communications. 749 * Thus if an error occurs during probing, 750 * better to reset the controller bus to get 751 * back to the sanity state. 752 */ 753 snd_hdac_bus_stop_chip(bus); 754 skl_init_chip(bus, true); 755 } 756 } 757 } 758 } 759 760 static const struct hdac_bus_ops bus_core_ops = { 761 .command = snd_hdac_bus_send_cmd, 762 .get_response = snd_hdac_bus_get_response, 763 }; 764 765 static int skl_i915_init(struct hdac_bus *bus) 766 { 767 int err; 768 769 /* 770 * The HDMI codec is in GPU so we need to ensure that it is powered 771 * up and ready for probe 772 */ 773 err = snd_hdac_i915_init(bus); 774 if (err < 0) 775 return err; 776 777 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true); 778 779 return 0; 780 } 781 782 static void skl_probe_work(struct work_struct *work) 783 { 784 struct skl *skl = container_of(work, struct skl, probe_work); 785 struct hdac_bus *bus = skl_to_bus(skl); 786 struct hdac_ext_link *hlink = NULL; 787 int err; 788 789 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 790 err = skl_i915_init(bus); 791 if (err < 0) 792 return; 793 } 794 795 err = skl_init_chip(bus, true); 796 if (err < 0) { 797 dev_err(bus->dev, "Init chip failed with err: %d\n", err); 798 goto out_err; 799 } 800 801 /* codec detection */ 802 if (!bus->codec_mask) 803 dev_info(bus->dev, "no hda codecs found!\n"); 804 805 /* create codec instances */ 806 skl_codec_create(bus); 807 808 /* register platform dai and controls */ 809 err = skl_platform_register(bus->dev); 810 if (err < 0) { 811 dev_err(bus->dev, "platform register failed: %d\n", err); 812 goto out_err; 813 } 814 815 err = skl_machine_device_register(skl); 816 if (err < 0) { 817 dev_err(bus->dev, "machine register failed: %d\n", err); 818 goto out_err; 819 } 820 821 /* 822 * we are done probing so decrement link counts 823 */ 824 list_for_each_entry(hlink, &bus->hlink_list, list) 825 snd_hdac_ext_bus_link_put(bus, hlink); 826 827 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 828 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); 829 830 /* configure PM */ 831 pm_runtime_put_noidle(bus->dev); 832 pm_runtime_allow(bus->dev); 833 skl->init_done = 1; 834 835 return; 836 837 out_err: 838 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 839 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); 840 } 841 842 /* 843 * constructor 844 */ 845 static int skl_create(struct pci_dev *pci, 846 const struct hdac_io_ops *io_ops, 847 struct skl **rskl) 848 { 849 struct hdac_ext_bus_ops *ext_ops = NULL; 850 struct skl *skl; 851 struct hdac_bus *bus; 852 struct hda_bus *hbus; 853 int err; 854 855 *rskl = NULL; 856 857 err = pci_enable_device(pci); 858 if (err < 0) 859 return err; 860 861 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); 862 if (!skl) { 863 pci_disable_device(pci); 864 return -ENOMEM; 865 } 866 867 hbus = skl_to_hbus(skl); 868 bus = skl_to_bus(skl); 869 870 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 871 ext_ops = snd_soc_hdac_hda_get_ops(); 872 #endif 873 snd_hdac_ext_bus_init(bus, &pci->dev, &bus_core_ops, io_ops, ext_ops); 874 bus->use_posbuf = 1; 875 skl->pci = pci; 876 INIT_WORK(&skl->probe_work, skl_probe_work); 877 bus->bdl_pos_adj = 0; 878 879 mutex_init(&hbus->prepare_mutex); 880 hbus->pci = pci; 881 hbus->mixer_assigned = -1; 882 hbus->modelname = "sklbus"; 883 884 *rskl = skl; 885 886 return 0; 887 } 888 889 static int skl_first_init(struct hdac_bus *bus) 890 { 891 struct skl *skl = bus_to_skl(bus); 892 struct pci_dev *pci = skl->pci; 893 int err; 894 unsigned short gcap; 895 int cp_streams, pb_streams, start_idx; 896 897 err = pci_request_regions(pci, "Skylake HD audio"); 898 if (err < 0) 899 return err; 900 901 bus->addr = pci_resource_start(pci, 0); 902 bus->remap_addr = pci_ioremap_bar(pci, 0); 903 if (bus->remap_addr == NULL) { 904 dev_err(bus->dev, "ioremap error\n"); 905 return -ENXIO; 906 } 907 908 snd_hdac_bus_reset_link(bus, true); 909 910 snd_hdac_bus_parse_capabilities(bus); 911 912 /* check if PPCAP exists */ 913 if (!bus->ppcap) { 914 dev_err(bus->dev, "bus ppcap not set, HDaudio or DSP not present?\n"); 915 return -ENODEV; 916 } 917 918 if (skl_acquire_irq(bus, 0) < 0) 919 return -EBUSY; 920 921 pci_set_master(pci); 922 synchronize_irq(bus->irq); 923 924 gcap = snd_hdac_chip_readw(bus, GCAP); 925 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); 926 927 /* read number of streams from GCAP register */ 928 cp_streams = (gcap >> 8) & 0x0f; 929 pb_streams = (gcap >> 12) & 0x0f; 930 931 if (!pb_streams && !cp_streams) { 932 dev_err(bus->dev, "no streams found in GCAP definitions?\n"); 933 return -EIO; 934 } 935 936 bus->num_streams = cp_streams + pb_streams; 937 938 /* allow 64bit DMA address if supported by H/W */ 939 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) { 940 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64)); 941 } else { 942 dma_set_mask(bus->dev, DMA_BIT_MASK(32)); 943 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32)); 944 } 945 946 /* initialize streams */ 947 snd_hdac_ext_stream_init_all 948 (bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); 949 start_idx = cp_streams; 950 snd_hdac_ext_stream_init_all 951 (bus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); 952 953 err = snd_hdac_bus_alloc_stream_pages(bus); 954 if (err < 0) 955 return err; 956 957 /* initialize chip */ 958 skl_init_pci(skl); 959 960 return skl_init_chip(bus, true); 961 } 962 963 static int skl_probe(struct pci_dev *pci, 964 const struct pci_device_id *pci_id) 965 { 966 struct skl *skl; 967 struct hdac_bus *bus = NULL; 968 int err; 969 970 switch (skl_pci_binding) { 971 case SND_SKL_PCI_BIND_AUTO: 972 /* 973 * detect DSP by checking class/subclass/prog-id information 974 * class=04 subclass 03 prog-if 00: no DSP, use legacy driver 975 * class=04 subclass 01 prog-if 00: DSP is present 976 * (and may be required e.g. for DMIC or SSP support) 977 * class=04 subclass 03 prog-if 80: use DSP or legacy mode 978 */ 979 if (pci->class == 0x040300) { 980 dev_info(&pci->dev, "The DSP is not enabled on this platform, aborting probe\n"); 981 return -ENODEV; 982 } 983 if (pci->class != 0x040100 && pci->class != 0x040380) { 984 dev_err(&pci->dev, "Unknown PCI class/subclass/prog-if information (0x%06x) found, aborting probe\n", pci->class); 985 return -ENODEV; 986 } 987 dev_info(&pci->dev, "DSP detected with PCI class/subclass/prog-if info 0x%06x\n", pci->class); 988 break; 989 case SND_SKL_PCI_BIND_LEGACY: 990 dev_info(&pci->dev, "Module parameter forced binding with HDaudio legacy, aborting probe\n"); 991 return -ENODEV; 992 case SND_SKL_PCI_BIND_ASOC: 993 dev_info(&pci->dev, "Module parameter forced binding with SKL driver, bypassed detection logic\n"); 994 break; 995 default: 996 dev_err(&pci->dev, "invalid value for skl_pci_binding module parameter, ignored\n"); 997 break; 998 } 999 1000 /* we use ext core ops, so provide NULL for ops here */ 1001 err = skl_create(pci, NULL, &skl); 1002 if (err < 0) 1003 return err; 1004 1005 bus = skl_to_bus(skl); 1006 1007 err = skl_first_init(bus); 1008 if (err < 0) { 1009 dev_err(bus->dev, "skl_first_init failed with err: %d\n", err); 1010 goto out_free; 1011 } 1012 1013 skl->pci_id = pci->device; 1014 1015 device_disable_async_suspend(bus->dev); 1016 1017 skl->nhlt = skl_nhlt_init(bus->dev); 1018 1019 if (skl->nhlt == NULL) { 1020 #if !IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 1021 dev_err(bus->dev, "no nhlt info found\n"); 1022 err = -ENODEV; 1023 goto out_free; 1024 #else 1025 dev_warn(bus->dev, "no nhlt info found, continuing to try to enable HDaudio codec\n"); 1026 #endif 1027 } else { 1028 1029 err = skl_nhlt_create_sysfs(skl); 1030 if (err < 0) { 1031 dev_err(bus->dev, "skl_nhlt_create_sysfs failed with err: %d\n", err); 1032 goto out_nhlt_free; 1033 } 1034 1035 skl_nhlt_update_topology_bin(skl); 1036 1037 /* create device for dsp clk */ 1038 err = skl_clock_device_register(skl); 1039 if (err < 0) { 1040 dev_err(bus->dev, "skl_clock_device_register failed with err: %d\n", err); 1041 goto out_clk_free; 1042 } 1043 } 1044 1045 pci_set_drvdata(skl->pci, bus); 1046 1047 1048 err = skl_find_machine(skl, (void *)pci_id->driver_data); 1049 if (err < 0) { 1050 dev_err(bus->dev, "skl_find_machine failed with err: %d\n", err); 1051 goto out_nhlt_free; 1052 } 1053 1054 err = skl_init_dsp(skl); 1055 if (err < 0) { 1056 dev_dbg(bus->dev, "error failed to register dsp\n"); 1057 goto out_nhlt_free; 1058 } 1059 skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge; 1060 skl->skl_sst->clock_power_gating = skl_clock_power_gating; 1061 1062 if (bus->mlcap) 1063 snd_hdac_ext_bus_get_ml_capabilities(bus); 1064 1065 snd_hdac_bus_stop_chip(bus); 1066 1067 /* create device for soc dmic */ 1068 err = skl_dmic_device_register(skl); 1069 if (err < 0) { 1070 dev_err(bus->dev, "skl_dmic_device_register failed with err: %d\n", err); 1071 goto out_dsp_free; 1072 } 1073 1074 schedule_work(&skl->probe_work); 1075 1076 return 0; 1077 1078 out_dsp_free: 1079 skl_free_dsp(skl); 1080 out_clk_free: 1081 skl_clock_device_unregister(skl); 1082 out_nhlt_free: 1083 skl_nhlt_free(skl->nhlt); 1084 out_free: 1085 skl_free(bus); 1086 1087 return err; 1088 } 1089 1090 static void skl_shutdown(struct pci_dev *pci) 1091 { 1092 struct hdac_bus *bus = pci_get_drvdata(pci); 1093 struct hdac_stream *s; 1094 struct hdac_ext_stream *stream; 1095 struct skl *skl; 1096 1097 if (!bus) 1098 return; 1099 1100 skl = bus_to_skl(bus); 1101 1102 if (!skl->init_done) 1103 return; 1104 1105 snd_hdac_ext_stop_streams(bus); 1106 list_for_each_entry(s, &bus->stream_list, list) { 1107 stream = stream_to_hdac_ext_stream(s); 1108 snd_hdac_ext_stream_decouple(bus, stream, false); 1109 } 1110 1111 snd_hdac_bus_stop_chip(bus); 1112 } 1113 1114 static void skl_remove(struct pci_dev *pci) 1115 { 1116 struct hdac_bus *bus = pci_get_drvdata(pci); 1117 struct skl *skl = bus_to_skl(bus); 1118 1119 release_firmware(skl->tplg); 1120 1121 pm_runtime_get_noresume(&pci->dev); 1122 1123 /* codec removal, invoke bus_device_remove */ 1124 snd_hdac_ext_bus_device_remove(bus); 1125 1126 skl->debugfs = NULL; 1127 skl_platform_unregister(&pci->dev); 1128 skl_free_dsp(skl); 1129 skl_machine_device_unregister(skl); 1130 skl_dmic_device_unregister(skl); 1131 skl_clock_device_unregister(skl); 1132 skl_nhlt_remove_sysfs(skl); 1133 skl_nhlt_free(skl->nhlt); 1134 skl_free(bus); 1135 dev_set_drvdata(&pci->dev, NULL); 1136 } 1137 1138 /* PCI IDs */ 1139 static const struct pci_device_id skl_ids[] = { 1140 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKL) 1141 /* Sunrise Point-LP */ 1142 { PCI_DEVICE(0x8086, 0x9d70), 1143 .driver_data = (unsigned long)&snd_soc_acpi_intel_skl_machines}, 1144 #endif 1145 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_APL) 1146 /* BXT-P */ 1147 { PCI_DEVICE(0x8086, 0x5a98), 1148 .driver_data = (unsigned long)&snd_soc_acpi_intel_bxt_machines}, 1149 #endif 1150 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_KBL) 1151 /* KBL */ 1152 { PCI_DEVICE(0x8086, 0x9D71), 1153 .driver_data = (unsigned long)&snd_soc_acpi_intel_kbl_machines}, 1154 #endif 1155 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_GLK) 1156 /* GLK */ 1157 { PCI_DEVICE(0x8086, 0x3198), 1158 .driver_data = (unsigned long)&snd_soc_acpi_intel_glk_machines}, 1159 #endif 1160 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CNL) 1161 /* CNL */ 1162 { PCI_DEVICE(0x8086, 0x9dc8), 1163 .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, 1164 #endif 1165 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CFL) 1166 /* CFL */ 1167 { PCI_DEVICE(0x8086, 0xa348), 1168 .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, 1169 #endif 1170 { 0, } 1171 }; 1172 MODULE_DEVICE_TABLE(pci, skl_ids); 1173 1174 /* pci_driver definition */ 1175 static struct pci_driver skl_driver = { 1176 .name = KBUILD_MODNAME, 1177 .id_table = skl_ids, 1178 .probe = skl_probe, 1179 .remove = skl_remove, 1180 .shutdown = skl_shutdown, 1181 .driver = { 1182 .pm = &skl_pm, 1183 }, 1184 }; 1185 module_pci_driver(skl_driver); 1186 1187 MODULE_LICENSE("GPL v2"); 1188 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver"); 1189