1 /* 2 * skl.c - Implementation of ASoC Intel SKL HD Audio driver 3 * 4 * Copyright (C) 2014-2015 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * 7 * Derived mostly from Intel HDA driver with following copyrights: 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; version 2 of the License. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 22 */ 23 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/platform_device.h> 28 #include <linux/firmware.h> 29 #include <linux/delay.h> 30 #include <sound/pcm.h> 31 #include <sound/soc-acpi.h> 32 #include <sound/soc-acpi-intel-match.h> 33 #include <sound/hda_register.h> 34 #include <sound/hdaudio.h> 35 #include <sound/hda_i915.h> 36 #include <sound/hda_codec.h> 37 #include "skl.h" 38 #include "skl-sst-dsp.h" 39 #include "skl-sst-ipc.h" 40 #include "../../../soc/codecs/hdac_hda.h" 41 42 /* 43 * initialize the PCI registers 44 */ 45 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, 46 unsigned char mask, unsigned char val) 47 { 48 unsigned char data; 49 50 pci_read_config_byte(pci, reg, &data); 51 data &= ~mask; 52 data |= (val & mask); 53 pci_write_config_byte(pci, reg, data); 54 } 55 56 static void skl_init_pci(struct skl *skl) 57 { 58 struct hdac_bus *bus = skl_to_bus(skl); 59 60 /* 61 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 62 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 63 * Ensuring these bits are 0 clears playback static on some HD Audio 64 * codecs. 65 * The PCI register TCSEL is defined in the Intel manuals. 66 */ 67 dev_dbg(bus->dev, "Clearing TCSEL\n"); 68 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); 69 } 70 71 static void update_pci_dword(struct pci_dev *pci, 72 unsigned int reg, u32 mask, u32 val) 73 { 74 u32 data = 0; 75 76 pci_read_config_dword(pci, reg, &data); 77 data &= ~mask; 78 data |= (val & mask); 79 pci_write_config_dword(pci, reg, data); 80 } 81 82 /* 83 * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits 84 * 85 * @dev: device pointer 86 * @enable: enable/disable flag 87 */ 88 static void skl_enable_miscbdcge(struct device *dev, bool enable) 89 { 90 struct pci_dev *pci = to_pci_dev(dev); 91 u32 val; 92 93 val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; 94 95 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); 96 } 97 98 /** 99 * skl_clock_power_gating: Enable/Disable clock and power gating 100 * 101 * @dev: Device pointer 102 * @enable: Enable/Disable flag 103 */ 104 static void skl_clock_power_gating(struct device *dev, bool enable) 105 { 106 struct pci_dev *pci = to_pci_dev(dev); 107 struct hdac_bus *bus = pci_get_drvdata(pci); 108 u32 val; 109 110 /* Update PDCGE bit of CGCTL register */ 111 val = enable ? AZX_CGCTL_ADSPDCGE : 0; 112 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); 113 114 /* Update L1SEN bit of EM2 register */ 115 val = enable ? AZX_REG_VS_EM2_L1SEN : 0; 116 snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val); 117 118 /* Update ADSPPGD bit of PGCTL register */ 119 val = enable ? 0 : AZX_PGCTL_ADSPPGD; 120 update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val); 121 } 122 123 /* 124 * While performing reset, controller may not come back properly causing 125 * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset 126 * (init chip) and then again set CGCTL.MISCBDCGE to 1 127 */ 128 static int skl_init_chip(struct hdac_bus *bus, bool full_reset) 129 { 130 struct hdac_ext_link *hlink; 131 int ret; 132 133 skl_enable_miscbdcge(bus->dev, false); 134 ret = snd_hdac_bus_init_chip(bus, full_reset); 135 136 /* Reset stream-to-link mapping */ 137 list_for_each_entry(hlink, &bus->hlink_list, list) 138 bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV); 139 140 skl_enable_miscbdcge(bus->dev, true); 141 142 return ret; 143 } 144 145 void skl_update_d0i3c(struct device *dev, bool enable) 146 { 147 struct pci_dev *pci = to_pci_dev(dev); 148 struct hdac_bus *bus = pci_get_drvdata(pci); 149 u8 reg; 150 int timeout = 50; 151 152 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 153 /* Do not write to D0I3C until command in progress bit is cleared */ 154 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 155 udelay(10); 156 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 157 } 158 159 /* Highly unlikely. But if it happens, flag error explicitly */ 160 if (!timeout) { 161 dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n"); 162 return; 163 } 164 165 if (enable) 166 reg = reg | AZX_REG_VS_D0I3C_I3; 167 else 168 reg = reg & (~AZX_REG_VS_D0I3C_I3); 169 170 snd_hdac_chip_writeb(bus, VS_D0I3C, reg); 171 172 timeout = 50; 173 /* Wait for cmd in progress to be cleared before exiting the function */ 174 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 175 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 176 udelay(10); 177 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 178 } 179 180 /* Highly unlikely. But if it happens, flag error explicitly */ 181 if (!timeout) { 182 dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n"); 183 return; 184 } 185 186 dev_dbg(bus->dev, "D0I3C register = 0x%x\n", 187 snd_hdac_chip_readb(bus, VS_D0I3C)); 188 } 189 190 /* called from IRQ */ 191 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) 192 { 193 snd_pcm_period_elapsed(hstr->substream); 194 } 195 196 static irqreturn_t skl_interrupt(int irq, void *dev_id) 197 { 198 struct hdac_bus *bus = dev_id; 199 u32 status; 200 201 if (!pm_runtime_active(bus->dev)) 202 return IRQ_NONE; 203 204 spin_lock(&bus->reg_lock); 205 206 status = snd_hdac_chip_readl(bus, INTSTS); 207 if (status == 0 || status == 0xffffffff) { 208 spin_unlock(&bus->reg_lock); 209 return IRQ_NONE; 210 } 211 212 /* clear rirb int */ 213 status = snd_hdac_chip_readb(bus, RIRBSTS); 214 if (status & RIRB_INT_MASK) { 215 if (status & RIRB_INT_RESPONSE) 216 snd_hdac_bus_update_rirb(bus); 217 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 218 } 219 220 spin_unlock(&bus->reg_lock); 221 222 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; 223 } 224 225 static irqreturn_t skl_threaded_handler(int irq, void *dev_id) 226 { 227 struct hdac_bus *bus = dev_id; 228 u32 status; 229 230 status = snd_hdac_chip_readl(bus, INTSTS); 231 232 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); 233 234 return IRQ_HANDLED; 235 } 236 237 static int skl_acquire_irq(struct hdac_bus *bus, int do_disconnect) 238 { 239 struct skl *skl = bus_to_skl(bus); 240 int ret; 241 242 ret = request_threaded_irq(skl->pci->irq, skl_interrupt, 243 skl_threaded_handler, 244 IRQF_SHARED, 245 KBUILD_MODNAME, bus); 246 if (ret) { 247 dev_err(bus->dev, 248 "unable to grab IRQ %d, disabling device\n", 249 skl->pci->irq); 250 return ret; 251 } 252 253 bus->irq = skl->pci->irq; 254 pci_intx(skl->pci, 1); 255 256 return 0; 257 } 258 259 static int skl_suspend_late(struct device *dev) 260 { 261 struct pci_dev *pci = to_pci_dev(dev); 262 struct hdac_bus *bus = pci_get_drvdata(pci); 263 struct skl *skl = bus_to_skl(bus); 264 265 return skl_suspend_late_dsp(skl); 266 } 267 268 #ifdef CONFIG_PM 269 static int _skl_suspend(struct hdac_bus *bus) 270 { 271 struct skl *skl = bus_to_skl(bus); 272 struct pci_dev *pci = to_pci_dev(bus->dev); 273 int ret; 274 275 snd_hdac_ext_bus_link_power_down_all(bus); 276 277 ret = skl_suspend_dsp(skl); 278 if (ret < 0) 279 return ret; 280 281 snd_hdac_bus_stop_chip(bus); 282 update_pci_dword(pci, AZX_PCIREG_PGCTL, 283 AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK); 284 skl_enable_miscbdcge(bus->dev, false); 285 snd_hdac_bus_enter_link_reset(bus); 286 skl_enable_miscbdcge(bus->dev, true); 287 skl_cleanup_resources(skl); 288 289 return 0; 290 } 291 292 static int _skl_resume(struct hdac_bus *bus) 293 { 294 struct skl *skl = bus_to_skl(bus); 295 296 skl_init_pci(skl); 297 skl_init_chip(bus, true); 298 299 return skl_resume_dsp(skl); 300 } 301 #endif 302 303 #ifdef CONFIG_PM_SLEEP 304 /* 305 * power management 306 */ 307 static int skl_suspend(struct device *dev) 308 { 309 struct pci_dev *pci = to_pci_dev(dev); 310 struct hdac_bus *bus = pci_get_drvdata(pci); 311 struct skl *skl = bus_to_skl(bus); 312 int ret = 0; 313 314 /* 315 * Do not suspend if streams which are marked ignore suspend are 316 * running, we need to save the state for these and continue 317 */ 318 if (skl->supend_active) { 319 /* turn off the links and stop the CORB/RIRB DMA if it is On */ 320 snd_hdac_ext_bus_link_power_down_all(bus); 321 322 if (bus->cmd_dma_state) 323 snd_hdac_bus_stop_cmd_io(bus); 324 325 enable_irq_wake(bus->irq); 326 pci_save_state(pci); 327 } else { 328 ret = _skl_suspend(bus); 329 if (ret < 0) 330 return ret; 331 skl->skl_sst->fw_loaded = false; 332 } 333 334 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 335 ret = snd_hdac_display_power(bus, false); 336 if (ret < 0) 337 dev_err(bus->dev, 338 "Cannot turn OFF display power on i915\n"); 339 } 340 341 return ret; 342 } 343 344 static int skl_resume(struct device *dev) 345 { 346 struct pci_dev *pci = to_pci_dev(dev); 347 struct hdac_bus *bus = pci_get_drvdata(pci); 348 struct skl *skl = bus_to_skl(bus); 349 struct hdac_ext_link *hlink = NULL; 350 int ret; 351 352 /* Turned OFF in HDMI codec driver after codec reconfiguration */ 353 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 354 ret = snd_hdac_display_power(bus, true); 355 if (ret < 0) { 356 dev_err(bus->dev, 357 "Cannot turn on display power on i915\n"); 358 return ret; 359 } 360 } 361 362 /* 363 * resume only when we are not in suspend active, otherwise need to 364 * restore the device 365 */ 366 if (skl->supend_active) { 367 pci_restore_state(pci); 368 snd_hdac_ext_bus_link_power_up_all(bus); 369 disable_irq_wake(bus->irq); 370 /* 371 * turn On the links which are On before active suspend 372 * and start the CORB/RIRB DMA if On before 373 * active suspend. 374 */ 375 list_for_each_entry(hlink, &bus->hlink_list, list) { 376 if (hlink->ref_count) 377 snd_hdac_ext_bus_link_power_up(hlink); 378 } 379 380 ret = 0; 381 if (bus->cmd_dma_state) 382 snd_hdac_bus_init_cmd_io(bus); 383 } else { 384 ret = _skl_resume(bus); 385 386 /* turn off the links which are off before suspend */ 387 list_for_each_entry(hlink, &bus->hlink_list, list) { 388 if (!hlink->ref_count) 389 snd_hdac_ext_bus_link_power_down(hlink); 390 } 391 392 if (!bus->cmd_dma_state) 393 snd_hdac_bus_stop_cmd_io(bus); 394 } 395 396 return ret; 397 } 398 #endif /* CONFIG_PM_SLEEP */ 399 400 #ifdef CONFIG_PM 401 static int skl_runtime_suspend(struct device *dev) 402 { 403 struct pci_dev *pci = to_pci_dev(dev); 404 struct hdac_bus *bus = pci_get_drvdata(pci); 405 406 dev_dbg(bus->dev, "in %s\n", __func__); 407 408 return _skl_suspend(bus); 409 } 410 411 static int skl_runtime_resume(struct device *dev) 412 { 413 struct pci_dev *pci = to_pci_dev(dev); 414 struct hdac_bus *bus = pci_get_drvdata(pci); 415 416 dev_dbg(bus->dev, "in %s\n", __func__); 417 418 return _skl_resume(bus); 419 } 420 #endif /* CONFIG_PM */ 421 422 static const struct dev_pm_ops skl_pm = { 423 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) 424 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) 425 .suspend_late = skl_suspend_late, 426 }; 427 428 /* 429 * destructor 430 */ 431 static int skl_free(struct hdac_bus *bus) 432 { 433 struct skl *skl = bus_to_skl(bus); 434 435 skl->init_done = 0; /* to be sure */ 436 437 snd_hdac_ext_stop_streams(bus); 438 439 if (bus->irq >= 0) 440 free_irq(bus->irq, (void *)bus); 441 snd_hdac_bus_free_stream_pages(bus); 442 snd_hdac_stream_free_all(bus); 443 snd_hdac_link_free_all(bus); 444 445 if (bus->remap_addr) 446 iounmap(bus->remap_addr); 447 448 pci_release_regions(skl->pci); 449 pci_disable_device(skl->pci); 450 451 snd_hdac_ext_bus_exit(bus); 452 453 cancel_work_sync(&skl->probe_work); 454 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 455 snd_hdac_i915_exit(bus); 456 457 return 0; 458 } 459 460 /* 461 * For each ssp there are 3 clocks (mclk/sclk/sclkfs). 462 * e.g. for ssp0, clocks will be named as 463 * "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs" 464 * So for skl+, there are 6 ssps, so 18 clocks will be created. 465 */ 466 static struct skl_ssp_clk skl_ssp_clks[] = { 467 {.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"}, 468 {.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"}, 469 {.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"}, 470 {.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"}, 471 {.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"}, 472 {.name = "ssp2_sclkfs"}, 473 {.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"}, 474 {.name = "ssp5_sclkfs"}, 475 }; 476 477 static struct snd_soc_acpi_mach *skl_find_hda_machine(struct skl *skl, 478 struct snd_soc_acpi_mach *machines) 479 { 480 struct hdac_bus *bus = skl_to_bus(skl); 481 struct snd_soc_acpi_mach *mach; 482 483 /* check if we have any codecs detected on bus */ 484 if (bus->codec_mask == 0) 485 return NULL; 486 487 /* point to common table */ 488 mach = snd_soc_acpi_intel_hda_machines; 489 490 /* all entries in the machine table use the same firmware */ 491 mach->fw_filename = machines->fw_filename; 492 493 return mach; 494 } 495 496 static int skl_find_machine(struct skl *skl, void *driver_data) 497 { 498 struct hdac_bus *bus = skl_to_bus(skl); 499 struct snd_soc_acpi_mach *mach = driver_data; 500 struct skl_machine_pdata *pdata; 501 502 mach = snd_soc_acpi_find_machine(mach); 503 if (!mach) { 504 dev_dbg(bus->dev, "No matching I2S machine driver found\n"); 505 mach = skl_find_hda_machine(skl, driver_data); 506 if (!mach) { 507 dev_err(bus->dev, "No matching machine driver found\n"); 508 return -ENODEV; 509 } 510 } 511 512 skl->mach = mach; 513 skl->fw_name = mach->fw_filename; 514 pdata = mach->pdata; 515 516 if (pdata) { 517 skl->use_tplg_pcm = pdata->use_tplg_pcm; 518 pdata->dmic_num = skl_get_dmic_geo(skl); 519 } 520 521 return 0; 522 } 523 524 static int skl_machine_device_register(struct skl *skl) 525 { 526 struct snd_soc_acpi_mach *mach = skl->mach; 527 struct hdac_bus *bus = skl_to_bus(skl); 528 struct skl_machine_pdata *pdata; 529 struct platform_device *pdev; 530 int ret; 531 532 pdev = platform_device_alloc(mach->drv_name, -1); 533 if (pdev == NULL) { 534 dev_err(bus->dev, "platform device alloc failed\n"); 535 return -EIO; 536 } 537 538 ret = platform_device_add(pdev); 539 if (ret) { 540 dev_err(bus->dev, "failed to add machine device\n"); 541 platform_device_put(pdev); 542 return -EIO; 543 } 544 545 if (mach->pdata) { 546 pdata = (struct skl_machine_pdata *)mach->pdata; 547 pdata->platform = dev_name(bus->dev); 548 pdata->codec_mask = bus->codec_mask; 549 dev_set_drvdata(&pdev->dev, mach->pdata); 550 } 551 552 skl->i2s_dev = pdev; 553 554 return 0; 555 } 556 557 static void skl_machine_device_unregister(struct skl *skl) 558 { 559 if (skl->i2s_dev) 560 platform_device_unregister(skl->i2s_dev); 561 } 562 563 static int skl_dmic_device_register(struct skl *skl) 564 { 565 struct hdac_bus *bus = skl_to_bus(skl); 566 struct platform_device *pdev; 567 int ret; 568 569 /* SKL has one dmic port, so allocate dmic device for this */ 570 pdev = platform_device_alloc("dmic-codec", -1); 571 if (!pdev) { 572 dev_err(bus->dev, "failed to allocate dmic device\n"); 573 return -ENOMEM; 574 } 575 576 ret = platform_device_add(pdev); 577 if (ret) { 578 dev_err(bus->dev, "failed to add dmic device: %d\n", ret); 579 platform_device_put(pdev); 580 return ret; 581 } 582 skl->dmic_dev = pdev; 583 584 return 0; 585 } 586 587 static void skl_dmic_device_unregister(struct skl *skl) 588 { 589 if (skl->dmic_dev) 590 platform_device_unregister(skl->dmic_dev); 591 } 592 593 static struct skl_clk_parent_src skl_clk_src[] = { 594 { .clk_id = SKL_XTAL, .name = "xtal" }, 595 { .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 }, 596 { .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 }, 597 }; 598 599 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id) 600 { 601 unsigned int i; 602 603 for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) { 604 if (skl_clk_src[i].clk_id == clk_id) 605 return &skl_clk_src[i]; 606 } 607 608 return NULL; 609 } 610 611 static void init_skl_xtal_rate(int pci_id) 612 { 613 switch (pci_id) { 614 case 0x9d70: 615 case 0x9d71: 616 skl_clk_src[0].rate = 24000000; 617 return; 618 619 default: 620 skl_clk_src[0].rate = 19200000; 621 return; 622 } 623 } 624 625 static int skl_clock_device_register(struct skl *skl) 626 { 627 struct platform_device_info pdevinfo = {NULL}; 628 struct skl_clk_pdata *clk_pdata; 629 630 clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata), 631 GFP_KERNEL); 632 if (!clk_pdata) 633 return -ENOMEM; 634 635 init_skl_xtal_rate(skl->pci->device); 636 637 clk_pdata->parent_clks = skl_clk_src; 638 clk_pdata->ssp_clks = skl_ssp_clks; 639 clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks); 640 641 /* Query NHLT to fill the rates and parent */ 642 skl_get_clks(skl, clk_pdata->ssp_clks); 643 clk_pdata->pvt_data = skl; 644 645 /* Register Platform device */ 646 pdevinfo.parent = &skl->pci->dev; 647 pdevinfo.id = -1; 648 pdevinfo.name = "skl-ssp-clk"; 649 pdevinfo.data = clk_pdata; 650 pdevinfo.size_data = sizeof(*clk_pdata); 651 skl->clk_dev = platform_device_register_full(&pdevinfo); 652 return PTR_ERR_OR_ZERO(skl->clk_dev); 653 } 654 655 static void skl_clock_device_unregister(struct skl *skl) 656 { 657 if (skl->clk_dev) 658 platform_device_unregister(skl->clk_dev); 659 } 660 661 #define IDISP_INTEL_VENDOR_ID 0x80860000 662 663 /* 664 * load the legacy codec driver 665 */ 666 static void load_codec_module(struct hda_codec *codec) 667 { 668 #ifdef MODULE 669 char modalias[MODULE_NAME_LEN]; 670 const char *mod = NULL; 671 672 snd_hdac_codec_modalias(&codec->core, modalias, sizeof(modalias)); 673 mod = modalias; 674 dev_dbg(&codec->core.dev, "loading %s codec module\n", mod); 675 request_module(mod); 676 #endif 677 } 678 679 /* 680 * Probe the given codec address 681 */ 682 static int probe_codec(struct hdac_bus *bus, int addr) 683 { 684 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 685 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 686 unsigned int res = -1; 687 struct skl *skl = bus_to_skl(bus); 688 struct hdac_hda_priv *hda_codec; 689 struct hdac_device *hdev; 690 int err; 691 692 mutex_lock(&bus->cmd_mutex); 693 snd_hdac_bus_send_cmd(bus, cmd); 694 snd_hdac_bus_get_response(bus, addr, &res); 695 mutex_unlock(&bus->cmd_mutex); 696 if (res == -1) 697 return -EIO; 698 dev_dbg(bus->dev, "codec #%d probed OK: %x\n", addr, res); 699 700 hda_codec = devm_kzalloc(&skl->pci->dev, sizeof(*hda_codec), 701 GFP_KERNEL); 702 if (!hda_codec) 703 return -ENOMEM; 704 705 hda_codec->codec.bus = skl_to_hbus(skl); 706 hdev = &hda_codec->codec.core; 707 708 err = snd_hdac_ext_bus_device_init(bus, addr, hdev); 709 if (err < 0) 710 return err; 711 712 /* use legacy bus only for HDA codecs, idisp uses ext bus */ 713 if ((res & 0xFFFF0000) != IDISP_INTEL_VENDOR_ID) { 714 hdev->type = HDA_DEV_LEGACY; 715 load_codec_module(&hda_codec->codec); 716 } 717 return 0; 718 } 719 720 /* Codec initialization */ 721 static void skl_codec_create(struct hdac_bus *bus) 722 { 723 int c, max_slots; 724 725 max_slots = HDA_MAX_CODECS; 726 727 /* First try to probe all given codec slots */ 728 for (c = 0; c < max_slots; c++) { 729 if ((bus->codec_mask & (1 << c))) { 730 if (probe_codec(bus, c) < 0) { 731 /* 732 * Some BIOSen give you wrong codec addresses 733 * that don't exist 734 */ 735 dev_warn(bus->dev, 736 "Codec #%d probe error; disabling it...\n", c); 737 bus->codec_mask &= ~(1 << c); 738 /* 739 * More badly, accessing to a non-existing 740 * codec often screws up the controller bus, 741 * and disturbs the further communications. 742 * Thus if an error occurs during probing, 743 * better to reset the controller bus to get 744 * back to the sanity state. 745 */ 746 snd_hdac_bus_stop_chip(bus); 747 skl_init_chip(bus, true); 748 } 749 } 750 } 751 } 752 753 static const struct hdac_bus_ops bus_core_ops = { 754 .command = snd_hdac_bus_send_cmd, 755 .get_response = snd_hdac_bus_get_response, 756 }; 757 758 static int skl_i915_init(struct hdac_bus *bus) 759 { 760 int err; 761 762 /* 763 * The HDMI codec is in GPU so we need to ensure that it is powered 764 * up and ready for probe 765 */ 766 err = snd_hdac_i915_init(bus); 767 if (err < 0) 768 return err; 769 770 err = snd_hdac_display_power(bus, true); 771 if (err < 0) 772 dev_err(bus->dev, "Cannot turn on display power on i915\n"); 773 774 return err; 775 } 776 777 static void skl_probe_work(struct work_struct *work) 778 { 779 struct skl *skl = container_of(work, struct skl, probe_work); 780 struct hdac_bus *bus = skl_to_bus(skl); 781 struct hdac_ext_link *hlink = NULL; 782 int err; 783 784 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 785 err = skl_i915_init(bus); 786 if (err < 0) 787 return; 788 } 789 790 err = skl_init_chip(bus, true); 791 if (err < 0) { 792 dev_err(bus->dev, "Init chip failed with err: %d\n", err); 793 goto out_err; 794 } 795 796 /* codec detection */ 797 if (!bus->codec_mask) 798 dev_info(bus->dev, "no hda codecs found!\n"); 799 800 /* create codec instances */ 801 skl_codec_create(bus); 802 803 /* register platform dai and controls */ 804 err = skl_platform_register(bus->dev); 805 if (err < 0) { 806 dev_err(bus->dev, "platform register failed: %d\n", err); 807 return; 808 } 809 810 if (bus->ppcap) { 811 err = skl_machine_device_register(skl); 812 if (err < 0) { 813 dev_err(bus->dev, "machine register failed: %d\n", err); 814 goto out_err; 815 } 816 } 817 818 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 819 err = snd_hdac_display_power(bus, false); 820 if (err < 0) { 821 dev_err(bus->dev, "Cannot turn off display power on i915\n"); 822 skl_machine_device_unregister(skl); 823 return; 824 } 825 } 826 827 /* 828 * we are done probing so decrement link counts 829 */ 830 list_for_each_entry(hlink, &bus->hlink_list, list) 831 snd_hdac_ext_bus_link_put(bus, hlink); 832 833 /* configure PM */ 834 pm_runtime_put_noidle(bus->dev); 835 pm_runtime_allow(bus->dev); 836 skl->init_done = 1; 837 838 return; 839 840 out_err: 841 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 842 err = snd_hdac_display_power(bus, false); 843 } 844 845 /* 846 * constructor 847 */ 848 static int skl_create(struct pci_dev *pci, 849 const struct hdac_io_ops *io_ops, 850 struct skl **rskl) 851 { 852 struct hdac_ext_bus_ops *ext_ops = NULL; 853 struct skl *skl; 854 struct hdac_bus *bus; 855 struct hda_bus *hbus; 856 int err; 857 858 *rskl = NULL; 859 860 err = pci_enable_device(pci); 861 if (err < 0) 862 return err; 863 864 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); 865 if (!skl) { 866 pci_disable_device(pci); 867 return -ENOMEM; 868 } 869 870 hbus = skl_to_hbus(skl); 871 bus = skl_to_bus(skl); 872 873 #if IS_ENABLED(CONFIG_SND_SOC_HDAC_HDA) 874 ext_ops = snd_soc_hdac_hda_get_ops(); 875 #endif 876 snd_hdac_ext_bus_init(bus, &pci->dev, &bus_core_ops, io_ops, ext_ops); 877 bus->use_posbuf = 1; 878 skl->pci = pci; 879 INIT_WORK(&skl->probe_work, skl_probe_work); 880 bus->bdl_pos_adj = 0; 881 882 mutex_init(&hbus->prepare_mutex); 883 hbus->pci = pci; 884 hbus->mixer_assigned = -1; 885 hbus->modelname = "sklbus"; 886 887 *rskl = skl; 888 889 return 0; 890 } 891 892 static int skl_first_init(struct hdac_bus *bus) 893 { 894 struct skl *skl = bus_to_skl(bus); 895 struct pci_dev *pci = skl->pci; 896 int err; 897 unsigned short gcap; 898 int cp_streams, pb_streams, start_idx; 899 900 err = pci_request_regions(pci, "Skylake HD audio"); 901 if (err < 0) 902 return err; 903 904 bus->addr = pci_resource_start(pci, 0); 905 bus->remap_addr = pci_ioremap_bar(pci, 0); 906 if (bus->remap_addr == NULL) { 907 dev_err(bus->dev, "ioremap error\n"); 908 return -ENXIO; 909 } 910 911 snd_hdac_bus_reset_link(bus, true); 912 913 snd_hdac_bus_parse_capabilities(bus); 914 915 if (skl_acquire_irq(bus, 0) < 0) 916 return -EBUSY; 917 918 pci_set_master(pci); 919 synchronize_irq(bus->irq); 920 921 gcap = snd_hdac_chip_readw(bus, GCAP); 922 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); 923 924 /* allow 64bit DMA address if supported by H/W */ 925 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) { 926 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64)); 927 } else { 928 dma_set_mask(bus->dev, DMA_BIT_MASK(32)); 929 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32)); 930 } 931 932 /* read number of streams from GCAP register */ 933 cp_streams = (gcap >> 8) & 0x0f; 934 pb_streams = (gcap >> 12) & 0x0f; 935 936 if (!pb_streams && !cp_streams) 937 return -EIO; 938 939 bus->num_streams = cp_streams + pb_streams; 940 941 /* initialize streams */ 942 snd_hdac_ext_stream_init_all 943 (bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); 944 start_idx = cp_streams; 945 snd_hdac_ext_stream_init_all 946 (bus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); 947 948 err = snd_hdac_bus_alloc_stream_pages(bus); 949 if (err < 0) 950 return err; 951 952 /* initialize chip */ 953 skl_init_pci(skl); 954 955 return skl_init_chip(bus, true); 956 } 957 958 static int skl_probe(struct pci_dev *pci, 959 const struct pci_device_id *pci_id) 960 { 961 struct skl *skl; 962 struct hdac_bus *bus = NULL; 963 int err; 964 965 /* we use ext core ops, so provide NULL for ops here */ 966 err = skl_create(pci, NULL, &skl); 967 if (err < 0) 968 return err; 969 970 bus = skl_to_bus(skl); 971 972 err = skl_first_init(bus); 973 if (err < 0) 974 goto out_free; 975 976 skl->pci_id = pci->device; 977 978 device_disable_async_suspend(bus->dev); 979 980 skl->nhlt = skl_nhlt_init(bus->dev); 981 982 if (skl->nhlt == NULL) { 983 err = -ENODEV; 984 goto out_free; 985 } 986 987 err = skl_nhlt_create_sysfs(skl); 988 if (err < 0) 989 goto out_nhlt_free; 990 991 skl_nhlt_update_topology_bin(skl); 992 993 pci_set_drvdata(skl->pci, bus); 994 995 /* check if dsp is there */ 996 if (bus->ppcap) { 997 /* create device for dsp clk */ 998 err = skl_clock_device_register(skl); 999 if (err < 0) 1000 goto out_clk_free; 1001 1002 err = skl_find_machine(skl, (void *)pci_id->driver_data); 1003 if (err < 0) 1004 goto out_nhlt_free; 1005 1006 err = skl_init_dsp(skl); 1007 if (err < 0) { 1008 dev_dbg(bus->dev, "error failed to register dsp\n"); 1009 goto out_nhlt_free; 1010 } 1011 skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge; 1012 skl->skl_sst->clock_power_gating = skl_clock_power_gating; 1013 } 1014 if (bus->mlcap) 1015 snd_hdac_ext_bus_get_ml_capabilities(bus); 1016 1017 snd_hdac_bus_stop_chip(bus); 1018 1019 /* create device for soc dmic */ 1020 err = skl_dmic_device_register(skl); 1021 if (err < 0) 1022 goto out_dsp_free; 1023 1024 schedule_work(&skl->probe_work); 1025 1026 return 0; 1027 1028 out_dsp_free: 1029 skl_free_dsp(skl); 1030 out_clk_free: 1031 skl_clock_device_unregister(skl); 1032 out_nhlt_free: 1033 skl_nhlt_free(skl->nhlt); 1034 out_free: 1035 skl_free(bus); 1036 1037 return err; 1038 } 1039 1040 static void skl_shutdown(struct pci_dev *pci) 1041 { 1042 struct hdac_bus *bus = pci_get_drvdata(pci); 1043 struct hdac_stream *s; 1044 struct hdac_ext_stream *stream; 1045 struct skl *skl; 1046 1047 if (!bus) 1048 return; 1049 1050 skl = bus_to_skl(bus); 1051 1052 if (!skl->init_done) 1053 return; 1054 1055 snd_hdac_ext_stop_streams(bus); 1056 list_for_each_entry(s, &bus->stream_list, list) { 1057 stream = stream_to_hdac_ext_stream(s); 1058 snd_hdac_ext_stream_decouple(bus, stream, false); 1059 } 1060 1061 snd_hdac_bus_stop_chip(bus); 1062 } 1063 1064 static void skl_remove(struct pci_dev *pci) 1065 { 1066 struct hdac_bus *bus = pci_get_drvdata(pci); 1067 struct skl *skl = bus_to_skl(bus); 1068 1069 release_firmware(skl->tplg); 1070 1071 pm_runtime_get_noresume(&pci->dev); 1072 1073 /* codec removal, invoke bus_device_remove */ 1074 snd_hdac_ext_bus_device_remove(bus); 1075 1076 skl->debugfs = NULL; 1077 skl_platform_unregister(&pci->dev); 1078 skl_free_dsp(skl); 1079 skl_machine_device_unregister(skl); 1080 skl_dmic_device_unregister(skl); 1081 skl_clock_device_unregister(skl); 1082 skl_nhlt_remove_sysfs(skl); 1083 skl_nhlt_free(skl->nhlt); 1084 skl_free(bus); 1085 dev_set_drvdata(&pci->dev, NULL); 1086 } 1087 1088 /* PCI IDs */ 1089 static const struct pci_device_id skl_ids[] = { 1090 /* Sunrise Point-LP */ 1091 { PCI_DEVICE(0x8086, 0x9d70), 1092 .driver_data = (unsigned long)&snd_soc_acpi_intel_skl_machines}, 1093 /* BXT-P */ 1094 { PCI_DEVICE(0x8086, 0x5a98), 1095 .driver_data = (unsigned long)&snd_soc_acpi_intel_bxt_machines}, 1096 /* KBL */ 1097 { PCI_DEVICE(0x8086, 0x9D71), 1098 .driver_data = (unsigned long)&snd_soc_acpi_intel_kbl_machines}, 1099 /* GLK */ 1100 { PCI_DEVICE(0x8086, 0x3198), 1101 .driver_data = (unsigned long)&snd_soc_acpi_intel_glk_machines}, 1102 /* CNL */ 1103 { PCI_DEVICE(0x8086, 0x9dc8), 1104 .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, 1105 { 0, } 1106 }; 1107 MODULE_DEVICE_TABLE(pci, skl_ids); 1108 1109 /* pci_driver definition */ 1110 static struct pci_driver skl_driver = { 1111 .name = KBUILD_MODNAME, 1112 .id_table = skl_ids, 1113 .probe = skl_probe, 1114 .remove = skl_remove, 1115 .shutdown = skl_shutdown, 1116 .driver = { 1117 .pm = &skl_pm, 1118 }, 1119 }; 1120 module_pci_driver(skl_driver); 1121 1122 MODULE_LICENSE("GPL v2"); 1123 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver"); 1124