xref: /openbmc/linux/sound/soc/intel/skylake/skl.c (revision 51b67a6e)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  skl.c - Implementation of ASoC Intel SKL HD Audio driver
4  *
5  *  Copyright (C) 2014-2015 Intel Corp
6  *  Author: Jeeja KP <jeeja.kp@intel.com>
7  *
8  *  Derived mostly from Intel HDA driver with following copyrights:
9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10  *                     PeiSen Hou <pshou@realtek.com.tw>
11  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
12  *
13  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
14  */
15 
16 #include <linux/module.h>
17 #include <linux/pci.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/platform_device.h>
20 #include <linux/firmware.h>
21 #include <linux/delay.h>
22 #include <sound/pcm.h>
23 #include <sound/soc-acpi.h>
24 #include <sound/soc-acpi-intel-match.h>
25 #include <sound/hda_register.h>
26 #include <sound/hdaudio.h>
27 #include <sound/hda_i915.h>
28 #include <sound/hda_codec.h>
29 #include <sound/intel-nhlt.h>
30 #include "skl.h"
31 #include "skl-sst-dsp.h"
32 #include "skl-sst-ipc.h"
33 
34 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
35 #include "../../../soc/codecs/hdac_hda.h"
36 #endif
37 static int skl_pci_binding;
38 module_param_named(pci_binding, skl_pci_binding, int, 0444);
39 MODULE_PARM_DESC(pci_binding, "PCI binding (0=auto, 1=only legacy, 2=only asoc");
40 
41 /*
42  * initialize the PCI registers
43  */
44 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg,
45 			    unsigned char mask, unsigned char val)
46 {
47 	unsigned char data;
48 
49 	pci_read_config_byte(pci, reg, &data);
50 	data &= ~mask;
51 	data |= (val & mask);
52 	pci_write_config_byte(pci, reg, data);
53 }
54 
55 static void skl_init_pci(struct skl_dev *skl)
56 {
57 	struct hdac_bus *bus = skl_to_bus(skl);
58 
59 	/*
60 	 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
61 	 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
62 	 * Ensuring these bits are 0 clears playback static on some HD Audio
63 	 * codecs.
64 	 * The PCI register TCSEL is defined in the Intel manuals.
65 	 */
66 	dev_dbg(bus->dev, "Clearing TCSEL\n");
67 	skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0);
68 }
69 
70 static void update_pci_dword(struct pci_dev *pci,
71 			unsigned int reg, u32 mask, u32 val)
72 {
73 	u32 data = 0;
74 
75 	pci_read_config_dword(pci, reg, &data);
76 	data &= ~mask;
77 	data |= (val & mask);
78 	pci_write_config_dword(pci, reg, data);
79 }
80 
81 /*
82  * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits
83  *
84  * @dev: device pointer
85  * @enable: enable/disable flag
86  */
87 static void skl_enable_miscbdcge(struct device *dev, bool enable)
88 {
89 	struct pci_dev *pci = to_pci_dev(dev);
90 	u32 val;
91 
92 	val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0;
93 
94 	update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val);
95 }
96 
97 /**
98  * skl_clock_power_gating: Enable/Disable clock and power gating
99  *
100  * @dev: Device pointer
101  * @enable: Enable/Disable flag
102  */
103 static void skl_clock_power_gating(struct device *dev, bool enable)
104 {
105 	struct pci_dev *pci = to_pci_dev(dev);
106 	struct hdac_bus *bus = pci_get_drvdata(pci);
107 	u32 val;
108 
109 	/* Update PDCGE bit of CGCTL register */
110 	val = enable ? AZX_CGCTL_ADSPDCGE : 0;
111 	update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val);
112 
113 	/* Update L1SEN bit of EM2 register */
114 	val = enable ? AZX_REG_VS_EM2_L1SEN : 0;
115 	snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val);
116 
117 	/* Update ADSPPGD bit of PGCTL register */
118 	val = enable ? 0 : AZX_PGCTL_ADSPPGD;
119 	update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val);
120 }
121 
122 /*
123  * While performing reset, controller may not come back properly causing
124  * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset
125  * (init chip) and then again set CGCTL.MISCBDCGE to 1
126  */
127 static int skl_init_chip(struct hdac_bus *bus, bool full_reset)
128 {
129 	struct hdac_ext_link *hlink;
130 	int ret;
131 
132 	skl_enable_miscbdcge(bus->dev, false);
133 	ret = snd_hdac_bus_init_chip(bus, full_reset);
134 
135 	/* Reset stream-to-link mapping */
136 	list_for_each_entry(hlink, &bus->hlink_list, list)
137 		writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
138 
139 	skl_enable_miscbdcge(bus->dev, true);
140 
141 	return ret;
142 }
143 
144 void skl_update_d0i3c(struct device *dev, bool enable)
145 {
146 	struct pci_dev *pci = to_pci_dev(dev);
147 	struct hdac_bus *bus = pci_get_drvdata(pci);
148 	u8 reg;
149 	int timeout = 50;
150 
151 	reg = snd_hdac_chip_readb(bus, VS_D0I3C);
152 	/* Do not write to D0I3C until command in progress bit is cleared */
153 	while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {
154 		udelay(10);
155 		reg = snd_hdac_chip_readb(bus, VS_D0I3C);
156 	}
157 
158 	/* Highly unlikely. But if it happens, flag error explicitly */
159 	if (!timeout) {
160 		dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n");
161 		return;
162 	}
163 
164 	if (enable)
165 		reg = reg | AZX_REG_VS_D0I3C_I3;
166 	else
167 		reg = reg & (~AZX_REG_VS_D0I3C_I3);
168 
169 	snd_hdac_chip_writeb(bus, VS_D0I3C, reg);
170 
171 	timeout = 50;
172 	/* Wait for cmd in progress to be cleared before exiting the function */
173 	reg = snd_hdac_chip_readb(bus, VS_D0I3C);
174 	while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {
175 		udelay(10);
176 		reg = snd_hdac_chip_readb(bus, VS_D0I3C);
177 	}
178 
179 	/* Highly unlikely. But if it happens, flag error explicitly */
180 	if (!timeout) {
181 		dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n");
182 		return;
183 	}
184 
185 	dev_dbg(bus->dev, "D0I3C register = 0x%x\n",
186 			snd_hdac_chip_readb(bus, VS_D0I3C));
187 }
188 
189 /**
190  * skl_dum_set - set DUM bit in EM2 register
191  * @bus: HD-audio core bus
192  *
193  * Addresses incorrect position reporting for capture streams.
194  * Used on device power up.
195  */
196 static void skl_dum_set(struct hdac_bus *bus)
197 {
198 	/* For the DUM bit to be set, CRST needs to be out of reset state */
199 	if (!(snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)) {
200 		skl_enable_miscbdcge(bus->dev, false);
201 		snd_hdac_bus_exit_link_reset(bus);
202 		skl_enable_miscbdcge(bus->dev, true);
203 	}
204 
205 	snd_hdac_chip_updatel(bus, VS_EM2, AZX_VS_EM2_DUM, AZX_VS_EM2_DUM);
206 }
207 
208 /* called from IRQ */
209 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)
210 {
211 	snd_pcm_period_elapsed(hstr->substream);
212 }
213 
214 static irqreturn_t skl_interrupt(int irq, void *dev_id)
215 {
216 	struct hdac_bus *bus = dev_id;
217 	u32 status;
218 
219 	if (!pm_runtime_active(bus->dev))
220 		return IRQ_NONE;
221 
222 	spin_lock(&bus->reg_lock);
223 
224 	status = snd_hdac_chip_readl(bus, INTSTS);
225 	if (status == 0 || status == 0xffffffff) {
226 		spin_unlock(&bus->reg_lock);
227 		return IRQ_NONE;
228 	}
229 
230 	/* clear rirb int */
231 	status = snd_hdac_chip_readb(bus, RIRBSTS);
232 	if (status & RIRB_INT_MASK) {
233 		if (status & RIRB_INT_RESPONSE)
234 			snd_hdac_bus_update_rirb(bus);
235 		snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
236 	}
237 
238 	spin_unlock(&bus->reg_lock);
239 
240 	return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
241 }
242 
243 static irqreturn_t skl_threaded_handler(int irq, void *dev_id)
244 {
245 	struct hdac_bus *bus = dev_id;
246 	u32 status;
247 
248 	status = snd_hdac_chip_readl(bus, INTSTS);
249 
250 	snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update);
251 
252 	return IRQ_HANDLED;
253 }
254 
255 static int skl_acquire_irq(struct hdac_bus *bus, int do_disconnect)
256 {
257 	struct skl_dev *skl = bus_to_skl(bus);
258 	int ret;
259 
260 	ret = request_threaded_irq(skl->pci->irq, skl_interrupt,
261 			skl_threaded_handler,
262 			IRQF_SHARED,
263 			KBUILD_MODNAME, bus);
264 	if (ret) {
265 		dev_err(bus->dev,
266 			"unable to grab IRQ %d, disabling device\n",
267 			skl->pci->irq);
268 		return ret;
269 	}
270 
271 	bus->irq = skl->pci->irq;
272 	pci_intx(skl->pci, 1);
273 
274 	return 0;
275 }
276 
277 static int skl_suspend_late(struct device *dev)
278 {
279 	struct pci_dev *pci = to_pci_dev(dev);
280 	struct hdac_bus *bus = pci_get_drvdata(pci);
281 	struct skl_dev *skl = bus_to_skl(bus);
282 
283 	return skl_suspend_late_dsp(skl);
284 }
285 
286 #ifdef CONFIG_PM
287 static int _skl_suspend(struct hdac_bus *bus)
288 {
289 	struct skl_dev *skl = bus_to_skl(bus);
290 	struct pci_dev *pci = to_pci_dev(bus->dev);
291 	int ret;
292 
293 	snd_hdac_ext_bus_link_power_down_all(bus);
294 
295 	ret = skl_suspend_dsp(skl);
296 	if (ret < 0)
297 		return ret;
298 
299 	snd_hdac_bus_stop_chip(bus);
300 	update_pci_dword(pci, AZX_PCIREG_PGCTL,
301 		AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK);
302 	skl_enable_miscbdcge(bus->dev, false);
303 	snd_hdac_bus_enter_link_reset(bus);
304 	skl_enable_miscbdcge(bus->dev, true);
305 	skl_cleanup_resources(skl);
306 
307 	return 0;
308 }
309 
310 static int _skl_resume(struct hdac_bus *bus)
311 {
312 	struct skl_dev *skl = bus_to_skl(bus);
313 
314 	skl_init_pci(skl);
315 	skl_dum_set(bus);
316 	skl_init_chip(bus, true);
317 
318 	return skl_resume_dsp(skl);
319 }
320 #endif
321 
322 #ifdef CONFIG_PM_SLEEP
323 /*
324  * power management
325  */
326 static int skl_suspend(struct device *dev)
327 {
328 	struct pci_dev *pci = to_pci_dev(dev);
329 	struct hdac_bus *bus = pci_get_drvdata(pci);
330 	struct skl_dev *skl  = bus_to_skl(bus);
331 	int ret;
332 
333 	/*
334 	 * Do not suspend if streams which are marked ignore suspend are
335 	 * running, we need to save the state for these and continue
336 	 */
337 	if (skl->supend_active) {
338 		/* turn off the links and stop the CORB/RIRB DMA if it is On */
339 		snd_hdac_ext_bus_link_power_down_all(bus);
340 
341 		if (bus->cmd_dma_state)
342 			snd_hdac_bus_stop_cmd_io(bus);
343 
344 		enable_irq_wake(bus->irq);
345 		pci_save_state(pci);
346 	} else {
347 		ret = _skl_suspend(bus);
348 		if (ret < 0)
349 			return ret;
350 		skl->fw_loaded = false;
351 	}
352 
353 	return 0;
354 }
355 
356 static int skl_resume(struct device *dev)
357 {
358 	struct pci_dev *pci = to_pci_dev(dev);
359 	struct hdac_bus *bus = pci_get_drvdata(pci);
360 	struct skl_dev *skl  = bus_to_skl(bus);
361 	struct hdac_ext_link *hlink = NULL;
362 	int ret;
363 
364 	/*
365 	 * resume only when we are not in suspend active, otherwise need to
366 	 * restore the device
367 	 */
368 	if (skl->supend_active) {
369 		pci_restore_state(pci);
370 		snd_hdac_ext_bus_link_power_up_all(bus);
371 		disable_irq_wake(bus->irq);
372 		/*
373 		 * turn On the links which are On before active suspend
374 		 * and start the CORB/RIRB DMA if On before
375 		 * active suspend.
376 		 */
377 		list_for_each_entry(hlink, &bus->hlink_list, list) {
378 			if (hlink->ref_count)
379 				snd_hdac_ext_bus_link_power_up(hlink);
380 		}
381 
382 		ret = 0;
383 		if (bus->cmd_dma_state)
384 			snd_hdac_bus_init_cmd_io(bus);
385 	} else {
386 		ret = _skl_resume(bus);
387 
388 		/* turn off the links which are off before suspend */
389 		list_for_each_entry(hlink, &bus->hlink_list, list) {
390 			if (!hlink->ref_count)
391 				snd_hdac_ext_bus_link_power_down(hlink);
392 		}
393 
394 		if (!bus->cmd_dma_state)
395 			snd_hdac_bus_stop_cmd_io(bus);
396 	}
397 
398 	return ret;
399 }
400 #endif /* CONFIG_PM_SLEEP */
401 
402 #ifdef CONFIG_PM
403 static int skl_runtime_suspend(struct device *dev)
404 {
405 	struct pci_dev *pci = to_pci_dev(dev);
406 	struct hdac_bus *bus = pci_get_drvdata(pci);
407 
408 	dev_dbg(bus->dev, "in %s\n", __func__);
409 
410 	return _skl_suspend(bus);
411 }
412 
413 static int skl_runtime_resume(struct device *dev)
414 {
415 	struct pci_dev *pci = to_pci_dev(dev);
416 	struct hdac_bus *bus = pci_get_drvdata(pci);
417 
418 	dev_dbg(bus->dev, "in %s\n", __func__);
419 
420 	return _skl_resume(bus);
421 }
422 #endif /* CONFIG_PM */
423 
424 static const struct dev_pm_ops skl_pm = {
425 	SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume)
426 	SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL)
427 	.suspend_late = skl_suspend_late,
428 };
429 
430 /*
431  * destructor
432  */
433 static int skl_free(struct hdac_bus *bus)
434 {
435 	struct skl_dev *skl  = bus_to_skl(bus);
436 
437 	skl->init_done = 0; /* to be sure */
438 
439 	snd_hdac_ext_stop_streams(bus);
440 
441 	if (bus->irq >= 0)
442 		free_irq(bus->irq, (void *)bus);
443 	snd_hdac_bus_free_stream_pages(bus);
444 	snd_hdac_stream_free_all(bus);
445 	snd_hdac_link_free_all(bus);
446 
447 	if (bus->remap_addr)
448 		iounmap(bus->remap_addr);
449 
450 	pci_release_regions(skl->pci);
451 	pci_disable_device(skl->pci);
452 
453 	snd_hdac_ext_bus_exit(bus);
454 
455 	if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
456 		snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
457 		snd_hdac_i915_exit(bus);
458 	}
459 
460 	return 0;
461 }
462 
463 /*
464  * For each ssp there are 3 clocks (mclk/sclk/sclkfs).
465  * e.g. for ssp0, clocks will be named as
466  *      "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs"
467  * So for skl+, there are 6 ssps, so 18 clocks will be created.
468  */
469 static struct skl_ssp_clk skl_ssp_clks[] = {
470 	{.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"},
471 	{.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"},
472 	{.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"},
473 	{.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"},
474 	{.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"},
475 						{.name = "ssp2_sclkfs"},
476 	{.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"},
477 						{.name = "ssp5_sclkfs"},
478 };
479 
480 static struct snd_soc_acpi_mach *skl_find_hda_machine(struct skl_dev *skl,
481 					struct snd_soc_acpi_mach *machines)
482 {
483 	struct hdac_bus *bus = skl_to_bus(skl);
484 	struct snd_soc_acpi_mach *mach;
485 
486 	/* check if we have any codecs detected on bus */
487 	if (bus->codec_mask == 0)
488 		return NULL;
489 
490 	/* point to common table */
491 	mach = snd_soc_acpi_intel_hda_machines;
492 
493 	/* all entries in the machine table use the same firmware */
494 	mach->fw_filename = machines->fw_filename;
495 
496 	return mach;
497 }
498 
499 static int skl_find_machine(struct skl_dev *skl, void *driver_data)
500 {
501 	struct hdac_bus *bus = skl_to_bus(skl);
502 	struct snd_soc_acpi_mach *mach = driver_data;
503 	struct skl_machine_pdata *pdata;
504 
505 	mach = snd_soc_acpi_find_machine(mach);
506 	if (!mach) {
507 		dev_dbg(bus->dev, "No matching I2S machine driver found\n");
508 		mach = skl_find_hda_machine(skl, driver_data);
509 		if (!mach) {
510 			dev_err(bus->dev, "No matching machine driver found\n");
511 			return -ENODEV;
512 		}
513 	}
514 
515 	skl->mach = mach;
516 	skl->fw_name = mach->fw_filename;
517 	pdata = mach->pdata;
518 
519 	if (pdata) {
520 		skl->use_tplg_pcm = pdata->use_tplg_pcm;
521 		mach->mach_params.dmic_num =
522 			intel_nhlt_get_dmic_geo(&skl->pci->dev,
523 						skl->nhlt);
524 	}
525 
526 	return 0;
527 }
528 
529 static int skl_machine_device_register(struct skl_dev *skl)
530 {
531 	struct snd_soc_acpi_mach *mach = skl->mach;
532 	struct hdac_bus *bus = skl_to_bus(skl);
533 	struct platform_device *pdev;
534 	int ret;
535 
536 	pdev = platform_device_alloc(mach->drv_name, -1);
537 	if (pdev == NULL) {
538 		dev_err(bus->dev, "platform device alloc failed\n");
539 		return -EIO;
540 	}
541 
542 	mach->mach_params.platform = dev_name(bus->dev);
543 	mach->mach_params.codec_mask = bus->codec_mask;
544 
545 	ret = platform_device_add_data(pdev, (const void *)mach, sizeof(*mach));
546 	if (ret) {
547 		dev_err(bus->dev, "failed to add machine device platform data\n");
548 		platform_device_put(pdev);
549 		return ret;
550 	}
551 
552 	ret = platform_device_add(pdev);
553 	if (ret) {
554 		dev_err(bus->dev, "failed to add machine device\n");
555 		platform_device_put(pdev);
556 		return -EIO;
557 	}
558 
559 
560 	skl->i2s_dev = pdev;
561 
562 	return 0;
563 }
564 
565 static void skl_machine_device_unregister(struct skl_dev *skl)
566 {
567 	if (skl->i2s_dev)
568 		platform_device_unregister(skl->i2s_dev);
569 }
570 
571 static int skl_dmic_device_register(struct skl_dev *skl)
572 {
573 	struct hdac_bus *bus = skl_to_bus(skl);
574 	struct platform_device *pdev;
575 	int ret;
576 
577 	/* SKL has one dmic port, so allocate dmic device for this */
578 	pdev = platform_device_alloc("dmic-codec", -1);
579 	if (!pdev) {
580 		dev_err(bus->dev, "failed to allocate dmic device\n");
581 		return -ENOMEM;
582 	}
583 
584 	ret = platform_device_add(pdev);
585 	if (ret) {
586 		dev_err(bus->dev, "failed to add dmic device: %d\n", ret);
587 		platform_device_put(pdev);
588 		return ret;
589 	}
590 	skl->dmic_dev = pdev;
591 
592 	return 0;
593 }
594 
595 static void skl_dmic_device_unregister(struct skl_dev *skl)
596 {
597 	if (skl->dmic_dev)
598 		platform_device_unregister(skl->dmic_dev);
599 }
600 
601 static struct skl_clk_parent_src skl_clk_src[] = {
602 	{ .clk_id = SKL_XTAL, .name = "xtal" },
603 	{ .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 },
604 	{ .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 },
605 };
606 
607 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id)
608 {
609 	unsigned int i;
610 
611 	for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) {
612 		if (skl_clk_src[i].clk_id == clk_id)
613 			return &skl_clk_src[i];
614 	}
615 
616 	return NULL;
617 }
618 
619 static void init_skl_xtal_rate(int pci_id)
620 {
621 	switch (pci_id) {
622 	case 0x9d70:
623 	case 0x9d71:
624 		skl_clk_src[0].rate = 24000000;
625 		return;
626 
627 	default:
628 		skl_clk_src[0].rate = 19200000;
629 		return;
630 	}
631 }
632 
633 static int skl_clock_device_register(struct skl_dev *skl)
634 {
635 	struct platform_device_info pdevinfo = {NULL};
636 	struct skl_clk_pdata *clk_pdata;
637 
638 	clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata),
639 							GFP_KERNEL);
640 	if (!clk_pdata)
641 		return -ENOMEM;
642 
643 	init_skl_xtal_rate(skl->pci->device);
644 
645 	clk_pdata->parent_clks = skl_clk_src;
646 	clk_pdata->ssp_clks = skl_ssp_clks;
647 	clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks);
648 
649 	/* Query NHLT to fill the rates and parent */
650 	skl_get_clks(skl, clk_pdata->ssp_clks);
651 	clk_pdata->pvt_data = skl;
652 
653 	/* Register Platform device */
654 	pdevinfo.parent = &skl->pci->dev;
655 	pdevinfo.id = -1;
656 	pdevinfo.name = "skl-ssp-clk";
657 	pdevinfo.data = clk_pdata;
658 	pdevinfo.size_data = sizeof(*clk_pdata);
659 	skl->clk_dev = platform_device_register_full(&pdevinfo);
660 	return PTR_ERR_OR_ZERO(skl->clk_dev);
661 }
662 
663 static void skl_clock_device_unregister(struct skl_dev *skl)
664 {
665 	if (skl->clk_dev)
666 		platform_device_unregister(skl->clk_dev);
667 }
668 
669 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
670 
671 #define IDISP_INTEL_VENDOR_ID	0x80860000
672 
673 /*
674  * load the legacy codec driver
675  */
676 static void load_codec_module(struct hda_codec *codec)
677 {
678 #ifdef MODULE
679 	char modalias[MODULE_NAME_LEN];
680 	const char *mod = NULL;
681 
682 	snd_hdac_codec_modalias(&codec->core, modalias, sizeof(modalias));
683 	mod = modalias;
684 	dev_dbg(&codec->core.dev, "loading %s codec module\n", mod);
685 	request_module(mod);
686 #endif
687 }
688 
689 #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */
690 
691 /*
692  * Probe the given codec address
693  */
694 static int probe_codec(struct hdac_bus *bus, int addr)
695 {
696 	unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
697 		(AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
698 	unsigned int res = -1;
699 	struct skl_dev *skl = bus_to_skl(bus);
700 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
701 	struct hdac_hda_priv *hda_codec;
702 	int err;
703 #endif
704 	struct hdac_device *hdev;
705 
706 	mutex_lock(&bus->cmd_mutex);
707 	snd_hdac_bus_send_cmd(bus, cmd);
708 	snd_hdac_bus_get_response(bus, addr, &res);
709 	mutex_unlock(&bus->cmd_mutex);
710 	if (res == -1)
711 		return -EIO;
712 	dev_dbg(bus->dev, "codec #%d probed OK: %x\n", addr, res);
713 
714 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
715 	hda_codec = devm_kzalloc(&skl->pci->dev, sizeof(*hda_codec),
716 				 GFP_KERNEL);
717 	if (!hda_codec)
718 		return -ENOMEM;
719 
720 	hda_codec->codec.bus = skl_to_hbus(skl);
721 	hdev = &hda_codec->codec.core;
722 
723 	err = snd_hdac_ext_bus_device_init(bus, addr, hdev);
724 	if (err < 0)
725 		return err;
726 
727 	/* use legacy bus only for HDA codecs, idisp uses ext bus */
728 	if ((res & 0xFFFF0000) != IDISP_INTEL_VENDOR_ID) {
729 		hdev->type = HDA_DEV_LEGACY;
730 		load_codec_module(&hda_codec->codec);
731 	}
732 	return 0;
733 #else
734 	hdev = devm_kzalloc(&skl->pci->dev, sizeof(*hdev), GFP_KERNEL);
735 	if (!hdev)
736 		return -ENOMEM;
737 
738 	return snd_hdac_ext_bus_device_init(bus, addr, hdev);
739 #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */
740 }
741 
742 /* Codec initialization */
743 static void skl_codec_create(struct hdac_bus *bus)
744 {
745 	int c, max_slots;
746 
747 	max_slots = HDA_MAX_CODECS;
748 
749 	/* First try to probe all given codec slots */
750 	for (c = 0; c < max_slots; c++) {
751 		if ((bus->codec_mask & (1 << c))) {
752 			if (probe_codec(bus, c) < 0) {
753 				/*
754 				 * Some BIOSen give you wrong codec addresses
755 				 * that don't exist
756 				 */
757 				dev_warn(bus->dev,
758 					 "Codec #%d probe error; disabling it...\n", c);
759 				bus->codec_mask &= ~(1 << c);
760 				/*
761 				 * More badly, accessing to a non-existing
762 				 * codec often screws up the controller bus,
763 				 * and disturbs the further communications.
764 				 * Thus if an error occurs during probing,
765 				 * better to reset the controller bus to get
766 				 * back to the sanity state.
767 				 */
768 				snd_hdac_bus_stop_chip(bus);
769 				skl_init_chip(bus, true);
770 			}
771 		}
772 	}
773 }
774 
775 static const struct hdac_bus_ops bus_core_ops = {
776 	.command = snd_hdac_bus_send_cmd,
777 	.get_response = snd_hdac_bus_get_response,
778 };
779 
780 static int skl_i915_init(struct hdac_bus *bus)
781 {
782 	int err;
783 
784 	/*
785 	 * The HDMI codec is in GPU so we need to ensure that it is powered
786 	 * up and ready for probe
787 	 */
788 	err = snd_hdac_i915_init(bus);
789 	if (err < 0)
790 		return err;
791 
792 	snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true);
793 
794 	return 0;
795 }
796 
797 static void skl_probe_work(struct work_struct *work)
798 {
799 	struct skl_dev *skl = container_of(work, struct skl_dev, probe_work);
800 	struct hdac_bus *bus = skl_to_bus(skl);
801 	struct hdac_ext_link *hlink = NULL;
802 	int err;
803 
804 	if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
805 		err = skl_i915_init(bus);
806 		if (err < 0)
807 			return;
808 	}
809 
810 	err = skl_init_chip(bus, true);
811 	if (err < 0) {
812 		dev_err(bus->dev, "Init chip failed with err: %d\n", err);
813 		goto out_err;
814 	}
815 
816 	/* codec detection */
817 	if (!bus->codec_mask)
818 		dev_info(bus->dev, "no hda codecs found!\n");
819 
820 	/* create codec instances */
821 	skl_codec_create(bus);
822 
823 	/* register platform dai and controls */
824 	err = skl_platform_register(bus->dev);
825 	if (err < 0) {
826 		dev_err(bus->dev, "platform register failed: %d\n", err);
827 		goto out_err;
828 	}
829 
830 	err = skl_machine_device_register(skl);
831 	if (err < 0) {
832 		dev_err(bus->dev, "machine register failed: %d\n", err);
833 		goto out_err;
834 	}
835 
836 	/*
837 	 * we are done probing so decrement link counts
838 	 */
839 	list_for_each_entry(hlink, &bus->hlink_list, list)
840 		snd_hdac_ext_bus_link_put(bus, hlink);
841 
842 	if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
843 		snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
844 
845 	/* configure PM */
846 	pm_runtime_put_noidle(bus->dev);
847 	pm_runtime_allow(bus->dev);
848 	skl->init_done = 1;
849 
850 	return;
851 
852 out_err:
853 	if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
854 		snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
855 }
856 
857 /*
858  * constructor
859  */
860 static int skl_create(struct pci_dev *pci,
861 		      struct skl_dev **rskl)
862 {
863 	struct hdac_ext_bus_ops *ext_ops = NULL;
864 	struct skl_dev *skl;
865 	struct hdac_bus *bus;
866 	struct hda_bus *hbus;
867 	int err;
868 
869 	*rskl = NULL;
870 
871 	err = pci_enable_device(pci);
872 	if (err < 0)
873 		return err;
874 
875 	skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL);
876 	if (!skl) {
877 		pci_disable_device(pci);
878 		return -ENOMEM;
879 	}
880 
881 	hbus = skl_to_hbus(skl);
882 	bus = skl_to_bus(skl);
883 
884 	INIT_LIST_HEAD(&skl->ppl_list);
885 	INIT_LIST_HEAD(&skl->bind_list);
886 
887 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
888 	ext_ops = snd_soc_hdac_hda_get_ops();
889 #endif
890 	snd_hdac_ext_bus_init(bus, &pci->dev, &bus_core_ops, ext_ops);
891 	bus->use_posbuf = 1;
892 	skl->pci = pci;
893 	INIT_WORK(&skl->probe_work, skl_probe_work);
894 	bus->bdl_pos_adj = 0;
895 
896 	mutex_init(&hbus->prepare_mutex);
897 	hbus->pci = pci;
898 	hbus->mixer_assigned = -1;
899 	hbus->modelname = "sklbus";
900 
901 	*rskl = skl;
902 
903 	return 0;
904 }
905 
906 static int skl_first_init(struct hdac_bus *bus)
907 {
908 	struct skl_dev *skl = bus_to_skl(bus);
909 	struct pci_dev *pci = skl->pci;
910 	int err;
911 	unsigned short gcap;
912 	int cp_streams, pb_streams, start_idx;
913 
914 	err = pci_request_regions(pci, "Skylake HD audio");
915 	if (err < 0)
916 		return err;
917 
918 	bus->addr = pci_resource_start(pci, 0);
919 	bus->remap_addr = pci_ioremap_bar(pci, 0);
920 	if (bus->remap_addr == NULL) {
921 		dev_err(bus->dev, "ioremap error\n");
922 		return -ENXIO;
923 	}
924 
925 	snd_hdac_bus_reset_link(bus, true);
926 
927 	snd_hdac_bus_parse_capabilities(bus);
928 
929 	/* check if PPCAP exists */
930 	if (!bus->ppcap) {
931 		dev_err(bus->dev, "bus ppcap not set, HDaudio or DSP not present?\n");
932 		return -ENODEV;
933 	}
934 
935 	if (skl_acquire_irq(bus, 0) < 0)
936 		return -EBUSY;
937 
938 	pci_set_master(pci);
939 	synchronize_irq(bus->irq);
940 
941 	gcap = snd_hdac_chip_readw(bus, GCAP);
942 	dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap);
943 
944 	/* read number of streams from GCAP register */
945 	cp_streams = (gcap >> 8) & 0x0f;
946 	pb_streams = (gcap >> 12) & 0x0f;
947 
948 	if (!pb_streams && !cp_streams) {
949 		dev_err(bus->dev, "no streams found in GCAP definitions?\n");
950 		return -EIO;
951 	}
952 
953 	bus->num_streams = cp_streams + pb_streams;
954 
955 	/* allow 64bit DMA address if supported by H/W */
956 	if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) {
957 		dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64));
958 	} else {
959 		dma_set_mask(bus->dev, DMA_BIT_MASK(32));
960 		dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32));
961 	}
962 
963 	/* initialize streams */
964 	snd_hdac_ext_stream_init_all
965 		(bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE);
966 	start_idx = cp_streams;
967 	snd_hdac_ext_stream_init_all
968 		(bus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK);
969 
970 	err = snd_hdac_bus_alloc_stream_pages(bus);
971 	if (err < 0)
972 		return err;
973 
974 	/* initialize chip */
975 	skl_init_pci(skl);
976 	skl_dum_set(bus);
977 
978 	return skl_init_chip(bus, true);
979 }
980 
981 static int skl_probe(struct pci_dev *pci,
982 		     const struct pci_device_id *pci_id)
983 {
984 	struct skl_dev *skl;
985 	struct hdac_bus *bus = NULL;
986 	int err;
987 
988 	switch (skl_pci_binding) {
989 	case SND_SKL_PCI_BIND_AUTO:
990 		/*
991 		 * detect DSP by checking class/subclass/prog-id information
992 		 * class=04 subclass 03 prog-if 00: no DSP, use legacy driver
993 		 * class=04 subclass 01 prog-if 00: DSP is present
994 		 *   (and may be required e.g. for DMIC or SSP support)
995 		 * class=04 subclass 03 prog-if 80: use DSP or legacy mode
996 		 */
997 		if (pci->class == 0x040300) {
998 			dev_info(&pci->dev, "The DSP is not enabled on this platform, aborting probe\n");
999 			return -ENODEV;
1000 		}
1001 		if (pci->class != 0x040100 && pci->class != 0x040380) {
1002 			dev_err(&pci->dev, "Unknown PCI class/subclass/prog-if information (0x%06x) found, aborting probe\n", pci->class);
1003 			return -ENODEV;
1004 		}
1005 		dev_info(&pci->dev, "DSP detected with PCI class/subclass/prog-if info 0x%06x\n", pci->class);
1006 		break;
1007 	case SND_SKL_PCI_BIND_LEGACY:
1008 		dev_info(&pci->dev, "Module parameter forced binding with HDaudio legacy, aborting probe\n");
1009 		return -ENODEV;
1010 	case SND_SKL_PCI_BIND_ASOC:
1011 		dev_info(&pci->dev, "Module parameter forced binding with SKL driver, bypassed detection logic\n");
1012 		break;
1013 	default:
1014 		dev_err(&pci->dev, "invalid value for skl_pci_binding module parameter, ignored\n");
1015 		break;
1016 	}
1017 
1018 	/* we use ext core ops, so provide NULL for ops here */
1019 	err = skl_create(pci, &skl);
1020 	if (err < 0)
1021 		return err;
1022 
1023 	bus = skl_to_bus(skl);
1024 
1025 	err = skl_first_init(bus);
1026 	if (err < 0) {
1027 		dev_err(bus->dev, "skl_first_init failed with err: %d\n", err);
1028 		goto out_free;
1029 	}
1030 
1031 	skl->pci_id = pci->device;
1032 
1033 	device_disable_async_suspend(bus->dev);
1034 
1035 	skl->nhlt = intel_nhlt_init(bus->dev);
1036 
1037 	if (skl->nhlt == NULL) {
1038 #if !IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
1039 		dev_err(bus->dev, "no nhlt info found\n");
1040 		err = -ENODEV;
1041 		goto out_free;
1042 #else
1043 		dev_warn(bus->dev, "no nhlt info found, continuing to try to enable HDaudio codec\n");
1044 #endif
1045 	} else {
1046 
1047 		err = skl_nhlt_create_sysfs(skl);
1048 		if (err < 0) {
1049 			dev_err(bus->dev, "skl_nhlt_create_sysfs failed with err: %d\n", err);
1050 			goto out_nhlt_free;
1051 		}
1052 
1053 		skl_nhlt_update_topology_bin(skl);
1054 
1055 		/* create device for dsp clk */
1056 		err = skl_clock_device_register(skl);
1057 		if (err < 0) {
1058 			dev_err(bus->dev, "skl_clock_device_register failed with err: %d\n", err);
1059 			goto out_clk_free;
1060 		}
1061 	}
1062 
1063 	pci_set_drvdata(skl->pci, bus);
1064 
1065 
1066 	err = skl_find_machine(skl, (void *)pci_id->driver_data);
1067 	if (err < 0) {
1068 		dev_err(bus->dev, "skl_find_machine failed with err: %d\n", err);
1069 		goto out_nhlt_free;
1070 	}
1071 
1072 	err = skl_init_dsp(skl);
1073 	if (err < 0) {
1074 		dev_dbg(bus->dev, "error failed to register dsp\n");
1075 		goto out_nhlt_free;
1076 	}
1077 	skl->enable_miscbdcge = skl_enable_miscbdcge;
1078 	skl->clock_power_gating = skl_clock_power_gating;
1079 
1080 	if (bus->mlcap)
1081 		snd_hdac_ext_bus_get_ml_capabilities(bus);
1082 
1083 	snd_hdac_bus_stop_chip(bus);
1084 
1085 	/* create device for soc dmic */
1086 	err = skl_dmic_device_register(skl);
1087 	if (err < 0) {
1088 		dev_err(bus->dev, "skl_dmic_device_register failed with err: %d\n", err);
1089 		goto out_dsp_free;
1090 	}
1091 
1092 	schedule_work(&skl->probe_work);
1093 
1094 	return 0;
1095 
1096 out_dsp_free:
1097 	skl_free_dsp(skl);
1098 out_clk_free:
1099 	skl_clock_device_unregister(skl);
1100 out_nhlt_free:
1101 	intel_nhlt_free(skl->nhlt);
1102 out_free:
1103 	skl_free(bus);
1104 
1105 	return err;
1106 }
1107 
1108 static void skl_shutdown(struct pci_dev *pci)
1109 {
1110 	struct hdac_bus *bus = pci_get_drvdata(pci);
1111 	struct hdac_stream *s;
1112 	struct hdac_ext_stream *stream;
1113 	struct skl_dev *skl;
1114 
1115 	if (!bus)
1116 		return;
1117 
1118 	skl = bus_to_skl(bus);
1119 
1120 	if (!skl->init_done)
1121 		return;
1122 
1123 	snd_hdac_ext_stop_streams(bus);
1124 	list_for_each_entry(s, &bus->stream_list, list) {
1125 		stream = stream_to_hdac_ext_stream(s);
1126 		snd_hdac_ext_stream_decouple(bus, stream, false);
1127 	}
1128 
1129 	snd_hdac_bus_stop_chip(bus);
1130 }
1131 
1132 static void skl_remove(struct pci_dev *pci)
1133 {
1134 	struct hdac_bus *bus = pci_get_drvdata(pci);
1135 	struct skl_dev *skl = bus_to_skl(bus);
1136 
1137 	cancel_work_sync(&skl->probe_work);
1138 
1139 	pm_runtime_get_noresume(&pci->dev);
1140 
1141 	/* codec removal, invoke bus_device_remove */
1142 	snd_hdac_ext_bus_device_remove(bus);
1143 
1144 	skl_platform_unregister(&pci->dev);
1145 	skl_free_dsp(skl);
1146 	skl_machine_device_unregister(skl);
1147 	skl_dmic_device_unregister(skl);
1148 	skl_clock_device_unregister(skl);
1149 	skl_nhlt_remove_sysfs(skl);
1150 	intel_nhlt_free(skl->nhlt);
1151 	skl_free(bus);
1152 	dev_set_drvdata(&pci->dev, NULL);
1153 }
1154 
1155 /* PCI IDs */
1156 static const struct pci_device_id skl_ids[] = {
1157 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKL)
1158 	/* Sunrise Point-LP */
1159 	{ PCI_DEVICE(0x8086, 0x9d70),
1160 		.driver_data = (unsigned long)&snd_soc_acpi_intel_skl_machines},
1161 #endif
1162 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_APL)
1163 	/* BXT-P */
1164 	{ PCI_DEVICE(0x8086, 0x5a98),
1165 		.driver_data = (unsigned long)&snd_soc_acpi_intel_bxt_machines},
1166 #endif
1167 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_KBL)
1168 	/* KBL */
1169 	{ PCI_DEVICE(0x8086, 0x9D71),
1170 		.driver_data = (unsigned long)&snd_soc_acpi_intel_kbl_machines},
1171 #endif
1172 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_GLK)
1173 	/* GLK */
1174 	{ PCI_DEVICE(0x8086, 0x3198),
1175 		.driver_data = (unsigned long)&snd_soc_acpi_intel_glk_machines},
1176 #endif
1177 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CNL)
1178 	/* CNL */
1179 	{ PCI_DEVICE(0x8086, 0x9dc8),
1180 		.driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
1181 #endif
1182 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CFL)
1183 	/* CFL */
1184 	{ PCI_DEVICE(0x8086, 0xa348),
1185 		.driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
1186 #endif
1187 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_LP)
1188 	/* CML-LP */
1189 	{ PCI_DEVICE(0x8086, 0x02c8),
1190 		.driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
1191 #endif
1192 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_H)
1193 	/* CML-H */
1194 	{ PCI_DEVICE(0x8086, 0x06c8),
1195 		.driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
1196 #endif
1197 	{ 0, }
1198 };
1199 MODULE_DEVICE_TABLE(pci, skl_ids);
1200 
1201 /* pci_driver definition */
1202 static struct pci_driver skl_driver = {
1203 	.name = KBUILD_MODNAME,
1204 	.id_table = skl_ids,
1205 	.probe = skl_probe,
1206 	.remove = skl_remove,
1207 	.shutdown = skl_shutdown,
1208 	.driver = {
1209 		.pm = &skl_pm,
1210 	},
1211 };
1212 module_pci_driver(skl_driver);
1213 
1214 MODULE_LICENSE("GPL v2");
1215 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver");
1216