1 /* 2 * skl.c - Implementation of ASoC Intel SKL HD Audio driver 3 * 4 * Copyright (C) 2014-2015 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * 7 * Derived mostly from Intel HDA driver with following copyrights: 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; version 2 of the License. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 22 */ 23 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/platform_device.h> 28 #include <linux/firmware.h> 29 #include <linux/delay.h> 30 #include <sound/pcm.h> 31 #include <sound/soc-acpi.h> 32 #include <sound/hda_register.h> 33 #include <sound/hdaudio.h> 34 #include <sound/hda_i915.h> 35 #include "skl.h" 36 #include "skl-sst-dsp.h" 37 #include "skl-sst-ipc.h" 38 39 static struct skl_machine_pdata skl_dmic_data; 40 41 /* 42 * initialize the PCI registers 43 */ 44 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, 45 unsigned char mask, unsigned char val) 46 { 47 unsigned char data; 48 49 pci_read_config_byte(pci, reg, &data); 50 data &= ~mask; 51 data |= (val & mask); 52 pci_write_config_byte(pci, reg, data); 53 } 54 55 static void skl_init_pci(struct skl *skl) 56 { 57 struct hdac_ext_bus *ebus = &skl->ebus; 58 59 /* 60 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 61 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 62 * Ensuring these bits are 0 clears playback static on some HD Audio 63 * codecs. 64 * The PCI register TCSEL is defined in the Intel manuals. 65 */ 66 dev_dbg(ebus_to_hbus(ebus)->dev, "Clearing TCSEL\n"); 67 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); 68 } 69 70 static void update_pci_dword(struct pci_dev *pci, 71 unsigned int reg, u32 mask, u32 val) 72 { 73 u32 data = 0; 74 75 pci_read_config_dword(pci, reg, &data); 76 data &= ~mask; 77 data |= (val & mask); 78 pci_write_config_dword(pci, reg, data); 79 } 80 81 /* 82 * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits 83 * 84 * @dev: device pointer 85 * @enable: enable/disable flag 86 */ 87 static void skl_enable_miscbdcge(struct device *dev, bool enable) 88 { 89 struct pci_dev *pci = to_pci_dev(dev); 90 u32 val; 91 92 val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; 93 94 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); 95 } 96 97 /** 98 * skl_clock_power_gating: Enable/Disable clock and power gating 99 * 100 * @dev: Device pointer 101 * @enable: Enable/Disable flag 102 */ 103 static void skl_clock_power_gating(struct device *dev, bool enable) 104 { 105 struct pci_dev *pci = to_pci_dev(dev); 106 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 107 struct hdac_bus *bus = ebus_to_hbus(ebus); 108 u32 val; 109 110 /* Update PDCGE bit of CGCTL register */ 111 val = enable ? AZX_CGCTL_ADSPDCGE : 0; 112 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); 113 114 /* Update L1SEN bit of EM2 register */ 115 val = enable ? AZX_REG_VS_EM2_L1SEN : 0; 116 snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val); 117 118 /* Update ADSPPGD bit of PGCTL register */ 119 val = enable ? 0 : AZX_PGCTL_ADSPPGD; 120 update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val); 121 } 122 123 /* 124 * While performing reset, controller may not come back properly causing 125 * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset 126 * (init chip) and then again set CGCTL.MISCBDCGE to 1 127 */ 128 static int skl_init_chip(struct hdac_bus *bus, bool full_reset) 129 { 130 int ret; 131 132 skl_enable_miscbdcge(bus->dev, false); 133 ret = snd_hdac_bus_init_chip(bus, full_reset); 134 skl_enable_miscbdcge(bus->dev, true); 135 136 return ret; 137 } 138 139 void skl_update_d0i3c(struct device *dev, bool enable) 140 { 141 struct pci_dev *pci = to_pci_dev(dev); 142 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 143 struct hdac_bus *bus = ebus_to_hbus(ebus); 144 u8 reg; 145 int timeout = 50; 146 147 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 148 /* Do not write to D0I3C until command in progress bit is cleared */ 149 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 150 udelay(10); 151 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 152 } 153 154 /* Highly unlikely. But if it happens, flag error explicitly */ 155 if (!timeout) { 156 dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n"); 157 return; 158 } 159 160 if (enable) 161 reg = reg | AZX_REG_VS_D0I3C_I3; 162 else 163 reg = reg & (~AZX_REG_VS_D0I3C_I3); 164 165 snd_hdac_chip_writeb(bus, VS_D0I3C, reg); 166 167 timeout = 50; 168 /* Wait for cmd in progress to be cleared before exiting the function */ 169 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 170 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 171 udelay(10); 172 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 173 } 174 175 /* Highly unlikely. But if it happens, flag error explicitly */ 176 if (!timeout) { 177 dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n"); 178 return; 179 } 180 181 dev_dbg(bus->dev, "D0I3C register = 0x%x\n", 182 snd_hdac_chip_readb(bus, VS_D0I3C)); 183 } 184 185 /* called from IRQ */ 186 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) 187 { 188 snd_pcm_period_elapsed(hstr->substream); 189 } 190 191 static irqreturn_t skl_interrupt(int irq, void *dev_id) 192 { 193 struct hdac_ext_bus *ebus = dev_id; 194 struct hdac_bus *bus = ebus_to_hbus(ebus); 195 u32 status; 196 197 if (!pm_runtime_active(bus->dev)) 198 return IRQ_NONE; 199 200 spin_lock(&bus->reg_lock); 201 202 status = snd_hdac_chip_readl(bus, INTSTS); 203 if (status == 0 || status == 0xffffffff) { 204 spin_unlock(&bus->reg_lock); 205 return IRQ_NONE; 206 } 207 208 /* clear rirb int */ 209 status = snd_hdac_chip_readb(bus, RIRBSTS); 210 if (status & RIRB_INT_MASK) { 211 if (status & RIRB_INT_RESPONSE) 212 snd_hdac_bus_update_rirb(bus); 213 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 214 } 215 216 spin_unlock(&bus->reg_lock); 217 218 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; 219 } 220 221 static irqreturn_t skl_threaded_handler(int irq, void *dev_id) 222 { 223 struct hdac_ext_bus *ebus = dev_id; 224 struct hdac_bus *bus = ebus_to_hbus(ebus); 225 u32 status; 226 227 status = snd_hdac_chip_readl(bus, INTSTS); 228 229 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); 230 231 return IRQ_HANDLED; 232 } 233 234 static int skl_acquire_irq(struct hdac_ext_bus *ebus, int do_disconnect) 235 { 236 struct skl *skl = ebus_to_skl(ebus); 237 struct hdac_bus *bus = ebus_to_hbus(ebus); 238 int ret; 239 240 ret = request_threaded_irq(skl->pci->irq, skl_interrupt, 241 skl_threaded_handler, 242 IRQF_SHARED, 243 KBUILD_MODNAME, ebus); 244 if (ret) { 245 dev_err(bus->dev, 246 "unable to grab IRQ %d, disabling device\n", 247 skl->pci->irq); 248 return ret; 249 } 250 251 bus->irq = skl->pci->irq; 252 pci_intx(skl->pci, 1); 253 254 return 0; 255 } 256 257 static int skl_suspend_late(struct device *dev) 258 { 259 struct pci_dev *pci = to_pci_dev(dev); 260 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 261 struct skl *skl = ebus_to_skl(ebus); 262 263 return skl_suspend_late_dsp(skl); 264 } 265 266 #ifdef CONFIG_PM 267 static int _skl_suspend(struct hdac_ext_bus *ebus) 268 { 269 struct skl *skl = ebus_to_skl(ebus); 270 struct hdac_bus *bus = ebus_to_hbus(ebus); 271 struct pci_dev *pci = to_pci_dev(bus->dev); 272 int ret; 273 274 snd_hdac_ext_bus_link_power_down_all(ebus); 275 276 ret = skl_suspend_dsp(skl); 277 if (ret < 0) 278 return ret; 279 280 snd_hdac_bus_stop_chip(bus); 281 update_pci_dword(pci, AZX_PCIREG_PGCTL, 282 AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK); 283 skl_enable_miscbdcge(bus->dev, false); 284 snd_hdac_bus_enter_link_reset(bus); 285 skl_enable_miscbdcge(bus->dev, true); 286 skl_cleanup_resources(skl); 287 288 return 0; 289 } 290 291 static int _skl_resume(struct hdac_ext_bus *ebus) 292 { 293 struct skl *skl = ebus_to_skl(ebus); 294 struct hdac_bus *bus = ebus_to_hbus(ebus); 295 296 skl_init_pci(skl); 297 skl_init_chip(bus, true); 298 299 return skl_resume_dsp(skl); 300 } 301 #endif 302 303 #ifdef CONFIG_PM_SLEEP 304 /* 305 * power management 306 */ 307 static int skl_suspend(struct device *dev) 308 { 309 struct pci_dev *pci = to_pci_dev(dev); 310 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 311 struct skl *skl = ebus_to_skl(ebus); 312 struct hdac_bus *bus = ebus_to_hbus(ebus); 313 int ret = 0; 314 315 /* 316 * Do not suspend if streams which are marked ignore suspend are 317 * running, we need to save the state for these and continue 318 */ 319 if (skl->supend_active) { 320 /* turn off the links and stop the CORB/RIRB DMA if it is On */ 321 snd_hdac_ext_bus_link_power_down_all(ebus); 322 323 if (ebus->cmd_dma_state) 324 snd_hdac_bus_stop_cmd_io(&ebus->bus); 325 326 enable_irq_wake(bus->irq); 327 pci_save_state(pci); 328 } else { 329 ret = _skl_suspend(ebus); 330 if (ret < 0) 331 return ret; 332 skl->skl_sst->fw_loaded = false; 333 } 334 335 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 336 ret = snd_hdac_display_power(bus, false); 337 if (ret < 0) 338 dev_err(bus->dev, 339 "Cannot turn OFF display power on i915\n"); 340 } 341 342 return ret; 343 } 344 345 static int skl_resume(struct device *dev) 346 { 347 struct pci_dev *pci = to_pci_dev(dev); 348 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 349 struct skl *skl = ebus_to_skl(ebus); 350 struct hdac_bus *bus = ebus_to_hbus(ebus); 351 struct hdac_ext_link *hlink = NULL; 352 int ret; 353 354 /* Turned OFF in HDMI codec driver after codec reconfiguration */ 355 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 356 ret = snd_hdac_display_power(bus, true); 357 if (ret < 0) { 358 dev_err(bus->dev, 359 "Cannot turn on display power on i915\n"); 360 return ret; 361 } 362 } 363 364 /* 365 * resume only when we are not in suspend active, otherwise need to 366 * restore the device 367 */ 368 if (skl->supend_active) { 369 pci_restore_state(pci); 370 snd_hdac_ext_bus_link_power_up_all(ebus); 371 disable_irq_wake(bus->irq); 372 /* 373 * turn On the links which are On before active suspend 374 * and start the CORB/RIRB DMA if On before 375 * active suspend. 376 */ 377 list_for_each_entry(hlink, &ebus->hlink_list, list) { 378 if (hlink->ref_count) 379 snd_hdac_ext_bus_link_power_up(hlink); 380 } 381 382 if (ebus->cmd_dma_state) 383 snd_hdac_bus_init_cmd_io(&ebus->bus); 384 ret = 0; 385 } else { 386 ret = _skl_resume(ebus); 387 388 /* turn off the links which are off before suspend */ 389 list_for_each_entry(hlink, &ebus->hlink_list, list) { 390 if (!hlink->ref_count) 391 snd_hdac_ext_bus_link_power_down(hlink); 392 } 393 394 if (!ebus->cmd_dma_state) 395 snd_hdac_bus_stop_cmd_io(&ebus->bus); 396 } 397 398 return ret; 399 } 400 #endif /* CONFIG_PM_SLEEP */ 401 402 #ifdef CONFIG_PM 403 static int skl_runtime_suspend(struct device *dev) 404 { 405 struct pci_dev *pci = to_pci_dev(dev); 406 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 407 struct hdac_bus *bus = ebus_to_hbus(ebus); 408 409 dev_dbg(bus->dev, "in %s\n", __func__); 410 411 return _skl_suspend(ebus); 412 } 413 414 static int skl_runtime_resume(struct device *dev) 415 { 416 struct pci_dev *pci = to_pci_dev(dev); 417 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 418 struct hdac_bus *bus = ebus_to_hbus(ebus); 419 420 dev_dbg(bus->dev, "in %s\n", __func__); 421 422 return _skl_resume(ebus); 423 } 424 #endif /* CONFIG_PM */ 425 426 static const struct dev_pm_ops skl_pm = { 427 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) 428 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) 429 .suspend_late = skl_suspend_late, 430 }; 431 432 /* 433 * destructor 434 */ 435 static int skl_free(struct hdac_ext_bus *ebus) 436 { 437 struct skl *skl = ebus_to_skl(ebus); 438 struct hdac_bus *bus = ebus_to_hbus(ebus); 439 440 skl->init_done = 0; /* to be sure */ 441 442 snd_hdac_ext_stop_streams(ebus); 443 444 if (bus->irq >= 0) 445 free_irq(bus->irq, (void *)ebus); 446 snd_hdac_bus_free_stream_pages(bus); 447 snd_hdac_stream_free_all(ebus); 448 snd_hdac_link_free_all(ebus); 449 450 if (bus->remap_addr) 451 iounmap(bus->remap_addr); 452 453 pci_release_regions(skl->pci); 454 pci_disable_device(skl->pci); 455 456 snd_hdac_ext_bus_exit(ebus); 457 458 cancel_work_sync(&skl->probe_work); 459 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 460 snd_hdac_i915_exit(&ebus->bus); 461 462 return 0; 463 } 464 465 /* 466 * For each ssp there are 3 clocks (mclk/sclk/sclkfs). 467 * e.g. for ssp0, clocks will be named as 468 * "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs" 469 * So for skl+, there are 6 ssps, so 18 clocks will be created. 470 */ 471 static struct skl_ssp_clk skl_ssp_clks[] = { 472 {.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"}, 473 {.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"}, 474 {.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"}, 475 {.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"}, 476 {.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"}, 477 {.name = "ssp2_sclkfs"}, 478 {.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"}, 479 {.name = "ssp5_sclkfs"}, 480 }; 481 482 static int skl_find_machine(struct skl *skl, void *driver_data) 483 { 484 struct snd_soc_acpi_mach *mach = driver_data; 485 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); 486 struct skl_machine_pdata *pdata; 487 488 mach = snd_soc_acpi_find_machine(mach); 489 if (mach == NULL) { 490 dev_err(bus->dev, "No matching machine driver found\n"); 491 return -ENODEV; 492 } 493 494 skl->mach = mach; 495 skl->fw_name = mach->fw_filename; 496 pdata = skl->mach->pdata; 497 498 if (mach->pdata) 499 skl->use_tplg_pcm = pdata->use_tplg_pcm; 500 501 return 0; 502 } 503 504 static int skl_machine_device_register(struct skl *skl) 505 { 506 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); 507 struct snd_soc_acpi_mach *mach = skl->mach; 508 struct platform_device *pdev; 509 int ret; 510 511 pdev = platform_device_alloc(mach->drv_name, -1); 512 if (pdev == NULL) { 513 dev_err(bus->dev, "platform device alloc failed\n"); 514 return -EIO; 515 } 516 517 ret = platform_device_add(pdev); 518 if (ret) { 519 dev_err(bus->dev, "failed to add machine device\n"); 520 platform_device_put(pdev); 521 return -EIO; 522 } 523 524 if (mach->pdata) 525 dev_set_drvdata(&pdev->dev, mach->pdata); 526 527 skl->i2s_dev = pdev; 528 529 return 0; 530 } 531 532 static void skl_machine_device_unregister(struct skl *skl) 533 { 534 if (skl->i2s_dev) 535 platform_device_unregister(skl->i2s_dev); 536 } 537 538 static int skl_dmic_device_register(struct skl *skl) 539 { 540 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); 541 struct platform_device *pdev; 542 int ret; 543 544 /* SKL has one dmic port, so allocate dmic device for this */ 545 pdev = platform_device_alloc("dmic-codec", -1); 546 if (!pdev) { 547 dev_err(bus->dev, "failed to allocate dmic device\n"); 548 return -ENOMEM; 549 } 550 551 ret = platform_device_add(pdev); 552 if (ret) { 553 dev_err(bus->dev, "failed to add dmic device: %d\n", ret); 554 platform_device_put(pdev); 555 return ret; 556 } 557 skl->dmic_dev = pdev; 558 559 return 0; 560 } 561 562 static void skl_dmic_device_unregister(struct skl *skl) 563 { 564 if (skl->dmic_dev) 565 platform_device_unregister(skl->dmic_dev); 566 } 567 568 static struct skl_clk_parent_src skl_clk_src[] = { 569 { .clk_id = SKL_XTAL, .name = "xtal" }, 570 { .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 }, 571 { .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 }, 572 }; 573 574 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id) 575 { 576 unsigned int i; 577 578 for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) { 579 if (skl_clk_src[i].clk_id == clk_id) 580 return &skl_clk_src[i]; 581 } 582 583 return NULL; 584 } 585 586 static void init_skl_xtal_rate(int pci_id) 587 { 588 switch (pci_id) { 589 case 0x9d70: 590 case 0x9d71: 591 skl_clk_src[0].rate = 24000000; 592 return; 593 594 default: 595 skl_clk_src[0].rate = 19200000; 596 return; 597 } 598 } 599 600 static int skl_clock_device_register(struct skl *skl) 601 { 602 struct platform_device_info pdevinfo = {NULL}; 603 struct skl_clk_pdata *clk_pdata; 604 605 clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata), 606 GFP_KERNEL); 607 if (!clk_pdata) 608 return -ENOMEM; 609 610 init_skl_xtal_rate(skl->pci->device); 611 612 clk_pdata->parent_clks = skl_clk_src; 613 clk_pdata->ssp_clks = skl_ssp_clks; 614 clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks); 615 616 /* Query NHLT to fill the rates and parent */ 617 skl_get_clks(skl, clk_pdata->ssp_clks); 618 clk_pdata->pvt_data = skl; 619 620 /* Register Platform device */ 621 pdevinfo.parent = &skl->pci->dev; 622 pdevinfo.id = -1; 623 pdevinfo.name = "skl-ssp-clk"; 624 pdevinfo.data = clk_pdata; 625 pdevinfo.size_data = sizeof(*clk_pdata); 626 skl->clk_dev = platform_device_register_full(&pdevinfo); 627 return PTR_ERR_OR_ZERO(skl->clk_dev); 628 } 629 630 static void skl_clock_device_unregister(struct skl *skl) 631 { 632 if (skl->clk_dev) 633 platform_device_unregister(skl->clk_dev); 634 } 635 636 /* 637 * Probe the given codec address 638 */ 639 static int probe_codec(struct hdac_ext_bus *ebus, int addr) 640 { 641 struct hdac_bus *bus = ebus_to_hbus(ebus); 642 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 643 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 644 unsigned int res = -1; 645 646 mutex_lock(&bus->cmd_mutex); 647 snd_hdac_bus_send_cmd(bus, cmd); 648 snd_hdac_bus_get_response(bus, addr, &res); 649 mutex_unlock(&bus->cmd_mutex); 650 if (res == -1) 651 return -EIO; 652 dev_dbg(bus->dev, "codec #%d probed OK\n", addr); 653 654 return snd_hdac_ext_bus_device_init(ebus, addr); 655 } 656 657 /* Codec initialization */ 658 static void skl_codec_create(struct hdac_ext_bus *ebus) 659 { 660 struct hdac_bus *bus = ebus_to_hbus(ebus); 661 int c, max_slots; 662 663 max_slots = HDA_MAX_CODECS; 664 665 /* First try to probe all given codec slots */ 666 for (c = 0; c < max_slots; c++) { 667 if ((bus->codec_mask & (1 << c))) { 668 if (probe_codec(ebus, c) < 0) { 669 /* 670 * Some BIOSen give you wrong codec addresses 671 * that don't exist 672 */ 673 dev_warn(bus->dev, 674 "Codec #%d probe error; disabling it...\n", c); 675 bus->codec_mask &= ~(1 << c); 676 /* 677 * More badly, accessing to a non-existing 678 * codec often screws up the controller bus, 679 * and disturbs the further communications. 680 * Thus if an error occurs during probing, 681 * better to reset the controller bus to get 682 * back to the sanity state. 683 */ 684 snd_hdac_bus_stop_chip(bus); 685 skl_init_chip(bus, true); 686 } 687 } 688 } 689 } 690 691 static const struct hdac_bus_ops bus_core_ops = { 692 .command = snd_hdac_bus_send_cmd, 693 .get_response = snd_hdac_bus_get_response, 694 }; 695 696 static int skl_i915_init(struct hdac_bus *bus) 697 { 698 int err; 699 700 /* 701 * The HDMI codec is in GPU so we need to ensure that it is powered 702 * up and ready for probe 703 */ 704 err = snd_hdac_i915_init(bus); 705 if (err < 0) 706 return err; 707 708 err = snd_hdac_display_power(bus, true); 709 if (err < 0) 710 dev_err(bus->dev, "Cannot turn on display power on i915\n"); 711 712 return err; 713 } 714 715 static void skl_probe_work(struct work_struct *work) 716 { 717 struct skl *skl = container_of(work, struct skl, probe_work); 718 struct hdac_ext_bus *ebus = &skl->ebus; 719 struct hdac_bus *bus = ebus_to_hbus(ebus); 720 struct hdac_ext_link *hlink = NULL; 721 int err; 722 723 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 724 err = skl_i915_init(bus); 725 if (err < 0) 726 return; 727 } 728 729 err = skl_init_chip(bus, true); 730 if (err < 0) { 731 dev_err(bus->dev, "Init chip failed with err: %d\n", err); 732 goto out_err; 733 } 734 735 /* codec detection */ 736 if (!bus->codec_mask) 737 dev_info(bus->dev, "no hda codecs found!\n"); 738 739 /* create codec instances */ 740 skl_codec_create(ebus); 741 742 /* register platform dai and controls */ 743 err = skl_platform_register(bus->dev); 744 if (err < 0) { 745 dev_err(bus->dev, "platform register failed: %d\n", err); 746 return; 747 } 748 749 if (bus->ppcap) { 750 err = skl_machine_device_register(skl); 751 if (err < 0) { 752 dev_err(bus->dev, "machine register failed: %d\n", err); 753 goto out_err; 754 } 755 } 756 757 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 758 err = snd_hdac_display_power(bus, false); 759 if (err < 0) { 760 dev_err(bus->dev, "Cannot turn off display power on i915\n"); 761 skl_machine_device_unregister(skl); 762 return; 763 } 764 } 765 766 /* 767 * we are done probing so decrement link counts 768 */ 769 list_for_each_entry(hlink, &ebus->hlink_list, list) 770 snd_hdac_ext_bus_link_put(ebus, hlink); 771 772 /* configure PM */ 773 pm_runtime_put_noidle(bus->dev); 774 pm_runtime_allow(bus->dev); 775 skl->init_done = 1; 776 777 return; 778 779 out_err: 780 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 781 err = snd_hdac_display_power(bus, false); 782 } 783 784 /* 785 * constructor 786 */ 787 static int skl_create(struct pci_dev *pci, 788 const struct hdac_io_ops *io_ops, 789 struct skl **rskl) 790 { 791 struct skl *skl; 792 struct hdac_ext_bus *ebus; 793 794 int err; 795 796 *rskl = NULL; 797 798 err = pci_enable_device(pci); 799 if (err < 0) 800 return err; 801 802 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); 803 if (!skl) { 804 pci_disable_device(pci); 805 return -ENOMEM; 806 } 807 ebus = &skl->ebus; 808 snd_hdac_ext_bus_init(ebus, &pci->dev, &bus_core_ops, io_ops); 809 ebus->bus.use_posbuf = 1; 810 skl->pci = pci; 811 INIT_WORK(&skl->probe_work, skl_probe_work); 812 813 ebus->bus.bdl_pos_adj = 0; 814 815 *rskl = skl; 816 817 return 0; 818 } 819 820 static int skl_first_init(struct hdac_ext_bus *ebus) 821 { 822 struct skl *skl = ebus_to_skl(ebus); 823 struct hdac_bus *bus = ebus_to_hbus(ebus); 824 struct pci_dev *pci = skl->pci; 825 int err; 826 unsigned short gcap; 827 int cp_streams, pb_streams, start_idx; 828 829 err = pci_request_regions(pci, "Skylake HD audio"); 830 if (err < 0) 831 return err; 832 833 bus->addr = pci_resource_start(pci, 0); 834 bus->remap_addr = pci_ioremap_bar(pci, 0); 835 if (bus->remap_addr == NULL) { 836 dev_err(bus->dev, "ioremap error\n"); 837 return -ENXIO; 838 } 839 840 skl_init_chip(bus, true); 841 842 snd_hdac_bus_parse_capabilities(bus); 843 844 if (skl_acquire_irq(ebus, 0) < 0) 845 return -EBUSY; 846 847 pci_set_master(pci); 848 synchronize_irq(bus->irq); 849 850 gcap = snd_hdac_chip_readw(bus, GCAP); 851 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); 852 853 /* allow 64bit DMA address if supported by H/W */ 854 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) { 855 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64)); 856 } else { 857 dma_set_mask(bus->dev, DMA_BIT_MASK(32)); 858 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32)); 859 } 860 861 /* read number of streams from GCAP register */ 862 cp_streams = (gcap >> 8) & 0x0f; 863 pb_streams = (gcap >> 12) & 0x0f; 864 865 if (!pb_streams && !cp_streams) 866 return -EIO; 867 868 ebus->num_streams = cp_streams + pb_streams; 869 870 /* initialize streams */ 871 snd_hdac_ext_stream_init_all 872 (ebus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); 873 start_idx = cp_streams; 874 snd_hdac_ext_stream_init_all 875 (ebus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); 876 877 err = snd_hdac_bus_alloc_stream_pages(bus); 878 if (err < 0) 879 return err; 880 881 /* initialize chip */ 882 skl_init_pci(skl); 883 884 return skl_init_chip(bus, true); 885 } 886 887 static int skl_probe(struct pci_dev *pci, 888 const struct pci_device_id *pci_id) 889 { 890 struct skl *skl; 891 struct hdac_ext_bus *ebus = NULL; 892 struct hdac_bus *bus = NULL; 893 int err; 894 895 /* we use ext core ops, so provide NULL for ops here */ 896 err = skl_create(pci, NULL, &skl); 897 if (err < 0) 898 return err; 899 900 ebus = &skl->ebus; 901 bus = ebus_to_hbus(ebus); 902 903 err = skl_first_init(ebus); 904 if (err < 0) 905 goto out_free; 906 907 skl->pci_id = pci->device; 908 909 device_disable_async_suspend(bus->dev); 910 911 skl->nhlt = skl_nhlt_init(bus->dev); 912 913 if (skl->nhlt == NULL) { 914 err = -ENODEV; 915 goto out_free; 916 } 917 918 err = skl_nhlt_create_sysfs(skl); 919 if (err < 0) 920 goto out_nhlt_free; 921 922 skl_nhlt_update_topology_bin(skl); 923 924 pci_set_drvdata(skl->pci, ebus); 925 926 skl_dmic_data.dmic_num = skl_get_dmic_geo(skl); 927 928 /* check if dsp is there */ 929 if (bus->ppcap) { 930 /* create device for dsp clk */ 931 err = skl_clock_device_register(skl); 932 if (err < 0) 933 goto out_clk_free; 934 935 err = skl_find_machine(skl, (void *)pci_id->driver_data); 936 if (err < 0) 937 goto out_nhlt_free; 938 939 err = skl_init_dsp(skl); 940 if (err < 0) { 941 dev_dbg(bus->dev, "error failed to register dsp\n"); 942 goto out_nhlt_free; 943 } 944 skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge; 945 skl->skl_sst->clock_power_gating = skl_clock_power_gating; 946 } 947 if (bus->mlcap) 948 snd_hdac_ext_bus_get_ml_capabilities(ebus); 949 950 snd_hdac_bus_stop_chip(bus); 951 952 /* create device for soc dmic */ 953 err = skl_dmic_device_register(skl); 954 if (err < 0) 955 goto out_dsp_free; 956 957 schedule_work(&skl->probe_work); 958 959 return 0; 960 961 out_dsp_free: 962 skl_free_dsp(skl); 963 out_clk_free: 964 skl_clock_device_unregister(skl); 965 out_nhlt_free: 966 skl_nhlt_free(skl->nhlt); 967 out_free: 968 skl_free(ebus); 969 970 return err; 971 } 972 973 static void skl_shutdown(struct pci_dev *pci) 974 { 975 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 976 struct hdac_bus *bus = ebus_to_hbus(ebus); 977 struct hdac_stream *s; 978 struct hdac_ext_stream *stream; 979 struct skl *skl; 980 981 if (ebus == NULL) 982 return; 983 984 skl = ebus_to_skl(ebus); 985 986 if (!skl->init_done) 987 return; 988 989 snd_hdac_ext_stop_streams(ebus); 990 list_for_each_entry(s, &bus->stream_list, list) { 991 stream = stream_to_hdac_ext_stream(s); 992 snd_hdac_ext_stream_decouple(ebus, stream, false); 993 } 994 995 snd_hdac_bus_stop_chip(bus); 996 } 997 998 static void skl_remove(struct pci_dev *pci) 999 { 1000 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 1001 struct skl *skl = ebus_to_skl(ebus); 1002 1003 release_firmware(skl->tplg); 1004 1005 pm_runtime_get_noresume(&pci->dev); 1006 1007 /* codec removal, invoke bus_device_remove */ 1008 snd_hdac_ext_bus_device_remove(ebus); 1009 1010 skl->debugfs = NULL; 1011 skl_platform_unregister(&pci->dev); 1012 skl_free_dsp(skl); 1013 skl_machine_device_unregister(skl); 1014 skl_dmic_device_unregister(skl); 1015 skl_clock_device_unregister(skl); 1016 skl_nhlt_remove_sysfs(skl); 1017 skl_nhlt_free(skl->nhlt); 1018 skl_free(ebus); 1019 dev_set_drvdata(&pci->dev, NULL); 1020 } 1021 1022 static struct snd_soc_acpi_codecs skl_codecs = { 1023 .num_codecs = 1, 1024 .codecs = {"10508825"} 1025 }; 1026 1027 static struct snd_soc_acpi_codecs kbl_codecs = { 1028 .num_codecs = 1, 1029 .codecs = {"10508825"} 1030 }; 1031 1032 static struct snd_soc_acpi_codecs bxt_codecs = { 1033 .num_codecs = 1, 1034 .codecs = {"MX98357A"} 1035 }; 1036 1037 static struct snd_soc_acpi_codecs kbl_poppy_codecs = { 1038 .num_codecs = 1, 1039 .codecs = {"10EC5663"} 1040 }; 1041 1042 static struct snd_soc_acpi_codecs kbl_5663_5514_codecs = { 1043 .num_codecs = 2, 1044 .codecs = {"10EC5663", "10EC5514"} 1045 }; 1046 1047 static struct snd_soc_acpi_codecs kbl_7219_98357_codecs = { 1048 .num_codecs = 1, 1049 .codecs = {"MX98357A"} 1050 }; 1051 1052 static struct skl_machine_pdata cnl_pdata = { 1053 .use_tplg_pcm = true, 1054 }; 1055 1056 static struct snd_soc_acpi_mach sst_skl_devdata[] = { 1057 { 1058 .id = "INT343A", 1059 .drv_name = "skl_alc286s_i2s", 1060 .fw_filename = "intel/dsp_fw_release.bin", 1061 }, 1062 { 1063 .id = "INT343B", 1064 .drv_name = "skl_n88l25_s4567", 1065 .fw_filename = "intel/dsp_fw_release.bin", 1066 .machine_quirk = snd_soc_acpi_codec_list, 1067 .quirk_data = &skl_codecs, 1068 .pdata = &skl_dmic_data 1069 }, 1070 { 1071 .id = "MX98357A", 1072 .drv_name = "skl_n88l25_m98357a", 1073 .fw_filename = "intel/dsp_fw_release.bin", 1074 .machine_quirk = snd_soc_acpi_codec_list, 1075 .quirk_data = &skl_codecs, 1076 .pdata = &skl_dmic_data 1077 }, 1078 {} 1079 }; 1080 1081 static struct snd_soc_acpi_mach sst_bxtp_devdata[] = { 1082 { 1083 .id = "INT343A", 1084 .drv_name = "bxt_alc298s_i2s", 1085 .fw_filename = "intel/dsp_fw_bxtn.bin", 1086 }, 1087 { 1088 .id = "DLGS7219", 1089 .drv_name = "bxt_da7219_max98357a_i2s", 1090 .fw_filename = "intel/dsp_fw_bxtn.bin", 1091 .machine_quirk = snd_soc_acpi_codec_list, 1092 .quirk_data = &bxt_codecs, 1093 }, 1094 {} 1095 }; 1096 1097 static struct snd_soc_acpi_mach sst_kbl_devdata[] = { 1098 { 1099 .id = "INT343A", 1100 .drv_name = "kbl_alc286s_i2s", 1101 .fw_filename = "intel/dsp_fw_kbl.bin", 1102 }, 1103 { 1104 .id = "INT343B", 1105 .drv_name = "kbl_n88l25_s4567", 1106 .fw_filename = "intel/dsp_fw_kbl.bin", 1107 .machine_quirk = snd_soc_acpi_codec_list, 1108 .quirk_data = &kbl_codecs, 1109 .pdata = &skl_dmic_data 1110 }, 1111 { 1112 .id = "MX98357A", 1113 .drv_name = "kbl_n88l25_m98357a", 1114 .fw_filename = "intel/dsp_fw_kbl.bin", 1115 .machine_quirk = snd_soc_acpi_codec_list, 1116 .quirk_data = &kbl_codecs, 1117 .pdata = &skl_dmic_data 1118 }, 1119 { 1120 .id = "MX98927", 1121 .drv_name = "kbl_r5514_5663_max", 1122 .fw_filename = "intel/dsp_fw_kbl.bin", 1123 .machine_quirk = snd_soc_acpi_codec_list, 1124 .quirk_data = &kbl_5663_5514_codecs, 1125 .pdata = &skl_dmic_data 1126 }, 1127 { 1128 .id = "MX98927", 1129 .drv_name = "kbl_rt5663_m98927", 1130 .fw_filename = "intel/dsp_fw_kbl.bin", 1131 .machine_quirk = snd_soc_acpi_codec_list, 1132 .quirk_data = &kbl_poppy_codecs, 1133 .pdata = &skl_dmic_data 1134 }, 1135 { 1136 .id = "10EC5663", 1137 .drv_name = "kbl_rt5663", 1138 .fw_filename = "intel/dsp_fw_kbl.bin", 1139 }, 1140 { 1141 .id = "DLGS7219", 1142 .drv_name = "kbl_da7219_max98357a", 1143 .fw_filename = "intel/dsp_fw_kbl.bin", 1144 .machine_quirk = snd_soc_acpi_codec_list, 1145 .quirk_data = &kbl_7219_98357_codecs, 1146 .pdata = &skl_dmic_data 1147 }, 1148 1149 {} 1150 }; 1151 1152 static struct snd_soc_acpi_mach sst_glk_devdata[] = { 1153 { 1154 .id = "INT343A", 1155 .drv_name = "glk_alc298s_i2s", 1156 .fw_filename = "intel/dsp_fw_glk.bin", 1157 }, 1158 {} 1159 }; 1160 1161 static const struct snd_soc_acpi_mach sst_cnl_devdata[] = { 1162 { 1163 .id = "INT34C2", 1164 .drv_name = "cnl_rt274", 1165 .fw_filename = "intel/dsp_fw_cnl.bin", 1166 .pdata = &cnl_pdata, 1167 }, 1168 {} 1169 }; 1170 1171 /* PCI IDs */ 1172 static const struct pci_device_id skl_ids[] = { 1173 /* Sunrise Point-LP */ 1174 { PCI_DEVICE(0x8086, 0x9d70), 1175 .driver_data = (unsigned long)&sst_skl_devdata}, 1176 /* BXT-P */ 1177 { PCI_DEVICE(0x8086, 0x5a98), 1178 .driver_data = (unsigned long)&sst_bxtp_devdata}, 1179 /* KBL */ 1180 { PCI_DEVICE(0x8086, 0x9D71), 1181 .driver_data = (unsigned long)&sst_kbl_devdata}, 1182 /* GLK */ 1183 { PCI_DEVICE(0x8086, 0x3198), 1184 .driver_data = (unsigned long)&sst_glk_devdata}, 1185 /* CNL */ 1186 { PCI_DEVICE(0x8086, 0x9dc8), 1187 .driver_data = (unsigned long)&sst_cnl_devdata}, 1188 { 0, } 1189 }; 1190 MODULE_DEVICE_TABLE(pci, skl_ids); 1191 1192 /* pci_driver definition */ 1193 static struct pci_driver skl_driver = { 1194 .name = KBUILD_MODNAME, 1195 .id_table = skl_ids, 1196 .probe = skl_probe, 1197 .remove = skl_remove, 1198 .shutdown = skl_shutdown, 1199 .driver = { 1200 .pm = &skl_pm, 1201 }, 1202 }; 1203 module_pci_driver(skl_driver); 1204 1205 MODULE_LICENSE("GPL v2"); 1206 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver"); 1207