1 /* 2 * skl.c - Implementation of ASoC Intel SKL HD Audio driver 3 * 4 * Copyright (C) 2014-2015 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * 7 * Derived mostly from Intel HDA driver with following copyrights: 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; version 2 of the License. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 22 */ 23 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/platform_device.h> 28 #include <linux/firmware.h> 29 #include <sound/pcm.h> 30 #include "../common/sst-acpi.h" 31 #include <sound/hda_register.h> 32 #include <sound/hdaudio.h> 33 #include <sound/hda_i915.h> 34 #include "skl.h" 35 #include "skl-sst-dsp.h" 36 #include "skl-sst-ipc.h" 37 38 static struct skl_machine_pdata skl_dmic_data; 39 40 /* 41 * initialize the PCI registers 42 */ 43 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, 44 unsigned char mask, unsigned char val) 45 { 46 unsigned char data; 47 48 pci_read_config_byte(pci, reg, &data); 49 data &= ~mask; 50 data |= (val & mask); 51 pci_write_config_byte(pci, reg, data); 52 } 53 54 static void skl_init_pci(struct skl *skl) 55 { 56 struct hdac_ext_bus *ebus = &skl->ebus; 57 58 /* 59 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 60 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 61 * Ensuring these bits are 0 clears playback static on some HD Audio 62 * codecs. 63 * The PCI register TCSEL is defined in the Intel manuals. 64 */ 65 dev_dbg(ebus_to_hbus(ebus)->dev, "Clearing TCSEL\n"); 66 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); 67 } 68 69 static void update_pci_dword(struct pci_dev *pci, 70 unsigned int reg, u32 mask, u32 val) 71 { 72 u32 data = 0; 73 74 pci_read_config_dword(pci, reg, &data); 75 data &= ~mask; 76 data |= (val & mask); 77 pci_write_config_dword(pci, reg, data); 78 } 79 80 /* 81 * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits 82 * 83 * @dev: device pointer 84 * @enable: enable/disable flag 85 */ 86 static void skl_enable_miscbdcge(struct device *dev, bool enable) 87 { 88 struct pci_dev *pci = to_pci_dev(dev); 89 u32 val; 90 91 val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; 92 93 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); 94 } 95 96 /* 97 * While performing reset, controller may not come back properly causing 98 * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset 99 * (init chip) and then again set CGCTL.MISCBDCGE to 1 100 */ 101 static int skl_init_chip(struct hdac_bus *bus, bool full_reset) 102 { 103 int ret; 104 105 skl_enable_miscbdcge(bus->dev, false); 106 ret = snd_hdac_bus_init_chip(bus, full_reset); 107 skl_enable_miscbdcge(bus->dev, true); 108 109 return ret; 110 } 111 112 /* called from IRQ */ 113 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) 114 { 115 snd_pcm_period_elapsed(hstr->substream); 116 } 117 118 static irqreturn_t skl_interrupt(int irq, void *dev_id) 119 { 120 struct hdac_ext_bus *ebus = dev_id; 121 struct hdac_bus *bus = ebus_to_hbus(ebus); 122 u32 status; 123 124 if (!pm_runtime_active(bus->dev)) 125 return IRQ_NONE; 126 127 spin_lock(&bus->reg_lock); 128 129 status = snd_hdac_chip_readl(bus, INTSTS); 130 if (status == 0 || status == 0xffffffff) { 131 spin_unlock(&bus->reg_lock); 132 return IRQ_NONE; 133 } 134 135 /* clear rirb int */ 136 status = snd_hdac_chip_readb(bus, RIRBSTS); 137 if (status & RIRB_INT_MASK) { 138 if (status & RIRB_INT_RESPONSE) 139 snd_hdac_bus_update_rirb(bus); 140 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 141 } 142 143 spin_unlock(&bus->reg_lock); 144 145 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; 146 } 147 148 static irqreturn_t skl_threaded_handler(int irq, void *dev_id) 149 { 150 struct hdac_ext_bus *ebus = dev_id; 151 struct hdac_bus *bus = ebus_to_hbus(ebus); 152 u32 status; 153 154 status = snd_hdac_chip_readl(bus, INTSTS); 155 156 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); 157 158 return IRQ_HANDLED; 159 } 160 161 static int skl_acquire_irq(struct hdac_ext_bus *ebus, int do_disconnect) 162 { 163 struct skl *skl = ebus_to_skl(ebus); 164 struct hdac_bus *bus = ebus_to_hbus(ebus); 165 int ret; 166 167 ret = request_threaded_irq(skl->pci->irq, skl_interrupt, 168 skl_threaded_handler, 169 IRQF_SHARED, 170 KBUILD_MODNAME, ebus); 171 if (ret) { 172 dev_err(bus->dev, 173 "unable to grab IRQ %d, disabling device\n", 174 skl->pci->irq); 175 return ret; 176 } 177 178 bus->irq = skl->pci->irq; 179 pci_intx(skl->pci, 1); 180 181 return 0; 182 } 183 184 #ifdef CONFIG_PM 185 static int _skl_suspend(struct hdac_ext_bus *ebus) 186 { 187 struct skl *skl = ebus_to_skl(ebus); 188 struct hdac_bus *bus = ebus_to_hbus(ebus); 189 struct pci_dev *pci = to_pci_dev(bus->dev); 190 int ret; 191 192 snd_hdac_ext_bus_link_power_down_all(ebus); 193 194 ret = skl_suspend_dsp(skl); 195 if (ret < 0) 196 return ret; 197 198 snd_hdac_bus_stop_chip(bus); 199 update_pci_dword(pci, AZX_PCIREG_PGCTL, 200 AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK); 201 skl_enable_miscbdcge(bus->dev, false); 202 snd_hdac_bus_enter_link_reset(bus); 203 skl_enable_miscbdcge(bus->dev, true); 204 skl_cleanup_resources(skl); 205 206 return 0; 207 } 208 209 static int _skl_resume(struct hdac_ext_bus *ebus) 210 { 211 struct skl *skl = ebus_to_skl(ebus); 212 struct hdac_bus *bus = ebus_to_hbus(ebus); 213 214 skl_init_pci(skl); 215 skl_init_chip(bus, true); 216 217 return skl_resume_dsp(skl); 218 } 219 #endif 220 221 #ifdef CONFIG_PM_SLEEP 222 /* 223 * power management 224 */ 225 static int skl_suspend(struct device *dev) 226 { 227 struct pci_dev *pci = to_pci_dev(dev); 228 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 229 struct skl *skl = ebus_to_skl(ebus); 230 struct hdac_bus *bus = ebus_to_hbus(ebus); 231 int ret = 0; 232 233 /* 234 * Do not suspend if streams which are marked ignore suspend are 235 * running, we need to save the state for these and continue 236 */ 237 if (skl->supend_active) { 238 /* turn off the links and stop the CORB/RIRB DMA if it is On */ 239 snd_hdac_ext_bus_link_power_down_all(ebus); 240 241 if (ebus->cmd_dma_state) 242 snd_hdac_bus_stop_cmd_io(&ebus->bus); 243 244 enable_irq_wake(bus->irq); 245 pci_save_state(pci); 246 pci_disable_device(pci); 247 } else { 248 ret = _skl_suspend(ebus); 249 if (ret < 0) 250 return ret; 251 skl->skl_sst->fw_loaded = false; 252 } 253 254 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 255 ret = snd_hdac_display_power(bus, false); 256 if (ret < 0) 257 dev_err(bus->dev, 258 "Cannot turn OFF display power on i915\n"); 259 } 260 261 return ret; 262 } 263 264 static int skl_resume(struct device *dev) 265 { 266 struct pci_dev *pci = to_pci_dev(dev); 267 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 268 struct skl *skl = ebus_to_skl(ebus); 269 struct hdac_bus *bus = ebus_to_hbus(ebus); 270 struct hdac_ext_link *hlink = NULL; 271 int ret; 272 273 /* Turned OFF in HDMI codec driver after codec reconfiguration */ 274 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 275 ret = snd_hdac_display_power(bus, true); 276 if (ret < 0) { 277 dev_err(bus->dev, 278 "Cannot turn on display power on i915\n"); 279 return ret; 280 } 281 } 282 283 /* 284 * resume only when we are not in suspend active, otherwise need to 285 * restore the device 286 */ 287 if (skl->supend_active) { 288 pci_restore_state(pci); 289 ret = pci_enable_device(pci); 290 snd_hdac_ext_bus_link_power_up_all(ebus); 291 disable_irq_wake(bus->irq); 292 /* 293 * turn On the links which are On before active suspend 294 * and start the CORB/RIRB DMA if On before 295 * active suspend. 296 */ 297 list_for_each_entry(hlink, &ebus->hlink_list, list) { 298 if (hlink->ref_count) 299 snd_hdac_ext_bus_link_power_up(hlink); 300 } 301 302 if (ebus->cmd_dma_state) 303 snd_hdac_bus_init_cmd_io(&ebus->bus); 304 } else { 305 ret = _skl_resume(ebus); 306 307 /* turn off the links which are off before suspend */ 308 list_for_each_entry(hlink, &ebus->hlink_list, list) { 309 if (!hlink->ref_count) 310 snd_hdac_ext_bus_link_power_down(hlink); 311 } 312 313 if (!ebus->cmd_dma_state) 314 snd_hdac_bus_stop_cmd_io(&ebus->bus); 315 } 316 317 return ret; 318 } 319 #endif /* CONFIG_PM_SLEEP */ 320 321 #ifdef CONFIG_PM 322 static int skl_runtime_suspend(struct device *dev) 323 { 324 struct pci_dev *pci = to_pci_dev(dev); 325 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 326 struct hdac_bus *bus = ebus_to_hbus(ebus); 327 328 dev_dbg(bus->dev, "in %s\n", __func__); 329 330 return _skl_suspend(ebus); 331 } 332 333 static int skl_runtime_resume(struct device *dev) 334 { 335 struct pci_dev *pci = to_pci_dev(dev); 336 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 337 struct hdac_bus *bus = ebus_to_hbus(ebus); 338 339 dev_dbg(bus->dev, "in %s\n", __func__); 340 341 return _skl_resume(ebus); 342 } 343 #endif /* CONFIG_PM */ 344 345 static const struct dev_pm_ops skl_pm = { 346 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) 347 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) 348 }; 349 350 /* 351 * destructor 352 */ 353 static int skl_free(struct hdac_ext_bus *ebus) 354 { 355 struct skl *skl = ebus_to_skl(ebus); 356 struct hdac_bus *bus = ebus_to_hbus(ebus); 357 358 skl->init_failed = 1; /* to be sure */ 359 360 snd_hdac_ext_stop_streams(ebus); 361 362 if (bus->irq >= 0) 363 free_irq(bus->irq, (void *)bus); 364 snd_hdac_bus_free_stream_pages(bus); 365 snd_hdac_stream_free_all(ebus); 366 snd_hdac_link_free_all(ebus); 367 368 if (bus->remap_addr) 369 iounmap(bus->remap_addr); 370 371 pci_release_regions(skl->pci); 372 pci_disable_device(skl->pci); 373 374 snd_hdac_ext_bus_exit(ebus); 375 376 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 377 snd_hdac_i915_exit(&ebus->bus); 378 return 0; 379 } 380 381 static int skl_machine_device_register(struct skl *skl, void *driver_data) 382 { 383 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); 384 struct platform_device *pdev; 385 struct sst_acpi_mach *mach = driver_data; 386 int ret; 387 388 mach = sst_acpi_find_machine(mach); 389 if (mach == NULL) { 390 dev_err(bus->dev, "No matching machine driver found\n"); 391 return -ENODEV; 392 } 393 skl->fw_name = mach->fw_filename; 394 395 pdev = platform_device_alloc(mach->drv_name, -1); 396 if (pdev == NULL) { 397 dev_err(bus->dev, "platform device alloc failed\n"); 398 return -EIO; 399 } 400 401 ret = platform_device_add(pdev); 402 if (ret) { 403 dev_err(bus->dev, "failed to add machine device\n"); 404 platform_device_put(pdev); 405 return -EIO; 406 } 407 408 if (mach->pdata) 409 dev_set_drvdata(&pdev->dev, mach->pdata); 410 411 skl->i2s_dev = pdev; 412 413 return 0; 414 } 415 416 static void skl_machine_device_unregister(struct skl *skl) 417 { 418 if (skl->i2s_dev) 419 platform_device_unregister(skl->i2s_dev); 420 } 421 422 static int skl_dmic_device_register(struct skl *skl) 423 { 424 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); 425 struct platform_device *pdev; 426 int ret; 427 428 /* SKL has one dmic port, so allocate dmic device for this */ 429 pdev = platform_device_alloc("dmic-codec", -1); 430 if (!pdev) { 431 dev_err(bus->dev, "failed to allocate dmic device\n"); 432 return -ENOMEM; 433 } 434 435 ret = platform_device_add(pdev); 436 if (ret) { 437 dev_err(bus->dev, "failed to add dmic device: %d\n", ret); 438 platform_device_put(pdev); 439 return ret; 440 } 441 skl->dmic_dev = pdev; 442 443 return 0; 444 } 445 446 static void skl_dmic_device_unregister(struct skl *skl) 447 { 448 if (skl->dmic_dev) 449 platform_device_unregister(skl->dmic_dev); 450 } 451 452 /* 453 * Probe the given codec address 454 */ 455 static int probe_codec(struct hdac_ext_bus *ebus, int addr) 456 { 457 struct hdac_bus *bus = ebus_to_hbus(ebus); 458 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 459 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 460 unsigned int res; 461 462 mutex_lock(&bus->cmd_mutex); 463 snd_hdac_bus_send_cmd(bus, cmd); 464 snd_hdac_bus_get_response(bus, addr, &res); 465 mutex_unlock(&bus->cmd_mutex); 466 if (res == -1) 467 return -EIO; 468 dev_dbg(bus->dev, "codec #%d probed OK\n", addr); 469 470 return snd_hdac_ext_bus_device_init(ebus, addr); 471 } 472 473 /* Codec initialization */ 474 static int skl_codec_create(struct hdac_ext_bus *ebus) 475 { 476 struct hdac_bus *bus = ebus_to_hbus(ebus); 477 int c, max_slots; 478 479 max_slots = HDA_MAX_CODECS; 480 481 /* First try to probe all given codec slots */ 482 for (c = 0; c < max_slots; c++) { 483 if ((bus->codec_mask & (1 << c))) { 484 if (probe_codec(ebus, c) < 0) { 485 /* 486 * Some BIOSen give you wrong codec addresses 487 * that don't exist 488 */ 489 dev_warn(bus->dev, 490 "Codec #%d probe error; disabling it...\n", c); 491 bus->codec_mask &= ~(1 << c); 492 /* 493 * More badly, accessing to a non-existing 494 * codec often screws up the controller bus, 495 * and disturbs the further communications. 496 * Thus if an error occurs during probing, 497 * better to reset the controller bus to get 498 * back to the sanity state. 499 */ 500 snd_hdac_bus_stop_chip(bus); 501 skl_init_chip(bus, true); 502 } 503 } 504 } 505 506 return 0; 507 } 508 509 static const struct hdac_bus_ops bus_core_ops = { 510 .command = snd_hdac_bus_send_cmd, 511 .get_response = snd_hdac_bus_get_response, 512 }; 513 514 /* 515 * constructor 516 */ 517 static int skl_create(struct pci_dev *pci, 518 const struct hdac_io_ops *io_ops, 519 struct skl **rskl) 520 { 521 struct skl *skl; 522 struct hdac_ext_bus *ebus; 523 524 int err; 525 526 *rskl = NULL; 527 528 err = pci_enable_device(pci); 529 if (err < 0) 530 return err; 531 532 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); 533 if (!skl) { 534 pci_disable_device(pci); 535 return -ENOMEM; 536 } 537 ebus = &skl->ebus; 538 snd_hdac_ext_bus_init(ebus, &pci->dev, &bus_core_ops, io_ops); 539 ebus->bus.use_posbuf = 1; 540 skl->pci = pci; 541 542 ebus->bus.bdl_pos_adj = 0; 543 544 *rskl = skl; 545 546 return 0; 547 } 548 549 static int skl_i915_init(struct hdac_bus *bus) 550 { 551 int err; 552 553 /* 554 * The HDMI codec is in GPU so we need to ensure that it is powered 555 * up and ready for probe 556 */ 557 err = snd_hdac_i915_init(bus); 558 if (err < 0) 559 return err; 560 561 err = snd_hdac_display_power(bus, true); 562 if (err < 0) { 563 dev_err(bus->dev, "Cannot turn on display power on i915\n"); 564 return err; 565 } 566 567 return err; 568 } 569 570 static int skl_first_init(struct hdac_ext_bus *ebus) 571 { 572 struct skl *skl = ebus_to_skl(ebus); 573 struct hdac_bus *bus = ebus_to_hbus(ebus); 574 struct pci_dev *pci = skl->pci; 575 int err; 576 unsigned short gcap; 577 int cp_streams, pb_streams, start_idx; 578 579 err = pci_request_regions(pci, "Skylake HD audio"); 580 if (err < 0) 581 return err; 582 583 bus->addr = pci_resource_start(pci, 0); 584 bus->remap_addr = pci_ioremap_bar(pci, 0); 585 if (bus->remap_addr == NULL) { 586 dev_err(bus->dev, "ioremap error\n"); 587 return -ENXIO; 588 } 589 590 snd_hdac_ext_bus_parse_capabilities(ebus); 591 592 if (skl_acquire_irq(ebus, 0) < 0) 593 return -EBUSY; 594 595 pci_set_master(pci); 596 synchronize_irq(bus->irq); 597 598 gcap = snd_hdac_chip_readw(bus, GCAP); 599 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); 600 601 /* allow 64bit DMA address if supported by H/W */ 602 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) { 603 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64)); 604 } else { 605 dma_set_mask(bus->dev, DMA_BIT_MASK(32)); 606 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32)); 607 } 608 609 /* read number of streams from GCAP register */ 610 cp_streams = (gcap >> 8) & 0x0f; 611 pb_streams = (gcap >> 12) & 0x0f; 612 613 if (!pb_streams && !cp_streams) 614 return -EIO; 615 616 ebus->num_streams = cp_streams + pb_streams; 617 618 /* initialize streams */ 619 snd_hdac_ext_stream_init_all 620 (ebus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); 621 start_idx = cp_streams; 622 snd_hdac_ext_stream_init_all 623 (ebus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); 624 625 err = snd_hdac_bus_alloc_stream_pages(bus); 626 if (err < 0) 627 return err; 628 629 /* initialize chip */ 630 skl_init_pci(skl); 631 632 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 633 err = skl_i915_init(bus); 634 if (err < 0) 635 return err; 636 } 637 638 skl_init_chip(bus, true); 639 640 /* codec detection */ 641 if (!bus->codec_mask) { 642 dev_info(bus->dev, "no hda codecs found!\n"); 643 } 644 645 return 0; 646 } 647 648 static int skl_probe(struct pci_dev *pci, 649 const struct pci_device_id *pci_id) 650 { 651 struct skl *skl; 652 struct hdac_ext_bus *ebus = NULL; 653 struct hdac_bus *bus = NULL; 654 struct hdac_ext_link *hlink = NULL; 655 int err; 656 657 /* we use ext core ops, so provide NULL for ops here */ 658 err = skl_create(pci, NULL, &skl); 659 if (err < 0) 660 return err; 661 662 ebus = &skl->ebus; 663 bus = ebus_to_hbus(ebus); 664 665 err = skl_first_init(ebus); 666 if (err < 0) 667 goto out_free; 668 669 skl->pci_id = pci->device; 670 671 device_disable_async_suspend(bus->dev); 672 673 skl->nhlt = skl_nhlt_init(bus->dev); 674 675 if (skl->nhlt == NULL) 676 goto out_free; 677 678 skl_nhlt_update_topology_bin(skl); 679 680 pci_set_drvdata(skl->pci, ebus); 681 682 skl_dmic_data.dmic_num = skl_get_dmic_geo(skl); 683 684 /* check if dsp is there */ 685 if (ebus->ppcap) { 686 err = skl_machine_device_register(skl, 687 (void *)pci_id->driver_data); 688 if (err < 0) 689 goto out_nhlt_free; 690 691 err = skl_init_dsp(skl); 692 if (err < 0) { 693 dev_dbg(bus->dev, "error failed to register dsp\n"); 694 goto out_mach_free; 695 } 696 skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge; 697 698 } 699 if (ebus->mlcap) 700 snd_hdac_ext_bus_get_ml_capabilities(ebus); 701 702 /* create device for soc dmic */ 703 err = skl_dmic_device_register(skl); 704 if (err < 0) 705 goto out_dsp_free; 706 707 /* register platform dai and controls */ 708 err = skl_platform_register(bus->dev); 709 if (err < 0) 710 goto out_dmic_free; 711 712 /* create codec instances */ 713 err = skl_codec_create(ebus); 714 if (err < 0) 715 goto out_unregister; 716 717 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 718 err = snd_hdac_display_power(bus, false); 719 if (err < 0) { 720 dev_err(bus->dev, "Cannot turn off display power on i915\n"); 721 return err; 722 } 723 } 724 725 /* 726 * we are done probling so decrement link counts 727 */ 728 list_for_each_entry(hlink, &ebus->hlink_list, list) 729 snd_hdac_ext_bus_link_put(ebus, hlink); 730 731 /* configure PM */ 732 pm_runtime_put_noidle(bus->dev); 733 pm_runtime_allow(bus->dev); 734 735 return 0; 736 737 out_unregister: 738 skl_platform_unregister(bus->dev); 739 out_dmic_free: 740 skl_dmic_device_unregister(skl); 741 out_dsp_free: 742 skl_free_dsp(skl); 743 out_mach_free: 744 skl_machine_device_unregister(skl); 745 out_nhlt_free: 746 skl_nhlt_free(skl->nhlt); 747 out_free: 748 skl->init_failed = 1; 749 skl_free(ebus); 750 751 return err; 752 } 753 754 static void skl_shutdown(struct pci_dev *pci) 755 { 756 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 757 struct hdac_bus *bus = ebus_to_hbus(ebus); 758 struct hdac_stream *s; 759 struct hdac_ext_stream *stream; 760 struct skl *skl; 761 762 if (ebus == NULL) 763 return; 764 765 skl = ebus_to_skl(ebus); 766 767 if (skl->init_failed) 768 return; 769 770 snd_hdac_ext_stop_streams(ebus); 771 list_for_each_entry(s, &bus->stream_list, list) { 772 stream = stream_to_hdac_ext_stream(s); 773 snd_hdac_ext_stream_decouple(ebus, stream, false); 774 } 775 776 snd_hdac_bus_stop_chip(bus); 777 } 778 779 static void skl_remove(struct pci_dev *pci) 780 { 781 struct hdac_ext_bus *ebus = pci_get_drvdata(pci); 782 struct skl *skl = ebus_to_skl(ebus); 783 784 release_firmware(skl->tplg); 785 786 if (pci_dev_run_wake(pci)) 787 pm_runtime_get_noresume(&pci->dev); 788 789 /* codec removal, invoke bus_device_remove */ 790 snd_hdac_ext_bus_device_remove(ebus); 791 792 skl_platform_unregister(&pci->dev); 793 skl_free_dsp(skl); 794 skl_machine_device_unregister(skl); 795 skl_dmic_device_unregister(skl); 796 skl_nhlt_free(skl->nhlt); 797 skl_free(ebus); 798 dev_set_drvdata(&pci->dev, NULL); 799 } 800 801 static struct sst_acpi_mach sst_skl_devdata[] = { 802 { "INT343A", "skl_alc286s_i2s", "intel/dsp_fw_release.bin", NULL, NULL, NULL }, 803 { "INT343B", "skl_n88l25_s4567", "intel/dsp_fw_release.bin", 804 NULL, NULL, &skl_dmic_data }, 805 { "MX98357A", "skl_n88l25_m98357a", "intel/dsp_fw_release.bin", 806 NULL, NULL, &skl_dmic_data }, 807 {} 808 }; 809 810 static struct sst_acpi_mach sst_bxtp_devdata[] = { 811 { "INT343A", "bxt_alc298s_i2s", "intel/dsp_fw_bxtn.bin", NULL, NULL, NULL }, 812 { "DLGS7219", "bxt_da7219_max98357a_i2s", "intel/dsp_fw_bxtn.bin", NULL, NULL, NULL }, 813 }; 814 815 static struct sst_acpi_mach sst_kbl_devdata[] = { 816 { "INT343A", "kbl_alc286s_i2s", "intel/dsp_fw_kbl.bin", NULL, NULL, NULL }, 817 { "INT343B", "kbl_n88l25_s4567", "intel/dsp_fw_kbl.bin", NULL, NULL, &skl_dmic_data }, 818 { "MX98357A", "kbl_n88l25_m98357a", "intel/dsp_fw_kbl.bin", NULL, NULL, &skl_dmic_data }, 819 {} 820 }; 821 822 /* PCI IDs */ 823 static const struct pci_device_id skl_ids[] = { 824 /* Sunrise Point-LP */ 825 { PCI_DEVICE(0x8086, 0x9d70), 826 .driver_data = (unsigned long)&sst_skl_devdata}, 827 /* BXT-P */ 828 { PCI_DEVICE(0x8086, 0x5a98), 829 .driver_data = (unsigned long)&sst_bxtp_devdata}, 830 /* KBL */ 831 { PCI_DEVICE(0x8086, 0x9D71), 832 .driver_data = (unsigned long)&sst_kbl_devdata}, 833 { 0, } 834 }; 835 MODULE_DEVICE_TABLE(pci, skl_ids); 836 837 /* pci_driver definition */ 838 static struct pci_driver skl_driver = { 839 .name = KBUILD_MODNAME, 840 .id_table = skl_ids, 841 .probe = skl_probe, 842 .remove = skl_remove, 843 .shutdown = skl_shutdown, 844 .driver = { 845 .pm = &skl_pm, 846 }, 847 }; 848 module_pci_driver(skl_driver); 849 850 MODULE_LICENSE("GPL v2"); 851 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver"); 852