xref: /openbmc/linux/sound/soc/intel/skylake/skl.c (revision 04b3c795)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  skl.c - Implementation of ASoC Intel SKL HD Audio driver
4  *
5  *  Copyright (C) 2014-2015 Intel Corp
6  *  Author: Jeeja KP <jeeja.kp@intel.com>
7  *
8  *  Derived mostly from Intel HDA driver with following copyrights:
9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10  *                     PeiSen Hou <pshou@realtek.com.tw>
11  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
12  *
13  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
14  */
15 
16 #include <linux/module.h>
17 #include <linux/pci.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/platform_device.h>
20 #include <linux/firmware.h>
21 #include <linux/delay.h>
22 #include <sound/pcm.h>
23 #include <sound/soc-acpi.h>
24 #include <sound/soc-acpi-intel-match.h>
25 #include <sound/hda_register.h>
26 #include <sound/hdaudio.h>
27 #include <sound/hda_i915.h>
28 #include <sound/hda_codec.h>
29 #include <sound/intel-nhlt.h>
30 #include <sound/intel-dsp-config.h>
31 #include "skl.h"
32 #include "skl-sst-dsp.h"
33 #include "skl-sst-ipc.h"
34 
35 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
36 #include "../../../soc/codecs/hdac_hda.h"
37 #endif
38 static int skl_pci_binding;
39 module_param_named(pci_binding, skl_pci_binding, int, 0444);
40 MODULE_PARM_DESC(pci_binding, "PCI binding (0=auto, 1=only legacy, 2=only asoc");
41 
42 /*
43  * initialize the PCI registers
44  */
45 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg,
46 			    unsigned char mask, unsigned char val)
47 {
48 	unsigned char data;
49 
50 	pci_read_config_byte(pci, reg, &data);
51 	data &= ~mask;
52 	data |= (val & mask);
53 	pci_write_config_byte(pci, reg, data);
54 }
55 
56 static void skl_init_pci(struct skl_dev *skl)
57 {
58 	struct hdac_bus *bus = skl_to_bus(skl);
59 
60 	/*
61 	 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
62 	 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
63 	 * Ensuring these bits are 0 clears playback static on some HD Audio
64 	 * codecs.
65 	 * The PCI register TCSEL is defined in the Intel manuals.
66 	 */
67 	dev_dbg(bus->dev, "Clearing TCSEL\n");
68 	skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0);
69 }
70 
71 static void update_pci_dword(struct pci_dev *pci,
72 			unsigned int reg, u32 mask, u32 val)
73 {
74 	u32 data = 0;
75 
76 	pci_read_config_dword(pci, reg, &data);
77 	data &= ~mask;
78 	data |= (val & mask);
79 	pci_write_config_dword(pci, reg, data);
80 }
81 
82 /*
83  * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits
84  *
85  * @dev: device pointer
86  * @enable: enable/disable flag
87  */
88 static void skl_enable_miscbdcge(struct device *dev, bool enable)
89 {
90 	struct pci_dev *pci = to_pci_dev(dev);
91 	u32 val;
92 
93 	val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0;
94 
95 	update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val);
96 }
97 
98 /**
99  * skl_clock_power_gating: Enable/Disable clock and power gating
100  *
101  * @dev: Device pointer
102  * @enable: Enable/Disable flag
103  */
104 static void skl_clock_power_gating(struct device *dev, bool enable)
105 {
106 	struct pci_dev *pci = to_pci_dev(dev);
107 	struct hdac_bus *bus = pci_get_drvdata(pci);
108 	u32 val;
109 
110 	/* Update PDCGE bit of CGCTL register */
111 	val = enable ? AZX_CGCTL_ADSPDCGE : 0;
112 	update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val);
113 
114 	/* Update L1SEN bit of EM2 register */
115 	val = enable ? AZX_REG_VS_EM2_L1SEN : 0;
116 	snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val);
117 
118 	/* Update ADSPPGD bit of PGCTL register */
119 	val = enable ? 0 : AZX_PGCTL_ADSPPGD;
120 	update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val);
121 }
122 
123 /*
124  * While performing reset, controller may not come back properly causing
125  * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset
126  * (init chip) and then again set CGCTL.MISCBDCGE to 1
127  */
128 static int skl_init_chip(struct hdac_bus *bus, bool full_reset)
129 {
130 	struct hdac_ext_link *hlink;
131 	int ret;
132 
133 	snd_hdac_set_codec_wakeup(bus, true);
134 	skl_enable_miscbdcge(bus->dev, false);
135 	ret = snd_hdac_bus_init_chip(bus, full_reset);
136 
137 	/* Reset stream-to-link mapping */
138 	list_for_each_entry(hlink, &bus->hlink_list, list)
139 		writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
140 
141 	skl_enable_miscbdcge(bus->dev, true);
142 	snd_hdac_set_codec_wakeup(bus, false);
143 
144 	return ret;
145 }
146 
147 void skl_update_d0i3c(struct device *dev, bool enable)
148 {
149 	struct pci_dev *pci = to_pci_dev(dev);
150 	struct hdac_bus *bus = pci_get_drvdata(pci);
151 	u8 reg;
152 	int timeout = 50;
153 
154 	reg = snd_hdac_chip_readb(bus, VS_D0I3C);
155 	/* Do not write to D0I3C until command in progress bit is cleared */
156 	while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {
157 		udelay(10);
158 		reg = snd_hdac_chip_readb(bus, VS_D0I3C);
159 	}
160 
161 	/* Highly unlikely. But if it happens, flag error explicitly */
162 	if (!timeout) {
163 		dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n");
164 		return;
165 	}
166 
167 	if (enable)
168 		reg = reg | AZX_REG_VS_D0I3C_I3;
169 	else
170 		reg = reg & (~AZX_REG_VS_D0I3C_I3);
171 
172 	snd_hdac_chip_writeb(bus, VS_D0I3C, reg);
173 
174 	timeout = 50;
175 	/* Wait for cmd in progress to be cleared before exiting the function */
176 	reg = snd_hdac_chip_readb(bus, VS_D0I3C);
177 	while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {
178 		udelay(10);
179 		reg = snd_hdac_chip_readb(bus, VS_D0I3C);
180 	}
181 
182 	/* Highly unlikely. But if it happens, flag error explicitly */
183 	if (!timeout) {
184 		dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n");
185 		return;
186 	}
187 
188 	dev_dbg(bus->dev, "D0I3C register = 0x%x\n",
189 			snd_hdac_chip_readb(bus, VS_D0I3C));
190 }
191 
192 /**
193  * skl_dum_set - set DUM bit in EM2 register
194  * @bus: HD-audio core bus
195  *
196  * Addresses incorrect position reporting for capture streams.
197  * Used on device power up.
198  */
199 static void skl_dum_set(struct hdac_bus *bus)
200 {
201 	/* For the DUM bit to be set, CRST needs to be out of reset state */
202 	if (!(snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)) {
203 		skl_enable_miscbdcge(bus->dev, false);
204 		snd_hdac_bus_exit_link_reset(bus);
205 		skl_enable_miscbdcge(bus->dev, true);
206 	}
207 
208 	snd_hdac_chip_updatel(bus, VS_EM2, AZX_VS_EM2_DUM, AZX_VS_EM2_DUM);
209 }
210 
211 /* called from IRQ */
212 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)
213 {
214 	snd_pcm_period_elapsed(hstr->substream);
215 }
216 
217 static irqreturn_t skl_interrupt(int irq, void *dev_id)
218 {
219 	struct hdac_bus *bus = dev_id;
220 	u32 status;
221 
222 	if (!pm_runtime_active(bus->dev))
223 		return IRQ_NONE;
224 
225 	spin_lock(&bus->reg_lock);
226 
227 	status = snd_hdac_chip_readl(bus, INTSTS);
228 	if (status == 0 || status == 0xffffffff) {
229 		spin_unlock(&bus->reg_lock);
230 		return IRQ_NONE;
231 	}
232 
233 	/* clear rirb int */
234 	status = snd_hdac_chip_readb(bus, RIRBSTS);
235 	if (status & RIRB_INT_MASK) {
236 		if (status & RIRB_INT_RESPONSE)
237 			snd_hdac_bus_update_rirb(bus);
238 		snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
239 	}
240 
241 	spin_unlock(&bus->reg_lock);
242 
243 	return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
244 }
245 
246 static irqreturn_t skl_threaded_handler(int irq, void *dev_id)
247 {
248 	struct hdac_bus *bus = dev_id;
249 	u32 status;
250 
251 	status = snd_hdac_chip_readl(bus, INTSTS);
252 
253 	snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update);
254 
255 	return IRQ_HANDLED;
256 }
257 
258 static int skl_acquire_irq(struct hdac_bus *bus, int do_disconnect)
259 {
260 	struct skl_dev *skl = bus_to_skl(bus);
261 	int ret;
262 
263 	ret = request_threaded_irq(skl->pci->irq, skl_interrupt,
264 			skl_threaded_handler,
265 			IRQF_SHARED,
266 			KBUILD_MODNAME, bus);
267 	if (ret) {
268 		dev_err(bus->dev,
269 			"unable to grab IRQ %d, disabling device\n",
270 			skl->pci->irq);
271 		return ret;
272 	}
273 
274 	bus->irq = skl->pci->irq;
275 	pci_intx(skl->pci, 1);
276 
277 	return 0;
278 }
279 
280 static int skl_suspend_late(struct device *dev)
281 {
282 	struct pci_dev *pci = to_pci_dev(dev);
283 	struct hdac_bus *bus = pci_get_drvdata(pci);
284 	struct skl_dev *skl = bus_to_skl(bus);
285 
286 	return skl_suspend_late_dsp(skl);
287 }
288 
289 #ifdef CONFIG_PM
290 static int _skl_suspend(struct hdac_bus *bus)
291 {
292 	struct skl_dev *skl = bus_to_skl(bus);
293 	struct pci_dev *pci = to_pci_dev(bus->dev);
294 	int ret;
295 
296 	snd_hdac_ext_bus_link_power_down_all(bus);
297 
298 	ret = skl_suspend_dsp(skl);
299 	if (ret < 0)
300 		return ret;
301 
302 	snd_hdac_bus_stop_chip(bus);
303 	update_pci_dword(pci, AZX_PCIREG_PGCTL,
304 		AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK);
305 	skl_enable_miscbdcge(bus->dev, false);
306 	snd_hdac_bus_enter_link_reset(bus);
307 	skl_enable_miscbdcge(bus->dev, true);
308 	skl_cleanup_resources(skl);
309 
310 	return 0;
311 }
312 
313 static int _skl_resume(struct hdac_bus *bus)
314 {
315 	struct skl_dev *skl = bus_to_skl(bus);
316 
317 	skl_init_pci(skl);
318 	skl_dum_set(bus);
319 	skl_init_chip(bus, true);
320 
321 	return skl_resume_dsp(skl);
322 }
323 #endif
324 
325 #ifdef CONFIG_PM_SLEEP
326 /*
327  * power management
328  */
329 static int skl_suspend(struct device *dev)
330 {
331 	struct pci_dev *pci = to_pci_dev(dev);
332 	struct hdac_bus *bus = pci_get_drvdata(pci);
333 	struct skl_dev *skl  = bus_to_skl(bus);
334 	int ret;
335 
336 	/*
337 	 * Do not suspend if streams which are marked ignore suspend are
338 	 * running, we need to save the state for these and continue
339 	 */
340 	if (skl->supend_active) {
341 		/* turn off the links and stop the CORB/RIRB DMA if it is On */
342 		snd_hdac_ext_bus_link_power_down_all(bus);
343 
344 		if (bus->cmd_dma_state)
345 			snd_hdac_bus_stop_cmd_io(bus);
346 
347 		enable_irq_wake(bus->irq);
348 		pci_save_state(pci);
349 	} else {
350 		ret = _skl_suspend(bus);
351 		if (ret < 0)
352 			return ret;
353 		skl->fw_loaded = false;
354 	}
355 
356 	return 0;
357 }
358 
359 static int skl_resume(struct device *dev)
360 {
361 	struct pci_dev *pci = to_pci_dev(dev);
362 	struct hdac_bus *bus = pci_get_drvdata(pci);
363 	struct skl_dev *skl  = bus_to_skl(bus);
364 	struct hdac_ext_link *hlink;
365 	int ret;
366 
367 	/*
368 	 * resume only when we are not in suspend active, otherwise need to
369 	 * restore the device
370 	 */
371 	if (skl->supend_active) {
372 		pci_restore_state(pci);
373 		snd_hdac_ext_bus_link_power_up_all(bus);
374 		disable_irq_wake(bus->irq);
375 		/*
376 		 * turn On the links which are On before active suspend
377 		 * and start the CORB/RIRB DMA if On before
378 		 * active suspend.
379 		 */
380 		list_for_each_entry(hlink, &bus->hlink_list, list) {
381 			if (hlink->ref_count)
382 				snd_hdac_ext_bus_link_power_up(hlink);
383 		}
384 
385 		ret = 0;
386 		if (bus->cmd_dma_state)
387 			snd_hdac_bus_init_cmd_io(bus);
388 	} else {
389 		ret = _skl_resume(bus);
390 
391 		/* turn off the links which are off before suspend */
392 		list_for_each_entry(hlink, &bus->hlink_list, list) {
393 			if (!hlink->ref_count)
394 				snd_hdac_ext_bus_link_power_down(hlink);
395 		}
396 
397 		if (!bus->cmd_dma_state)
398 			snd_hdac_bus_stop_cmd_io(bus);
399 	}
400 
401 	return ret;
402 }
403 #endif /* CONFIG_PM_SLEEP */
404 
405 #ifdef CONFIG_PM
406 static int skl_runtime_suspend(struct device *dev)
407 {
408 	struct pci_dev *pci = to_pci_dev(dev);
409 	struct hdac_bus *bus = pci_get_drvdata(pci);
410 
411 	dev_dbg(bus->dev, "in %s\n", __func__);
412 
413 	return _skl_suspend(bus);
414 }
415 
416 static int skl_runtime_resume(struct device *dev)
417 {
418 	struct pci_dev *pci = to_pci_dev(dev);
419 	struct hdac_bus *bus = pci_get_drvdata(pci);
420 
421 	dev_dbg(bus->dev, "in %s\n", __func__);
422 
423 	return _skl_resume(bus);
424 }
425 #endif /* CONFIG_PM */
426 
427 static const struct dev_pm_ops skl_pm = {
428 	SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume)
429 	SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL)
430 	.suspend_late = skl_suspend_late,
431 };
432 
433 /*
434  * destructor
435  */
436 static int skl_free(struct hdac_bus *bus)
437 {
438 	struct skl_dev *skl  = bus_to_skl(bus);
439 
440 	skl->init_done = 0; /* to be sure */
441 
442 	snd_hdac_ext_stop_streams(bus);
443 
444 	if (bus->irq >= 0)
445 		free_irq(bus->irq, (void *)bus);
446 	snd_hdac_bus_free_stream_pages(bus);
447 	snd_hdac_stream_free_all(bus);
448 	snd_hdac_link_free_all(bus);
449 
450 	if (bus->remap_addr)
451 		iounmap(bus->remap_addr);
452 
453 	pci_release_regions(skl->pci);
454 	pci_disable_device(skl->pci);
455 
456 	snd_hdac_ext_bus_exit(bus);
457 
458 	if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
459 		snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
460 		snd_hdac_i915_exit(bus);
461 	}
462 
463 	return 0;
464 }
465 
466 /*
467  * For each ssp there are 3 clocks (mclk/sclk/sclkfs).
468  * e.g. for ssp0, clocks will be named as
469  *      "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs"
470  * So for skl+, there are 6 ssps, so 18 clocks will be created.
471  */
472 static struct skl_ssp_clk skl_ssp_clks[] = {
473 	{.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"},
474 	{.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"},
475 	{.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"},
476 	{.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"},
477 	{.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"},
478 						{.name = "ssp2_sclkfs"},
479 	{.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"},
480 						{.name = "ssp5_sclkfs"},
481 };
482 
483 static struct snd_soc_acpi_mach *skl_find_hda_machine(struct skl_dev *skl,
484 					struct snd_soc_acpi_mach *machines)
485 {
486 	struct snd_soc_acpi_mach *mach;
487 
488 	/* point to common table */
489 	mach = snd_soc_acpi_intel_hda_machines;
490 
491 	/* all entries in the machine table use the same firmware */
492 	mach->fw_filename = machines->fw_filename;
493 
494 	return mach;
495 }
496 
497 static int skl_find_machine(struct skl_dev *skl, void *driver_data)
498 {
499 	struct hdac_bus *bus = skl_to_bus(skl);
500 	struct snd_soc_acpi_mach *mach = driver_data;
501 	struct skl_machine_pdata *pdata;
502 
503 	mach = snd_soc_acpi_find_machine(mach);
504 	if (!mach) {
505 		dev_dbg(bus->dev, "No matching I2S machine driver found\n");
506 		mach = skl_find_hda_machine(skl, driver_data);
507 		if (!mach) {
508 			dev_err(bus->dev, "No matching machine driver found\n");
509 			return -ENODEV;
510 		}
511 	}
512 
513 	skl->mach = mach;
514 	skl->fw_name = mach->fw_filename;
515 	pdata = mach->pdata;
516 
517 	if (pdata) {
518 		skl->use_tplg_pcm = pdata->use_tplg_pcm;
519 		mach->mach_params.dmic_num =
520 			intel_nhlt_get_dmic_geo(&skl->pci->dev,
521 						skl->nhlt);
522 	}
523 
524 	return 0;
525 }
526 
527 static int skl_machine_device_register(struct skl_dev *skl)
528 {
529 	struct snd_soc_acpi_mach *mach = skl->mach;
530 	struct hdac_bus *bus = skl_to_bus(skl);
531 	struct platform_device *pdev;
532 	int ret;
533 
534 	pdev = platform_device_alloc(mach->drv_name, -1);
535 	if (pdev == NULL) {
536 		dev_err(bus->dev, "platform device alloc failed\n");
537 		return -EIO;
538 	}
539 
540 	mach->mach_params.platform = dev_name(bus->dev);
541 	mach->mach_params.codec_mask = bus->codec_mask;
542 
543 	ret = platform_device_add_data(pdev, (const void *)mach, sizeof(*mach));
544 	if (ret) {
545 		dev_err(bus->dev, "failed to add machine device platform data\n");
546 		platform_device_put(pdev);
547 		return ret;
548 	}
549 
550 	ret = platform_device_add(pdev);
551 	if (ret) {
552 		dev_err(bus->dev, "failed to add machine device\n");
553 		platform_device_put(pdev);
554 		return -EIO;
555 	}
556 
557 
558 	skl->i2s_dev = pdev;
559 
560 	return 0;
561 }
562 
563 static void skl_machine_device_unregister(struct skl_dev *skl)
564 {
565 	if (skl->i2s_dev)
566 		platform_device_unregister(skl->i2s_dev);
567 }
568 
569 static int skl_dmic_device_register(struct skl_dev *skl)
570 {
571 	struct hdac_bus *bus = skl_to_bus(skl);
572 	struct platform_device *pdev;
573 	int ret;
574 
575 	/* SKL has one dmic port, so allocate dmic device for this */
576 	pdev = platform_device_alloc("dmic-codec", -1);
577 	if (!pdev) {
578 		dev_err(bus->dev, "failed to allocate dmic device\n");
579 		return -ENOMEM;
580 	}
581 
582 	ret = platform_device_add(pdev);
583 	if (ret) {
584 		dev_err(bus->dev, "failed to add dmic device: %d\n", ret);
585 		platform_device_put(pdev);
586 		return ret;
587 	}
588 	skl->dmic_dev = pdev;
589 
590 	return 0;
591 }
592 
593 static void skl_dmic_device_unregister(struct skl_dev *skl)
594 {
595 	if (skl->dmic_dev)
596 		platform_device_unregister(skl->dmic_dev);
597 }
598 
599 static struct skl_clk_parent_src skl_clk_src[] = {
600 	{ .clk_id = SKL_XTAL, .name = "xtal" },
601 	{ .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 },
602 	{ .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 },
603 };
604 
605 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id)
606 {
607 	unsigned int i;
608 
609 	for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) {
610 		if (skl_clk_src[i].clk_id == clk_id)
611 			return &skl_clk_src[i];
612 	}
613 
614 	return NULL;
615 }
616 
617 static void init_skl_xtal_rate(int pci_id)
618 {
619 	switch (pci_id) {
620 	case 0x9d70:
621 	case 0x9d71:
622 		skl_clk_src[0].rate = 24000000;
623 		return;
624 
625 	default:
626 		skl_clk_src[0].rate = 19200000;
627 		return;
628 	}
629 }
630 
631 static int skl_clock_device_register(struct skl_dev *skl)
632 {
633 	struct platform_device_info pdevinfo = {NULL};
634 	struct skl_clk_pdata *clk_pdata;
635 
636 	if (!skl->nhlt)
637 		return 0;
638 
639 	clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata),
640 							GFP_KERNEL);
641 	if (!clk_pdata)
642 		return -ENOMEM;
643 
644 	init_skl_xtal_rate(skl->pci->device);
645 
646 	clk_pdata->parent_clks = skl_clk_src;
647 	clk_pdata->ssp_clks = skl_ssp_clks;
648 	clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks);
649 
650 	/* Query NHLT to fill the rates and parent */
651 	skl_get_clks(skl, clk_pdata->ssp_clks);
652 	clk_pdata->pvt_data = skl;
653 
654 	/* Register Platform device */
655 	pdevinfo.parent = &skl->pci->dev;
656 	pdevinfo.id = -1;
657 	pdevinfo.name = "skl-ssp-clk";
658 	pdevinfo.data = clk_pdata;
659 	pdevinfo.size_data = sizeof(*clk_pdata);
660 	skl->clk_dev = platform_device_register_full(&pdevinfo);
661 	return PTR_ERR_OR_ZERO(skl->clk_dev);
662 }
663 
664 static void skl_clock_device_unregister(struct skl_dev *skl)
665 {
666 	if (skl->clk_dev)
667 		platform_device_unregister(skl->clk_dev);
668 }
669 
670 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
671 
672 #define IDISP_INTEL_VENDOR_ID	0x80860000
673 
674 /*
675  * load the legacy codec driver
676  */
677 static void load_codec_module(struct hda_codec *codec)
678 {
679 #ifdef MODULE
680 	char modalias[MODULE_NAME_LEN];
681 	const char *mod = NULL;
682 
683 	snd_hdac_codec_modalias(&codec->core, modalias, sizeof(modalias));
684 	mod = modalias;
685 	dev_dbg(&codec->core.dev, "loading %s codec module\n", mod);
686 	request_module(mod);
687 #endif
688 }
689 
690 #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */
691 
692 /*
693  * Probe the given codec address
694  */
695 static int probe_codec(struct hdac_bus *bus, int addr)
696 {
697 	unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
698 		(AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
699 	unsigned int res = -1;
700 	struct skl_dev *skl = bus_to_skl(bus);
701 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
702 	struct hdac_hda_priv *hda_codec;
703 	int err;
704 #endif
705 	struct hdac_device *hdev;
706 
707 	mutex_lock(&bus->cmd_mutex);
708 	snd_hdac_bus_send_cmd(bus, cmd);
709 	snd_hdac_bus_get_response(bus, addr, &res);
710 	mutex_unlock(&bus->cmd_mutex);
711 	if (res == -1)
712 		return -EIO;
713 	dev_dbg(bus->dev, "codec #%d probed OK: %x\n", addr, res);
714 
715 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
716 	hda_codec = devm_kzalloc(&skl->pci->dev, sizeof(*hda_codec),
717 				 GFP_KERNEL);
718 	if (!hda_codec)
719 		return -ENOMEM;
720 
721 	hda_codec->codec.bus = skl_to_hbus(skl);
722 	hdev = &hda_codec->codec.core;
723 
724 	err = snd_hdac_ext_bus_device_init(bus, addr, hdev);
725 	if (err < 0)
726 		return err;
727 
728 	/* use legacy bus only for HDA codecs, idisp uses ext bus */
729 	if ((res & 0xFFFF0000) != IDISP_INTEL_VENDOR_ID) {
730 		hdev->type = HDA_DEV_LEGACY;
731 		load_codec_module(&hda_codec->codec);
732 	}
733 	return 0;
734 #else
735 	hdev = devm_kzalloc(&skl->pci->dev, sizeof(*hdev), GFP_KERNEL);
736 	if (!hdev)
737 		return -ENOMEM;
738 
739 	return snd_hdac_ext_bus_device_init(bus, addr, hdev);
740 #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */
741 }
742 
743 /* Codec initialization */
744 static void skl_codec_create(struct hdac_bus *bus)
745 {
746 	int c, max_slots;
747 
748 	max_slots = HDA_MAX_CODECS;
749 
750 	/* First try to probe all given codec slots */
751 	for (c = 0; c < max_slots; c++) {
752 		if ((bus->codec_mask & (1 << c))) {
753 			if (probe_codec(bus, c) < 0) {
754 				/*
755 				 * Some BIOSen give you wrong codec addresses
756 				 * that don't exist
757 				 */
758 				dev_warn(bus->dev,
759 					 "Codec #%d probe error; disabling it...\n", c);
760 				bus->codec_mask &= ~(1 << c);
761 				/*
762 				 * More badly, accessing to a non-existing
763 				 * codec often screws up the controller bus,
764 				 * and disturbs the further communications.
765 				 * Thus if an error occurs during probing,
766 				 * better to reset the controller bus to get
767 				 * back to the sanity state.
768 				 */
769 				snd_hdac_bus_stop_chip(bus);
770 				skl_init_chip(bus, true);
771 			}
772 		}
773 	}
774 }
775 
776 static int skl_i915_init(struct hdac_bus *bus)
777 {
778 	int err;
779 
780 	/*
781 	 * The HDMI codec is in GPU so we need to ensure that it is powered
782 	 * up and ready for probe
783 	 */
784 	err = snd_hdac_i915_init(bus);
785 	if (err < 0)
786 		return err;
787 
788 	snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true);
789 
790 	return 0;
791 }
792 
793 static void skl_probe_work(struct work_struct *work)
794 {
795 	struct skl_dev *skl = container_of(work, struct skl_dev, probe_work);
796 	struct hdac_bus *bus = skl_to_bus(skl);
797 	struct hdac_ext_link *hlink;
798 	int err;
799 
800 	if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
801 		err = skl_i915_init(bus);
802 		if (err < 0)
803 			return;
804 	}
805 
806 	skl_init_pci(skl);
807 	skl_dum_set(bus);
808 
809 	err = skl_init_chip(bus, true);
810 	if (err < 0) {
811 		dev_err(bus->dev, "Init chip failed with err: %d\n", err);
812 		goto out_err;
813 	}
814 
815 	/* codec detection */
816 	if (!bus->codec_mask)
817 		dev_info(bus->dev, "no hda codecs found!\n");
818 
819 	/* create codec instances */
820 	skl_codec_create(bus);
821 
822 	/* register platform dai and controls */
823 	err = skl_platform_register(bus->dev);
824 	if (err < 0) {
825 		dev_err(bus->dev, "platform register failed: %d\n", err);
826 		goto out_err;
827 	}
828 
829 	err = skl_machine_device_register(skl);
830 	if (err < 0) {
831 		dev_err(bus->dev, "machine register failed: %d\n", err);
832 		goto out_err;
833 	}
834 
835 	/*
836 	 * we are done probing so decrement link counts
837 	 */
838 	list_for_each_entry(hlink, &bus->hlink_list, list)
839 		snd_hdac_ext_bus_link_put(bus, hlink);
840 
841 	if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
842 		snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
843 
844 	/* configure PM */
845 	pm_runtime_put_noidle(bus->dev);
846 	pm_runtime_allow(bus->dev);
847 	skl->init_done = 1;
848 
849 	return;
850 
851 out_err:
852 	if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
853 		snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
854 }
855 
856 /*
857  * constructor
858  */
859 static int skl_create(struct pci_dev *pci,
860 		      struct skl_dev **rskl)
861 {
862 	struct hdac_ext_bus_ops *ext_ops = NULL;
863 	struct skl_dev *skl;
864 	struct hdac_bus *bus;
865 	struct hda_bus *hbus;
866 	int err;
867 
868 	*rskl = NULL;
869 
870 	err = pci_enable_device(pci);
871 	if (err < 0)
872 		return err;
873 
874 	skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL);
875 	if (!skl) {
876 		pci_disable_device(pci);
877 		return -ENOMEM;
878 	}
879 
880 	hbus = skl_to_hbus(skl);
881 	bus = skl_to_bus(skl);
882 
883 	INIT_LIST_HEAD(&skl->ppl_list);
884 	INIT_LIST_HEAD(&skl->bind_list);
885 
886 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
887 	ext_ops = snd_soc_hdac_hda_get_ops();
888 #endif
889 	snd_hdac_ext_bus_init(bus, &pci->dev, NULL, ext_ops);
890 	bus->use_posbuf = 1;
891 	skl->pci = pci;
892 	INIT_WORK(&skl->probe_work, skl_probe_work);
893 	bus->bdl_pos_adj = 0;
894 
895 	mutex_init(&hbus->prepare_mutex);
896 	hbus->pci = pci;
897 	hbus->mixer_assigned = -1;
898 	hbus->modelname = "sklbus";
899 
900 	*rskl = skl;
901 
902 	return 0;
903 }
904 
905 static int skl_first_init(struct hdac_bus *bus)
906 {
907 	struct skl_dev *skl = bus_to_skl(bus);
908 	struct pci_dev *pci = skl->pci;
909 	int err;
910 	unsigned short gcap;
911 	int cp_streams, pb_streams, start_idx;
912 
913 	err = pci_request_regions(pci, "Skylake HD audio");
914 	if (err < 0)
915 		return err;
916 
917 	bus->addr = pci_resource_start(pci, 0);
918 	bus->remap_addr = pci_ioremap_bar(pci, 0);
919 	if (bus->remap_addr == NULL) {
920 		dev_err(bus->dev, "ioremap error\n");
921 		return -ENXIO;
922 	}
923 
924 	snd_hdac_bus_parse_capabilities(bus);
925 
926 	/* check if PPCAP exists */
927 	if (!bus->ppcap) {
928 		dev_err(bus->dev, "bus ppcap not set, HDaudio or DSP not present?\n");
929 		return -ENODEV;
930 	}
931 
932 	if (skl_acquire_irq(bus, 0) < 0)
933 		return -EBUSY;
934 
935 	pci_set_master(pci);
936 	synchronize_irq(bus->irq);
937 
938 	gcap = snd_hdac_chip_readw(bus, GCAP);
939 	dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap);
940 
941 	/* read number of streams from GCAP register */
942 	cp_streams = (gcap >> 8) & 0x0f;
943 	pb_streams = (gcap >> 12) & 0x0f;
944 
945 	if (!pb_streams && !cp_streams) {
946 		dev_err(bus->dev, "no streams found in GCAP definitions?\n");
947 		return -EIO;
948 	}
949 
950 	bus->num_streams = cp_streams + pb_streams;
951 
952 	/* allow 64bit DMA address if supported by H/W */
953 	if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) {
954 		dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64));
955 	} else {
956 		dma_set_mask(bus->dev, DMA_BIT_MASK(32));
957 		dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32));
958 	}
959 
960 	/* initialize streams */
961 	snd_hdac_ext_stream_init_all
962 		(bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE);
963 	start_idx = cp_streams;
964 	snd_hdac_ext_stream_init_all
965 		(bus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK);
966 
967 	err = snd_hdac_bus_alloc_stream_pages(bus);
968 	if (err < 0)
969 		return err;
970 
971 	return 0;
972 }
973 
974 static int skl_probe(struct pci_dev *pci,
975 		     const struct pci_device_id *pci_id)
976 {
977 	struct skl_dev *skl;
978 	struct hdac_bus *bus = NULL;
979 	int err;
980 
981 	switch (skl_pci_binding) {
982 	case SND_SKL_PCI_BIND_AUTO:
983 		err = snd_intel_dsp_driver_probe(pci);
984 		if (err != SND_INTEL_DSP_DRIVER_ANY &&
985 		    err != SND_INTEL_DSP_DRIVER_SST)
986 			return -ENODEV;
987 		break;
988 	case SND_SKL_PCI_BIND_LEGACY:
989 		dev_info(&pci->dev, "Module parameter forced binding with HDaudio legacy, aborting probe\n");
990 		return -ENODEV;
991 	case SND_SKL_PCI_BIND_ASOC:
992 		dev_info(&pci->dev, "Module parameter forced binding with SKL driver, bypassed detection logic\n");
993 		break;
994 	default:
995 		dev_err(&pci->dev, "invalid value for skl_pci_binding module parameter, ignored\n");
996 		break;
997 	}
998 
999 	/* we use ext core ops, so provide NULL for ops here */
1000 	err = skl_create(pci, &skl);
1001 	if (err < 0)
1002 		return err;
1003 
1004 	bus = skl_to_bus(skl);
1005 
1006 	err = skl_first_init(bus);
1007 	if (err < 0) {
1008 		dev_err(bus->dev, "skl_first_init failed with err: %d\n", err);
1009 		goto out_free;
1010 	}
1011 
1012 	skl->pci_id = pci->device;
1013 
1014 	device_disable_async_suspend(bus->dev);
1015 
1016 	skl->nhlt = intel_nhlt_init(bus->dev);
1017 
1018 	if (skl->nhlt == NULL) {
1019 #if !IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
1020 		dev_err(bus->dev, "no nhlt info found\n");
1021 		err = -ENODEV;
1022 		goto out_free;
1023 #else
1024 		dev_warn(bus->dev, "no nhlt info found, continuing to try to enable HDaudio codec\n");
1025 #endif
1026 	} else {
1027 
1028 		err = skl_nhlt_create_sysfs(skl);
1029 		if (err < 0) {
1030 			dev_err(bus->dev, "skl_nhlt_create_sysfs failed with err: %d\n", err);
1031 			goto out_nhlt_free;
1032 		}
1033 
1034 		skl_nhlt_update_topology_bin(skl);
1035 
1036 		/* create device for dsp clk */
1037 		err = skl_clock_device_register(skl);
1038 		if (err < 0) {
1039 			dev_err(bus->dev, "skl_clock_device_register failed with err: %d\n", err);
1040 			goto out_clk_free;
1041 		}
1042 	}
1043 
1044 	pci_set_drvdata(skl->pci, bus);
1045 
1046 
1047 	err = skl_find_machine(skl, (void *)pci_id->driver_data);
1048 	if (err < 0) {
1049 		dev_err(bus->dev, "skl_find_machine failed with err: %d\n", err);
1050 		goto out_nhlt_free;
1051 	}
1052 
1053 	err = skl_init_dsp(skl);
1054 	if (err < 0) {
1055 		dev_dbg(bus->dev, "error failed to register dsp\n");
1056 		goto out_nhlt_free;
1057 	}
1058 	skl->enable_miscbdcge = skl_enable_miscbdcge;
1059 	skl->clock_power_gating = skl_clock_power_gating;
1060 
1061 	if (bus->mlcap)
1062 		snd_hdac_ext_bus_get_ml_capabilities(bus);
1063 
1064 	/* create device for soc dmic */
1065 	err = skl_dmic_device_register(skl);
1066 	if (err < 0) {
1067 		dev_err(bus->dev, "skl_dmic_device_register failed with err: %d\n", err);
1068 		goto out_dsp_free;
1069 	}
1070 
1071 	schedule_work(&skl->probe_work);
1072 
1073 	return 0;
1074 
1075 out_dsp_free:
1076 	skl_free_dsp(skl);
1077 out_clk_free:
1078 	skl_clock_device_unregister(skl);
1079 out_nhlt_free:
1080 	if (skl->nhlt)
1081 		intel_nhlt_free(skl->nhlt);
1082 out_free:
1083 	skl_free(bus);
1084 
1085 	return err;
1086 }
1087 
1088 static void skl_shutdown(struct pci_dev *pci)
1089 {
1090 	struct hdac_bus *bus = pci_get_drvdata(pci);
1091 	struct hdac_stream *s;
1092 	struct hdac_ext_stream *stream;
1093 	struct skl_dev *skl;
1094 
1095 	if (!bus)
1096 		return;
1097 
1098 	skl = bus_to_skl(bus);
1099 
1100 	if (!skl->init_done)
1101 		return;
1102 
1103 	snd_hdac_ext_stop_streams(bus);
1104 	list_for_each_entry(s, &bus->stream_list, list) {
1105 		stream = stream_to_hdac_ext_stream(s);
1106 		snd_hdac_ext_stream_decouple(bus, stream, false);
1107 	}
1108 
1109 	snd_hdac_bus_stop_chip(bus);
1110 }
1111 
1112 static void skl_remove(struct pci_dev *pci)
1113 {
1114 	struct hdac_bus *bus = pci_get_drvdata(pci);
1115 	struct skl_dev *skl = bus_to_skl(bus);
1116 
1117 	cancel_work_sync(&skl->probe_work);
1118 
1119 	pm_runtime_get_noresume(&pci->dev);
1120 
1121 	/* codec removal, invoke bus_device_remove */
1122 	snd_hdac_ext_bus_device_remove(bus);
1123 
1124 	skl_platform_unregister(&pci->dev);
1125 	skl_free_dsp(skl);
1126 	skl_machine_device_unregister(skl);
1127 	skl_dmic_device_unregister(skl);
1128 	skl_clock_device_unregister(skl);
1129 	skl_nhlt_remove_sysfs(skl);
1130 	if (skl->nhlt)
1131 		intel_nhlt_free(skl->nhlt);
1132 	skl_free(bus);
1133 	dev_set_drvdata(&pci->dev, NULL);
1134 }
1135 
1136 /* PCI IDs */
1137 static const struct pci_device_id skl_ids[] = {
1138 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKL)
1139 	/* Sunrise Point-LP */
1140 	{ PCI_DEVICE(0x8086, 0x9d70),
1141 		.driver_data = (unsigned long)&snd_soc_acpi_intel_skl_machines},
1142 #endif
1143 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_APL)
1144 	/* BXT-P */
1145 	{ PCI_DEVICE(0x8086, 0x5a98),
1146 		.driver_data = (unsigned long)&snd_soc_acpi_intel_bxt_machines},
1147 #endif
1148 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_KBL)
1149 	/* KBL */
1150 	{ PCI_DEVICE(0x8086, 0x9D71),
1151 		.driver_data = (unsigned long)&snd_soc_acpi_intel_kbl_machines},
1152 #endif
1153 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_GLK)
1154 	/* GLK */
1155 	{ PCI_DEVICE(0x8086, 0x3198),
1156 		.driver_data = (unsigned long)&snd_soc_acpi_intel_glk_machines},
1157 #endif
1158 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CNL)
1159 	/* CNL */
1160 	{ PCI_DEVICE(0x8086, 0x9dc8),
1161 		.driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
1162 #endif
1163 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CFL)
1164 	/* CFL */
1165 	{ PCI_DEVICE(0x8086, 0xa348),
1166 		.driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
1167 #endif
1168 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_LP)
1169 	/* CML-LP */
1170 	{ PCI_DEVICE(0x8086, 0x02c8),
1171 		.driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
1172 #endif
1173 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_H)
1174 	/* CML-H */
1175 	{ PCI_DEVICE(0x8086, 0x06c8),
1176 		.driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
1177 #endif
1178 	{ 0, }
1179 };
1180 MODULE_DEVICE_TABLE(pci, skl_ids);
1181 
1182 /* pci_driver definition */
1183 static struct pci_driver skl_driver = {
1184 	.name = KBUILD_MODNAME,
1185 	.id_table = skl_ids,
1186 	.probe = skl_probe,
1187 	.remove = skl_remove,
1188 	.shutdown = skl_shutdown,
1189 	.driver = {
1190 		.pm = &skl_pm,
1191 	},
1192 };
1193 module_pci_driver(skl_driver);
1194 
1195 MODULE_LICENSE("GPL v2");
1196 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver");
1197