1 /* 2 * skl.c - Implementation of ASoC Intel SKL HD Audio driver 3 * 4 * Copyright (C) 2014-2015 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * 7 * Derived mostly from Intel HDA driver with following copyrights: 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; version 2 of the License. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 22 */ 23 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/platform_device.h> 28 #include <linux/firmware.h> 29 #include <linux/delay.h> 30 #include <sound/pcm.h> 31 #include <sound/soc-acpi.h> 32 #include <sound/soc-acpi-intel-match.h> 33 #include <sound/hda_register.h> 34 #include <sound/hdaudio.h> 35 #include <sound/hda_i915.h> 36 #include <sound/hda_codec.h> 37 #include "skl.h" 38 #include "skl-sst-dsp.h" 39 #include "skl-sst-ipc.h" 40 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 41 #include "../../../soc/codecs/hdac_hda.h" 42 #endif 43 44 /* 45 * initialize the PCI registers 46 */ 47 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, 48 unsigned char mask, unsigned char val) 49 { 50 unsigned char data; 51 52 pci_read_config_byte(pci, reg, &data); 53 data &= ~mask; 54 data |= (val & mask); 55 pci_write_config_byte(pci, reg, data); 56 } 57 58 static void skl_init_pci(struct skl *skl) 59 { 60 struct hdac_bus *bus = skl_to_bus(skl); 61 62 /* 63 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 64 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 65 * Ensuring these bits are 0 clears playback static on some HD Audio 66 * codecs. 67 * The PCI register TCSEL is defined in the Intel manuals. 68 */ 69 dev_dbg(bus->dev, "Clearing TCSEL\n"); 70 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); 71 } 72 73 static void update_pci_dword(struct pci_dev *pci, 74 unsigned int reg, u32 mask, u32 val) 75 { 76 u32 data = 0; 77 78 pci_read_config_dword(pci, reg, &data); 79 data &= ~mask; 80 data |= (val & mask); 81 pci_write_config_dword(pci, reg, data); 82 } 83 84 /* 85 * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits 86 * 87 * @dev: device pointer 88 * @enable: enable/disable flag 89 */ 90 static void skl_enable_miscbdcge(struct device *dev, bool enable) 91 { 92 struct pci_dev *pci = to_pci_dev(dev); 93 u32 val; 94 95 val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; 96 97 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); 98 } 99 100 /** 101 * skl_clock_power_gating: Enable/Disable clock and power gating 102 * 103 * @dev: Device pointer 104 * @enable: Enable/Disable flag 105 */ 106 static void skl_clock_power_gating(struct device *dev, bool enable) 107 { 108 struct pci_dev *pci = to_pci_dev(dev); 109 struct hdac_bus *bus = pci_get_drvdata(pci); 110 u32 val; 111 112 /* Update PDCGE bit of CGCTL register */ 113 val = enable ? AZX_CGCTL_ADSPDCGE : 0; 114 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); 115 116 /* Update L1SEN bit of EM2 register */ 117 val = enable ? AZX_REG_VS_EM2_L1SEN : 0; 118 snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val); 119 120 /* Update ADSPPGD bit of PGCTL register */ 121 val = enable ? 0 : AZX_PGCTL_ADSPPGD; 122 update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val); 123 } 124 125 /* 126 * While performing reset, controller may not come back properly causing 127 * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset 128 * (init chip) and then again set CGCTL.MISCBDCGE to 1 129 */ 130 static int skl_init_chip(struct hdac_bus *bus, bool full_reset) 131 { 132 struct hdac_ext_link *hlink; 133 int ret; 134 135 skl_enable_miscbdcge(bus->dev, false); 136 ret = snd_hdac_bus_init_chip(bus, full_reset); 137 138 /* Reset stream-to-link mapping */ 139 list_for_each_entry(hlink, &bus->hlink_list, list) 140 bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV); 141 142 skl_enable_miscbdcge(bus->dev, true); 143 144 return ret; 145 } 146 147 void skl_update_d0i3c(struct device *dev, bool enable) 148 { 149 struct pci_dev *pci = to_pci_dev(dev); 150 struct hdac_bus *bus = pci_get_drvdata(pci); 151 u8 reg; 152 int timeout = 50; 153 154 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 155 /* Do not write to D0I3C until command in progress bit is cleared */ 156 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 157 udelay(10); 158 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 159 } 160 161 /* Highly unlikely. But if it happens, flag error explicitly */ 162 if (!timeout) { 163 dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n"); 164 return; 165 } 166 167 if (enable) 168 reg = reg | AZX_REG_VS_D0I3C_I3; 169 else 170 reg = reg & (~AZX_REG_VS_D0I3C_I3); 171 172 snd_hdac_chip_writeb(bus, VS_D0I3C, reg); 173 174 timeout = 50; 175 /* Wait for cmd in progress to be cleared before exiting the function */ 176 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 177 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 178 udelay(10); 179 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 180 } 181 182 /* Highly unlikely. But if it happens, flag error explicitly */ 183 if (!timeout) { 184 dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n"); 185 return; 186 } 187 188 dev_dbg(bus->dev, "D0I3C register = 0x%x\n", 189 snd_hdac_chip_readb(bus, VS_D0I3C)); 190 } 191 192 /* called from IRQ */ 193 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) 194 { 195 snd_pcm_period_elapsed(hstr->substream); 196 } 197 198 static irqreturn_t skl_interrupt(int irq, void *dev_id) 199 { 200 struct hdac_bus *bus = dev_id; 201 u32 status; 202 203 if (!pm_runtime_active(bus->dev)) 204 return IRQ_NONE; 205 206 spin_lock(&bus->reg_lock); 207 208 status = snd_hdac_chip_readl(bus, INTSTS); 209 if (status == 0 || status == 0xffffffff) { 210 spin_unlock(&bus->reg_lock); 211 return IRQ_NONE; 212 } 213 214 /* clear rirb int */ 215 status = snd_hdac_chip_readb(bus, RIRBSTS); 216 if (status & RIRB_INT_MASK) { 217 if (status & RIRB_INT_RESPONSE) 218 snd_hdac_bus_update_rirb(bus); 219 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 220 } 221 222 spin_unlock(&bus->reg_lock); 223 224 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; 225 } 226 227 static irqreturn_t skl_threaded_handler(int irq, void *dev_id) 228 { 229 struct hdac_bus *bus = dev_id; 230 u32 status; 231 232 status = snd_hdac_chip_readl(bus, INTSTS); 233 234 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); 235 236 return IRQ_HANDLED; 237 } 238 239 static int skl_acquire_irq(struct hdac_bus *bus, int do_disconnect) 240 { 241 struct skl *skl = bus_to_skl(bus); 242 int ret; 243 244 ret = request_threaded_irq(skl->pci->irq, skl_interrupt, 245 skl_threaded_handler, 246 IRQF_SHARED, 247 KBUILD_MODNAME, bus); 248 if (ret) { 249 dev_err(bus->dev, 250 "unable to grab IRQ %d, disabling device\n", 251 skl->pci->irq); 252 return ret; 253 } 254 255 bus->irq = skl->pci->irq; 256 pci_intx(skl->pci, 1); 257 258 return 0; 259 } 260 261 static int skl_suspend_late(struct device *dev) 262 { 263 struct pci_dev *pci = to_pci_dev(dev); 264 struct hdac_bus *bus = pci_get_drvdata(pci); 265 struct skl *skl = bus_to_skl(bus); 266 267 return skl_suspend_late_dsp(skl); 268 } 269 270 #ifdef CONFIG_PM 271 static int _skl_suspend(struct hdac_bus *bus) 272 { 273 struct skl *skl = bus_to_skl(bus); 274 struct pci_dev *pci = to_pci_dev(bus->dev); 275 int ret; 276 277 snd_hdac_ext_bus_link_power_down_all(bus); 278 279 ret = skl_suspend_dsp(skl); 280 if (ret < 0) 281 return ret; 282 283 snd_hdac_bus_stop_chip(bus); 284 update_pci_dword(pci, AZX_PCIREG_PGCTL, 285 AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK); 286 skl_enable_miscbdcge(bus->dev, false); 287 snd_hdac_bus_enter_link_reset(bus); 288 skl_enable_miscbdcge(bus->dev, true); 289 skl_cleanup_resources(skl); 290 291 return 0; 292 } 293 294 static int _skl_resume(struct hdac_bus *bus) 295 { 296 struct skl *skl = bus_to_skl(bus); 297 298 skl_init_pci(skl); 299 skl_init_chip(bus, true); 300 301 return skl_resume_dsp(skl); 302 } 303 #endif 304 305 #ifdef CONFIG_PM_SLEEP 306 /* 307 * power management 308 */ 309 static int skl_suspend(struct device *dev) 310 { 311 struct pci_dev *pci = to_pci_dev(dev); 312 struct hdac_bus *bus = pci_get_drvdata(pci); 313 struct skl *skl = bus_to_skl(bus); 314 int ret = 0; 315 316 /* 317 * Do not suspend if streams which are marked ignore suspend are 318 * running, we need to save the state for these and continue 319 */ 320 if (skl->supend_active) { 321 /* turn off the links and stop the CORB/RIRB DMA if it is On */ 322 snd_hdac_ext_bus_link_power_down_all(bus); 323 324 if (bus->cmd_dma_state) 325 snd_hdac_bus_stop_cmd_io(bus); 326 327 enable_irq_wake(bus->irq); 328 pci_save_state(pci); 329 } else { 330 ret = _skl_suspend(bus); 331 if (ret < 0) 332 return ret; 333 skl->skl_sst->fw_loaded = false; 334 } 335 336 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 337 ret = snd_hdac_display_power(bus, false); 338 if (ret < 0) 339 dev_err(bus->dev, 340 "Cannot turn OFF display power on i915\n"); 341 } 342 343 return ret; 344 } 345 346 static int skl_resume(struct device *dev) 347 { 348 struct pci_dev *pci = to_pci_dev(dev); 349 struct hdac_bus *bus = pci_get_drvdata(pci); 350 struct skl *skl = bus_to_skl(bus); 351 struct hdac_ext_link *hlink = NULL; 352 int ret; 353 354 /* Turned OFF in HDMI codec driver after codec reconfiguration */ 355 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 356 ret = snd_hdac_display_power(bus, true); 357 if (ret < 0) { 358 dev_err(bus->dev, 359 "Cannot turn on display power on i915\n"); 360 return ret; 361 } 362 } 363 364 /* 365 * resume only when we are not in suspend active, otherwise need to 366 * restore the device 367 */ 368 if (skl->supend_active) { 369 pci_restore_state(pci); 370 snd_hdac_ext_bus_link_power_up_all(bus); 371 disable_irq_wake(bus->irq); 372 /* 373 * turn On the links which are On before active suspend 374 * and start the CORB/RIRB DMA if On before 375 * active suspend. 376 */ 377 list_for_each_entry(hlink, &bus->hlink_list, list) { 378 if (hlink->ref_count) 379 snd_hdac_ext_bus_link_power_up(hlink); 380 } 381 382 ret = 0; 383 if (bus->cmd_dma_state) 384 snd_hdac_bus_init_cmd_io(bus); 385 } else { 386 ret = _skl_resume(bus); 387 388 /* turn off the links which are off before suspend */ 389 list_for_each_entry(hlink, &bus->hlink_list, list) { 390 if (!hlink->ref_count) 391 snd_hdac_ext_bus_link_power_down(hlink); 392 } 393 394 if (!bus->cmd_dma_state) 395 snd_hdac_bus_stop_cmd_io(bus); 396 } 397 398 return ret; 399 } 400 #endif /* CONFIG_PM_SLEEP */ 401 402 #ifdef CONFIG_PM 403 static int skl_runtime_suspend(struct device *dev) 404 { 405 struct pci_dev *pci = to_pci_dev(dev); 406 struct hdac_bus *bus = pci_get_drvdata(pci); 407 408 dev_dbg(bus->dev, "in %s\n", __func__); 409 410 return _skl_suspend(bus); 411 } 412 413 static int skl_runtime_resume(struct device *dev) 414 { 415 struct pci_dev *pci = to_pci_dev(dev); 416 struct hdac_bus *bus = pci_get_drvdata(pci); 417 418 dev_dbg(bus->dev, "in %s\n", __func__); 419 420 return _skl_resume(bus); 421 } 422 #endif /* CONFIG_PM */ 423 424 static const struct dev_pm_ops skl_pm = { 425 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) 426 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) 427 .suspend_late = skl_suspend_late, 428 }; 429 430 /* 431 * destructor 432 */ 433 static int skl_free(struct hdac_bus *bus) 434 { 435 struct skl *skl = bus_to_skl(bus); 436 437 skl->init_done = 0; /* to be sure */ 438 439 snd_hdac_ext_stop_streams(bus); 440 441 if (bus->irq >= 0) 442 free_irq(bus->irq, (void *)bus); 443 snd_hdac_bus_free_stream_pages(bus); 444 snd_hdac_stream_free_all(bus); 445 snd_hdac_link_free_all(bus); 446 447 if (bus->remap_addr) 448 iounmap(bus->remap_addr); 449 450 pci_release_regions(skl->pci); 451 pci_disable_device(skl->pci); 452 453 snd_hdac_ext_bus_exit(bus); 454 455 cancel_work_sync(&skl->probe_work); 456 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 457 snd_hdac_i915_exit(bus); 458 459 return 0; 460 } 461 462 /* 463 * For each ssp there are 3 clocks (mclk/sclk/sclkfs). 464 * e.g. for ssp0, clocks will be named as 465 * "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs" 466 * So for skl+, there are 6 ssps, so 18 clocks will be created. 467 */ 468 static struct skl_ssp_clk skl_ssp_clks[] = { 469 {.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"}, 470 {.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"}, 471 {.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"}, 472 {.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"}, 473 {.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"}, 474 {.name = "ssp2_sclkfs"}, 475 {.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"}, 476 {.name = "ssp5_sclkfs"}, 477 }; 478 479 static struct snd_soc_acpi_mach *skl_find_hda_machine(struct skl *skl, 480 struct snd_soc_acpi_mach *machines) 481 { 482 struct hdac_bus *bus = skl_to_bus(skl); 483 struct snd_soc_acpi_mach *mach; 484 485 /* check if we have any codecs detected on bus */ 486 if (bus->codec_mask == 0) 487 return NULL; 488 489 /* point to common table */ 490 mach = snd_soc_acpi_intel_hda_machines; 491 492 /* all entries in the machine table use the same firmware */ 493 mach->fw_filename = machines->fw_filename; 494 495 return mach; 496 } 497 498 static int skl_find_machine(struct skl *skl, void *driver_data) 499 { 500 struct hdac_bus *bus = skl_to_bus(skl); 501 struct snd_soc_acpi_mach *mach = driver_data; 502 struct skl_machine_pdata *pdata; 503 504 mach = snd_soc_acpi_find_machine(mach); 505 if (!mach) { 506 dev_dbg(bus->dev, "No matching I2S machine driver found\n"); 507 mach = skl_find_hda_machine(skl, driver_data); 508 if (!mach) { 509 dev_err(bus->dev, "No matching machine driver found\n"); 510 return -ENODEV; 511 } 512 } 513 514 skl->mach = mach; 515 skl->fw_name = mach->fw_filename; 516 pdata = mach->pdata; 517 518 if (pdata) { 519 skl->use_tplg_pcm = pdata->use_tplg_pcm; 520 pdata->dmic_num = skl_get_dmic_geo(skl); 521 } 522 523 return 0; 524 } 525 526 static int skl_machine_device_register(struct skl *skl) 527 { 528 struct snd_soc_acpi_mach *mach = skl->mach; 529 struct hdac_bus *bus = skl_to_bus(skl); 530 struct skl_machine_pdata *pdata; 531 struct platform_device *pdev; 532 int ret; 533 534 pdev = platform_device_alloc(mach->drv_name, -1); 535 if (pdev == NULL) { 536 dev_err(bus->dev, "platform device alloc failed\n"); 537 return -EIO; 538 } 539 540 ret = platform_device_add(pdev); 541 if (ret) { 542 dev_err(bus->dev, "failed to add machine device\n"); 543 platform_device_put(pdev); 544 return -EIO; 545 } 546 547 if (mach->pdata) { 548 pdata = (struct skl_machine_pdata *)mach->pdata; 549 pdata->platform = dev_name(bus->dev); 550 pdata->codec_mask = bus->codec_mask; 551 dev_set_drvdata(&pdev->dev, mach->pdata); 552 } 553 554 skl->i2s_dev = pdev; 555 556 return 0; 557 } 558 559 static void skl_machine_device_unregister(struct skl *skl) 560 { 561 if (skl->i2s_dev) 562 platform_device_unregister(skl->i2s_dev); 563 } 564 565 static int skl_dmic_device_register(struct skl *skl) 566 { 567 struct hdac_bus *bus = skl_to_bus(skl); 568 struct platform_device *pdev; 569 int ret; 570 571 /* SKL has one dmic port, so allocate dmic device for this */ 572 pdev = platform_device_alloc("dmic-codec", -1); 573 if (!pdev) { 574 dev_err(bus->dev, "failed to allocate dmic device\n"); 575 return -ENOMEM; 576 } 577 578 ret = platform_device_add(pdev); 579 if (ret) { 580 dev_err(bus->dev, "failed to add dmic device: %d\n", ret); 581 platform_device_put(pdev); 582 return ret; 583 } 584 skl->dmic_dev = pdev; 585 586 return 0; 587 } 588 589 static void skl_dmic_device_unregister(struct skl *skl) 590 { 591 if (skl->dmic_dev) 592 platform_device_unregister(skl->dmic_dev); 593 } 594 595 static struct skl_clk_parent_src skl_clk_src[] = { 596 { .clk_id = SKL_XTAL, .name = "xtal" }, 597 { .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 }, 598 { .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 }, 599 }; 600 601 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id) 602 { 603 unsigned int i; 604 605 for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) { 606 if (skl_clk_src[i].clk_id == clk_id) 607 return &skl_clk_src[i]; 608 } 609 610 return NULL; 611 } 612 613 static void init_skl_xtal_rate(int pci_id) 614 { 615 switch (pci_id) { 616 case 0x9d70: 617 case 0x9d71: 618 skl_clk_src[0].rate = 24000000; 619 return; 620 621 default: 622 skl_clk_src[0].rate = 19200000; 623 return; 624 } 625 } 626 627 static int skl_clock_device_register(struct skl *skl) 628 { 629 struct platform_device_info pdevinfo = {NULL}; 630 struct skl_clk_pdata *clk_pdata; 631 632 clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata), 633 GFP_KERNEL); 634 if (!clk_pdata) 635 return -ENOMEM; 636 637 init_skl_xtal_rate(skl->pci->device); 638 639 clk_pdata->parent_clks = skl_clk_src; 640 clk_pdata->ssp_clks = skl_ssp_clks; 641 clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks); 642 643 /* Query NHLT to fill the rates and parent */ 644 skl_get_clks(skl, clk_pdata->ssp_clks); 645 clk_pdata->pvt_data = skl; 646 647 /* Register Platform device */ 648 pdevinfo.parent = &skl->pci->dev; 649 pdevinfo.id = -1; 650 pdevinfo.name = "skl-ssp-clk"; 651 pdevinfo.data = clk_pdata; 652 pdevinfo.size_data = sizeof(*clk_pdata); 653 skl->clk_dev = platform_device_register_full(&pdevinfo); 654 return PTR_ERR_OR_ZERO(skl->clk_dev); 655 } 656 657 static void skl_clock_device_unregister(struct skl *skl) 658 { 659 if (skl->clk_dev) 660 platform_device_unregister(skl->clk_dev); 661 } 662 663 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 664 665 #define IDISP_INTEL_VENDOR_ID 0x80860000 666 667 /* 668 * load the legacy codec driver 669 */ 670 static void load_codec_module(struct hda_codec *codec) 671 { 672 #ifdef MODULE 673 char modalias[MODULE_NAME_LEN]; 674 const char *mod = NULL; 675 676 snd_hdac_codec_modalias(&codec->core, modalias, sizeof(modalias)); 677 mod = modalias; 678 dev_dbg(&codec->core.dev, "loading %s codec module\n", mod); 679 request_module(mod); 680 #endif 681 } 682 683 #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */ 684 685 /* 686 * Probe the given codec address 687 */ 688 static int probe_codec(struct hdac_bus *bus, int addr) 689 { 690 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 691 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 692 unsigned int res = -1; 693 struct skl *skl = bus_to_skl(bus); 694 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 695 struct hdac_hda_priv *hda_codec; 696 int err; 697 #endif 698 struct hdac_device *hdev; 699 700 mutex_lock(&bus->cmd_mutex); 701 snd_hdac_bus_send_cmd(bus, cmd); 702 snd_hdac_bus_get_response(bus, addr, &res); 703 mutex_unlock(&bus->cmd_mutex); 704 if (res == -1) 705 return -EIO; 706 dev_dbg(bus->dev, "codec #%d probed OK: %x\n", addr, res); 707 708 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 709 hda_codec = devm_kzalloc(&skl->pci->dev, sizeof(*hda_codec), 710 GFP_KERNEL); 711 if (!hda_codec) 712 return -ENOMEM; 713 714 hda_codec->codec.bus = skl_to_hbus(skl); 715 hdev = &hda_codec->codec.core; 716 717 err = snd_hdac_ext_bus_device_init(bus, addr, hdev); 718 if (err < 0) 719 return err; 720 721 /* use legacy bus only for HDA codecs, idisp uses ext bus */ 722 if ((res & 0xFFFF0000) != IDISP_INTEL_VENDOR_ID) { 723 hdev->type = HDA_DEV_LEGACY; 724 load_codec_module(&hda_codec->codec); 725 } 726 return 0; 727 #else 728 hdev = devm_kzalloc(&skl->pci->dev, sizeof(*hdev), GFP_KERNEL); 729 if (!hdev) 730 return -ENOMEM; 731 732 return snd_hdac_ext_bus_device_init(bus, addr, hdev); 733 #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */ 734 } 735 736 /* Codec initialization */ 737 static void skl_codec_create(struct hdac_bus *bus) 738 { 739 int c, max_slots; 740 741 max_slots = HDA_MAX_CODECS; 742 743 /* First try to probe all given codec slots */ 744 for (c = 0; c < max_slots; c++) { 745 if ((bus->codec_mask & (1 << c))) { 746 if (probe_codec(bus, c) < 0) { 747 /* 748 * Some BIOSen give you wrong codec addresses 749 * that don't exist 750 */ 751 dev_warn(bus->dev, 752 "Codec #%d probe error; disabling it...\n", c); 753 bus->codec_mask &= ~(1 << c); 754 /* 755 * More badly, accessing to a non-existing 756 * codec often screws up the controller bus, 757 * and disturbs the further communications. 758 * Thus if an error occurs during probing, 759 * better to reset the controller bus to get 760 * back to the sanity state. 761 */ 762 snd_hdac_bus_stop_chip(bus); 763 skl_init_chip(bus, true); 764 } 765 } 766 } 767 } 768 769 static const struct hdac_bus_ops bus_core_ops = { 770 .command = snd_hdac_bus_send_cmd, 771 .get_response = snd_hdac_bus_get_response, 772 }; 773 774 static int skl_i915_init(struct hdac_bus *bus) 775 { 776 int err; 777 778 /* 779 * The HDMI codec is in GPU so we need to ensure that it is powered 780 * up and ready for probe 781 */ 782 err = snd_hdac_i915_init(bus); 783 if (err < 0) 784 return err; 785 786 err = snd_hdac_display_power(bus, true); 787 if (err < 0) 788 dev_err(bus->dev, "Cannot turn on display power on i915\n"); 789 790 return err; 791 } 792 793 static void skl_probe_work(struct work_struct *work) 794 { 795 struct skl *skl = container_of(work, struct skl, probe_work); 796 struct hdac_bus *bus = skl_to_bus(skl); 797 struct hdac_ext_link *hlink = NULL; 798 int err; 799 800 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 801 err = skl_i915_init(bus); 802 if (err < 0) 803 return; 804 } 805 806 err = skl_init_chip(bus, true); 807 if (err < 0) { 808 dev_err(bus->dev, "Init chip failed with err: %d\n", err); 809 goto out_err; 810 } 811 812 /* codec detection */ 813 if (!bus->codec_mask) 814 dev_info(bus->dev, "no hda codecs found!\n"); 815 816 /* create codec instances */ 817 skl_codec_create(bus); 818 819 /* register platform dai and controls */ 820 err = skl_platform_register(bus->dev); 821 if (err < 0) { 822 dev_err(bus->dev, "platform register failed: %d\n", err); 823 return; 824 } 825 826 if (bus->ppcap) { 827 err = skl_machine_device_register(skl); 828 if (err < 0) { 829 dev_err(bus->dev, "machine register failed: %d\n", err); 830 goto out_err; 831 } 832 } 833 834 /* 835 * we are done probing so decrement link counts 836 */ 837 list_for_each_entry(hlink, &bus->hlink_list, list) 838 snd_hdac_ext_bus_link_put(bus, hlink); 839 840 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 841 err = snd_hdac_display_power(bus, false); 842 if (err < 0) { 843 dev_err(bus->dev, "Cannot turn off display power on i915\n"); 844 skl_machine_device_unregister(skl); 845 return; 846 } 847 } 848 849 /* configure PM */ 850 pm_runtime_put_noidle(bus->dev); 851 pm_runtime_allow(bus->dev); 852 skl->init_done = 1; 853 854 return; 855 856 out_err: 857 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 858 err = snd_hdac_display_power(bus, false); 859 } 860 861 /* 862 * constructor 863 */ 864 static int skl_create(struct pci_dev *pci, 865 const struct hdac_io_ops *io_ops, 866 struct skl **rskl) 867 { 868 struct hdac_ext_bus_ops *ext_ops = NULL; 869 struct skl *skl; 870 struct hdac_bus *bus; 871 struct hda_bus *hbus; 872 int err; 873 874 *rskl = NULL; 875 876 err = pci_enable_device(pci); 877 if (err < 0) 878 return err; 879 880 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); 881 if (!skl) { 882 pci_disable_device(pci); 883 return -ENOMEM; 884 } 885 886 hbus = skl_to_hbus(skl); 887 bus = skl_to_bus(skl); 888 889 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 890 ext_ops = snd_soc_hdac_hda_get_ops(); 891 #endif 892 snd_hdac_ext_bus_init(bus, &pci->dev, &bus_core_ops, io_ops, ext_ops); 893 bus->use_posbuf = 1; 894 skl->pci = pci; 895 INIT_WORK(&skl->probe_work, skl_probe_work); 896 bus->bdl_pos_adj = 0; 897 898 mutex_init(&hbus->prepare_mutex); 899 hbus->pci = pci; 900 hbus->mixer_assigned = -1; 901 hbus->modelname = "sklbus"; 902 903 *rskl = skl; 904 905 return 0; 906 } 907 908 static int skl_first_init(struct hdac_bus *bus) 909 { 910 struct skl *skl = bus_to_skl(bus); 911 struct pci_dev *pci = skl->pci; 912 int err; 913 unsigned short gcap; 914 int cp_streams, pb_streams, start_idx; 915 916 err = pci_request_regions(pci, "Skylake HD audio"); 917 if (err < 0) 918 return err; 919 920 bus->addr = pci_resource_start(pci, 0); 921 bus->remap_addr = pci_ioremap_bar(pci, 0); 922 if (bus->remap_addr == NULL) { 923 dev_err(bus->dev, "ioremap error\n"); 924 return -ENXIO; 925 } 926 927 snd_hdac_bus_reset_link(bus, true); 928 929 snd_hdac_bus_parse_capabilities(bus); 930 931 if (skl_acquire_irq(bus, 0) < 0) 932 return -EBUSY; 933 934 pci_set_master(pci); 935 synchronize_irq(bus->irq); 936 937 gcap = snd_hdac_chip_readw(bus, GCAP); 938 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); 939 940 /* allow 64bit DMA address if supported by H/W */ 941 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) { 942 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64)); 943 } else { 944 dma_set_mask(bus->dev, DMA_BIT_MASK(32)); 945 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32)); 946 } 947 948 /* read number of streams from GCAP register */ 949 cp_streams = (gcap >> 8) & 0x0f; 950 pb_streams = (gcap >> 12) & 0x0f; 951 952 if (!pb_streams && !cp_streams) 953 return -EIO; 954 955 bus->num_streams = cp_streams + pb_streams; 956 957 /* initialize streams */ 958 snd_hdac_ext_stream_init_all 959 (bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); 960 start_idx = cp_streams; 961 snd_hdac_ext_stream_init_all 962 (bus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); 963 964 err = snd_hdac_bus_alloc_stream_pages(bus); 965 if (err < 0) 966 return err; 967 968 /* initialize chip */ 969 skl_init_pci(skl); 970 971 return skl_init_chip(bus, true); 972 } 973 974 static int skl_probe(struct pci_dev *pci, 975 const struct pci_device_id *pci_id) 976 { 977 struct skl *skl; 978 struct hdac_bus *bus = NULL; 979 int err; 980 981 /* we use ext core ops, so provide NULL for ops here */ 982 err = skl_create(pci, NULL, &skl); 983 if (err < 0) 984 return err; 985 986 bus = skl_to_bus(skl); 987 988 err = skl_first_init(bus); 989 if (err < 0) 990 goto out_free; 991 992 skl->pci_id = pci->device; 993 994 device_disable_async_suspend(bus->dev); 995 996 skl->nhlt = skl_nhlt_init(bus->dev); 997 998 if (skl->nhlt == NULL) { 999 err = -ENODEV; 1000 goto out_free; 1001 } 1002 1003 err = skl_nhlt_create_sysfs(skl); 1004 if (err < 0) 1005 goto out_nhlt_free; 1006 1007 skl_nhlt_update_topology_bin(skl); 1008 1009 pci_set_drvdata(skl->pci, bus); 1010 1011 /* check if dsp is there */ 1012 if (bus->ppcap) { 1013 /* create device for dsp clk */ 1014 err = skl_clock_device_register(skl); 1015 if (err < 0) 1016 goto out_clk_free; 1017 1018 err = skl_find_machine(skl, (void *)pci_id->driver_data); 1019 if (err < 0) 1020 goto out_nhlt_free; 1021 1022 err = skl_init_dsp(skl); 1023 if (err < 0) { 1024 dev_dbg(bus->dev, "error failed to register dsp\n"); 1025 goto out_nhlt_free; 1026 } 1027 skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge; 1028 skl->skl_sst->clock_power_gating = skl_clock_power_gating; 1029 } 1030 if (bus->mlcap) 1031 snd_hdac_ext_bus_get_ml_capabilities(bus); 1032 1033 snd_hdac_bus_stop_chip(bus); 1034 1035 /* create device for soc dmic */ 1036 err = skl_dmic_device_register(skl); 1037 if (err < 0) 1038 goto out_dsp_free; 1039 1040 schedule_work(&skl->probe_work); 1041 1042 return 0; 1043 1044 out_dsp_free: 1045 skl_free_dsp(skl); 1046 out_clk_free: 1047 skl_clock_device_unregister(skl); 1048 out_nhlt_free: 1049 skl_nhlt_free(skl->nhlt); 1050 out_free: 1051 skl_free(bus); 1052 1053 return err; 1054 } 1055 1056 static void skl_shutdown(struct pci_dev *pci) 1057 { 1058 struct hdac_bus *bus = pci_get_drvdata(pci); 1059 struct hdac_stream *s; 1060 struct hdac_ext_stream *stream; 1061 struct skl *skl; 1062 1063 if (!bus) 1064 return; 1065 1066 skl = bus_to_skl(bus); 1067 1068 if (!skl->init_done) 1069 return; 1070 1071 snd_hdac_ext_stop_streams(bus); 1072 list_for_each_entry(s, &bus->stream_list, list) { 1073 stream = stream_to_hdac_ext_stream(s); 1074 snd_hdac_ext_stream_decouple(bus, stream, false); 1075 } 1076 1077 snd_hdac_bus_stop_chip(bus); 1078 } 1079 1080 static void skl_remove(struct pci_dev *pci) 1081 { 1082 struct hdac_bus *bus = pci_get_drvdata(pci); 1083 struct skl *skl = bus_to_skl(bus); 1084 1085 release_firmware(skl->tplg); 1086 1087 pm_runtime_get_noresume(&pci->dev); 1088 1089 /* codec removal, invoke bus_device_remove */ 1090 snd_hdac_ext_bus_device_remove(bus); 1091 1092 skl->debugfs = NULL; 1093 skl_platform_unregister(&pci->dev); 1094 skl_free_dsp(skl); 1095 skl_machine_device_unregister(skl); 1096 skl_dmic_device_unregister(skl); 1097 skl_clock_device_unregister(skl); 1098 skl_nhlt_remove_sysfs(skl); 1099 skl_nhlt_free(skl->nhlt); 1100 skl_free(bus); 1101 dev_set_drvdata(&pci->dev, NULL); 1102 } 1103 1104 /* PCI IDs */ 1105 static const struct pci_device_id skl_ids[] = { 1106 /* Sunrise Point-LP */ 1107 { PCI_DEVICE(0x8086, 0x9d70), 1108 .driver_data = (unsigned long)&snd_soc_acpi_intel_skl_machines}, 1109 /* BXT-P */ 1110 { PCI_DEVICE(0x8086, 0x5a98), 1111 .driver_data = (unsigned long)&snd_soc_acpi_intel_bxt_machines}, 1112 /* KBL */ 1113 { PCI_DEVICE(0x8086, 0x9D71), 1114 .driver_data = (unsigned long)&snd_soc_acpi_intel_kbl_machines}, 1115 /* GLK */ 1116 { PCI_DEVICE(0x8086, 0x3198), 1117 .driver_data = (unsigned long)&snd_soc_acpi_intel_glk_machines}, 1118 /* CNL */ 1119 { PCI_DEVICE(0x8086, 0x9dc8), 1120 .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines}, 1121 { 0, } 1122 }; 1123 MODULE_DEVICE_TABLE(pci, skl_ids); 1124 1125 /* pci_driver definition */ 1126 static struct pci_driver skl_driver = { 1127 .name = KBUILD_MODNAME, 1128 .id_table = skl_ids, 1129 .probe = skl_probe, 1130 .remove = skl_remove, 1131 .shutdown = skl_shutdown, 1132 .driver = { 1133 .pm = &skl_pm, 1134 }, 1135 }; 1136 module_pci_driver(skl_driver); 1137 1138 MODULE_LICENSE("GPL v2"); 1139 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver"); 1140